clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers

Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets
on MT6735.

Signed-off-by: Yassine Oudjana <y.oudjana@p

clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers

Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets
on MT6735.

Signed-off-by: Yassine Oudjana <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers

Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
clock and reset controllers. These provide the base cloc

clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers

Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg
clock and reset controllers. These provide the base clocks and resets
on the platform, enough to bring up all essential blocks including
PWRAP, MSDC and peripherals (UART, I2C, SPI).

Signed-off-by: Yassine Oudjana <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: add drivers for MT7988 SoC

Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
typical MediaTek designs.

Also add driver for XFIPLL clock generating the 156.25MHz clock f

clk: mediatek: add drivers for MT7988 SoC

Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
typical MediaTek designs.

Also add driver for XFIPLL clock generating the 156.25MHz clock for
the XFI SerDes. It needs an undocumented software workaround and has
an unknown internal design.

Signed-off-by: Sam Shih <[email protected]>
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
[[email protected]: Add module license to infracfg file]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 adsp clock support

Add MT8188 adsp clock controller which provides clock gate
control for Audio DSP.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: A

clk: mediatek: Add MT8188 adsp clock support

Add MT8188 adsp clock controller which provides clock gate
control for Audio DSP.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 imp i2c wrapper clock support

Add MT8188 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.

Signed-off-by: Garmin.Chang <Garmin.Chang@med

clk: mediatek: Add MT8188 imp i2c wrapper clock support

Add MT8188 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 wpesys clock support

Add MT8188 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: Garmin.Chang <[email protected]>
Revie

clk: mediatek: Add MT8188 wpesys clock support

Add MT8188 wpesys clock controllers which provide clock gate
control in Wrapping Engine.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 vppsys1 clock support

Add MT8188 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek

clk: mediatek: Add MT8188 vppsys1 clock support

Add MT8188 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 vppsys0 clock support

Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek

clk: mediatek: Add MT8188 vppsys0 clock support

Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 vencsys clock support

Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.

Signed-off-by: Garmin.Chang <[email protected]>
Revi

clk: mediatek: Add MT8188 vencsys clock support

Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 vdosys1 clock support

Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate de

clk: mediatek: Add MT8188 vdosys1 clock support

Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 vdosys0 clock support

Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate de

clk: mediatek: Add MT8188 vdosys0 clock support

Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 vdecsys clock support

Add MT8188 vdec clock controllers which provide clock gate
control for video decoder.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewe

clk: mediatek: Add MT8188 vdecsys clock support

Add MT8188 vdec clock controllers which provide clock gate
control for video decoder.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 mfgcfg clock support

Add MT8188 mfg clock controller which provides clock gate
control for GPU.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Angelo

clk: mediatek: Add MT8188 mfgcfg clock support

Add MT8188 mfg clock controller which provides clock gate
control for GPU.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 ipesys clock support

Add MT8188 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: Garmin.Chang <[email protected]>

clk: mediatek: Add MT8188 ipesys clock support

Add MT8188 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 imgsys clock support

Add MT8188 imgsys clock controllers which provide clock gate
control for image IP blocks.

Signed-off-by: Garmin.Chang <[email protected]>
Revi

clk: mediatek: Add MT8188 imgsys clock support

Add MT8188 imgsys clock controllers which provide clock gate
control for image IP blocks.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 ccusys clock support

Add MT8188 ccusys clock controller which provides clock gate
control in Camera Computing Unit.

Signed-off-by: Garmin.Chang <[email protected]>

clk: mediatek: Add MT8188 ccusys clock support

Add MT8188 ccusys clock controller which provides clock gate
control in Camera Computing Unit.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 camsys clock support

Add MT8188 camsys clock controllers which provide clock gate
control for camera IP blocks.

Signed-off-by: Garmin.Chang <[email protected]>
Rev

clk: mediatek: Add MT8188 camsys clock support

Add MT8188 camsys clock controllers which provide clock gate
control for camera IP blocks.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 infrastructure clock support

Add MT8188 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.

Signed-off-by: Garmin

clk: mediatek: Add MT8188 infrastructure clock support

Add MT8188 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 peripheral clock support

Add MT8188 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.

Signed-off-by: Garmin.Chang <Garmin.Chan

clk: mediatek: Add MT8188 peripheral clock support

Add MT8188 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 topckgen clock support

Add MT8188 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.

Signed-off-by: Garmin.Chan

clk: mediatek: Add MT8188 topckgen clock support

Add MT8188 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Add MT8188 apmixedsys clock support

Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.

Signed-off-by: Garmin.Chang <Garmi

clk: mediatek: Add MT8188 apmixedsys clock support

Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.

Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: mt8135: Move apmixedsys to its own file

In preparation for migrating mt8135 clocks to the common simple
probe mechanism, move the apmixedsys clocks to a different file.

Signed-off-by

clk: mediatek: mt8135: Move apmixedsys to its own file

In preparation for migrating mt8135 clocks to the common simple
probe mechanism, move the apmixedsys clocks to a different file.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-51-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: mt8192: Move apmixedsys clock driver to its own file

This is the last man standing in clk-mt8192.c that won't allow us to
use the module_platform_driver() macro, and for *no* good rea

clk: mediatek: mt8192: Move apmixedsys clock driver to its own file

This is the last man standing in clk-mt8192.c that won't allow us to
use the module_platform_driver() macro, and for *no* good reason.
Move it to clk-mt8192-apmixedsys.c and while at it, also add a
.remove() callback for it.

Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was
just due to them being in the same file and probing different clocks,
and since now there's just one platform_driver struct per file, it
seemed natural to rename the `-simple` variant to just "clk-mt8192".

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Miles Chen <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-48-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Split configuration options for MT8186 clock drivers

When building clock drivers for MT8186, some may want to build in only
some of them to, for example, get CPUFreq up faster, and so

clk: mediatek: Split configuration options for MT8186 clock drivers

When building clock drivers for MT8186, some may want to build in only
some of them to, for example, get CPUFreq up faster, and some may want
to leave out some clock drivers entirely as a machine may not need the
Warp Engine or the camera ISP (hence, their clock drivers).

Split the various clock drivers in their own configuration options,
keeping MT8186 configuration options consistent with other MediaTek
SoCs.

While at it, also allow building the remaining clock drivers as modules
by switching COMMON_CLK_MT8186 to tristate.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-47-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>

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clk: mediatek: Split MT8195 clock drivers and allow module build

MT8195 clock drivers were encapsulated in one single (and big) Kconfig
option: there's no reason to do that, as it is totally unneces

clk: mediatek: Split MT8195 clock drivers and allow module build

MT8195 clock drivers were encapsulated in one single (and big) Kconfig
option: there's no reason to do that, as it is totally unnecessary to
build in all or none of them.

Split them out: keep boot-critical clocks as bool and allow choosing
non critical clocks as tristate.

As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS
are not for build-time but rather for runtime, as clocks registered
by those have runtime dependencies on either or both VPP and IMGSYS.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Tested-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/20230306140543.1813621-40-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <[email protected]>

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