| af94002b | 13-Jan-2021 |
Guo Ren <[email protected]> |
csky: Fixup swapon
Current csky's swappon is broken by wrong swap PTE entry format. Now redesign the new format for abiv1 & abiv2 and make swappon + zram work properly on csky machines.
C-SKY PTE h
csky: Fixup swapon
Current csky's swappon is broken by wrong swap PTE entry format. Now redesign the new format for abiv1 & abiv2 and make swappon + zram work properly on csky machines.
C-SKY PTE has VALID, DIRTY to emulate PRESENT, READ, WRITE, EXEC attributes. GLOBAL bit is shared by two pages in the same tlb entry. So we need to keep GLOBAL, VALID, PRESENT zero in swp_pte.
To distinguish PAGE_NONE and swp_pte, we need to use an additional bit (abiv1 is _PAGE_READ, abiv2 is _PAGE_WRITE).
Signed-off-by: Guo Ren <[email protected]> Cc: Arnd Bergmann <[email protected]>
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| a8fac05a | 11-Jan-2021 |
Guo Ren <[email protected]> |
csky: pgtable.h: Coding convention
C-SKY page table attributes only have 'Dirty' and 'Valid' to emulate 'PRESENT, READ, WRITE, EXEC, DIRTY, ACCESSED'.
This patch cleanup unnecessary definition.
Si
csky: pgtable.h: Coding convention
C-SKY page table attributes only have 'Dirty' and 'Valid' to emulate 'PRESENT, READ, WRITE, EXEC, DIRTY, ACCESSED'.
This patch cleanup unnecessary definition.
Signed-off-by: Guo Ren <[email protected]> Cc: Arnd Bergmann <[email protected]>
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| a5447fb9 | 28-Jul-2020 |
Guo Ren <[email protected]> |
csky: Fixup kprobes handler couldn't change pc
The "Changing Execution Path" section in the Documentation/kprobes.txt said:
Since kprobes can probe into a running kernel code, it can change the reg
csky: Fixup kprobes handler couldn't change pc
The "Changing Execution Path" section in the Documentation/kprobes.txt said:
Since kprobes can probe into a running kernel code, it can change the register set, including instruction pointer.
Signed-off-by: Guo Ren <[email protected]> Cc: Arnd Bergmann <[email protected]>
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| 20f69538 | 24-May-2020 |
Guo Ren <[email protected]> |
csky: Coding convention in entry.S
There is no fixup or feature in the patch, we only cleanup with:
- Remove unnecessary reg used (r11, r12), just use r9 & r10 & syscallid regs as temp useage.
csky: Coding convention in entry.S
There is no fixup or feature in the patch, we only cleanup with:
- Remove unnecessary reg used (r11, r12), just use r9 & r10 & syscallid regs as temp useage. - Add _TIF_SYSCALL_WORK and _TIF_WORK_MASK to gather macros.
Signed-off-by: Guo Ren <[email protected]>
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| e0bbb538 | 24-May-2020 |
Guo Ren <[email protected]> |
csky: Fixup abiv2 syscall_trace break a4 & a5
Current implementation could destory a4 & a5 when strace, so we need to get them from pt_regs by SAVE_ALL.
Signed-off-by: Guo Ren <[email protected]
csky: Fixup abiv2 syscall_trace break a4 & a5
Current implementation could destory a4 & a5 when strace, so we need to get them from pt_regs by SAVE_ALL.
Signed-off-by: Guo Ren <[email protected]>
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| 165f2d28 | 21-Apr-2020 |
Liu Yibin <[email protected]> |
csky: Fixup msa highest 3 bits mask
Just as comment mentioned, the msa format:
cr<30/31, 15> MSA register format: 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 BA Reserved SH WA
csky: Fixup msa highest 3 bits mask
Just as comment mentioned, the msa format:
cr<30/31, 15> MSA register format: 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 BA Reserved SH WA B SO SEC C D V
So we should shift 29 bits not 28 bits for mask
Signed-off-by: Liu Yibin <[email protected]> Signed-off-by: Guo Ren <[email protected]>
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| aefd9461 | 28-Mar-2020 |
Guo Ren <[email protected]> |
csky: Fixup cpu speculative execution to IO area
For the memory size ( > 512MB, < 1GB), the MSA setting is:
- SSEG0: PHY_START , PHY_START + 512MB - SSEG1: PHY_START + 512MB, PHY_START + 1
csky: Fixup cpu speculative execution to IO area
For the memory size ( > 512MB, < 1GB), the MSA setting is:
- SSEG0: PHY_START , PHY_START + 512MB - SSEG1: PHY_START + 512MB, PHY_START + 1GB
But the real memory is no more than 1GB, there is a gap between the end size of memory and border of 1GB. CPU could speculatively execute to that gap and if the gap of the bus couldn't respond to the CPU request, then the crash will happen.
Now make the setting with:
- SSEG0: PHY_START , PHY_START + 512MB (no change) - SSEG1: Disabled (We use highmem to use the memory of 512MB~1GB)
We also deprecated zhole_szie[] settings, it's only used by arm style CPUs. All memory gap should use Reserved setting of dts in csky system.
Signed-off-by: Guo Ren <[email protected]>
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| 89a3927a | 18-Feb-2020 |
Guo Ren <[email protected]> |
csky: Implement ftrace with regs
This patch implements FTRACE_WITH_REGS for csky, which allows a traced function's arguments (and some other registers) to be captured into a struct pt_regs, allowing
csky: Implement ftrace with regs
This patch implements FTRACE_WITH_REGS for csky, which allows a traced function's arguments (and some other registers) to be captured into a struct pt_regs, allowing these to be inspected and/or modified.
Signed-off-by: Guo Ren <[email protected]>
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