1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <[email protected]> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin ([email protected]) 12 * Shaohua Li ([email protected]) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 27 #include <linux/mod_devicetable.h> 28 29 #include <linux/types.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/list.h> 33 #include <linux/compiler.h> 34 #include <linux/errno.h> 35 #include <linux/kobject.h> 36 #include <linux/atomic.h> 37 #include <linux/device.h> 38 #include <linux/interrupt.h> 39 #include <linux/io.h> 40 #include <linux/resource_ext.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 46 PCI_STATUS_SIG_SYSTEM_ERROR | \ 47 PCI_STATUS_REC_MASTER_ABORT | \ 48 PCI_STATUS_REC_TARGET_ABORT | \ 49 PCI_STATUS_SIG_TARGET_ABORT | \ 50 PCI_STATUS_PARITY) 51 52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 53 #define PCI_NUM_RESET_METHODS 7 54 55 #define PCI_RESET_PROBE true 56 #define PCI_RESET_DO_RESET false 57 58 /* 59 * The PCI interface treats multi-function devices as independent 60 * devices. The slot/function address of each device is encoded 61 * in a single byte as follows: 62 * 63 * 7:3 = slot 64 * 2:0 = function 65 * 66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 67 * In the interest of not exposing interfaces to user-space unnecessarily, 68 * the following kernel-only defines are being added here. 69 */ 70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 73 74 /* pci_slot represents a physical slot */ 75 struct pci_slot { 76 struct pci_bus *bus; /* Bus this slot is on */ 77 struct list_head list; /* Node in list of slots */ 78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 80 struct kobject kobj; 81 }; 82 83 static inline const char *pci_slot_name(const struct pci_slot *slot) 84 { 85 return kobject_name(&slot->kobj); 86 } 87 88 /* File state for mmap()s on /proc/bus/pci/X/Y */ 89 enum pci_mmap_state { 90 pci_mmap_io, 91 pci_mmap_mem 92 }; 93 94 /* For PCI devices, the region numbers are assigned this way: */ 95 enum { 96 /* #0-5: standard PCI resources */ 97 PCI_STD_RESOURCES, 98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 99 100 /* #6: expansion ROM resource */ 101 PCI_ROM_RESOURCE, 102 103 /* Device-specific resources */ 104 #ifdef CONFIG_PCI_IOV 105 PCI_IOV_RESOURCES, 106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 107 #endif 108 109 /* PCI-to-PCI (P2P) bridge windows */ 110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 113 114 /* CardBus bridge windows */ 115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 119 120 /* Total number of bridge resources for P2P and CardBus */ 121 #define PCI_BRIDGE_RESOURCE_NUM 4 122 123 /* Resources assigned to buses behind the bridge */ 124 PCI_BRIDGE_RESOURCES, 125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 126 PCI_BRIDGE_RESOURCE_NUM - 1, 127 128 /* Total resources associated with a PCI device */ 129 PCI_NUM_RESOURCES, 130 131 /* Preserve this for compatibility */ 132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 133 }; 134 135 /** 136 * enum pci_interrupt_pin - PCI INTx interrupt values 137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 138 * @PCI_INTERRUPT_INTA: PCI INTA pin 139 * @PCI_INTERRUPT_INTB: PCI INTB pin 140 * @PCI_INTERRUPT_INTC: PCI INTC pin 141 * @PCI_INTERRUPT_INTD: PCI INTD pin 142 * 143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 144 * PCI_INTERRUPT_PIN register. 145 */ 146 enum pci_interrupt_pin { 147 PCI_INTERRUPT_UNKNOWN, 148 PCI_INTERRUPT_INTA, 149 PCI_INTERRUPT_INTB, 150 PCI_INTERRUPT_INTC, 151 PCI_INTERRUPT_INTD, 152 }; 153 154 /* The number of legacy PCI INTx interrupts */ 155 #define PCI_NUM_INTX 4 156 157 /* 158 * Reading from a device that doesn't respond typically returns ~0. A 159 * successful read from a device may also return ~0, so you need additional 160 * information to reliably identify errors. 161 */ 162 #define PCI_ERROR_RESPONSE (~0ULL) 163 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 164 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 165 166 /* 167 * pci_power_t values must match the bits in the Capabilities PME_Support 168 * and Control/Status PowerState fields in the Power Management capability. 169 */ 170 typedef int __bitwise pci_power_t; 171 172 #define PCI_D0 ((pci_power_t __force) 0) 173 #define PCI_D1 ((pci_power_t __force) 1) 174 #define PCI_D2 ((pci_power_t __force) 2) 175 #define PCI_D3hot ((pci_power_t __force) 3) 176 #define PCI_D3cold ((pci_power_t __force) 4) 177 #define PCI_UNKNOWN ((pci_power_t __force) 5) 178 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 179 180 /* Remember to update this when the list above changes! */ 181 extern const char *pci_power_names[]; 182 183 static inline const char *pci_power_name(pci_power_t state) 184 { 185 return pci_power_names[1 + (__force int) state]; 186 } 187 188 /** 189 * typedef pci_channel_state_t 190 * 191 * The pci_channel state describes connectivity between the CPU and 192 * the PCI device. If some PCI bus between here and the PCI device 193 * has crashed or locked up, this info is reflected here. 194 */ 195 typedef unsigned int __bitwise pci_channel_state_t; 196 197 enum { 198 /* I/O channel is in normal state */ 199 pci_channel_io_normal = (__force pci_channel_state_t) 1, 200 201 /* I/O to channel is blocked */ 202 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 203 204 /* PCI card is dead */ 205 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 206 }; 207 208 typedef unsigned int __bitwise pcie_reset_state_t; 209 210 enum pcie_reset_state { 211 /* Reset is NOT asserted (Use to deassert reset) */ 212 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 213 214 /* Use #PERST to reset PCIe device */ 215 pcie_warm_reset = (__force pcie_reset_state_t) 2, 216 217 /* Use PCIe Hot Reset to reset device */ 218 pcie_hot_reset = (__force pcie_reset_state_t) 3 219 }; 220 221 typedef unsigned short __bitwise pci_dev_flags_t; 222 enum pci_dev_flags { 223 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 224 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 225 /* Device configuration is irrevocably lost if disabled into D3 */ 226 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 227 /* Provide indication device is assigned by a Virtual Machine Manager */ 228 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 229 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 230 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 231 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 232 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 233 /* Do not use bus resets for device */ 234 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 235 /* Do not use PM reset even if device advertises NoSoftRst- */ 236 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 237 /* Get VPD from function 0 VPD */ 238 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 239 /* A non-root bridge where translation occurs, stop alias search here */ 240 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 241 /* Do not use FLR even if device advertises PCI_AF_CAP */ 242 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 243 /* Don't use Relaxed Ordering for TLPs directed at this device */ 244 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 245 /* Device does honor MSI masking despite saying otherwise */ 246 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 247 }; 248 249 enum pci_irq_reroute_variant { 250 INTEL_IRQ_REROUTE_VARIANT = 1, 251 MAX_IRQ_REROUTE_VARIANTS = 3 252 }; 253 254 typedef unsigned short __bitwise pci_bus_flags_t; 255 enum pci_bus_flags { 256 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 257 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 258 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 259 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 260 }; 261 262 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 263 enum pcie_link_width { 264 PCIE_LNK_WIDTH_RESRV = 0x00, 265 PCIE_LNK_X1 = 0x01, 266 PCIE_LNK_X2 = 0x02, 267 PCIE_LNK_X4 = 0x04, 268 PCIE_LNK_X8 = 0x08, 269 PCIE_LNK_X12 = 0x0c, 270 PCIE_LNK_X16 = 0x10, 271 PCIE_LNK_X32 = 0x20, 272 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 273 }; 274 275 /* See matching string table in pci_speed_string() */ 276 enum pci_bus_speed { 277 PCI_SPEED_33MHz = 0x00, 278 PCI_SPEED_66MHz = 0x01, 279 PCI_SPEED_66MHz_PCIX = 0x02, 280 PCI_SPEED_100MHz_PCIX = 0x03, 281 PCI_SPEED_133MHz_PCIX = 0x04, 282 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 283 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 284 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 285 PCI_SPEED_66MHz_PCIX_266 = 0x09, 286 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 287 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 288 AGP_UNKNOWN = 0x0c, 289 AGP_1X = 0x0d, 290 AGP_2X = 0x0e, 291 AGP_4X = 0x0f, 292 AGP_8X = 0x10, 293 PCI_SPEED_66MHz_PCIX_533 = 0x11, 294 PCI_SPEED_100MHz_PCIX_533 = 0x12, 295 PCI_SPEED_133MHz_PCIX_533 = 0x13, 296 PCIE_SPEED_2_5GT = 0x14, 297 PCIE_SPEED_5_0GT = 0x15, 298 PCIE_SPEED_8_0GT = 0x16, 299 PCIE_SPEED_16_0GT = 0x17, 300 PCIE_SPEED_32_0GT = 0x18, 301 PCIE_SPEED_64_0GT = 0x19, 302 PCI_SPEED_UNKNOWN = 0xff, 303 }; 304 305 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 306 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 307 308 struct pci_vpd { 309 struct mutex lock; 310 unsigned int len; 311 u8 cap; 312 }; 313 314 struct irq_affinity; 315 struct pcie_link_state; 316 struct pci_sriov; 317 struct pci_p2pdma; 318 struct rcec_ea; 319 320 /* The pci_dev structure describes PCI devices */ 321 struct pci_dev { 322 struct list_head bus_list; /* Node in per-bus list */ 323 struct pci_bus *bus; /* Bus this device is on */ 324 struct pci_bus *subordinate; /* Bus this device bridges to */ 325 326 void *sysdata; /* Hook for sys-specific extension */ 327 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 328 struct pci_slot *slot; /* Physical slot this device is in */ 329 330 unsigned int devfn; /* Encoded device & function index */ 331 unsigned short vendor; 332 unsigned short device; 333 unsigned short subsystem_vendor; 334 unsigned short subsystem_device; 335 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 336 u8 revision; /* PCI revision, low byte of class word */ 337 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 338 #ifdef CONFIG_PCIEAER 339 u16 aer_cap; /* AER capability offset */ 340 struct aer_stats *aer_stats; /* AER stats for this device */ 341 #endif 342 #ifdef CONFIG_PCIEPORTBUS 343 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 344 struct pci_dev *rcec; /* Associated RCEC device */ 345 #endif 346 u32 devcap; /* PCIe Device Capabilities */ 347 u8 pcie_cap; /* PCIe capability offset */ 348 u8 msi_cap; /* MSI capability offset */ 349 u8 msix_cap; /* MSI-X capability offset */ 350 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 351 u8 rom_base_reg; /* Config register controlling ROM */ 352 u8 pin; /* Interrupt pin this device uses */ 353 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 354 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 355 356 struct pci_driver *driver; /* Driver bound to this device */ 357 u64 dma_mask; /* Mask of the bits of bus address this 358 device implements. Normally this is 359 0xffffffff. You only need to change 360 this if your device has broken DMA 361 or supports 64-bit transfers. */ 362 363 struct device_dma_parameters dma_parms; 364 365 pci_power_t current_state; /* Current operating state. In ACPI, 366 this is D0-D3, D0 being fully 367 functional, and D3 being off. */ 368 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 369 u8 pm_cap; /* PM capability offset */ 370 unsigned int pme_support:5; /* Bitmask of states from which PME# 371 can be generated */ 372 unsigned int pme_poll:1; /* Poll device's PME status bit */ 373 unsigned int d1_support:1; /* Low power state D1 is supported */ 374 unsigned int d2_support:1; /* Low power state D2 is supported */ 375 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 376 unsigned int no_d3cold:1; /* D3cold is forbidden */ 377 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 378 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 379 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 380 decoding during BAR sizing */ 381 unsigned int wakeup_prepared:1; 382 unsigned int runtime_d3cold:1; /* Whether go through runtime 383 D3cold, not set for devices 384 powered on/off by the 385 corresponding bridge */ 386 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 387 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 388 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 389 controlled exclusively by 390 user sysfs */ 391 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 392 bit manually */ 393 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 394 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 395 396 #ifdef CONFIG_PCIEASPM 397 struct pcie_link_state *link_state; /* ASPM link state */ 398 unsigned int ltr_path:1; /* Latency Tolerance Reporting 399 supported from root to here */ 400 u16 l1ss; /* L1SS Capability pointer */ 401 #endif 402 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 403 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ 404 405 pci_channel_state_t error_state; /* Current connectivity state */ 406 struct device dev; /* Generic device interface */ 407 408 int cfg_size; /* Size of config space */ 409 410 /* 411 * Instead of touching interrupt line and base address registers 412 * directly, use the values stored here. They might be different! 413 */ 414 unsigned int irq; 415 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 416 417 bool match_driver; /* Skip attaching driver */ 418 419 unsigned int transparent:1; /* Subtractive decode bridge */ 420 unsigned int io_window:1; /* Bridge has I/O window */ 421 unsigned int pref_window:1; /* Bridge has pref mem window */ 422 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 423 unsigned int multifunction:1; /* Multi-function device */ 424 425 unsigned int is_busmaster:1; /* Is busmaster */ 426 unsigned int no_msi:1; /* May not use MSI */ 427 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ 428 unsigned int block_cfg_access:1; /* Config space access blocked */ 429 unsigned int broken_parity_status:1; /* Generates false positive parity */ 430 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 431 unsigned int msi_enabled:1; 432 unsigned int msix_enabled:1; 433 unsigned int ari_enabled:1; /* ARI forwarding */ 434 unsigned int ats_enabled:1; /* Address Translation Svc */ 435 unsigned int pasid_enabled:1; /* Process Address Space ID */ 436 unsigned int pri_enabled:1; /* Page Request Interface */ 437 unsigned int is_managed:1; /* Managed via devres */ 438 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 439 unsigned int needs_freset:1; /* Requires fundamental reset */ 440 unsigned int state_saved:1; 441 unsigned int is_physfn:1; 442 unsigned int is_virtfn:1; 443 unsigned int is_hotplug_bridge:1; 444 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 445 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 446 /* 447 * Devices marked being untrusted are the ones that can potentially 448 * execute DMA attacks and similar. They are typically connected 449 * through external ports such as Thunderbolt but not limited to 450 * that. When an IOMMU is enabled they should be getting full 451 * mappings to make sure they cannot access arbitrary memory. 452 */ 453 unsigned int untrusted:1; 454 /* 455 * Info from the platform, e.g., ACPI or device tree, may mark a 456 * device as "external-facing". An external-facing device is 457 * itself internal but devices downstream from it are external. 458 */ 459 unsigned int external_facing:1; 460 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 461 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 462 unsigned int irq_managed:1; 463 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 464 unsigned int is_probed:1; /* Device probing in progress */ 465 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 466 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 467 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 468 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 469 pci_dev_flags_t dev_flags; 470 atomic_t enable_cnt; /* pci_enable_device has been called */ 471 472 u32 saved_config_space[16]; /* Config space saved at suspend time */ 473 struct hlist_head saved_cap_space; 474 int rom_attr_enabled; /* Display of ROM attribute enabled? */ 475 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 476 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 477 478 #ifdef CONFIG_HOTPLUG_PCI_PCIE 479 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 480 #endif 481 #ifdef CONFIG_PCIE_PTM 482 unsigned int ptm_root:1; 483 unsigned int ptm_enabled:1; 484 u8 ptm_granularity; 485 #endif 486 #ifdef CONFIG_PCI_MSI 487 void __iomem *msix_base; 488 raw_spinlock_t msi_lock; 489 #endif 490 struct pci_vpd vpd; 491 #ifdef CONFIG_PCIE_DPC 492 u16 dpc_cap; 493 unsigned int dpc_rp_extensions:1; 494 u8 dpc_rp_log_size; 495 #endif 496 #ifdef CONFIG_PCI_ATS 497 union { 498 struct pci_sriov *sriov; /* PF: SR-IOV info */ 499 struct pci_dev *physfn; /* VF: related PF */ 500 }; 501 u16 ats_cap; /* ATS Capability offset */ 502 u8 ats_stu; /* ATS Smallest Translation Unit */ 503 #endif 504 #ifdef CONFIG_PCI_PRI 505 u16 pri_cap; /* PRI Capability offset */ 506 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 507 unsigned int pasid_required:1; /* PRG Response PASID Required */ 508 #endif 509 #ifdef CONFIG_PCI_PASID 510 u16 pasid_cap; /* PASID Capability offset */ 511 u16 pasid_features; 512 #endif 513 #ifdef CONFIG_PCI_P2PDMA 514 struct pci_p2pdma __rcu *p2pdma; 515 #endif 516 u16 acs_cap; /* ACS Capability offset */ 517 phys_addr_t rom; /* Physical address if not from BAR */ 518 size_t romlen; /* Length if not from BAR */ 519 char *driver_override; /* Driver name to force a match */ 520 521 unsigned long priv_flags; /* Private flags for the PCI driver */ 522 523 /* These methods index pci_reset_fn_methods[] */ 524 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 525 }; 526 527 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 528 { 529 #ifdef CONFIG_PCI_IOV 530 if (dev->is_virtfn) 531 dev = dev->physfn; 532 #endif 533 return dev; 534 } 535 536 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 537 538 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 539 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 540 541 static inline int pci_channel_offline(struct pci_dev *pdev) 542 { 543 return (pdev->error_state != pci_channel_io_normal); 544 } 545 546 /* 547 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 548 * Group number is limited to a 16-bit value, therefore (int)-1 is 549 * not a valid PCI domain number, and can be used as a sentinel 550 * value indicating ->domain_nr is not set by the driver (and 551 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 552 * pci_bus_find_domain_nr()). 553 */ 554 #define PCI_DOMAIN_NR_NOT_SET (-1) 555 556 struct pci_host_bridge { 557 struct device dev; 558 struct pci_bus *bus; /* Root bus */ 559 struct pci_ops *ops; 560 struct pci_ops *child_ops; 561 void *sysdata; 562 int busnr; 563 int domain_nr; 564 struct list_head windows; /* resource_entry */ 565 struct list_head dma_ranges; /* dma ranges resource list */ 566 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 567 int (*map_irq)(const struct pci_dev *, u8, u8); 568 void (*release_fn)(struct pci_host_bridge *); 569 void *release_data; 570 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 571 unsigned int no_ext_tags:1; /* No Extended Tags */ 572 unsigned int native_aer:1; /* OS may use PCIe AER */ 573 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 574 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 575 unsigned int native_pme:1; /* OS may use PCIe PME */ 576 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 577 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 578 unsigned int preserve_config:1; /* Preserve FW resource setup */ 579 unsigned int size_windows:1; /* Enable root bus sizing */ 580 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 581 582 /* Resource alignment requirements */ 583 resource_size_t (*align_resource)(struct pci_dev *dev, 584 const struct resource *res, 585 resource_size_t start, 586 resource_size_t size, 587 resource_size_t align); 588 unsigned long private[] ____cacheline_aligned; 589 }; 590 591 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 592 593 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 594 { 595 return (void *)bridge->private; 596 } 597 598 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 599 { 600 return container_of(priv, struct pci_host_bridge, private); 601 } 602 603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 604 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 605 size_t priv); 606 void pci_free_host_bridge(struct pci_host_bridge *bridge); 607 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 608 609 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 610 void (*release_fn)(struct pci_host_bridge *), 611 void *release_data); 612 613 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 614 615 /* 616 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond 617 * to P2P or CardBus bridge windows) go in a table. Additional ones (for 618 * buses below host bridges or subtractive decode bridges) go in the list. 619 * Use pci_bus_for_each_resource() to iterate through all the resources. 620 */ 621 622 /* 623 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly 624 * and there's no way to program the bridge with the details of the window. 625 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- 626 * decode bit set, because they are explicit and can be programmed with _SRS. 627 */ 628 #define PCI_SUBTRACTIVE_DECODE 0x1 629 630 struct pci_bus_resource { 631 struct list_head list; 632 struct resource *res; 633 unsigned int flags; 634 }; 635 636 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 637 638 struct pci_bus { 639 struct list_head node; /* Node in list of buses */ 640 struct pci_bus *parent; /* Parent bus this bridge is on */ 641 struct list_head children; /* List of child buses */ 642 struct list_head devices; /* List of devices on this bus */ 643 struct pci_dev *self; /* Bridge device as seen by parent */ 644 struct list_head slots; /* List of slots on this bus; 645 protected by pci_slot_mutex */ 646 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 647 struct list_head resources; /* Address space routed to this bus */ 648 struct resource busn_res; /* Bus numbers routed to this bus */ 649 650 struct pci_ops *ops; /* Configuration access functions */ 651 void *sysdata; /* Hook for sys-specific extension */ 652 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 653 654 unsigned char number; /* Bus number */ 655 unsigned char primary; /* Number of primary bridge */ 656 unsigned char max_bus_speed; /* enum pci_bus_speed */ 657 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 658 #ifdef CONFIG_PCI_DOMAINS_GENERIC 659 int domain_nr; 660 #endif 661 662 char name[48]; 663 664 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 665 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 666 struct device *bridge; 667 struct device dev; 668 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ 669 struct bin_attribute *legacy_mem; /* Legacy mem */ 670 unsigned int is_added:1; 671 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 672 }; 673 674 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 675 676 static inline u16 pci_dev_id(struct pci_dev *dev) 677 { 678 return PCI_DEVID(dev->bus->number, dev->devfn); 679 } 680 681 /* 682 * Returns true if the PCI bus is root (behind host-PCI bridge), 683 * false otherwise 684 * 685 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 686 * This is incorrect because "virtual" buses added for SR-IOV (via 687 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 688 */ 689 static inline bool pci_is_root_bus(struct pci_bus *pbus) 690 { 691 return !(pbus->parent); 692 } 693 694 /** 695 * pci_is_bridge - check if the PCI device is a bridge 696 * @dev: PCI device 697 * 698 * Return true if the PCI device is bridge whether it has subordinate 699 * or not. 700 */ 701 static inline bool pci_is_bridge(struct pci_dev *dev) 702 { 703 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 704 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 705 } 706 707 #define for_each_pci_bridge(dev, bus) \ 708 list_for_each_entry(dev, &bus->devices, bus_list) \ 709 if (!pci_is_bridge(dev)) {} else 710 711 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 712 { 713 dev = pci_physfn(dev); 714 if (pci_is_root_bus(dev->bus)) 715 return NULL; 716 717 return dev->bus->self; 718 } 719 720 #ifdef CONFIG_PCI_MSI 721 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 722 { 723 return pci_dev->msi_enabled || pci_dev->msix_enabled; 724 } 725 #else 726 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 727 #endif 728 729 /* Error values that may be returned by PCI functions */ 730 #define PCIBIOS_SUCCESSFUL 0x00 731 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 732 #define PCIBIOS_BAD_VENDOR_ID 0x83 733 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 734 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 735 #define PCIBIOS_SET_FAILED 0x88 736 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 737 738 /* Translate above to generic errno for passing back through non-PCI code */ 739 static inline int pcibios_err_to_errno(int err) 740 { 741 if (err <= PCIBIOS_SUCCESSFUL) 742 return err; /* Assume already errno */ 743 744 switch (err) { 745 case PCIBIOS_FUNC_NOT_SUPPORTED: 746 return -ENOENT; 747 case PCIBIOS_BAD_VENDOR_ID: 748 return -ENOTTY; 749 case PCIBIOS_DEVICE_NOT_FOUND: 750 return -ENODEV; 751 case PCIBIOS_BAD_REGISTER_NUMBER: 752 return -EFAULT; 753 case PCIBIOS_SET_FAILED: 754 return -EIO; 755 case PCIBIOS_BUFFER_TOO_SMALL: 756 return -ENOSPC; 757 } 758 759 return -ERANGE; 760 } 761 762 /* Low-level architecture-dependent routines */ 763 764 struct pci_ops { 765 int (*add_bus)(struct pci_bus *bus); 766 void (*remove_bus)(struct pci_bus *bus); 767 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 768 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 769 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 770 }; 771 772 /* 773 * ACPI needs to be able to access PCI config space before we've done a 774 * PCI bus scan and created pci_bus structures. 775 */ 776 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 777 int reg, int len, u32 *val); 778 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 779 int reg, int len, u32 val); 780 781 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 782 typedef u64 pci_bus_addr_t; 783 #else 784 typedef u32 pci_bus_addr_t; 785 #endif 786 787 struct pci_bus_region { 788 pci_bus_addr_t start; 789 pci_bus_addr_t end; 790 }; 791 792 struct pci_dynids { 793 spinlock_t lock; /* Protects list, index */ 794 struct list_head list; /* For IDs added at runtime */ 795 }; 796 797 798 /* 799 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 800 * a set of callbacks in struct pci_error_handlers, that device driver 801 * will be notified of PCI bus errors, and will be driven to recovery 802 * when an error occurs. 803 */ 804 805 typedef unsigned int __bitwise pci_ers_result_t; 806 807 enum pci_ers_result { 808 /* No result/none/not supported in device driver */ 809 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 810 811 /* Device driver can recover without slot reset */ 812 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 813 814 /* Device driver wants slot to be reset */ 815 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 816 817 /* Device has completely failed, is unrecoverable */ 818 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 819 820 /* Device driver is fully recovered and operational */ 821 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 822 823 /* No AER capabilities registered for the driver */ 824 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 825 }; 826 827 /* PCI bus error event callbacks */ 828 struct pci_error_handlers { 829 /* PCI bus error detected on this device */ 830 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 831 pci_channel_state_t error); 832 833 /* MMIO has been re-enabled, but not DMA */ 834 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 835 836 /* PCI slot has been reset */ 837 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 838 839 /* PCI function reset prepare or completed */ 840 void (*reset_prepare)(struct pci_dev *dev); 841 void (*reset_done)(struct pci_dev *dev); 842 843 /* Device driver may resume normal operations */ 844 void (*resume)(struct pci_dev *dev); 845 }; 846 847 848 struct module; 849 850 /** 851 * struct pci_driver - PCI driver structure 852 * @node: List of driver structures. 853 * @name: Driver name. 854 * @id_table: Pointer to table of device IDs the driver is 855 * interested in. Most drivers should export this 856 * table using MODULE_DEVICE_TABLE(pci,...). 857 * @probe: This probing function gets called (during execution 858 * of pci_register_driver() for already existing 859 * devices or later if a new device gets inserted) for 860 * all PCI devices which match the ID table and are not 861 * "owned" by the other drivers yet. This function gets 862 * passed a "struct pci_dev \*" for each device whose 863 * entry in the ID table matches the device. The probe 864 * function returns zero when the driver chooses to 865 * take "ownership" of the device or an error code 866 * (negative number) otherwise. 867 * The probe function always gets called from process 868 * context, so it can sleep. 869 * @remove: The remove() function gets called whenever a device 870 * being handled by this driver is removed (either during 871 * deregistration of the driver or when it's manually 872 * pulled out of a hot-pluggable slot). 873 * The remove function always gets called from process 874 * context, so it can sleep. 875 * @suspend: Put device into low power state. 876 * @resume: Wake device from low power state. 877 * (Please see Documentation/power/pci.rst for descriptions 878 * of PCI Power Management and the related functions.) 879 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 880 * Intended to stop any idling DMA operations. 881 * Useful for enabling wake-on-lan (NIC) or changing 882 * the power state of a device before reboot. 883 * e.g. drivers/net/e100.c. 884 * @sriov_configure: Optional driver callback to allow configuration of 885 * number of VFs to enable via sysfs "sriov_numvfs" file. 886 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 887 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 888 * This will change MSI-X Table Size in the VF Message Control 889 * registers. 890 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 891 * MSI-X vectors available for distribution to the VFs. 892 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 893 * @groups: Sysfs attribute groups. 894 * @dev_groups: Attributes attached to the device that will be 895 * created once it is bound to the driver. 896 * @driver: Driver model structure. 897 * @dynids: List of dynamically added device IDs. 898 */ 899 struct pci_driver { 900 struct list_head node; 901 const char *name; 902 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 903 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 904 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 905 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 906 int (*resume)(struct pci_dev *dev); /* Device woken up */ 907 void (*shutdown)(struct pci_dev *dev); 908 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 909 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 910 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 911 const struct pci_error_handlers *err_handler; 912 const struct attribute_group **groups; 913 const struct attribute_group **dev_groups; 914 struct device_driver driver; 915 struct pci_dynids dynids; 916 }; 917 918 static inline struct pci_driver *to_pci_driver(struct device_driver *drv) 919 { 920 return drv ? container_of(drv, struct pci_driver, driver) : NULL; 921 } 922 923 /** 924 * PCI_DEVICE - macro used to describe a specific PCI device 925 * @vend: the 16 bit PCI Vendor ID 926 * @dev: the 16 bit PCI Device ID 927 * 928 * This macro is used to create a struct pci_device_id that matches a 929 * specific device. The subvendor and subdevice fields will be set to 930 * PCI_ANY_ID. 931 */ 932 #define PCI_DEVICE(vend,dev) \ 933 .vendor = (vend), .device = (dev), \ 934 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 935 936 /** 937 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 938 * override_only flags. 939 * @vend: the 16 bit PCI Vendor ID 940 * @dev: the 16 bit PCI Device ID 941 * @driver_override: the 32 bit PCI Device override_only 942 * 943 * This macro is used to create a struct pci_device_id that matches only a 944 * driver_override device. The subvendor and subdevice fields will be set to 945 * PCI_ANY_ID. 946 */ 947 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 948 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 949 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 950 951 /** 952 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 953 * "driver_override" PCI device. 954 * @vend: the 16 bit PCI Vendor ID 955 * @dev: the 16 bit PCI Device ID 956 * 957 * This macro is used to create a struct pci_device_id that matches a 958 * specific device. The subvendor and subdevice fields will be set to 959 * PCI_ANY_ID and the driver_override will be set to 960 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 961 */ 962 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 963 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 964 965 /** 966 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 967 * @vend: the 16 bit PCI Vendor ID 968 * @dev: the 16 bit PCI Device ID 969 * @subvend: the 16 bit PCI Subvendor ID 970 * @subdev: the 16 bit PCI Subdevice ID 971 * 972 * This macro is used to create a struct pci_device_id that matches a 973 * specific device with subsystem information. 974 */ 975 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 976 .vendor = (vend), .device = (dev), \ 977 .subvendor = (subvend), .subdevice = (subdev) 978 979 /** 980 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 981 * @dev_class: the class, subclass, prog-if triple for this device 982 * @dev_class_mask: the class mask for this device 983 * 984 * This macro is used to create a struct pci_device_id that matches a 985 * specific PCI class. The vendor, device, subvendor, and subdevice 986 * fields will be set to PCI_ANY_ID. 987 */ 988 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 989 .class = (dev_class), .class_mask = (dev_class_mask), \ 990 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 991 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 992 993 /** 994 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 995 * @vend: the vendor name 996 * @dev: the 16 bit PCI Device ID 997 * 998 * This macro is used to create a struct pci_device_id that matches a 999 * specific PCI device. The subvendor, and subdevice fields will be set 1000 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1001 * private data. 1002 */ 1003 #define PCI_VDEVICE(vend, dev) \ 1004 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1005 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1006 1007 /** 1008 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1009 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1010 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1011 * @data: the driver data to be filled 1012 * 1013 * This macro is used to create a struct pci_device_id that matches a 1014 * specific PCI device. The subvendor, and subdevice fields will be set 1015 * to PCI_ANY_ID. 1016 */ 1017 #define PCI_DEVICE_DATA(vend, dev, data) \ 1018 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1019 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1020 .driver_data = (kernel_ulong_t)(data) 1021 1022 enum { 1023 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1024 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1025 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1026 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1027 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1028 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1029 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1030 }; 1031 1032 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ 1033 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1034 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1035 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1036 1037 /* These external functions are only available when PCI support is enabled */ 1038 #ifdef CONFIG_PCI 1039 1040 extern unsigned int pci_flags; 1041 1042 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1043 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1044 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1045 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1046 1047 void pcie_bus_configure_settings(struct pci_bus *bus); 1048 1049 enum pcie_bus_config_types { 1050 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1051 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1052 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1053 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1054 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1055 }; 1056 1057 extern enum pcie_bus_config_types pcie_bus_config; 1058 1059 extern struct bus_type pci_bus_type; 1060 1061 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1062 * code, or PCI core code. */ 1063 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1064 /* Some device drivers need know if PCI is initiated */ 1065 int no_pci_devices(void); 1066 1067 void pcibios_resource_survey_bus(struct pci_bus *bus); 1068 void pcibios_bus_add_device(struct pci_dev *pdev); 1069 void pcibios_add_bus(struct pci_bus *bus); 1070 void pcibios_remove_bus(struct pci_bus *bus); 1071 void pcibios_fixup_bus(struct pci_bus *); 1072 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1073 /* Architecture-specific versions may override this (weak) */ 1074 char *pcibios_setup(char *str); 1075 1076 /* Used only when drivers/pci/setup.c is used */ 1077 resource_size_t pcibios_align_resource(void *, const struct resource *, 1078 resource_size_t, 1079 resource_size_t); 1080 1081 /* Weak but can be overridden by arch */ 1082 void pci_fixup_cardbus(struct pci_bus *); 1083 1084 /* Generic PCI functions used internally */ 1085 1086 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1087 struct resource *res); 1088 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1089 struct pci_bus_region *region); 1090 void pcibios_scan_specific_bus(int busn); 1091 struct pci_bus *pci_find_bus(int domain, int busnr); 1092 void pci_bus_add_devices(const struct pci_bus *bus); 1093 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1094 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1095 struct pci_ops *ops, void *sysdata, 1096 struct list_head *resources); 1097 int pci_host_probe(struct pci_host_bridge *bridge); 1098 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1099 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1100 void pci_bus_release_busn_res(struct pci_bus *b); 1101 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1102 struct pci_ops *ops, void *sysdata, 1103 struct list_head *resources); 1104 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1105 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1106 int busnr); 1107 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1108 const char *name, 1109 struct hotplug_slot *hotplug); 1110 void pci_destroy_slot(struct pci_slot *slot); 1111 #ifdef CONFIG_SYSFS 1112 void pci_dev_assign_slot(struct pci_dev *dev); 1113 #else 1114 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1115 #endif 1116 int pci_scan_slot(struct pci_bus *bus, int devfn); 1117 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1118 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1119 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1120 void pci_bus_add_device(struct pci_dev *dev); 1121 void pci_read_bridge_bases(struct pci_bus *child); 1122 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1123 struct resource *res); 1124 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1125 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1126 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1127 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1128 void pci_dev_put(struct pci_dev *dev); 1129 void pci_remove_bus(struct pci_bus *b); 1130 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1131 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1132 void pci_stop_root_bus(struct pci_bus *bus); 1133 void pci_remove_root_bus(struct pci_bus *bus); 1134 void pci_setup_cardbus(struct pci_bus *bus); 1135 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1136 void pci_sort_breadthfirst(void); 1137 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1138 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1139 1140 /* Generic PCI functions exported to card drivers */ 1141 1142 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1143 u8 pci_find_capability(struct pci_dev *dev, int cap); 1144 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1145 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1146 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1147 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1148 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1149 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1150 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1151 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1152 1153 u64 pci_get_dsn(struct pci_dev *dev); 1154 1155 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1156 struct pci_dev *from); 1157 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1158 unsigned int ss_vendor, unsigned int ss_device, 1159 struct pci_dev *from); 1160 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1161 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1162 unsigned int devfn); 1163 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1164 int pci_dev_present(const struct pci_device_id *ids); 1165 1166 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1167 int where, u8 *val); 1168 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1169 int where, u16 *val); 1170 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1171 int where, u32 *val); 1172 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1173 int where, u8 val); 1174 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1175 int where, u16 val); 1176 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1177 int where, u32 val); 1178 1179 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1180 int where, int size, u32 *val); 1181 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1182 int where, int size, u32 val); 1183 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1184 int where, int size, u32 *val); 1185 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1186 int where, int size, u32 val); 1187 1188 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1189 1190 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1191 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1192 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1193 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1194 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1195 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1196 1197 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1198 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1199 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1200 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1201 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, 1202 u16 clear, u16 set); 1203 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1204 u32 clear, u32 set); 1205 1206 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1207 u16 set) 1208 { 1209 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1210 } 1211 1212 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1213 u32 set) 1214 { 1215 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1216 } 1217 1218 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1219 u16 clear) 1220 { 1221 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1222 } 1223 1224 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1225 u32 clear) 1226 { 1227 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1228 } 1229 1230 /* User-space driven config access */ 1231 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1232 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1233 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1234 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1235 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1236 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1237 1238 int __must_check pci_enable_device(struct pci_dev *dev); 1239 int __must_check pci_enable_device_io(struct pci_dev *dev); 1240 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1241 int __must_check pci_reenable_device(struct pci_dev *); 1242 int __must_check pcim_enable_device(struct pci_dev *pdev); 1243 void pcim_pin_device(struct pci_dev *pdev); 1244 1245 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1246 { 1247 /* 1248 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1249 * writable and no quirk has marked the feature broken. 1250 */ 1251 return !pdev->broken_intx_masking; 1252 } 1253 1254 static inline int pci_is_enabled(struct pci_dev *pdev) 1255 { 1256 return (atomic_read(&pdev->enable_cnt) > 0); 1257 } 1258 1259 static inline int pci_is_managed(struct pci_dev *pdev) 1260 { 1261 return pdev->is_managed; 1262 } 1263 1264 void pci_disable_device(struct pci_dev *dev); 1265 1266 extern unsigned int pcibios_max_latency; 1267 void pci_set_master(struct pci_dev *dev); 1268 void pci_clear_master(struct pci_dev *dev); 1269 1270 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1271 int pci_set_cacheline_size(struct pci_dev *dev); 1272 int __must_check pci_set_mwi(struct pci_dev *dev); 1273 int __must_check pcim_set_mwi(struct pci_dev *dev); 1274 int pci_try_set_mwi(struct pci_dev *dev); 1275 void pci_clear_mwi(struct pci_dev *dev); 1276 void pci_disable_parity(struct pci_dev *dev); 1277 void pci_intx(struct pci_dev *dev, int enable); 1278 bool pci_check_and_mask_intx(struct pci_dev *dev); 1279 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1280 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1281 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1282 int pcix_get_max_mmrbc(struct pci_dev *dev); 1283 int pcix_get_mmrbc(struct pci_dev *dev); 1284 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1285 int pcie_get_readrq(struct pci_dev *dev); 1286 int pcie_set_readrq(struct pci_dev *dev, int rq); 1287 int pcie_get_mps(struct pci_dev *dev); 1288 int pcie_set_mps(struct pci_dev *dev, int mps); 1289 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1290 enum pci_bus_speed *speed, 1291 enum pcie_link_width *width); 1292 void pcie_print_link_status(struct pci_dev *dev); 1293 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1294 int pcie_flr(struct pci_dev *dev); 1295 int __pci_reset_function_locked(struct pci_dev *dev); 1296 int pci_reset_function(struct pci_dev *dev); 1297 int pci_reset_function_locked(struct pci_dev *dev); 1298 int pci_try_reset_function(struct pci_dev *dev); 1299 int pci_probe_reset_slot(struct pci_slot *slot); 1300 int pci_probe_reset_bus(struct pci_bus *bus); 1301 int pci_reset_bus(struct pci_dev *dev); 1302 void pci_reset_secondary_bus(struct pci_dev *dev); 1303 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1304 void pci_update_resource(struct pci_dev *dev, int resno); 1305 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1306 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 1307 void pci_release_resource(struct pci_dev *dev, int resno); 1308 static inline int pci_rebar_bytes_to_size(u64 bytes) 1309 { 1310 bytes = roundup_pow_of_two(bytes); 1311 1312 /* Return BAR size as defined in the resizable BAR specification */ 1313 return max(ilog2(bytes), 20) - 20; 1314 } 1315 1316 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1317 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); 1318 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1319 bool pci_device_is_present(struct pci_dev *pdev); 1320 void pci_ignore_hotplug(struct pci_dev *dev); 1321 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1322 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1323 1324 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1325 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1326 const char *fmt, ...); 1327 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1328 1329 /* ROM control related routines */ 1330 int pci_enable_rom(struct pci_dev *pdev); 1331 void pci_disable_rom(struct pci_dev *pdev); 1332 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1333 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1334 1335 /* Power management related routines */ 1336 int pci_save_state(struct pci_dev *dev); 1337 void pci_restore_state(struct pci_dev *dev); 1338 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1339 int pci_load_saved_state(struct pci_dev *dev, 1340 struct pci_saved_state *state); 1341 int pci_load_and_free_saved_state(struct pci_dev *dev, 1342 struct pci_saved_state **state); 1343 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1344 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1345 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1346 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1347 void pci_pme_active(struct pci_dev *dev, bool enable); 1348 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1349 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1350 int pci_prepare_to_sleep(struct pci_dev *dev); 1351 int pci_back_from_sleep(struct pci_dev *dev); 1352 bool pci_dev_run_wake(struct pci_dev *dev); 1353 void pci_d3cold_enable(struct pci_dev *dev); 1354 void pci_d3cold_disable(struct pci_dev *dev); 1355 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1356 void pci_resume_bus(struct pci_bus *bus); 1357 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1358 1359 /* For use by arch with custom probe code */ 1360 void set_pcie_port_type(struct pci_dev *pdev); 1361 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1362 1363 /* Functions for PCI Hotplug drivers to use */ 1364 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 1365 unsigned int pci_rescan_bus(struct pci_bus *bus); 1366 void pci_lock_rescan_remove(void); 1367 void pci_unlock_rescan_remove(void); 1368 1369 /* Vital Product Data routines */ 1370 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1371 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1372 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1373 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1374 1375 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1376 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1377 void pci_bus_assign_resources(const struct pci_bus *bus); 1378 void pci_bus_claim_resources(struct pci_bus *bus); 1379 void pci_bus_size_bridges(struct pci_bus *bus); 1380 int pci_claim_resource(struct pci_dev *, int); 1381 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1382 void pci_assign_unassigned_resources(void); 1383 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1384 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1385 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1386 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); 1387 void pdev_enable_device(struct pci_dev *); 1388 int pci_enable_resources(struct pci_dev *, int mask); 1389 void pci_assign_irq(struct pci_dev *dev); 1390 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1391 #define HAVE_PCI_REQ_REGIONS 2 1392 int __must_check pci_request_regions(struct pci_dev *, const char *); 1393 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1394 void pci_release_regions(struct pci_dev *); 1395 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1396 void pci_release_region(struct pci_dev *, int); 1397 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1398 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1399 void pci_release_selected_regions(struct pci_dev *, int); 1400 1401 /* drivers/pci/bus.c */ 1402 void pci_add_resource(struct list_head *resources, struct resource *res); 1403 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1404 resource_size_t offset); 1405 void pci_free_resource_list(struct list_head *resources); 1406 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, 1407 unsigned int flags); 1408 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1409 void pci_bus_remove_resources(struct pci_bus *bus); 1410 int devm_request_pci_bus_resources(struct device *dev, 1411 struct list_head *resources); 1412 1413 /* Temporary until new and working PCI SBR API in place */ 1414 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1415 1416 #define pci_bus_for_each_resource(bus, res, i) \ 1417 for (i = 0; \ 1418 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1419 i++) 1420 1421 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1422 struct resource *res, resource_size_t size, 1423 resource_size_t align, resource_size_t min, 1424 unsigned long type_mask, 1425 resource_size_t (*alignf)(void *, 1426 const struct resource *, 1427 resource_size_t, 1428 resource_size_t), 1429 void *alignf_data); 1430 1431 1432 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, 1433 resource_size_t size); 1434 unsigned long pci_address_to_pio(phys_addr_t addr); 1435 phys_addr_t pci_pio_to_address(unsigned long pio); 1436 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1437 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1438 phys_addr_t phys_addr); 1439 void pci_unmap_iospace(struct resource *res); 1440 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1441 resource_size_t offset, 1442 resource_size_t size); 1443 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1444 struct resource *res); 1445 1446 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1447 { 1448 struct pci_bus_region region; 1449 1450 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1451 return region.start; 1452 } 1453 1454 /* Proper probing supporting hot-pluggable devices */ 1455 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1456 const char *mod_name); 1457 1458 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1459 #define pci_register_driver(driver) \ 1460 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1461 1462 void pci_unregister_driver(struct pci_driver *dev); 1463 1464 /** 1465 * module_pci_driver() - Helper macro for registering a PCI driver 1466 * @__pci_driver: pci_driver struct 1467 * 1468 * Helper macro for PCI drivers which do not do anything special in module 1469 * init/exit. This eliminates a lot of boilerplate. Each module may only 1470 * use this macro once, and calling it replaces module_init() and module_exit() 1471 */ 1472 #define module_pci_driver(__pci_driver) \ 1473 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1474 1475 /** 1476 * builtin_pci_driver() - Helper macro for registering a PCI driver 1477 * @__pci_driver: pci_driver struct 1478 * 1479 * Helper macro for PCI drivers which do not do anything special in their 1480 * init code. This eliminates a lot of boilerplate. Each driver may only 1481 * use this macro once, and calling it replaces device_initcall(...) 1482 */ 1483 #define builtin_pci_driver(__pci_driver) \ 1484 builtin_driver(__pci_driver, pci_register_driver) 1485 1486 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1487 int pci_add_dynid(struct pci_driver *drv, 1488 unsigned int vendor, unsigned int device, 1489 unsigned int subvendor, unsigned int subdevice, 1490 unsigned int class, unsigned int class_mask, 1491 unsigned long driver_data); 1492 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1493 struct pci_dev *dev); 1494 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1495 int pass); 1496 1497 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1498 void *userdata); 1499 int pci_cfg_space_size(struct pci_dev *dev); 1500 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1501 void pci_setup_bridge(struct pci_bus *bus); 1502 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1503 unsigned long type); 1504 1505 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1506 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1507 1508 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1509 unsigned int command_bits, u32 flags); 1510 1511 /* 1512 * Virtual interrupts allow for more interrupts to be allocated 1513 * than the device has interrupts for. These are not programmed 1514 * into the device's MSI-X table and must be handled by some 1515 * other driver means. 1516 */ 1517 #define PCI_IRQ_VIRTUAL (1 << 4) 1518 1519 #define PCI_IRQ_ALL_TYPES \ 1520 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1521 1522 #include <linux/dmapool.h> 1523 1524 struct msix_entry { 1525 u32 vector; /* Kernel uses to write allocated vector */ 1526 u16 entry; /* Driver uses to specify entry, OS writes */ 1527 }; 1528 1529 #ifdef CONFIG_PCI_MSI 1530 int pci_msi_vec_count(struct pci_dev *dev); 1531 void pci_disable_msi(struct pci_dev *dev); 1532 int pci_msix_vec_count(struct pci_dev *dev); 1533 void pci_disable_msix(struct pci_dev *dev); 1534 void pci_restore_msi_state(struct pci_dev *dev); 1535 int pci_msi_enabled(void); 1536 int pci_enable_msi(struct pci_dev *dev); 1537 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1538 int minvec, int maxvec); 1539 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1540 struct msix_entry *entries, int nvec) 1541 { 1542 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1543 if (rc < 0) 1544 return rc; 1545 return 0; 1546 } 1547 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1548 unsigned int max_vecs, unsigned int flags, 1549 struct irq_affinity *affd); 1550 1551 void pci_free_irq_vectors(struct pci_dev *dev); 1552 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1553 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1554 1555 #else 1556 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1557 static inline void pci_disable_msi(struct pci_dev *dev) { } 1558 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1559 static inline void pci_disable_msix(struct pci_dev *dev) { } 1560 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1561 static inline int pci_msi_enabled(void) { return 0; } 1562 static inline int pci_enable_msi(struct pci_dev *dev) 1563 { return -ENOSYS; } 1564 static inline int pci_enable_msix_range(struct pci_dev *dev, 1565 struct msix_entry *entries, int minvec, int maxvec) 1566 { return -ENOSYS; } 1567 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1568 struct msix_entry *entries, int nvec) 1569 { return -ENOSYS; } 1570 1571 static inline int 1572 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1573 unsigned int max_vecs, unsigned int flags, 1574 struct irq_affinity *aff_desc) 1575 { 1576 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) 1577 return 1; 1578 return -ENOSPC; 1579 } 1580 1581 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1582 { 1583 } 1584 1585 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1586 { 1587 if (WARN_ON_ONCE(nr > 0)) 1588 return -EINVAL; 1589 return dev->irq; 1590 } 1591 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1592 int vec) 1593 { 1594 return cpu_possible_mask; 1595 } 1596 #endif 1597 1598 /** 1599 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1600 * @d: the INTx IRQ domain 1601 * @node: the DT node for the device whose interrupt we're translating 1602 * @intspec: the interrupt specifier data from the DT 1603 * @intsize: the number of entries in @intspec 1604 * @out_hwirq: pointer at which to write the hwirq number 1605 * @out_type: pointer at which to write the interrupt type 1606 * 1607 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1608 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1609 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1610 * INTx value to obtain the hwirq number. 1611 * 1612 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1613 */ 1614 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1615 struct device_node *node, 1616 const u32 *intspec, 1617 unsigned int intsize, 1618 unsigned long *out_hwirq, 1619 unsigned int *out_type) 1620 { 1621 const u32 intx = intspec[0]; 1622 1623 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1624 return -EINVAL; 1625 1626 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1627 return 0; 1628 } 1629 1630 #ifdef CONFIG_PCIEPORTBUS 1631 extern bool pcie_ports_disabled; 1632 extern bool pcie_ports_native; 1633 #else 1634 #define pcie_ports_disabled true 1635 #define pcie_ports_native false 1636 #endif 1637 1638 #define PCIE_LINK_STATE_L0S BIT(0) 1639 #define PCIE_LINK_STATE_L1 BIT(1) 1640 #define PCIE_LINK_STATE_CLKPM BIT(2) 1641 #define PCIE_LINK_STATE_L1_1 BIT(3) 1642 #define PCIE_LINK_STATE_L1_2 BIT(4) 1643 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) 1644 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) 1645 1646 #ifdef CONFIG_PCIEASPM 1647 int pci_disable_link_state(struct pci_dev *pdev, int state); 1648 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1649 void pcie_no_aspm(void); 1650 bool pcie_aspm_support_enabled(void); 1651 bool pcie_aspm_enabled(struct pci_dev *pdev); 1652 #else 1653 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1654 { return 0; } 1655 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1656 { return 0; } 1657 static inline void pcie_no_aspm(void) { } 1658 static inline bool pcie_aspm_support_enabled(void) { return false; } 1659 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1660 #endif 1661 1662 #ifdef CONFIG_PCIEAER 1663 bool pci_aer_available(void); 1664 #else 1665 static inline bool pci_aer_available(void) { return false; } 1666 #endif 1667 1668 bool pci_ats_disabled(void); 1669 1670 #ifdef CONFIG_PCIE_PTM 1671 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 1672 bool pcie_ptm_enabled(struct pci_dev *dev); 1673 #else 1674 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 1675 { return -EINVAL; } 1676 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 1677 { return false; } 1678 #endif 1679 1680 void pci_cfg_access_lock(struct pci_dev *dev); 1681 bool pci_cfg_access_trylock(struct pci_dev *dev); 1682 void pci_cfg_access_unlock(struct pci_dev *dev); 1683 1684 void pci_dev_lock(struct pci_dev *dev); 1685 int pci_dev_trylock(struct pci_dev *dev); 1686 void pci_dev_unlock(struct pci_dev *dev); 1687 1688 /* 1689 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1690 * a PCI domain is defined to be a set of PCI buses which share 1691 * configuration space. 1692 */ 1693 #ifdef CONFIG_PCI_DOMAINS 1694 extern int pci_domains_supported; 1695 #else 1696 enum { pci_domains_supported = 0 }; 1697 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1698 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 1699 #endif /* CONFIG_PCI_DOMAINS */ 1700 1701 /* 1702 * Generic implementation for PCI domain support. If your 1703 * architecture does not need custom management of PCI 1704 * domains then this implementation will be used 1705 */ 1706 #ifdef CONFIG_PCI_DOMAINS_GENERIC 1707 static inline int pci_domain_nr(struct pci_bus *bus) 1708 { 1709 return bus->domain_nr; 1710 } 1711 #ifdef CONFIG_ACPI 1712 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 1713 #else 1714 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 1715 { return 0; } 1716 #endif 1717 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1718 #endif 1719 1720 /* Some architectures require additional setup to direct VGA traffic */ 1721 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1722 unsigned int command_bits, u32 flags); 1723 void pci_register_set_vga_state(arch_set_vga_state_t func); 1724 1725 static inline int 1726 pci_request_io_regions(struct pci_dev *pdev, const char *name) 1727 { 1728 return pci_request_selected_regions(pdev, 1729 pci_select_bars(pdev, IORESOURCE_IO), name); 1730 } 1731 1732 static inline void 1733 pci_release_io_regions(struct pci_dev *pdev) 1734 { 1735 return pci_release_selected_regions(pdev, 1736 pci_select_bars(pdev, IORESOURCE_IO)); 1737 } 1738 1739 static inline int 1740 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 1741 { 1742 return pci_request_selected_regions(pdev, 1743 pci_select_bars(pdev, IORESOURCE_MEM), name); 1744 } 1745 1746 static inline void 1747 pci_release_mem_regions(struct pci_dev *pdev) 1748 { 1749 return pci_release_selected_regions(pdev, 1750 pci_select_bars(pdev, IORESOURCE_MEM)); 1751 } 1752 1753 #else /* CONFIG_PCI is not enabled */ 1754 1755 static inline void pci_set_flags(int flags) { } 1756 static inline void pci_add_flags(int flags) { } 1757 static inline void pci_clear_flags(int flags) { } 1758 static inline int pci_has_flag(int flag) { return 0; } 1759 1760 /* 1761 * If the system does not have PCI, clearly these return errors. Define 1762 * these as simple inline functions to avoid hair in drivers. 1763 */ 1764 #define _PCI_NOP(o, s, t) \ 1765 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1766 int where, t val) \ 1767 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 1768 1769 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 1770 _PCI_NOP(o, word, u16 x) \ 1771 _PCI_NOP(o, dword, u32 x) 1772 _PCI_NOP_ALL(read, *) 1773 _PCI_NOP_ALL(write,) 1774 1775 static inline struct pci_dev *pci_get_device(unsigned int vendor, 1776 unsigned int device, 1777 struct pci_dev *from) 1778 { return NULL; } 1779 1780 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 1781 unsigned int device, 1782 unsigned int ss_vendor, 1783 unsigned int ss_device, 1784 struct pci_dev *from) 1785 { return NULL; } 1786 1787 static inline struct pci_dev *pci_get_class(unsigned int class, 1788 struct pci_dev *from) 1789 { return NULL; } 1790 1791 1792 static inline int pci_dev_present(const struct pci_device_id *ids) 1793 { return 0; } 1794 1795 #define no_pci_devices() (1) 1796 #define pci_dev_put(dev) do { } while (0) 1797 1798 static inline void pci_set_master(struct pci_dev *dev) { } 1799 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 1800 static inline void pci_disable_device(struct pci_dev *dev) { } 1801 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 1802 static inline int pci_assign_resource(struct pci_dev *dev, int i) 1803 { return -EBUSY; } 1804 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 1805 struct module *owner, 1806 const char *mod_name) 1807 { return 0; } 1808 static inline int pci_register_driver(struct pci_driver *drv) 1809 { return 0; } 1810 static inline void pci_unregister_driver(struct pci_driver *drv) { } 1811 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 1812 { return 0; } 1813 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, 1814 int cap) 1815 { return 0; } 1816 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) 1817 { return 0; } 1818 1819 static inline u64 pci_get_dsn(struct pci_dev *dev) 1820 { return 0; } 1821 1822 /* Power management related routines */ 1823 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 1824 static inline void pci_restore_state(struct pci_dev *dev) { } 1825 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1826 { return 0; } 1827 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1828 { return 0; } 1829 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 1830 pm_message_t state) 1831 { return PCI_D0; } 1832 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1833 int enable) 1834 { return 0; } 1835 1836 static inline struct resource *pci_find_resource(struct pci_dev *dev, 1837 struct resource *res) 1838 { return NULL; } 1839 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 1840 { return -EIO; } 1841 static inline void pci_release_regions(struct pci_dev *dev) { } 1842 1843 static inline int pci_register_io_range(struct fwnode_handle *fwnode, 1844 phys_addr_t addr, resource_size_t size) 1845 { return -EINVAL; } 1846 1847 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 1848 1849 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 1850 { return NULL; } 1851 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 1852 unsigned int devfn) 1853 { return NULL; } 1854 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 1855 unsigned int bus, unsigned int devfn) 1856 { return NULL; } 1857 1858 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 1859 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 1860 1861 #define dev_is_pci(d) (false) 1862 #define dev_is_pf(d) (false) 1863 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1864 { return false; } 1865 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1866 struct device_node *node, 1867 const u32 *intspec, 1868 unsigned int intsize, 1869 unsigned long *out_hwirq, 1870 unsigned int *out_type) 1871 { return -EINVAL; } 1872 1873 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1874 struct pci_dev *dev) 1875 { return NULL; } 1876 static inline bool pci_ats_disabled(void) { return true; } 1877 1878 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1879 { 1880 return -EINVAL; 1881 } 1882 1883 static inline int 1884 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1885 unsigned int max_vecs, unsigned int flags, 1886 struct irq_affinity *aff_desc) 1887 { 1888 return -ENOSPC; 1889 } 1890 #endif /* CONFIG_PCI */ 1891 1892 static inline int 1893 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1894 unsigned int max_vecs, unsigned int flags) 1895 { 1896 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, 1897 NULL); 1898 } 1899 1900 /* Include architecture-dependent settings and functions */ 1901 1902 #include <asm/pci.h> 1903 1904 /* These two functions provide almost identical functionality. Depending 1905 * on the architecture, one will be implemented as a wrapper around the 1906 * other (in drivers/pci/mmap.c). 1907 * 1908 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 1909 * is expected to be an offset within that region. 1910 * 1911 * pci_mmap_page_range() is the legacy architecture-specific interface, 1912 * which accepts a "user visible" resource address converted by 1913 * pci_resource_to_user(), as used in the legacy mmap() interface in 1914 * /proc/bus/pci/. 1915 */ 1916 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 1917 struct vm_area_struct *vma, 1918 enum pci_mmap_state mmap_state, int write_combine); 1919 int pci_mmap_page_range(struct pci_dev *pdev, int bar, 1920 struct vm_area_struct *vma, 1921 enum pci_mmap_state mmap_state, int write_combine); 1922 1923 #ifndef arch_can_pci_mmap_wc 1924 #define arch_can_pci_mmap_wc() 0 1925 #endif 1926 1927 #ifndef arch_can_pci_mmap_io 1928 #define arch_can_pci_mmap_io() 0 1929 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 1930 #else 1931 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 1932 #endif 1933 1934 #ifndef pci_root_bus_fwnode 1935 #define pci_root_bus_fwnode(bus) NULL 1936 #endif 1937 1938 /* 1939 * These helpers provide future and backwards compatibility 1940 * for accessing popular PCI BAR info 1941 */ 1942 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1943 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1944 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1945 #define pci_resource_len(dev,bar) \ 1946 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \ 1947 \ 1948 (pci_resource_end((dev), (bar)) - \ 1949 pci_resource_start((dev), (bar)) + 1)) 1950 1951 /* 1952 * Similar to the helpers above, these manipulate per-pci_dev 1953 * driver-specific data. They are really just a wrapper around 1954 * the generic device structure functions of these calls. 1955 */ 1956 static inline void *pci_get_drvdata(struct pci_dev *pdev) 1957 { 1958 return dev_get_drvdata(&pdev->dev); 1959 } 1960 1961 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 1962 { 1963 dev_set_drvdata(&pdev->dev, data); 1964 } 1965 1966 static inline const char *pci_name(const struct pci_dev *pdev) 1967 { 1968 return dev_name(&pdev->dev); 1969 } 1970 1971 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1972 const struct resource *rsrc, 1973 resource_size_t *start, resource_size_t *end); 1974 1975 /* 1976 * The world is not perfect and supplies us with broken PCI devices. 1977 * For at least a part of these bugs we need a work-around, so both 1978 * generic (drivers/pci/quirks.c) and per-architecture code can define 1979 * fixup hooks to be called for particular buggy devices. 1980 */ 1981 1982 struct pci_fixup { 1983 u16 vendor; /* Or PCI_ANY_ID */ 1984 u16 device; /* Or PCI_ANY_ID */ 1985 u32 class; /* Or PCI_ANY_ID */ 1986 unsigned int class_shift; /* should be 0, 8, 16 */ 1987 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 1988 int hook_offset; 1989 #else 1990 void (*hook)(struct pci_dev *dev); 1991 #endif 1992 }; 1993 1994 enum pci_fixup_pass { 1995 pci_fixup_early, /* Before probing BARs */ 1996 pci_fixup_header, /* After reading configuration header */ 1997 pci_fixup_final, /* Final phase of device fixups */ 1998 pci_fixup_enable, /* pci_enable_device() time */ 1999 pci_fixup_resume, /* pci_device_resume() */ 2000 pci_fixup_suspend, /* pci_device_suspend() */ 2001 pci_fixup_resume_early, /* pci_device_resume_early() */ 2002 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2003 }; 2004 2005 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2006 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2007 class_shift, hook) \ 2008 __ADDRESSABLE(hook) \ 2009 asm(".section " #sec ", \"a\" \n" \ 2010 ".balign 16 \n" \ 2011 ".short " #vendor ", " #device " \n" \ 2012 ".long " #class ", " #class_shift " \n" \ 2013 ".long " #hook " - . \n" \ 2014 ".previous \n"); 2015 2016 /* 2017 * Clang's LTO may rename static functions in C, but has no way to 2018 * handle such renamings when referenced from inline asm. To work 2019 * around this, create global C stubs for these cases. 2020 */ 2021 #ifdef CONFIG_LTO_CLANG 2022 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2023 class_shift, hook, stub) \ 2024 void __cficanonical stub(struct pci_dev *dev); \ 2025 void __cficanonical stub(struct pci_dev *dev) \ 2026 { \ 2027 hook(dev); \ 2028 } \ 2029 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2030 class_shift, stub) 2031 #else 2032 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2033 class_shift, hook, stub) \ 2034 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2035 class_shift, hook) 2036 #endif 2037 2038 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2039 class_shift, hook) \ 2040 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2041 class_shift, hook, __UNIQUE_ID(hook)) 2042 #else 2043 /* Anonymous variables would be nice... */ 2044 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2045 class_shift, hook) \ 2046 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2047 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2048 = { vendor, device, class, class_shift, hook }; 2049 #endif 2050 2051 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2052 class_shift, hook) \ 2053 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2054 hook, vendor, device, class, class_shift, hook) 2055 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2056 class_shift, hook) \ 2057 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2058 hook, vendor, device, class, class_shift, hook) 2059 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2060 class_shift, hook) \ 2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2062 hook, vendor, device, class, class_shift, hook) 2063 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2064 class_shift, hook) \ 2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2066 hook, vendor, device, class, class_shift, hook) 2067 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2068 class_shift, hook) \ 2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2070 resume##hook, vendor, device, class, class_shift, hook) 2071 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2072 class_shift, hook) \ 2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2074 resume_early##hook, vendor, device, class, class_shift, hook) 2075 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2076 class_shift, hook) \ 2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2078 suspend##hook, vendor, device, class, class_shift, hook) 2079 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2080 class_shift, hook) \ 2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2082 suspend_late##hook, vendor, device, class, class_shift, hook) 2083 2084 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2085 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2086 hook, vendor, device, PCI_ANY_ID, 0, hook) 2087 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2088 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2089 hook, vendor, device, PCI_ANY_ID, 0, hook) 2090 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2091 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2092 hook, vendor, device, PCI_ANY_ID, 0, hook) 2093 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2094 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2095 hook, vendor, device, PCI_ANY_ID, 0, hook) 2096 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2097 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2098 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2099 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2100 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2101 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2102 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2103 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2104 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2105 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2106 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2107 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2108 2109 #ifdef CONFIG_PCI_QUIRKS 2110 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2111 #else 2112 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2113 struct pci_dev *dev) { } 2114 #endif 2115 2116 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2117 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2118 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2119 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2120 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, 2121 const char *name); 2122 void pcim_iounmap_regions(struct pci_dev *pdev, int mask); 2123 2124 extern int pci_pci_problems; 2125 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2126 #define PCIPCI_TRITON 2 2127 #define PCIPCI_NATOMA 4 2128 #define PCIPCI_VIAETBF 8 2129 #define PCIPCI_VSFX 16 2130 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2131 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2132 2133 extern unsigned long pci_cardbus_io_size; 2134 extern unsigned long pci_cardbus_mem_size; 2135 extern u8 pci_dfl_cache_line_size; 2136 extern u8 pci_cache_line_size; 2137 2138 /* Architecture-specific versions may override these (weak) */ 2139 void pcibios_disable_device(struct pci_dev *dev); 2140 void pcibios_set_master(struct pci_dev *dev); 2141 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2142 enum pcie_reset_state state); 2143 int pcibios_device_add(struct pci_dev *dev); 2144 void pcibios_release_device(struct pci_dev *dev); 2145 #ifdef CONFIG_PCI 2146 void pcibios_penalize_isa_irq(int irq, int active); 2147 #else 2148 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2149 #endif 2150 int pcibios_alloc_irq(struct pci_dev *dev); 2151 void pcibios_free_irq(struct pci_dev *dev); 2152 resource_size_t pcibios_default_alignment(void); 2153 2154 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2155 void __init pci_mmcfg_early_init(void); 2156 void __init pci_mmcfg_late_init(void); 2157 #else 2158 static inline void pci_mmcfg_early_init(void) { } 2159 static inline void pci_mmcfg_late_init(void) { } 2160 #endif 2161 2162 int pci_ext_cfg_avail(void); 2163 2164 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2165 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2166 2167 #ifdef CONFIG_PCI_IOV 2168 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2169 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2170 int pci_iov_vf_id(struct pci_dev *dev); 2171 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2172 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2173 void pci_disable_sriov(struct pci_dev *dev); 2174 2175 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2176 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2177 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2178 int pci_num_vf(struct pci_dev *dev); 2179 int pci_vfs_assigned(struct pci_dev *dev); 2180 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2181 int pci_sriov_get_totalvfs(struct pci_dev *dev); 2182 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2183 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 2184 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2185 2186 /* Arch may override these (weak) */ 2187 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2188 int pcibios_sriov_disable(struct pci_dev *pdev); 2189 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); 2190 #else 2191 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2192 { 2193 return -ENOSYS; 2194 } 2195 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2196 { 2197 return -ENOSYS; 2198 } 2199 2200 static inline int pci_iov_vf_id(struct pci_dev *dev) 2201 { 2202 return -ENOSYS; 2203 } 2204 2205 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2206 struct pci_driver *pf_driver) 2207 { 2208 return ERR_PTR(-EINVAL); 2209 } 2210 2211 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2212 { return -ENODEV; } 2213 2214 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2215 struct pci_dev *virtfn, int id) 2216 { 2217 return -ENODEV; 2218 } 2219 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2220 { 2221 return -ENOSYS; 2222 } 2223 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2224 int id) { } 2225 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2226 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2227 static inline int pci_vfs_assigned(struct pci_dev *dev) 2228 { return 0; } 2229 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2230 { return 0; } 2231 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) 2232 { return 0; } 2233 #define pci_sriov_configure_simple NULL 2234 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) 2235 { return 0; } 2236 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2237 #endif 2238 2239 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) 2240 void pci_hp_create_module_link(struct pci_slot *pci_slot); 2241 void pci_hp_remove_module_link(struct pci_slot *pci_slot); 2242 #endif 2243 2244 /** 2245 * pci_pcie_cap - get the saved PCIe capability offset 2246 * @dev: PCI device 2247 * 2248 * PCIe capability offset is calculated at PCI device initialization 2249 * time and saved in the data structure. This function returns saved 2250 * PCIe capability offset. Using this instead of pci_find_capability() 2251 * reduces unnecessary search in the PCI configuration space. If you 2252 * need to calculate PCIe capability offset from raw device for some 2253 * reasons, please use pci_find_capability() instead. 2254 */ 2255 static inline int pci_pcie_cap(struct pci_dev *dev) 2256 { 2257 return dev->pcie_cap; 2258 } 2259 2260 /** 2261 * pci_is_pcie - check if the PCI device is PCI Express capable 2262 * @dev: PCI device 2263 * 2264 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2265 */ 2266 static inline bool pci_is_pcie(struct pci_dev *dev) 2267 { 2268 return pci_pcie_cap(dev); 2269 } 2270 2271 /** 2272 * pcie_caps_reg - get the PCIe Capabilities Register 2273 * @dev: PCI device 2274 */ 2275 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2276 { 2277 return dev->pcie_flags_reg; 2278 } 2279 2280 /** 2281 * pci_pcie_type - get the PCIe device/port type 2282 * @dev: PCI device 2283 */ 2284 static inline int pci_pcie_type(const struct pci_dev *dev) 2285 { 2286 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2287 } 2288 2289 /** 2290 * pcie_find_root_port - Get the PCIe root port device 2291 * @dev: PCI device 2292 * 2293 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2294 * for a given PCI/PCIe Device. 2295 */ 2296 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2297 { 2298 while (dev) { 2299 if (pci_is_pcie(dev) && 2300 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2301 return dev; 2302 dev = pci_upstream_bridge(dev); 2303 } 2304 2305 return NULL; 2306 } 2307 2308 void pci_request_acs(void); 2309 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2310 bool pci_acs_path_enabled(struct pci_dev *start, 2311 struct pci_dev *end, u16 acs_flags); 2312 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2313 2314 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2315 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2316 2317 /* Large Resource Data Type Tag Item Names */ 2318 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2319 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2320 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2321 2322 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2323 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2324 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2325 2326 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2327 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2328 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2329 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2330 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2331 2332 /** 2333 * pci_vpd_alloc - Allocate buffer and read VPD into it 2334 * @dev: PCI device 2335 * @size: pointer to field where VPD length is returned 2336 * 2337 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2338 */ 2339 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2340 2341 /** 2342 * pci_vpd_find_id_string - Locate id string in VPD 2343 * @buf: Pointer to buffered VPD data 2344 * @len: The length of the buffer area in which to search 2345 * @size: Pointer to field where length of id string is returned 2346 * 2347 * Returns the index of the id string or -ENOENT if not found. 2348 */ 2349 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2350 2351 /** 2352 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2353 * @buf: Pointer to buffered VPD data 2354 * @len: The length of the buffer area in which to search 2355 * @kw: The keyword to search for 2356 * @size: Pointer to field where length of found keyword data is returned 2357 * 2358 * Returns the index of the information field keyword data or -ENOENT if 2359 * not found. 2360 */ 2361 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2362 const char *kw, unsigned int *size); 2363 2364 /** 2365 * pci_vpd_check_csum - Check VPD checksum 2366 * @buf: Pointer to buffered VPD data 2367 * @len: VPD size 2368 * 2369 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2370 */ 2371 int pci_vpd_check_csum(const void *buf, unsigned int len); 2372 2373 /* PCI <-> OF binding helpers */ 2374 #ifdef CONFIG_OF 2375 struct device_node; 2376 struct irq_domain; 2377 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2378 bool pci_host_of_has_msi_map(struct device *dev); 2379 2380 /* Arch may override this (weak) */ 2381 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2382 2383 #else /* CONFIG_OF */ 2384 static inline struct irq_domain * 2385 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2386 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2387 #endif /* CONFIG_OF */ 2388 2389 static inline struct device_node * 2390 pci_device_to_OF_node(const struct pci_dev *pdev) 2391 { 2392 return pdev ? pdev->dev.of_node : NULL; 2393 } 2394 2395 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2396 { 2397 return bus ? bus->dev.of_node : NULL; 2398 } 2399 2400 #ifdef CONFIG_ACPI 2401 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2402 2403 void 2404 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2405 bool pci_pr3_present(struct pci_dev *pdev); 2406 #else 2407 static inline struct irq_domain * 2408 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2409 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2410 #endif 2411 2412 #ifdef CONFIG_EEH 2413 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2414 { 2415 return pdev->dev.archdata.edev; 2416 } 2417 #endif 2418 2419 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2420 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2421 int pci_for_each_dma_alias(struct pci_dev *pdev, 2422 int (*fn)(struct pci_dev *pdev, 2423 u16 alias, void *data), void *data); 2424 2425 /* Helper functions for operation of device flag */ 2426 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2427 { 2428 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2429 } 2430 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2431 { 2432 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2433 } 2434 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2435 { 2436 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2437 } 2438 2439 /** 2440 * pci_ari_enabled - query ARI forwarding status 2441 * @bus: the PCI bus 2442 * 2443 * Returns true if ARI forwarding is enabled. 2444 */ 2445 static inline bool pci_ari_enabled(struct pci_bus *bus) 2446 { 2447 return bus->self && bus->self->ari_enabled; 2448 } 2449 2450 /** 2451 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2452 * @pdev: PCI device to check 2453 * 2454 * Walk upwards from @pdev and check for each encountered bridge if it's part 2455 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2456 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2457 */ 2458 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2459 { 2460 struct pci_dev *parent = pdev; 2461 2462 if (pdev->is_thunderbolt) 2463 return true; 2464 2465 while ((parent = pci_upstream_bridge(parent))) 2466 if (parent->is_thunderbolt) 2467 return true; 2468 2469 return false; 2470 } 2471 2472 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) 2473 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2474 #endif 2475 2476 #include <linux/dma-mapping.h> 2477 2478 #define pci_printk(level, pdev, fmt, arg...) \ 2479 dev_printk(level, &(pdev)->dev, fmt, ##arg) 2480 2481 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2482 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2483 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2484 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2485 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2486 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2487 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2488 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2489 2490 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2491 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2492 2493 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2494 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2495 2496 #define pci_WARN(pdev, condition, fmt, arg...) \ 2497 WARN(condition, "%s %s: " fmt, \ 2498 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2499 2500 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2501 WARN_ONCE(condition, "%s %s: " fmt, \ 2502 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2503 2504 #endif /* LINUX_PCI_H */ 2505