ARM: aspeed: Kconfig: Fix indentation

The convention for indentation seems to be a single tab. Help text is
further indented by an additional two whitespaces. Fix the lines that
violate these rules.

ARM: aspeed: Kconfig: Fix indentation

The convention for indentation seems to be a single tab. Help text is
further indented by an additional two whitespaces. Fix the lines that
violate these rules.

Signed-off-by: Juerg Haefliger <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
Acked-by: Andrew Jeffery <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]'
Signed-off-by: Arnd Bergmann <[email protected]>

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ARM: rework endianess selection

Choosing big-endian vs little-endian kernels in Kconfig has not worked
correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long
time ago.

The problems is

ARM: rework endianess selection

Choosing big-endian vs little-endian kernels in Kconfig has not worked
correctly since the introduction of CONFIG_ARCH_MULTIPLATFORM a long
time ago.

The problems is that CONFIG_BIG_ENDIAN depends on
ARCH_SUPPORTS_BIG_ENDIAN, which can set by any one platform
in the config, but would actually have to be supported by all
of them.

This was mostly ok for ARMv6/ARMv7 builds, since these are BE8 and
tend to just work aside from problems in nonportable device drivers.
For ARMv4/v5 machines, CONFIG_BIG_ENDIAN and CONFIG_ARCH_MULTIPLATFORM
were never set together, so this was disabled on all those machines
except for IXP4xx.

As IXP4xx can now become part of ARCH_MULTIPLATFORM, it seems better to
formalize this logic: all ARMv4/v5 platforms get an explicit dependency
on being either big-endian (ixp4xx) or little-endian (the rest). We may
want to fix ixp4xx in the future to support both, but it does not work
in LE mode at the moment.

For the ARMv6/v7 platforms, there are two ways this could be handled

a) allow both modes only for platforms selecting
'ARCH_SUPPORTS_BIG_ENDIAN' today, but only LE mode for the
others, given that these were added intentionally at some
point.

b) allow both modes everwhere, given that it was already possible
to build that way by e.g. selecting ARCH_VIRT, and that the
list is not an accurate reflection of which platforms may or
may not work.

Out of these, I picked b) because it seemed slighly more logical
to me.

Signed-off-by: Arnd Bergmann <[email protected]>

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ARM: aspeed: Drop unneeded select of HAVE_SMP

Support for the 6th generation Aspeed SoCs depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for MACH_ASPEED_G6 to
select HAVE_

ARM: aspeed: Drop unneeded select of HAVE_SMP

Support for the 6th generation Aspeed SoCs depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for MACH_ASPEED_G6 to
select HAVE_SMP.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Cc: Joel Stanley <[email protected]>
Cc: Andrew Jeffery <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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ARM: aspeed: ast2500 is ARMv6K

Linux supports both the original ARMv6 level (early ARM1136) and ARMv6K
(later ARM1136, ARM1176 and ARM11mpcore).

ast2500 falls into the second categoy, being based o

ARM: aspeed: ast2500 is ARMv6K

Linux supports both the original ARMv6 level (early ARM1136) and ARMv6K
(later ARM1136, ARM1176 and ARM11mpcore).

ast2500 falls into the second categoy, being based on arm1176jzf-s.
This is enabled by default when using ARCH_MULTI_V6, so we should
not 'select CPU_V6'.

Removing this will lead to more efficient use of atomic instructions.

Fixes: 8c2ed9bcfbeb ("arm: Add Aspeed machine")
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>

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ARM: aspeed: Add ASPEED AST2600 architecture

The AST2600 is a Cortex A7 dual core CPU that uses the ARM GIC for
interrupts and ARM timer as a clocksource.

Reviewed-by: Andrew Jeffery <[email protected].

ARM: aspeed: Add ASPEED AST2600 architecture

The AST2600 is a Cortex A7 dual core CPU that uses the ARM GIC for
interrupts and ARM timer as a clocksource.

Reviewed-by: Andrew Jeffery <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>

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ARM: aspeed: Select timer in each SoC

In preparation for adding the ast2600 which does not use this timer.

Reviewed-by: Andrew Jeffery <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project

treewide: Add SPDX license identifier - Makefile/Kconfig

Add SPDX license identifiers to all Make/Kconfig files which:

- Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

GPL-2.0-only

Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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clocksource/drivers/fttmr010: Merge Moxa into FTTMR010

This merges the Moxa Art timer driver into the Faraday FTTMR010
driver and replaces all Kconfig symbols to use the Faraday
driver instead. We a

clocksource/drivers/fttmr010: Merge Moxa into FTTMR010

This merges the Moxa Art timer driver into the Faraday FTTMR010
driver and replaces all Kconfig symbols to use the Faraday
driver instead. We are now so similar that the drivers can
be merged by just adding a few lines to the Faraday timer.

Differences:

- The Faraday driver explicitly sets the counter to count
upwards for the clocksource, removing the need for the
clocksource core to invert the value.

- The Faraday driver also handles sched_clock()

On the Aspeed, the counter can only count downwards, so support
the timers in downward-counting mode as well, and flag the
Aspeed to use this mode. This mode was tested on the Gemini so
I have high hopes that it'll work fine on the Aspeed as well.

After this we have one driver for all three SoCs and a generic
Faraday FTTMR010 timer driver, which is nice.

Cc: Joel Stanley <[email protected]>
Cc: Jonas Jensen <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>

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ARM: aspeed: Select pinctrl drivers

Signed-off-by: Andrew Jeffery <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>

arm: Add Aspeed machine

Aspeed devices are a common Baseboard Management Controller (BMC)
system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and
support for a large number of peripher

arm: Add Aspeed machine

Aspeed devices are a common Baseboard Management Controller (BMC)
system on chip containing an ARM9 or ARM11 core, off-chip DDR RAM and
support for a large number of peripherals.

This patch adds basic support for the ast2400 and ast2500 machines,
capable of booting to a prompt in QEMU (-M palmetto-bmc), on an
Palmetto OpenPower development machine, and on the ast2500 EVB.

Signed-off-by: Joel Stanley <[email protected]>

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