1 use crate::ir::types::*;
2 use crate::ir::{ExternalName, TrapCode};
3 use crate::isa::aarch64;
4 use crate::isa::aarch64::inst::*;
5
6 use alloc::boxed::Box;
7
8 #[cfg(test)]
simm9_zero() -> SImm99 fn simm9_zero() -> SImm9 {
10 SImm9::maybe_from_i64(0).unwrap()
11 }
12
13 #[cfg(test)]
simm7_scaled_zero(scale_ty: Type) -> SImm7Scaled14 fn simm7_scaled_zero(scale_ty: Type) -> SImm7Scaled {
15 SImm7Scaled::maybe_from_i64(0, scale_ty).unwrap()
16 }
17
18 #[test]
test_aarch64_binemit()19 fn test_aarch64_binemit() {
20 let mut insns = Vec::<(Inst, &str, &str)>::new();
21
22 // N.B.: the architecture is little-endian, so when transcribing the 32-bit
23 // hex instructions from e.g. objdump disassembly, one must swap the bytes
24 // seen below. (E.g., a `ret` is normally written as the u32 `D65F03C0`,
25 // but we write it here as C0035FD6.)
26
27 // Useful helper script to produce the encodings from the text:
28 //
29 // #!/bin/sh
30 // tmp=`mktemp /tmp/XXXXXXXX.o`
31 // aarch64-linux-gnu-as /dev/stdin -o $tmp
32 // aarch64-linux-gnu-objdump -d $tmp
33 // rm -f $tmp
34 //
35 // Then:
36 //
37 // $ echo "mov x1, x2" | aarch64inst.sh
38 insns.push((Inst::Ret {}, "C0035FD6", "ret"));
39 insns.push((
40 Inst::AuthenticatedRet {
41 key: APIKey::ASP,
42 is_hint: true,
43 },
44 "BF2303D5C0035FD6",
45 "autiasp ; ret",
46 ));
47 insns.push((
48 Inst::AuthenticatedRet {
49 key: APIKey::BSP,
50 is_hint: false,
51 },
52 "FF0F5FD6",
53 "retabsp",
54 ));
55 insns.push((Inst::Paci { key: APIKey::BSP }, "7F2303D5", "pacibsp"));
56 insns.push((Inst::Xpaclri, "FF2003D5", "xpaclri"));
57 insns.push((
58 Inst::Bti {
59 targets: BranchTargetType::J,
60 },
61 "9F2403D5",
62 "bti j",
63 ));
64 insns.push((Inst::Nop0, "", "nop-zero-len"));
65 insns.push((Inst::Nop4, "1F2003D5", "nop"));
66 insns.push((Inst::Csdb, "9F2203D5", "csdb"));
67 insns.push((
68 Inst::Udf {
69 trap_code: TrapCode::STACK_OVERFLOW,
70 },
71 "1FC10000",
72 "udf #0xc11f",
73 ));
74 insns.push((
75 Inst::AluRRR {
76 alu_op: ALUOp::Add,
77 size: OperandSize::Size32,
78 rd: writable_xreg(1),
79 rn: xreg(2),
80 rm: xreg(3),
81 },
82 "4100030B",
83 "add w1, w2, w3",
84 ));
85 insns.push((
86 Inst::AluRRR {
87 alu_op: ALUOp::Add,
88 size: OperandSize::Size64,
89 rd: writable_xreg(4),
90 rn: xreg(5),
91 rm: xreg(6),
92 },
93 "A400068B",
94 "add x4, x5, x6",
95 ));
96 insns.push((
97 Inst::AluRRR {
98 alu_op: ALUOp::Adc,
99 size: OperandSize::Size32,
100 rd: writable_xreg(1),
101 rn: xreg(2),
102 rm: xreg(3),
103 },
104 "4100031A",
105 "adc w1, w2, w3",
106 ));
107 insns.push((
108 Inst::AluRRR {
109 alu_op: ALUOp::Adc,
110 size: OperandSize::Size64,
111 rd: writable_xreg(4),
112 rn: xreg(5),
113 rm: xreg(6),
114 },
115 "A400069A",
116 "adc x4, x5, x6",
117 ));
118 insns.push((
119 Inst::AluRRR {
120 alu_op: ALUOp::AdcS,
121 size: OperandSize::Size32,
122 rd: writable_xreg(1),
123 rn: xreg(2),
124 rm: xreg(3),
125 },
126 "4100033A",
127 "adcs w1, w2, w3",
128 ));
129 insns.push((
130 Inst::AluRRR {
131 alu_op: ALUOp::AdcS,
132 size: OperandSize::Size64,
133 rd: writable_xreg(4),
134 rn: xreg(5),
135 rm: xreg(6),
136 },
137 "A40006BA",
138 "adcs x4, x5, x6",
139 ));
140 insns.push((
141 Inst::AluRRR {
142 alu_op: ALUOp::Sub,
143 size: OperandSize::Size32,
144 rd: writable_xreg(1),
145 rn: xreg(2),
146 rm: xreg(3),
147 },
148 "4100034B",
149 "sub w1, w2, w3",
150 ));
151 insns.push((
152 Inst::AluRRR {
153 alu_op: ALUOp::Sub,
154 size: OperandSize::Size64,
155 rd: writable_xreg(4),
156 rn: xreg(5),
157 rm: xreg(6),
158 },
159 "A40006CB",
160 "sub x4, x5, x6",
161 ));
162 insns.push((
163 Inst::AluRRR {
164 alu_op: ALUOp::Sbc,
165 size: OperandSize::Size32,
166 rd: writable_xreg(1),
167 rn: xreg(2),
168 rm: xreg(3),
169 },
170 "4100035A",
171 "sbc w1, w2, w3",
172 ));
173 insns.push((
174 Inst::AluRRR {
175 alu_op: ALUOp::Sbc,
176 size: OperandSize::Size64,
177 rd: writable_xreg(4),
178 rn: xreg(5),
179 rm: xreg(6),
180 },
181 "A40006DA",
182 "sbc x4, x5, x6",
183 ));
184 insns.push((
185 Inst::AluRRR {
186 alu_op: ALUOp::SbcS,
187 size: OperandSize::Size32,
188 rd: writable_xreg(1),
189 rn: xreg(2),
190 rm: xreg(3),
191 },
192 "4100037A",
193 "sbcs w1, w2, w3",
194 ));
195 insns.push((
196 Inst::AluRRR {
197 alu_op: ALUOp::SbcS,
198 size: OperandSize::Size64,
199 rd: writable_xreg(4),
200 rn: xreg(5),
201 rm: xreg(6),
202 },
203 "A40006FA",
204 "sbcs x4, x5, x6",
205 ));
206
207 insns.push((
208 Inst::AluRRR {
209 alu_op: ALUOp::Orr,
210 size: OperandSize::Size32,
211 rd: writable_xreg(1),
212 rn: xreg(2),
213 rm: xreg(3),
214 },
215 "4100032A",
216 "orr w1, w2, w3",
217 ));
218 insns.push((
219 Inst::AluRRR {
220 alu_op: ALUOp::Orr,
221 size: OperandSize::Size64,
222 rd: writable_xreg(4),
223 rn: xreg(5),
224 rm: xreg(6),
225 },
226 "A40006AA",
227 "orr x4, x5, x6",
228 ));
229 insns.push((
230 Inst::AluRRR {
231 alu_op: ALUOp::And,
232 size: OperandSize::Size32,
233 rd: writable_xreg(1),
234 rn: xreg(2),
235 rm: xreg(3),
236 },
237 "4100030A",
238 "and w1, w2, w3",
239 ));
240 insns.push((
241 Inst::AluRRR {
242 alu_op: ALUOp::And,
243 size: OperandSize::Size64,
244 rd: writable_xreg(4),
245 rn: xreg(5),
246 rm: xreg(6),
247 },
248 "A400068A",
249 "and x4, x5, x6",
250 ));
251 insns.push((
252 Inst::AluRRR {
253 alu_op: ALUOp::AndS,
254 size: OperandSize::Size32,
255 rd: writable_xreg(1),
256 rn: xreg(2),
257 rm: xreg(3),
258 },
259 "4100036A",
260 "ands w1, w2, w3",
261 ));
262 insns.push((
263 Inst::AluRRR {
264 alu_op: ALUOp::AndS,
265 size: OperandSize::Size64,
266 rd: writable_xreg(4),
267 rn: xreg(5),
268 rm: xreg(6),
269 },
270 "A40006EA",
271 "ands x4, x5, x6",
272 ));
273 insns.push((
274 Inst::AluRRR {
275 alu_op: ALUOp::SubS,
276 size: OperandSize::Size32,
277 rd: writable_zero_reg(),
278 rn: xreg(2),
279 rm: xreg(3),
280 },
281 "5F00036B",
282 // TODO: Display as cmp
283 "subs wzr, w2, w3",
284 ));
285 insns.push((
286 Inst::AluRRR {
287 alu_op: ALUOp::SubS,
288 size: OperandSize::Size32,
289 rd: writable_xreg(1),
290 rn: xreg(2),
291 rm: xreg(3),
292 },
293 "4100036B",
294 "subs w1, w2, w3",
295 ));
296 insns.push((
297 Inst::AluRRR {
298 alu_op: ALUOp::SubS,
299 size: OperandSize::Size64,
300 rd: writable_xreg(4),
301 rn: xreg(5),
302 rm: xreg(6),
303 },
304 "A40006EB",
305 "subs x4, x5, x6",
306 ));
307 insns.push((
308 Inst::AluRRR {
309 alu_op: ALUOp::AddS,
310 size: OperandSize::Size32,
311 rd: writable_xreg(1),
312 rn: xreg(2),
313 rm: xreg(3),
314 },
315 "4100032B",
316 "adds w1, w2, w3",
317 ));
318 insns.push((
319 Inst::AluRRR {
320 alu_op: ALUOp::AddS,
321 size: OperandSize::Size64,
322 rd: writable_xreg(4),
323 rn: xreg(5),
324 rm: xreg(6),
325 },
326 "A40006AB",
327 "adds x4, x5, x6",
328 ));
329 insns.push((
330 Inst::AluRRImm12 {
331 alu_op: ALUOp::AddS,
332 size: OperandSize::Size64,
333 rd: writable_zero_reg(),
334 rn: xreg(5),
335 imm12: Imm12::maybe_from_u64(1).unwrap(),
336 },
337 "BF0400B1",
338 // TODO: Display as cmn.
339 "adds xzr, x5, #1",
340 ));
341 insns.push((
342 Inst::AluRRR {
343 alu_op: ALUOp::SDiv,
344 size: OperandSize::Size64,
345 rd: writable_xreg(4),
346 rn: xreg(5),
347 rm: xreg(6),
348 },
349 "A40CC69A",
350 "sdiv x4, x5, x6",
351 ));
352 insns.push((
353 Inst::AluRRR {
354 alu_op: ALUOp::UDiv,
355 size: OperandSize::Size64,
356 rd: writable_xreg(4),
357 rn: xreg(5),
358 rm: xreg(6),
359 },
360 "A408C69A",
361 "udiv x4, x5, x6",
362 ));
363
364 insns.push((
365 Inst::AluRRR {
366 alu_op: ALUOp::Eor,
367 size: OperandSize::Size32,
368 rd: writable_xreg(4),
369 rn: xreg(5),
370 rm: xreg(6),
371 },
372 "A400064A",
373 "eor w4, w5, w6",
374 ));
375 insns.push((
376 Inst::AluRRR {
377 alu_op: ALUOp::Eor,
378 size: OperandSize::Size64,
379 rd: writable_xreg(4),
380 rn: xreg(5),
381 rm: xreg(6),
382 },
383 "A40006CA",
384 "eor x4, x5, x6",
385 ));
386 insns.push((
387 Inst::AluRRR {
388 alu_op: ALUOp::AndNot,
389 size: OperandSize::Size32,
390 rd: writable_xreg(4),
391 rn: xreg(5),
392 rm: xreg(6),
393 },
394 "A400260A",
395 "bic w4, w5, w6",
396 ));
397 insns.push((
398 Inst::AluRRR {
399 alu_op: ALUOp::AndNot,
400 size: OperandSize::Size64,
401 rd: writable_xreg(4),
402 rn: xreg(5),
403 rm: xreg(6),
404 },
405 "A400268A",
406 "bic x4, x5, x6",
407 ));
408 insns.push((
409 Inst::AluRRR {
410 alu_op: ALUOp::OrrNot,
411 size: OperandSize::Size32,
412 rd: writable_xreg(4),
413 rn: xreg(5),
414 rm: xreg(6),
415 },
416 "A400262A",
417 "orn w4, w5, w6",
418 ));
419 insns.push((
420 Inst::AluRRR {
421 alu_op: ALUOp::OrrNot,
422 size: OperandSize::Size64,
423 rd: writable_xreg(4),
424 rn: xreg(5),
425 rm: xreg(6),
426 },
427 "A40026AA",
428 "orn x4, x5, x6",
429 ));
430 insns.push((
431 Inst::AluRRR {
432 alu_op: ALUOp::EorNot,
433 size: OperandSize::Size32,
434 rd: writable_xreg(4),
435 rn: xreg(5),
436 rm: xreg(6),
437 },
438 "A400264A",
439 "eon w4, w5, w6",
440 ));
441 insns.push((
442 Inst::AluRRR {
443 alu_op: ALUOp::EorNot,
444 size: OperandSize::Size64,
445 rd: writable_xreg(4),
446 rn: xreg(5),
447 rm: xreg(6),
448 },
449 "A40026CA",
450 "eon x4, x5, x6",
451 ));
452
453 insns.push((
454 Inst::AluRRR {
455 alu_op: ALUOp::Extr,
456 size: OperandSize::Size32,
457 rd: writable_xreg(4),
458 rn: xreg(5),
459 rm: xreg(6),
460 },
461 "A42CC61A",
462 "extr w4, w5, w6",
463 ));
464 insns.push((
465 Inst::AluRRR {
466 alu_op: ALUOp::Extr,
467 size: OperandSize::Size64,
468 rd: writable_xreg(4),
469 rn: xreg(5),
470 rm: xreg(6),
471 },
472 "A42CC69A",
473 "extr x4, x5, x6",
474 ));
475 insns.push((
476 Inst::AluRRR {
477 alu_op: ALUOp::Lsr,
478 size: OperandSize::Size32,
479 rd: writable_xreg(4),
480 rn: xreg(5),
481 rm: xreg(6),
482 },
483 "A424C61A",
484 "lsr w4, w5, w6",
485 ));
486 insns.push((
487 Inst::AluRRR {
488 alu_op: ALUOp::Lsr,
489 size: OperandSize::Size64,
490 rd: writable_xreg(4),
491 rn: xreg(5),
492 rm: xreg(6),
493 },
494 "A424C69A",
495 "lsr x4, x5, x6",
496 ));
497 insns.push((
498 Inst::AluRRR {
499 alu_op: ALUOp::Asr,
500 size: OperandSize::Size32,
501 rd: writable_xreg(4),
502 rn: xreg(5),
503 rm: xreg(6),
504 },
505 "A428C61A",
506 "asr w4, w5, w6",
507 ));
508 insns.push((
509 Inst::AluRRR {
510 alu_op: ALUOp::Asr,
511 size: OperandSize::Size64,
512 rd: writable_xreg(4),
513 rn: xreg(5),
514 rm: xreg(6),
515 },
516 "A428C69A",
517 "asr x4, x5, x6",
518 ));
519 insns.push((
520 Inst::AluRRR {
521 alu_op: ALUOp::Lsl,
522 size: OperandSize::Size32,
523 rd: writable_xreg(4),
524 rn: xreg(5),
525 rm: xreg(6),
526 },
527 "A420C61A",
528 "lsl w4, w5, w6",
529 ));
530 insns.push((
531 Inst::AluRRR {
532 alu_op: ALUOp::Lsl,
533 size: OperandSize::Size64,
534 rd: writable_xreg(4),
535 rn: xreg(5),
536 rm: xreg(6),
537 },
538 "A420C69A",
539 "lsl x4, x5, x6",
540 ));
541
542 insns.push((
543 Inst::AluRRImm12 {
544 alu_op: ALUOp::Add,
545 size: OperandSize::Size32,
546 rd: writable_xreg(7),
547 rn: xreg(8),
548 imm12: Imm12 {
549 bits: 0x123,
550 shift12: false,
551 },
552 },
553 "078D0411",
554 "add w7, w8, #291",
555 ));
556 insns.push((
557 Inst::AluRRImm12 {
558 alu_op: ALUOp::Add,
559 size: OperandSize::Size32,
560 rd: writable_xreg(7),
561 rn: xreg(8),
562 imm12: Imm12 {
563 bits: 0x123,
564 shift12: true,
565 },
566 },
567 "078D4411",
568 "add w7, w8, #1191936",
569 ));
570 insns.push((
571 Inst::AluRRImm12 {
572 alu_op: ALUOp::Add,
573 size: OperandSize::Size64,
574 rd: writable_xreg(7),
575 rn: xreg(8),
576 imm12: Imm12 {
577 bits: 0x123,
578 shift12: false,
579 },
580 },
581 "078D0491",
582 "add x7, x8, #291",
583 ));
584 insns.push((
585 Inst::AluRRImm12 {
586 alu_op: ALUOp::Sub,
587 size: OperandSize::Size32,
588 rd: writable_xreg(7),
589 rn: xreg(8),
590 imm12: Imm12 {
591 bits: 0x123,
592 shift12: false,
593 },
594 },
595 "078D0451",
596 "sub w7, w8, #291",
597 ));
598 insns.push((
599 Inst::AluRRImm12 {
600 alu_op: ALUOp::Sub,
601 size: OperandSize::Size64,
602 rd: writable_xreg(7),
603 rn: xreg(8),
604 imm12: Imm12 {
605 bits: 0x123,
606 shift12: false,
607 },
608 },
609 "078D04D1",
610 "sub x7, x8, #291",
611 ));
612 insns.push((
613 Inst::AluRRImm12 {
614 alu_op: ALUOp::SubS,
615 size: OperandSize::Size32,
616 rd: writable_xreg(7),
617 rn: xreg(8),
618 imm12: Imm12 {
619 bits: 0x123,
620 shift12: false,
621 },
622 },
623 "078D0471",
624 "subs w7, w8, #291",
625 ));
626 insns.push((
627 Inst::AluRRImm12 {
628 alu_op: ALUOp::SubS,
629 size: OperandSize::Size64,
630 rd: writable_xreg(7),
631 rn: xreg(8),
632 imm12: Imm12 {
633 bits: 0x123,
634 shift12: false,
635 },
636 },
637 "078D04F1",
638 "subs x7, x8, #291",
639 ));
640
641 insns.push((
642 Inst::AluRRRExtend {
643 alu_op: ALUOp::Add,
644 size: OperandSize::Size32,
645 rd: writable_xreg(7),
646 rn: xreg(8),
647 rm: xreg(9),
648 extendop: ExtendOp::SXTB,
649 },
650 "0781290B",
651 "add w7, w8, w9, SXTB",
652 ));
653
654 insns.push((
655 Inst::AluRRRExtend {
656 alu_op: ALUOp::Add,
657 size: OperandSize::Size64,
658 rd: writable_xreg(15),
659 rn: xreg(16),
660 rm: xreg(17),
661 extendop: ExtendOp::UXTB,
662 },
663 "0F02318B",
664 "add x15, x16, x17, UXTB",
665 ));
666
667 insns.push((
668 Inst::AluRRRExtend {
669 alu_op: ALUOp::Sub,
670 size: OperandSize::Size32,
671 rd: writable_xreg(1),
672 rn: xreg(2),
673 rm: xreg(3),
674 extendop: ExtendOp::SXTH,
675 },
676 "41A0234B",
677 "sub w1, w2, w3, SXTH",
678 ));
679
680 insns.push((
681 Inst::AluRRRExtend {
682 alu_op: ALUOp::Sub,
683 size: OperandSize::Size64,
684 rd: writable_xreg(20),
685 rn: xreg(21),
686 rm: xreg(22),
687 extendop: ExtendOp::UXTW,
688 },
689 "B44236CB",
690 "sub x20, x21, x22, UXTW",
691 ));
692
693 insns.push((
694 Inst::AluRRRShift {
695 alu_op: ALUOp::Add,
696 size: OperandSize::Size32,
697 rd: writable_xreg(10),
698 rn: xreg(11),
699 rm: xreg(12),
700 shiftop: ShiftOpAndAmt::new(
701 ShiftOp::LSL,
702 ShiftOpShiftImm::maybe_from_shift(20).unwrap(),
703 ),
704 },
705 "6A510C0B",
706 "add w10, w11, w12, LSL 20",
707 ));
708 insns.push((
709 Inst::AluRRRShift {
710 alu_op: ALUOp::Add,
711 size: OperandSize::Size64,
712 rd: writable_xreg(10),
713 rn: xreg(11),
714 rm: xreg(12),
715 shiftop: ShiftOpAndAmt::new(
716 ShiftOp::ASR,
717 ShiftOpShiftImm::maybe_from_shift(42).unwrap(),
718 ),
719 },
720 "6AA98C8B",
721 "add x10, x11, x12, ASR 42",
722 ));
723 insns.push((
724 Inst::AluRRRShift {
725 alu_op: ALUOp::Sub,
726 size: OperandSize::Size32,
727 rd: writable_xreg(10),
728 rn: xreg(11),
729 rm: xreg(12),
730 shiftop: ShiftOpAndAmt::new(
731 ShiftOp::LSL,
732 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
733 ),
734 },
735 "6A5D0C4B",
736 "sub w10, w11, w12, LSL 23",
737 ));
738 insns.push((
739 Inst::AluRRRShift {
740 alu_op: ALUOp::Sub,
741 size: OperandSize::Size64,
742 rd: writable_xreg(10),
743 rn: xreg(11),
744 rm: xreg(12),
745 shiftop: ShiftOpAndAmt::new(
746 ShiftOp::LSL,
747 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
748 ),
749 },
750 "6A5D0CCB",
751 "sub x10, x11, x12, LSL 23",
752 ));
753 insns.push((
754 Inst::AluRRRShift {
755 alu_op: ALUOp::Orr,
756 size: OperandSize::Size32,
757 rd: writable_xreg(10),
758 rn: xreg(11),
759 rm: xreg(12),
760 shiftop: ShiftOpAndAmt::new(
761 ShiftOp::LSL,
762 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
763 ),
764 },
765 "6A5D0C2A",
766 "orr w10, w11, w12, LSL 23",
767 ));
768 insns.push((
769 Inst::AluRRRShift {
770 alu_op: ALUOp::Orr,
771 size: OperandSize::Size64,
772 rd: writable_xreg(10),
773 rn: xreg(11),
774 rm: xreg(12),
775 shiftop: ShiftOpAndAmt::new(
776 ShiftOp::LSL,
777 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
778 ),
779 },
780 "6A5D0CAA",
781 "orr x10, x11, x12, LSL 23",
782 ));
783 insns.push((
784 Inst::AluRRRShift {
785 alu_op: ALUOp::And,
786 size: OperandSize::Size32,
787 rd: writable_xreg(10),
788 rn: xreg(11),
789 rm: xreg(12),
790 shiftop: ShiftOpAndAmt::new(
791 ShiftOp::LSL,
792 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
793 ),
794 },
795 "6A5D0C0A",
796 "and w10, w11, w12, LSL 23",
797 ));
798 insns.push((
799 Inst::AluRRRShift {
800 alu_op: ALUOp::And,
801 size: OperandSize::Size64,
802 rd: writable_xreg(10),
803 rn: xreg(11),
804 rm: xreg(12),
805 shiftop: ShiftOpAndAmt::new(
806 ShiftOp::LSL,
807 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
808 ),
809 },
810 "6A5D0C8A",
811 "and x10, x11, x12, LSL 23",
812 ));
813 insns.push((
814 Inst::AluRRRShift {
815 alu_op: ALUOp::AndS,
816 size: OperandSize::Size32,
817 rd: writable_xreg(10),
818 rn: xreg(11),
819 rm: xreg(12),
820 shiftop: ShiftOpAndAmt::new(
821 ShiftOp::LSL,
822 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
823 ),
824 },
825 "6A5D0C6A",
826 "ands w10, w11, w12, LSL 23",
827 ));
828 insns.push((
829 Inst::AluRRRShift {
830 alu_op: ALUOp::AndS,
831 size: OperandSize::Size64,
832 rd: writable_xreg(10),
833 rn: xreg(11),
834 rm: xreg(12),
835 shiftop: ShiftOpAndAmt::new(
836 ShiftOp::LSL,
837 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
838 ),
839 },
840 "6A5D0CEA",
841 "ands x10, x11, x12, LSL 23",
842 ));
843 insns.push((
844 Inst::AluRRRShift {
845 alu_op: ALUOp::Eor,
846 size: OperandSize::Size32,
847 rd: writable_xreg(10),
848 rn: xreg(11),
849 rm: xreg(12),
850 shiftop: ShiftOpAndAmt::new(
851 ShiftOp::LSL,
852 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
853 ),
854 },
855 "6A5D0C4A",
856 "eor w10, w11, w12, LSL 23",
857 ));
858 insns.push((
859 Inst::AluRRRShift {
860 alu_op: ALUOp::Eor,
861 size: OperandSize::Size64,
862 rd: writable_xreg(10),
863 rn: xreg(11),
864 rm: xreg(12),
865 shiftop: ShiftOpAndAmt::new(
866 ShiftOp::LSL,
867 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
868 ),
869 },
870 "6A5D0CCA",
871 "eor x10, x11, x12, LSL 23",
872 ));
873 insns.push((
874 Inst::AluRRRShift {
875 alu_op: ALUOp::OrrNot,
876 size: OperandSize::Size32,
877 rd: writable_xreg(10),
878 rn: xreg(11),
879 rm: xreg(12),
880 shiftop: ShiftOpAndAmt::new(
881 ShiftOp::LSL,
882 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
883 ),
884 },
885 "6A5D2C2A",
886 "orn w10, w11, w12, LSL 23",
887 ));
888 insns.push((
889 Inst::AluRRRShift {
890 alu_op: ALUOp::OrrNot,
891 size: OperandSize::Size64,
892 rd: writable_xreg(10),
893 rn: xreg(11),
894 rm: xreg(12),
895 shiftop: ShiftOpAndAmt::new(
896 ShiftOp::LSL,
897 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
898 ),
899 },
900 "6A5D2CAA",
901 "orn x10, x11, x12, LSL 23",
902 ));
903 insns.push((
904 Inst::AluRRRShift {
905 alu_op: ALUOp::AndNot,
906 size: OperandSize::Size32,
907 rd: writable_xreg(10),
908 rn: xreg(11),
909 rm: xreg(12),
910 shiftop: ShiftOpAndAmt::new(
911 ShiftOp::LSL,
912 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
913 ),
914 },
915 "6A5D2C0A",
916 "bic w10, w11, w12, LSL 23",
917 ));
918 insns.push((
919 Inst::AluRRRShift {
920 alu_op: ALUOp::AndNot,
921 size: OperandSize::Size64,
922 rd: writable_xreg(10),
923 rn: xreg(11),
924 rm: xreg(12),
925 shiftop: ShiftOpAndAmt::new(
926 ShiftOp::LSL,
927 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
928 ),
929 },
930 "6A5D2C8A",
931 "bic x10, x11, x12, LSL 23",
932 ));
933 insns.push((
934 Inst::AluRRRShift {
935 alu_op: ALUOp::EorNot,
936 size: OperandSize::Size32,
937 rd: writable_xreg(10),
938 rn: xreg(11),
939 rm: xreg(12),
940 shiftop: ShiftOpAndAmt::new(
941 ShiftOp::LSL,
942 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
943 ),
944 },
945 "6A5D2C4A",
946 "eon w10, w11, w12, LSL 23",
947 ));
948 insns.push((
949 Inst::AluRRRShift {
950 alu_op: ALUOp::EorNot,
951 size: OperandSize::Size64,
952 rd: writable_xreg(10),
953 rn: xreg(11),
954 rm: xreg(12),
955 shiftop: ShiftOpAndAmt::new(
956 ShiftOp::LSL,
957 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
958 ),
959 },
960 "6A5D2CCA",
961 "eon x10, x11, x12, LSL 23",
962 ));
963 insns.push((
964 Inst::AluRRRShift {
965 alu_op: ALUOp::AddS,
966 size: OperandSize::Size32,
967 rd: writable_xreg(10),
968 rn: xreg(11),
969 rm: xreg(12),
970 shiftop: ShiftOpAndAmt::new(
971 ShiftOp::LSL,
972 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
973 ),
974 },
975 "6A5D0C2B",
976 "adds w10, w11, w12, LSL 23",
977 ));
978 insns.push((
979 Inst::AluRRRShift {
980 alu_op: ALUOp::AddS,
981 size: OperandSize::Size64,
982 rd: writable_xreg(10),
983 rn: xreg(11),
984 rm: xreg(12),
985 shiftop: ShiftOpAndAmt::new(
986 ShiftOp::LSL,
987 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
988 ),
989 },
990 "6A5D0CAB",
991 "adds x10, x11, x12, LSL 23",
992 ));
993 insns.push((
994 Inst::AluRRRShift {
995 alu_op: ALUOp::SubS,
996 size: OperandSize::Size32,
997 rd: writable_xreg(10),
998 rn: xreg(11),
999 rm: xreg(12),
1000 shiftop: ShiftOpAndAmt::new(
1001 ShiftOp::LSL,
1002 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
1003 ),
1004 },
1005 "6A5D0C6B",
1006 "subs w10, w11, w12, LSL 23",
1007 ));
1008 insns.push((
1009 Inst::AluRRRShift {
1010 alu_op: ALUOp::SubS,
1011 size: OperandSize::Size64,
1012 rd: writable_xreg(10),
1013 rn: xreg(11),
1014 rm: xreg(12),
1015 shiftop: ShiftOpAndAmt::new(
1016 ShiftOp::LSL,
1017 ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
1018 ),
1019 },
1020 "6A5D0CEB",
1021 "subs x10, x11, x12, LSL 23",
1022 ));
1023
1024 insns.push((
1025 Inst::AluRRRExtend {
1026 alu_op: ALUOp::SubS,
1027 size: OperandSize::Size64,
1028 rd: writable_zero_reg(),
1029 rn: stack_reg(),
1030 rm: xreg(12),
1031 extendop: ExtendOp::UXTX,
1032 },
1033 "FF632CEB",
1034 "subs xzr, sp, x12, UXTX",
1035 ));
1036
1037 insns.push((
1038 Inst::AluRRRR {
1039 alu_op: ALUOp3::MAdd,
1040 size: OperandSize::Size32,
1041 rd: writable_xreg(1),
1042 rn: xreg(2),
1043 rm: xreg(3),
1044 ra: xreg(4),
1045 },
1046 "4110031B",
1047 "madd w1, w2, w3, w4",
1048 ));
1049 insns.push((
1050 Inst::AluRRRR {
1051 alu_op: ALUOp3::MAdd,
1052 size: OperandSize::Size64,
1053 rd: writable_xreg(1),
1054 rn: xreg(2),
1055 rm: xreg(3),
1056 ra: xreg(4),
1057 },
1058 "4110039B",
1059 "madd x1, x2, x3, x4",
1060 ));
1061 insns.push((
1062 Inst::AluRRRR {
1063 alu_op: ALUOp3::MSub,
1064 size: OperandSize::Size32,
1065 rd: writable_xreg(1),
1066 rn: xreg(2),
1067 rm: xreg(3),
1068 ra: xreg(4),
1069 },
1070 "4190031B",
1071 "msub w1, w2, w3, w4",
1072 ));
1073 insns.push((
1074 Inst::AluRRRR {
1075 alu_op: ALUOp3::MSub,
1076 size: OperandSize::Size64,
1077 rd: writable_xreg(1),
1078 rn: xreg(2),
1079 rm: xreg(3),
1080 ra: xreg(4),
1081 },
1082 "4190039B",
1083 "msub x1, x2, x3, x4",
1084 ));
1085 insns.push((
1086 Inst::AluRRRR {
1087 alu_op: ALUOp3::UMAddL,
1088 size: OperandSize::Size32,
1089 rd: writable_xreg(1),
1090 rn: xreg(2),
1091 rm: xreg(3),
1092 ra: xreg(4),
1093 },
1094 "4110A39B",
1095 "umaddl x1, w2, w3, x4",
1096 ));
1097 insns.push((
1098 Inst::AluRRRR {
1099 alu_op: ALUOp3::SMAddL,
1100 size: OperandSize::Size32,
1101 rd: writable_xreg(1),
1102 rn: xreg(2),
1103 rm: xreg(3),
1104 ra: xreg(4),
1105 },
1106 "4110239B",
1107 "smaddl x1, w2, w3, x4",
1108 ));
1109 insns.push((
1110 Inst::AluRRR {
1111 alu_op: ALUOp::SMulH,
1112 size: OperandSize::Size64,
1113 rd: writable_xreg(1),
1114 rn: xreg(2),
1115 rm: xreg(3),
1116 },
1117 "417C439B",
1118 "smulh x1, x2, x3",
1119 ));
1120 insns.push((
1121 Inst::AluRRR {
1122 alu_op: ALUOp::UMulH,
1123 size: OperandSize::Size64,
1124 rd: writable_xreg(1),
1125 rn: xreg(2),
1126 rm: xreg(3),
1127 },
1128 "417CC39B",
1129 "umulh x1, x2, x3",
1130 ));
1131
1132 insns.push((
1133 Inst::AluRRImmShift {
1134 alu_op: ALUOp::Extr,
1135 size: OperandSize::Size32,
1136 rd: writable_xreg(20),
1137 rn: xreg(21),
1138 immshift: ImmShift::maybe_from_u64(19).unwrap(),
1139 },
1140 "B44E9513",
1141 "extr w20, w21, #19",
1142 ));
1143 insns.push((
1144 Inst::AluRRImmShift {
1145 alu_op: ALUOp::Extr,
1146 size: OperandSize::Size64,
1147 rd: writable_xreg(20),
1148 rn: xreg(21),
1149 immshift: ImmShift::maybe_from_u64(42).unwrap(),
1150 },
1151 "B4AAD593",
1152 "extr x20, x21, #42",
1153 ));
1154 insns.push((
1155 Inst::AluRRImmShift {
1156 alu_op: ALUOp::Lsr,
1157 size: OperandSize::Size32,
1158 rd: writable_xreg(10),
1159 rn: xreg(11),
1160 immshift: ImmShift::maybe_from_u64(13).unwrap(),
1161 },
1162 "6A7D0D53",
1163 "lsr w10, w11, #13",
1164 ));
1165 insns.push((
1166 Inst::AluRRImmShift {
1167 alu_op: ALUOp::Lsr,
1168 size: OperandSize::Size64,
1169 rd: writable_xreg(10),
1170 rn: xreg(11),
1171 immshift: ImmShift::maybe_from_u64(57).unwrap(),
1172 },
1173 "6AFD79D3",
1174 "lsr x10, x11, #57",
1175 ));
1176 insns.push((
1177 Inst::AluRRImmShift {
1178 alu_op: ALUOp::Asr,
1179 size: OperandSize::Size32,
1180 rd: writable_xreg(4),
1181 rn: xreg(5),
1182 immshift: ImmShift::maybe_from_u64(7).unwrap(),
1183 },
1184 "A47C0713",
1185 "asr w4, w5, #7",
1186 ));
1187 insns.push((
1188 Inst::AluRRImmShift {
1189 alu_op: ALUOp::Asr,
1190 size: OperandSize::Size64,
1191 rd: writable_xreg(4),
1192 rn: xreg(5),
1193 immshift: ImmShift::maybe_from_u64(35).unwrap(),
1194 },
1195 "A4FC6393",
1196 "asr x4, x5, #35",
1197 ));
1198 insns.push((
1199 Inst::AluRRImmShift {
1200 alu_op: ALUOp::Lsl,
1201 size: OperandSize::Size32,
1202 rd: writable_xreg(8),
1203 rn: xreg(9),
1204 immshift: ImmShift::maybe_from_u64(24).unwrap(),
1205 },
1206 "281D0853",
1207 "lsl w8, w9, #24",
1208 ));
1209 insns.push((
1210 Inst::AluRRImmShift {
1211 alu_op: ALUOp::Lsl,
1212 size: OperandSize::Size64,
1213 rd: writable_xreg(8),
1214 rn: xreg(9),
1215 immshift: ImmShift::maybe_from_u64(63).unwrap(),
1216 },
1217 "280141D3",
1218 "lsl x8, x9, #63",
1219 ));
1220 insns.push((
1221 Inst::AluRRImmShift {
1222 alu_op: ALUOp::Lsl,
1223 size: OperandSize::Size32,
1224 rd: writable_xreg(10),
1225 rn: xreg(11),
1226 immshift: ImmShift::maybe_from_u64(0).unwrap(),
1227 },
1228 "6A7D0053",
1229 "lsl w10, w11, #0",
1230 ));
1231 insns.push((
1232 Inst::AluRRImmShift {
1233 alu_op: ALUOp::Lsl,
1234 size: OperandSize::Size64,
1235 rd: writable_xreg(10),
1236 rn: xreg(11),
1237 immshift: ImmShift::maybe_from_u64(0).unwrap(),
1238 },
1239 "6AFD40D3",
1240 "lsl x10, x11, #0",
1241 ));
1242
1243 insns.push((
1244 Inst::AluRRImmLogic {
1245 alu_op: ALUOp::And,
1246 size: OperandSize::Size32,
1247 rd: writable_xreg(21),
1248 rn: xreg(27),
1249 imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
1250 },
1251 "753B0112",
1252 "and w21, w27, #2147500031",
1253 ));
1254 insns.push((
1255 Inst::AluRRImmLogic {
1256 alu_op: ALUOp::And,
1257 size: OperandSize::Size64,
1258 rd: writable_xreg(7),
1259 rn: xreg(6),
1260 imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
1261 },
1262 "C7381592",
1263 "and x7, x6, #288221580125796352",
1264 ));
1265 insns.push((
1266 Inst::AluRRImmLogic {
1267 alu_op: ALUOp::AndS,
1268 size: OperandSize::Size32,
1269 rd: writable_xreg(21),
1270 rn: xreg(27),
1271 imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
1272 },
1273 "753B0172",
1274 "ands w21, w27, #2147500031",
1275 ));
1276 insns.push((
1277 Inst::AluRRImmLogic {
1278 alu_op: ALUOp::AndS,
1279 size: OperandSize::Size64,
1280 rd: writable_xreg(7),
1281 rn: xreg(6),
1282 imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
1283 },
1284 "C73815F2",
1285 "ands x7, x6, #288221580125796352",
1286 ));
1287 insns.push((
1288 Inst::AluRRImmLogic {
1289 alu_op: ALUOp::Orr,
1290 size: OperandSize::Size32,
1291 rd: writable_xreg(1),
1292 rn: xreg(5),
1293 imml: ImmLogic::maybe_from_u64(0x100000, I32).unwrap(),
1294 },
1295 "A1000C32",
1296 "orr w1, w5, #1048576",
1297 ));
1298 insns.push((
1299 Inst::AluRRImmLogic {
1300 alu_op: ALUOp::Orr,
1301 size: OperandSize::Size64,
1302 rd: writable_xreg(4),
1303 rn: xreg(5),
1304 imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1305 },
1306 "A4C401B2",
1307 "orr x4, x5, #9331882296111890817",
1308 ));
1309 insns.push((
1310 Inst::AluRRImmLogic {
1311 alu_op: ALUOp::Eor,
1312 size: OperandSize::Size32,
1313 rd: writable_xreg(1),
1314 rn: xreg(5),
1315 imml: ImmLogic::maybe_from_u64(0x00007fff, I32).unwrap(),
1316 },
1317 "A1380052",
1318 "eor w1, w5, #32767",
1319 ));
1320 insns.push((
1321 Inst::AluRRImmLogic {
1322 alu_op: ALUOp::Eor,
1323 size: OperandSize::Size64,
1324 rd: writable_xreg(10),
1325 rn: xreg(8),
1326 imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
1327 },
1328 "0AC501D2",
1329 "eor x10, x8, #9331882296111890817",
1330 ));
1331
1332 insns.push((
1333 Inst::BitRR {
1334 op: BitOp::RBit,
1335 size: OperandSize::Size32,
1336 rd: writable_xreg(1),
1337 rn: xreg(10),
1338 },
1339 "4101C05A",
1340 "rbit w1, w10",
1341 ));
1342
1343 insns.push((
1344 Inst::BitRR {
1345 op: BitOp::RBit,
1346 size: OperandSize::Size64,
1347 rd: writable_xreg(1),
1348 rn: xreg(10),
1349 },
1350 "4101C0DA",
1351 "rbit x1, x10",
1352 ));
1353
1354 insns.push((
1355 Inst::BitRR {
1356 op: BitOp::Clz,
1357 size: OperandSize::Size32,
1358 rd: writable_xreg(15),
1359 rn: xreg(3),
1360 },
1361 "6F10C05A",
1362 "clz w15, w3",
1363 ));
1364
1365 insns.push((
1366 Inst::BitRR {
1367 op: BitOp::Clz,
1368 size: OperandSize::Size64,
1369 rd: writable_xreg(15),
1370 rn: xreg(3),
1371 },
1372 "6F10C0DA",
1373 "clz x15, x3",
1374 ));
1375
1376 insns.push((
1377 Inst::BitRR {
1378 op: BitOp::Cls,
1379 size: OperandSize::Size32,
1380 rd: writable_xreg(21),
1381 rn: xreg(16),
1382 },
1383 "1516C05A",
1384 "cls w21, w16",
1385 ));
1386
1387 insns.push((
1388 Inst::BitRR {
1389 op: BitOp::Cls,
1390 size: OperandSize::Size64,
1391 rd: writable_xreg(21),
1392 rn: xreg(16),
1393 },
1394 "1516C0DA",
1395 "cls x21, x16",
1396 ));
1397
1398 insns.push((
1399 Inst::BitRR {
1400 op: BitOp::Rev16,
1401 size: OperandSize::Size64,
1402 rd: writable_xreg(2),
1403 rn: xreg(11),
1404 },
1405 "6205C0DA",
1406 "rev16 x2, x11",
1407 ));
1408
1409 insns.push((
1410 Inst::BitRR {
1411 op: BitOp::Rev16,
1412 size: OperandSize::Size32,
1413 rd: writable_xreg(3),
1414 rn: xreg(21),
1415 },
1416 "A306C05A",
1417 "rev16 w3, w21",
1418 ));
1419
1420 insns.push((
1421 Inst::BitRR {
1422 op: BitOp::Rev32,
1423 size: OperandSize::Size64,
1424 rd: writable_xreg(2),
1425 rn: xreg(11),
1426 },
1427 "6209C0DA",
1428 "rev32 x2, x11",
1429 ));
1430
1431 insns.push((
1432 Inst::BitRR {
1433 op: BitOp::Rev32,
1434 size: OperandSize::Size32,
1435 rd: writable_xreg(3),
1436 rn: xreg(21),
1437 },
1438 "A30AC05A",
1439 "rev32 w3, w21",
1440 ));
1441
1442 insns.push((
1443 Inst::BitRR {
1444 op: BitOp::Rev64,
1445 size: OperandSize::Size64,
1446 rd: writable_xreg(1),
1447 rn: xreg(10),
1448 },
1449 "410DC0DA",
1450 "rev64 x1, x10",
1451 ));
1452
1453 insns.push((
1454 Inst::ULoad8 {
1455 rd: writable_xreg(1),
1456 mem: AMode::Unscaled {
1457 rn: xreg(2),
1458 simm9: simm9_zero(),
1459 },
1460 flags: MemFlags::trusted(),
1461 },
1462 "41004038",
1463 "ldurb w1, [x2]",
1464 ));
1465 insns.push((
1466 Inst::ULoad8 {
1467 rd: writable_xreg(1),
1468 mem: AMode::UnsignedOffset {
1469 rn: xreg(2),
1470 uimm12: UImm12Scaled::zero(I8),
1471 },
1472 flags: MemFlags::trusted(),
1473 },
1474 "41004039",
1475 "ldrb w1, [x2]",
1476 ));
1477 insns.push((
1478 Inst::ULoad8 {
1479 rd: writable_xreg(1),
1480 mem: AMode::RegReg {
1481 rn: xreg(2),
1482 rm: xreg(5),
1483 },
1484 flags: MemFlags::trusted(),
1485 },
1486 "41686538",
1487 "ldrb w1, [x2, x5]",
1488 ));
1489 insns.push((
1490 Inst::SLoad8 {
1491 rd: writable_xreg(1),
1492 mem: AMode::Unscaled {
1493 rn: xreg(2),
1494 simm9: simm9_zero(),
1495 },
1496 flags: MemFlags::trusted(),
1497 },
1498 "41008038",
1499 "ldursb x1, [x2]",
1500 ));
1501 insns.push((
1502 Inst::SLoad8 {
1503 rd: writable_xreg(1),
1504 mem: AMode::UnsignedOffset {
1505 rn: xreg(2),
1506 uimm12: UImm12Scaled::maybe_from_i64(63, I8).unwrap(),
1507 },
1508 flags: MemFlags::trusted(),
1509 },
1510 "41FC8039",
1511 "ldrsb x1, [x2, #63]",
1512 ));
1513 insns.push((
1514 Inst::SLoad8 {
1515 rd: writable_xreg(1),
1516 mem: AMode::RegReg {
1517 rn: xreg(2),
1518 rm: xreg(5),
1519 },
1520 flags: MemFlags::trusted(),
1521 },
1522 "4168A538",
1523 "ldrsb x1, [x2, x5]",
1524 ));
1525 insns.push((
1526 Inst::ULoad16 {
1527 rd: writable_xreg(1),
1528 mem: AMode::Unscaled {
1529 rn: xreg(2),
1530 simm9: SImm9::maybe_from_i64(5).unwrap(),
1531 },
1532 flags: MemFlags::trusted(),
1533 },
1534 "41504078",
1535 "ldurh w1, [x2, #5]",
1536 ));
1537 insns.push((
1538 Inst::ULoad16 {
1539 rd: writable_xreg(1),
1540 mem: AMode::UnsignedOffset {
1541 rn: xreg(2),
1542 uimm12: UImm12Scaled::maybe_from_i64(8, I16).unwrap(),
1543 },
1544 flags: MemFlags::trusted(),
1545 },
1546 "41104079",
1547 "ldrh w1, [x2, #8]",
1548 ));
1549 insns.push((
1550 Inst::ULoad16 {
1551 rd: writable_xreg(1),
1552 mem: AMode::RegScaled {
1553 rn: xreg(2),
1554 rm: xreg(3),
1555 },
1556 flags: MemFlags::trusted(),
1557 },
1558 "41786378",
1559 "ldrh w1, [x2, x3, LSL #1]",
1560 ));
1561 insns.push((
1562 Inst::SLoad16 {
1563 rd: writable_xreg(1),
1564 mem: AMode::Unscaled {
1565 rn: xreg(2),
1566 simm9: simm9_zero(),
1567 },
1568 flags: MemFlags::trusted(),
1569 },
1570 "41008078",
1571 "ldursh x1, [x2]",
1572 ));
1573 insns.push((
1574 Inst::SLoad16 {
1575 rd: writable_xreg(28),
1576 mem: AMode::UnsignedOffset {
1577 rn: xreg(20),
1578 uimm12: UImm12Scaled::maybe_from_i64(24, I16).unwrap(),
1579 },
1580 flags: MemFlags::trusted(),
1581 },
1582 "9C328079",
1583 "ldrsh x28, [x20, #24]",
1584 ));
1585 insns.push((
1586 Inst::SLoad16 {
1587 rd: writable_xreg(28),
1588 mem: AMode::RegScaled {
1589 rn: xreg(20),
1590 rm: xreg(20),
1591 },
1592 flags: MemFlags::trusted(),
1593 },
1594 "9C7AB478",
1595 "ldrsh x28, [x20, x20, LSL #1]",
1596 ));
1597 insns.push((
1598 Inst::ULoad32 {
1599 rd: writable_xreg(1),
1600 mem: AMode::Unscaled {
1601 rn: xreg(2),
1602 simm9: simm9_zero(),
1603 },
1604 flags: MemFlags::trusted(),
1605 },
1606 "410040B8",
1607 "ldur w1, [x2]",
1608 ));
1609 insns.push((
1610 Inst::ULoad32 {
1611 rd: writable_xreg(12),
1612 mem: AMode::UnsignedOffset {
1613 rn: xreg(0),
1614 uimm12: UImm12Scaled::maybe_from_i64(204, I32).unwrap(),
1615 },
1616 flags: MemFlags::trusted(),
1617 },
1618 "0CCC40B9",
1619 "ldr w12, [x0, #204]",
1620 ));
1621 insns.push((
1622 Inst::ULoad32 {
1623 rd: writable_xreg(1),
1624 mem: AMode::RegScaled {
1625 rn: xreg(2),
1626 rm: xreg(12),
1627 },
1628 flags: MemFlags::trusted(),
1629 },
1630 "41786CB8",
1631 "ldr w1, [x2, x12, LSL #2]",
1632 ));
1633 insns.push((
1634 Inst::SLoad32 {
1635 rd: writable_xreg(1),
1636 mem: AMode::Unscaled {
1637 rn: xreg(2),
1638 simm9: simm9_zero(),
1639 },
1640 flags: MemFlags::trusted(),
1641 },
1642 "410080B8",
1643 "ldursw x1, [x2]",
1644 ));
1645 insns.push((
1646 Inst::SLoad32 {
1647 rd: writable_xreg(12),
1648 mem: AMode::UnsignedOffset {
1649 rn: xreg(1),
1650 uimm12: UImm12Scaled::maybe_from_i64(16380, I32).unwrap(),
1651 },
1652 flags: MemFlags::trusted(),
1653 },
1654 "2CFCBFB9",
1655 "ldrsw x12, [x1, #16380]",
1656 ));
1657 insns.push((
1658 Inst::SLoad32 {
1659 rd: writable_xreg(1),
1660 mem: AMode::RegScaled {
1661 rn: xreg(5),
1662 rm: xreg(1),
1663 },
1664 flags: MemFlags::trusted(),
1665 },
1666 "A178A1B8",
1667 "ldrsw x1, [x5, x1, LSL #2]",
1668 ));
1669 insns.push((
1670 Inst::ULoad64 {
1671 rd: writable_xreg(1),
1672 mem: AMode::Unscaled {
1673 rn: xreg(2),
1674 simm9: simm9_zero(),
1675 },
1676 flags: MemFlags::trusted(),
1677 },
1678 "410040F8",
1679 "ldur x1, [x2]",
1680 ));
1681 insns.push((
1682 Inst::ULoad64 {
1683 rd: writable_xreg(1),
1684 mem: AMode::Unscaled {
1685 rn: xreg(2),
1686 simm9: SImm9::maybe_from_i64(-256).unwrap(),
1687 },
1688 flags: MemFlags::trusted(),
1689 },
1690 "410050F8",
1691 "ldur x1, [x2, #-256]",
1692 ));
1693 insns.push((
1694 Inst::ULoad64 {
1695 rd: writable_xreg(1),
1696 mem: AMode::Unscaled {
1697 rn: xreg(2),
1698 simm9: SImm9::maybe_from_i64(255).unwrap(),
1699 },
1700 flags: MemFlags::trusted(),
1701 },
1702 "41F04FF8",
1703 "ldur x1, [x2, #255]",
1704 ));
1705 insns.push((
1706 Inst::ULoad64 {
1707 rd: writable_xreg(1),
1708 mem: AMode::UnsignedOffset {
1709 rn: xreg(2),
1710 uimm12: UImm12Scaled::maybe_from_i64(32760, I64).unwrap(),
1711 },
1712 flags: MemFlags::trusted(),
1713 },
1714 "41FC7FF9",
1715 "ldr x1, [x2, #32760]",
1716 ));
1717 insns.push((
1718 Inst::ULoad64 {
1719 rd: writable_xreg(1),
1720 mem: AMode::RegReg {
1721 rn: xreg(2),
1722 rm: xreg(3),
1723 },
1724 flags: MemFlags::trusted(),
1725 },
1726 "416863F8",
1727 "ldr x1, [x2, x3]",
1728 ));
1729 insns.push((
1730 Inst::ULoad64 {
1731 rd: writable_xreg(1),
1732 mem: AMode::RegScaled {
1733 rn: xreg(2),
1734 rm: xreg(3),
1735 },
1736 flags: MemFlags::trusted(),
1737 },
1738 "417863F8",
1739 "ldr x1, [x2, x3, LSL #3]",
1740 ));
1741 insns.push((
1742 Inst::ULoad64 {
1743 rd: writable_xreg(1),
1744 mem: AMode::RegScaledExtended {
1745 rn: xreg(2),
1746 rm: xreg(3),
1747 extendop: ExtendOp::SXTW,
1748 },
1749 flags: MemFlags::trusted(),
1750 },
1751 "41D863F8",
1752 "ldr x1, [x2, w3, SXTW #3]",
1753 ));
1754 insns.push((
1755 Inst::ULoad64 {
1756 rd: writable_xreg(1),
1757 mem: AMode::RegExtended {
1758 rn: xreg(2),
1759 rm: xreg(3),
1760 extendop: ExtendOp::SXTW,
1761 },
1762 flags: MemFlags::trusted(),
1763 },
1764 "41C863F8",
1765 "ldr x1, [x2, w3, SXTW]",
1766 ));
1767 insns.push((
1768 Inst::ULoad64 {
1769 rd: writable_xreg(1),
1770 mem: AMode::Label {
1771 label: MemLabel::PCRel(64),
1772 },
1773 flags: MemFlags::trusted(),
1774 },
1775 "01020058",
1776 "ldr x1, pc+64",
1777 ));
1778 insns.push((
1779 Inst::ULoad64 {
1780 rd: writable_xreg(1),
1781 mem: AMode::SPPreIndexed {
1782 simm9: SImm9::maybe_from_i64(16).unwrap(),
1783 },
1784 flags: MemFlags::trusted(),
1785 },
1786 "E10F41F8",
1787 "ldr x1, [sp, #16]!",
1788 ));
1789 insns.push((
1790 Inst::ULoad64 {
1791 rd: writable_xreg(1),
1792 mem: AMode::SPPostIndexed {
1793 simm9: SImm9::maybe_from_i64(16).unwrap(),
1794 },
1795 flags: MemFlags::trusted(),
1796 },
1797 "E10741F8",
1798 "ldr x1, [sp], #16",
1799 ));
1800 insns.push((
1801 Inst::ULoad64 {
1802 rd: writable_xreg(1),
1803 mem: AMode::FPOffset { off: 32768 },
1804 flags: MemFlags::trusted(),
1805 },
1806 "100090D2A1EB70F8",
1807 "movz x16, #32768 ; ldr x1, [fp, x16, SXTX]",
1808 ));
1809 insns.push((
1810 Inst::ULoad64 {
1811 rd: writable_xreg(1),
1812 mem: AMode::FPOffset { off: -32768 },
1813 flags: MemFlags::trusted(),
1814 },
1815 "F0FF8F92A1EB70F8",
1816 "movn x16, #32767 ; ldr x1, [fp, x16, SXTX]",
1817 ));
1818 insns.push((
1819 Inst::ULoad64 {
1820 rd: writable_xreg(1),
1821 mem: AMode::FPOffset { off: 1048576 }, // 2^20
1822 flags: MemFlags::trusted(),
1823 },
1824 "1002A0D2A1EB70F8",
1825 "movz x16, #16, LSL #16 ; ldr x1, [fp, x16, SXTX]",
1826 ));
1827 insns.push((
1828 Inst::ULoad64 {
1829 rd: writable_xreg(1),
1830 mem: AMode::FPOffset { off: 1048576 + 1 }, // 2^20 + 1
1831 flags: MemFlags::trusted(),
1832 },
1833 "300080521002A072A1EB70F8",
1834 "movz w16, #1 ; movk w16, w16, #16, LSL #16 ; ldr x1, [fp, x16, SXTX]",
1835 ));
1836
1837 insns.push((
1838 Inst::ULoad64 {
1839 rd: writable_xreg(1),
1840 mem: AMode::RegOffset {
1841 rn: xreg(7),
1842 off: 8,
1843 },
1844 flags: MemFlags::trusted(),
1845 },
1846 "E18040F8",
1847 "ldr x1, [x7, #8]",
1848 ));
1849
1850 insns.push((
1851 Inst::ULoad64 {
1852 rd: writable_xreg(1),
1853 mem: AMode::RegOffset {
1854 rn: xreg(7),
1855 off: 1024,
1856 },
1857 flags: MemFlags::trusted(),
1858 },
1859 "E10042F9",
1860 "ldr x1, [x7, #1024]",
1861 ));
1862
1863 insns.push((
1864 Inst::ULoad64 {
1865 rd: writable_xreg(1),
1866 mem: AMode::RegOffset {
1867 rn: xreg(7),
1868 off: 1048576,
1869 },
1870 flags: MemFlags::trusted(),
1871 },
1872 "1002A0D2E1E870F8",
1873 "movz x16, #16, LSL #16 ; ldr x1, [x7, x16, SXTX]",
1874 ));
1875
1876 insns.push((
1877 Inst::Store8 {
1878 rd: xreg(1),
1879 mem: AMode::Unscaled {
1880 rn: xreg(2),
1881 simm9: simm9_zero(),
1882 },
1883 flags: MemFlags::trusted(),
1884 },
1885 "41000038",
1886 "sturb w1, [x2]",
1887 ));
1888 insns.push((
1889 Inst::Store8 {
1890 rd: xreg(1),
1891 mem: AMode::UnsignedOffset {
1892 rn: xreg(2),
1893 uimm12: UImm12Scaled::maybe_from_i64(4095, I8).unwrap(),
1894 },
1895 flags: MemFlags::trusted(),
1896 },
1897 "41FC3F39",
1898 "strb w1, [x2, #4095]",
1899 ));
1900 insns.push((
1901 Inst::Store16 {
1902 rd: xreg(1),
1903 mem: AMode::Unscaled {
1904 rn: xreg(2),
1905 simm9: simm9_zero(),
1906 },
1907 flags: MemFlags::trusted(),
1908 },
1909 "41000078",
1910 "sturh w1, [x2]",
1911 ));
1912 insns.push((
1913 Inst::Store16 {
1914 rd: xreg(1),
1915 mem: AMode::UnsignedOffset {
1916 rn: xreg(2),
1917 uimm12: UImm12Scaled::maybe_from_i64(8190, I16).unwrap(),
1918 },
1919 flags: MemFlags::trusted(),
1920 },
1921 "41FC3F79",
1922 "strh w1, [x2, #8190]",
1923 ));
1924 insns.push((
1925 Inst::Store32 {
1926 rd: xreg(1),
1927 mem: AMode::Unscaled {
1928 rn: xreg(2),
1929 simm9: simm9_zero(),
1930 },
1931 flags: MemFlags::trusted(),
1932 },
1933 "410000B8",
1934 "stur w1, [x2]",
1935 ));
1936 insns.push((
1937 Inst::Store32 {
1938 rd: xreg(1),
1939 mem: AMode::UnsignedOffset {
1940 rn: xreg(2),
1941 uimm12: UImm12Scaled::maybe_from_i64(16380, I32).unwrap(),
1942 },
1943 flags: MemFlags::trusted(),
1944 },
1945 "41FC3FB9",
1946 "str w1, [x2, #16380]",
1947 ));
1948 insns.push((
1949 Inst::Store64 {
1950 rd: xreg(1),
1951 mem: AMode::Unscaled {
1952 rn: xreg(2),
1953 simm9: simm9_zero(),
1954 },
1955 flags: MemFlags::trusted(),
1956 },
1957 "410000F8",
1958 "stur x1, [x2]",
1959 ));
1960 insns.push((
1961 Inst::Store64 {
1962 rd: xreg(1),
1963 mem: AMode::UnsignedOffset {
1964 rn: xreg(2),
1965 uimm12: UImm12Scaled::maybe_from_i64(32760, I64).unwrap(),
1966 },
1967 flags: MemFlags::trusted(),
1968 },
1969 "41FC3FF9",
1970 "str x1, [x2, #32760]",
1971 ));
1972 insns.push((
1973 Inst::Store64 {
1974 rd: xreg(1),
1975 mem: AMode::RegReg {
1976 rn: xreg(2),
1977 rm: xreg(3),
1978 },
1979 flags: MemFlags::trusted(),
1980 },
1981 "416823F8",
1982 "str x1, [x2, x3]",
1983 ));
1984 insns.push((
1985 Inst::Store64 {
1986 rd: xreg(1),
1987 mem: AMode::RegScaled {
1988 rn: xreg(2),
1989 rm: xreg(3),
1990 },
1991 flags: MemFlags::trusted(),
1992 },
1993 "417823F8",
1994 "str x1, [x2, x3, LSL #3]",
1995 ));
1996 insns.push((
1997 Inst::Store64 {
1998 rd: xreg(1),
1999 mem: AMode::RegScaledExtended {
2000 rn: xreg(2),
2001 rm: xreg(3),
2002 extendop: ExtendOp::UXTW,
2003 },
2004 flags: MemFlags::trusted(),
2005 },
2006 "415823F8",
2007 "str x1, [x2, w3, UXTW #3]",
2008 ));
2009 insns.push((
2010 Inst::Store64 {
2011 rd: xreg(1),
2012 mem: AMode::RegExtended {
2013 rn: xreg(2),
2014 rm: xreg(3),
2015 extendop: ExtendOp::UXTW,
2016 },
2017 flags: MemFlags::trusted(),
2018 },
2019 "414823F8",
2020 "str x1, [x2, w3, UXTW]",
2021 ));
2022 insns.push((
2023 Inst::Store64 {
2024 rd: xreg(1),
2025 mem: AMode::SPPreIndexed {
2026 simm9: SImm9::maybe_from_i64(16).unwrap(),
2027 },
2028 flags: MemFlags::trusted(),
2029 },
2030 "E10F01F8",
2031 "str x1, [sp, #16]!",
2032 ));
2033 insns.push((
2034 Inst::Store64 {
2035 rd: xreg(1),
2036 mem: AMode::SPPostIndexed {
2037 simm9: SImm9::maybe_from_i64(16).unwrap(),
2038 },
2039 flags: MemFlags::trusted(),
2040 },
2041 "E10701F8",
2042 "str x1, [sp], #16",
2043 ));
2044
2045 insns.push((
2046 Inst::StoreP64 {
2047 rt: xreg(8),
2048 rt2: xreg(9),
2049 mem: PairAMode::SignedOffset {
2050 reg: xreg(10),
2051 simm7: simm7_scaled_zero(I64),
2052 },
2053 flags: MemFlags::trusted(),
2054 },
2055 "482500A9",
2056 "stp x8, x9, [x10]",
2057 ));
2058 insns.push((
2059 Inst::StoreP64 {
2060 rt: xreg(8),
2061 rt2: xreg(9),
2062 mem: PairAMode::SignedOffset {
2063 reg: xreg(10),
2064 simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2065 },
2066 flags: MemFlags::trusted(),
2067 },
2068 "48A51FA9",
2069 "stp x8, x9, [x10, #504]",
2070 ));
2071 insns.push((
2072 Inst::StoreP64 {
2073 rt: xreg(8),
2074 rt2: xreg(9),
2075 mem: PairAMode::SignedOffset {
2076 reg: xreg(10),
2077 simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2078 },
2079 flags: MemFlags::trusted(),
2080 },
2081 "48253CA9",
2082 "stp x8, x9, [x10, #-64]",
2083 ));
2084 insns.push((
2085 Inst::StoreP64 {
2086 rt: xreg(21),
2087 rt2: xreg(28),
2088 mem: PairAMode::SignedOffset {
2089 reg: xreg(1),
2090 simm7: SImm7Scaled::maybe_from_i64(-512, I64).unwrap(),
2091 },
2092 flags: MemFlags::trusted(),
2093 },
2094 "357020A9",
2095 "stp x21, x28, [x1, #-512]",
2096 ));
2097 insns.push((
2098 Inst::StoreP64 {
2099 rt: xreg(8),
2100 rt2: xreg(9),
2101 mem: PairAMode::SPPreIndexed {
2102 simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2103 },
2104 flags: MemFlags::trusted(),
2105 },
2106 "E827BCA9",
2107 "stp x8, x9, [sp, #-64]!",
2108 ));
2109 insns.push((
2110 Inst::StoreP64 {
2111 rt: xreg(15),
2112 rt2: xreg(16),
2113 mem: PairAMode::SPPostIndexed {
2114 simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2115 },
2116 flags: MemFlags::trusted(),
2117 },
2118 "EFC39FA8",
2119 "stp x15, x16, [sp], #504",
2120 ));
2121
2122 insns.push((
2123 Inst::LoadP64 {
2124 rt: writable_xreg(8),
2125 rt2: writable_xreg(9),
2126 mem: PairAMode::SignedOffset {
2127 reg: xreg(10),
2128 simm7: simm7_scaled_zero(I64),
2129 },
2130 flags: MemFlags::trusted(),
2131 },
2132 "482540A9",
2133 "ldp x8, x9, [x10]",
2134 ));
2135 insns.push((
2136 Inst::LoadP64 {
2137 rt: writable_xreg(8),
2138 rt2: writable_xreg(9),
2139 mem: PairAMode::SignedOffset {
2140 reg: xreg(10),
2141 simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2142 },
2143 flags: MemFlags::trusted(),
2144 },
2145 "48A55FA9",
2146 "ldp x8, x9, [x10, #504]",
2147 ));
2148 insns.push((
2149 Inst::LoadP64 {
2150 rt: writable_xreg(8),
2151 rt2: writable_xreg(9),
2152 mem: PairAMode::SignedOffset {
2153 reg: xreg(10),
2154 simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2155 },
2156 flags: MemFlags::trusted(),
2157 },
2158 "48257CA9",
2159 "ldp x8, x9, [x10, #-64]",
2160 ));
2161 insns.push((
2162 Inst::LoadP64 {
2163 rt: writable_xreg(8),
2164 rt2: writable_xreg(9),
2165 mem: PairAMode::SignedOffset {
2166 reg: xreg(10),
2167 simm7: SImm7Scaled::maybe_from_i64(-512, I64).unwrap(),
2168 },
2169 flags: MemFlags::trusted(),
2170 },
2171 "482560A9",
2172 "ldp x8, x9, [x10, #-512]",
2173 ));
2174 insns.push((
2175 Inst::LoadP64 {
2176 rt: writable_xreg(8),
2177 rt2: writable_xreg(9),
2178 mem: PairAMode::SPPreIndexed {
2179 simm7: SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
2180 },
2181 flags: MemFlags::trusted(),
2182 },
2183 "E827FCA9",
2184 "ldp x8, x9, [sp, #-64]!",
2185 ));
2186 insns.push((
2187 Inst::LoadP64 {
2188 rt: writable_xreg(8),
2189 rt2: writable_xreg(25),
2190 mem: PairAMode::SPPostIndexed {
2191 simm7: SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
2192 },
2193 flags: MemFlags::trusted(),
2194 },
2195 "E8E7DFA8",
2196 "ldp x8, x25, [sp], #504",
2197 ));
2198
2199 insns.push((
2200 Inst::Mov {
2201 size: OperandSize::Size64,
2202 rd: writable_xreg(8),
2203 rm: xreg(9),
2204 },
2205 "E80309AA",
2206 "mov x8, x9",
2207 ));
2208 insns.push((
2209 Inst::Mov {
2210 size: OperandSize::Size32,
2211 rd: writable_xreg(8),
2212 rm: xreg(9),
2213 },
2214 "E803092A",
2215 "mov w8, w9",
2216 ));
2217
2218 insns.push((
2219 Inst::MovWide {
2220 op: MoveWideOp::MovZ,
2221 rd: writable_xreg(8),
2222 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2223 size: OperandSize::Size64,
2224 },
2225 "E8FF9FD2",
2226 "movz x8, #65535",
2227 ));
2228 insns.push((
2229 Inst::MovWide {
2230 op: MoveWideOp::MovZ,
2231 rd: writable_xreg(8),
2232 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2233 size: OperandSize::Size64,
2234 },
2235 "E8FFBFD2",
2236 "movz x8, #65535, LSL #16",
2237 ));
2238 insns.push((
2239 Inst::MovWide {
2240 op: MoveWideOp::MovZ,
2241 rd: writable_xreg(8),
2242 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
2243 size: OperandSize::Size64,
2244 },
2245 "E8FFDFD2",
2246 "movz x8, #65535, LSL #32",
2247 ));
2248 insns.push((
2249 Inst::MovWide {
2250 op: MoveWideOp::MovZ,
2251 rd: writable_xreg(8),
2252 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
2253 size: OperandSize::Size64,
2254 },
2255 "E8FFFFD2",
2256 "movz x8, #65535, LSL #48",
2257 ));
2258 insns.push((
2259 Inst::MovWide {
2260 op: MoveWideOp::MovZ,
2261 rd: writable_xreg(8),
2262 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2263 size: OperandSize::Size32,
2264 },
2265 "E8FFBF52",
2266 "movz w8, #65535, LSL #16",
2267 ));
2268
2269 insns.push((
2270 Inst::MovWide {
2271 op: MoveWideOp::MovN,
2272 rd: writable_xreg(8),
2273 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2274 size: OperandSize::Size64,
2275 },
2276 "E8FF9F92",
2277 "movn x8, #65535",
2278 ));
2279 insns.push((
2280 Inst::MovWide {
2281 op: MoveWideOp::MovN,
2282 rd: writable_xreg(8),
2283 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2284 size: OperandSize::Size64,
2285 },
2286 "E8FFBF92",
2287 "movn x8, #65535, LSL #16",
2288 ));
2289 insns.push((
2290 Inst::MovWide {
2291 op: MoveWideOp::MovN,
2292 rd: writable_xreg(8),
2293 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
2294 size: OperandSize::Size64,
2295 },
2296 "E8FFDF92",
2297 "movn x8, #65535, LSL #32",
2298 ));
2299 insns.push((
2300 Inst::MovWide {
2301 op: MoveWideOp::MovN,
2302 rd: writable_xreg(8),
2303 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
2304 size: OperandSize::Size64,
2305 },
2306 "E8FFFF92",
2307 "movn x8, #65535, LSL #48",
2308 ));
2309 insns.push((
2310 Inst::MovWide {
2311 op: MoveWideOp::MovN,
2312 rd: writable_xreg(8),
2313 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2314 size: OperandSize::Size32,
2315 },
2316 "E8FF9F12",
2317 "movn w8, #65535",
2318 ));
2319
2320 insns.push((
2321 Inst::MovK {
2322 rd: writable_xreg(12),
2323 rn: xreg(12),
2324 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_0000).unwrap(),
2325 size: OperandSize::Size64,
2326 },
2327 "0C0080F2",
2328 "movk x12, x12, #0",
2329 ));
2330 insns.push((
2331 Inst::MovK {
2332 rd: writable_xreg(19),
2333 rn: xreg(19),
2334 imm: MoveWideConst::maybe_with_shift(0x0000, 16).unwrap(),
2335 size: OperandSize::Size64,
2336 },
2337 "1300A0F2",
2338 "movk x19, x19, #0, LSL #16",
2339 ));
2340 insns.push((
2341 Inst::MovK {
2342 rd: writable_xreg(3),
2343 rn: xreg(3),
2344 imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
2345 size: OperandSize::Size64,
2346 },
2347 "E3FF9FF2",
2348 "movk x3, x3, #65535",
2349 ));
2350 insns.push((
2351 Inst::MovK {
2352 rd: writable_xreg(8),
2353 rn: xreg(8),
2354 imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
2355 size: OperandSize::Size64,
2356 },
2357 "E8FFBFF2",
2358 "movk x8, x8, #65535, LSL #16",
2359 ));
2360 insns.push((
2361 Inst::MovK {
2362 rd: writable_xreg(8),
2363 rn: xreg(8),
2364 imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
2365 size: OperandSize::Size64,
2366 },
2367 "E8FFDFF2",
2368 "movk x8, x8, #65535, LSL #32",
2369 ));
2370 insns.push((
2371 Inst::MovK {
2372 rd: writable_xreg(8),
2373 rn: xreg(8),
2374 imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
2375 size: OperandSize::Size64,
2376 },
2377 "E8FFFFF2",
2378 "movk x8, x8, #65535, LSL #48",
2379 ));
2380
2381 insns.push((
2382 Inst::CSel {
2383 rd: writable_xreg(10),
2384 rn: xreg(12),
2385 rm: xreg(14),
2386 cond: Cond::Hs,
2387 },
2388 "8A218E9A",
2389 "csel x10, x12, x14, hs",
2390 ));
2391 insns.push((
2392 Inst::CSNeg {
2393 rd: writable_xreg(10),
2394 rn: xreg(12),
2395 rm: xreg(14),
2396 cond: Cond::Hs,
2397 },
2398 "8A258EDA",
2399 "csneg x10, x12, x14, hs",
2400 ));
2401 insns.push((
2402 Inst::CSet {
2403 rd: writable_xreg(15),
2404 cond: Cond::Ge,
2405 },
2406 "EFB79F9A",
2407 "cset x15, ge",
2408 ));
2409 insns.push((
2410 Inst::CSetm {
2411 rd: writable_xreg(0),
2412 cond: Cond::Eq,
2413 },
2414 "E0139FDA",
2415 "csetm x0, eq",
2416 ));
2417 insns.push((
2418 Inst::CSetm {
2419 rd: writable_xreg(16),
2420 cond: Cond::Vs,
2421 },
2422 "F0739FDA",
2423 "csetm x16, vs",
2424 ));
2425 insns.push((
2426 Inst::CCmp {
2427 size: OperandSize::Size64,
2428 rn: xreg(22),
2429 rm: xreg(1),
2430 nzcv: NZCV::new(false, false, true, true),
2431 cond: Cond::Eq,
2432 },
2433 "C30241FA",
2434 "ccmp x22, x1, #nzCV, eq",
2435 ));
2436 insns.push((
2437 Inst::CCmp {
2438 size: OperandSize::Size32,
2439 rn: xreg(3),
2440 rm: xreg(28),
2441 nzcv: NZCV::new(true, true, true, true),
2442 cond: Cond::Gt,
2443 },
2444 "6FC05C7A",
2445 "ccmp w3, w28, #NZCV, gt",
2446 ));
2447 insns.push((
2448 Inst::CCmpImm {
2449 size: OperandSize::Size64,
2450 rn: xreg(22),
2451 imm: UImm5::maybe_from_u8(5).unwrap(),
2452 nzcv: NZCV::new(false, false, true, true),
2453 cond: Cond::Eq,
2454 },
2455 "C30A45FA",
2456 "ccmp x22, #5, #nzCV, eq",
2457 ));
2458 insns.push((
2459 Inst::CCmpImm {
2460 size: OperandSize::Size32,
2461 rn: xreg(3),
2462 imm: UImm5::maybe_from_u8(30).unwrap(),
2463 nzcv: NZCV::new(true, true, true, true),
2464 cond: Cond::Gt,
2465 },
2466 "6FC85E7A",
2467 "ccmp w3, #30, #NZCV, gt",
2468 ));
2469 insns.push((
2470 Inst::MovToFpu {
2471 rd: writable_vreg(31),
2472 rn: xreg(0),
2473 size: ScalarSize::Size64,
2474 },
2475 "1F00679E",
2476 "fmov d31, x0",
2477 ));
2478 insns.push((
2479 Inst::MovToFpu {
2480 rd: writable_vreg(1),
2481 rn: xreg(28),
2482 size: ScalarSize::Size32,
2483 },
2484 "8103271E",
2485 "fmov s1, w28",
2486 ));
2487 insns.push((
2488 Inst::FpuMoveFPImm {
2489 rd: writable_vreg(31),
2490 imm: ASIMDFPModImm::maybe_from_u64(f64::to_bits(1.0), ScalarSize::Size64).unwrap(),
2491 size: ScalarSize::Size64,
2492 },
2493 "1F106E1E",
2494 "fmov d31, #1",
2495 ));
2496 insns.push((
2497 Inst::FpuMoveFPImm {
2498 rd: writable_vreg(1),
2499 imm: ASIMDFPModImm::maybe_from_u64(f32::to_bits(31.0).into(), ScalarSize::Size32)
2500 .unwrap(),
2501 size: ScalarSize::Size32,
2502 },
2503 "01F0271E",
2504 "fmov s1, #31",
2505 ));
2506 insns.push((
2507 Inst::MovToVec {
2508 rd: writable_vreg(0),
2509 ri: vreg(0),
2510 rn: xreg(0),
2511 idx: 7,
2512 size: VectorSize::Size8x8,
2513 },
2514 "001C0F4E",
2515 "mov v0.b[7], v0.b[7], w0",
2516 ));
2517 insns.push((
2518 Inst::MovToVec {
2519 rd: writable_vreg(20),
2520 ri: vreg(20),
2521 rn: xreg(21),
2522 idx: 0,
2523 size: VectorSize::Size64x2,
2524 },
2525 "B41E084E",
2526 "mov v20.d[0], v20.d[0], x21",
2527 ));
2528 insns.push((
2529 Inst::MovFromVec {
2530 rd: writable_xreg(3),
2531 rn: vreg(27),
2532 idx: 14,
2533 size: ScalarSize::Size8,
2534 },
2535 "633F1D0E",
2536 "umov w3, v27.b[14]",
2537 ));
2538 insns.push((
2539 Inst::MovFromVec {
2540 rd: writable_xreg(24),
2541 rn: vreg(5),
2542 idx: 3,
2543 size: ScalarSize::Size16,
2544 },
2545 "B83C0E0E",
2546 "umov w24, v5.h[3]",
2547 ));
2548 insns.push((
2549 Inst::MovFromVec {
2550 rd: writable_xreg(12),
2551 rn: vreg(17),
2552 idx: 1,
2553 size: ScalarSize::Size32,
2554 },
2555 "2C3E0C0E",
2556 "mov w12, v17.s[1]",
2557 ));
2558 insns.push((
2559 Inst::MovFromVec {
2560 rd: writable_xreg(21),
2561 rn: vreg(20),
2562 idx: 0,
2563 size: ScalarSize::Size64,
2564 },
2565 "953E084E",
2566 "mov x21, v20.d[0]",
2567 ));
2568 insns.push((
2569 Inst::MovFromVecSigned {
2570 rd: writable_xreg(0),
2571 rn: vreg(0),
2572 idx: 15,
2573 size: VectorSize::Size8x16,
2574 scalar_size: OperandSize::Size32,
2575 },
2576 "002C1F0E",
2577 "smov w0, v0.b[15]",
2578 ));
2579 insns.push((
2580 Inst::MovFromVecSigned {
2581 rd: writable_xreg(12),
2582 rn: vreg(13),
2583 idx: 7,
2584 size: VectorSize::Size8x8,
2585 scalar_size: OperandSize::Size64,
2586 },
2587 "AC2D0F4E",
2588 "smov x12, v13.b[7]",
2589 ));
2590 insns.push((
2591 Inst::MovFromVecSigned {
2592 rd: writable_xreg(23),
2593 rn: vreg(31),
2594 idx: 7,
2595 size: VectorSize::Size16x8,
2596 scalar_size: OperandSize::Size32,
2597 },
2598 "F72F1E0E",
2599 "smov w23, v31.h[7]",
2600 ));
2601 insns.push((
2602 Inst::MovFromVecSigned {
2603 rd: writable_xreg(24),
2604 rn: vreg(5),
2605 idx: 1,
2606 size: VectorSize::Size32x2,
2607 scalar_size: OperandSize::Size64,
2608 },
2609 "B82C0C4E",
2610 "smov x24, v5.s[1]",
2611 ));
2612 insns.push((
2613 Inst::MovToNZCV { rn: xreg(13) },
2614 "0D421BD5",
2615 "msr nzcv, x13",
2616 ));
2617 insns.push((
2618 Inst::MovFromNZCV {
2619 rd: writable_xreg(27),
2620 },
2621 "1B423BD5",
2622 "mrs x27, nzcv",
2623 ));
2624 insns.push((
2625 Inst::VecDup {
2626 rd: writable_vreg(24),
2627 rn: xreg(8),
2628 size: VectorSize::Size8x8,
2629 },
2630 "180D010E",
2631 "dup v24.8b, w8",
2632 ));
2633 insns.push((
2634 Inst::VecDup {
2635 rd: writable_vreg(25),
2636 rn: xreg(7),
2637 size: VectorSize::Size8x8,
2638 },
2639 "F90C010E",
2640 "dup v25.8b, w7",
2641 ));
2642 insns.push((
2643 Inst::VecDup {
2644 rd: writable_vreg(1),
2645 rn: xreg(22),
2646 size: VectorSize::Size16x4,
2647 },
2648 "C10E020E",
2649 "dup v1.4h, w22",
2650 ));
2651 insns.push((
2652 Inst::VecDup {
2653 rd: writable_vreg(2),
2654 rn: xreg(23),
2655 size: VectorSize::Size16x8,
2656 },
2657 "E20E024E",
2658 "dup v2.8h, w23",
2659 ));
2660 insns.push((
2661 Inst::VecDup {
2662 rd: writable_vreg(30),
2663 rn: xreg(28),
2664 size: VectorSize::Size32x2,
2665 },
2666 "9E0F040E",
2667 "dup v30.2s, w28",
2668 ));
2669 insns.push((
2670 Inst::VecDup {
2671 rd: writable_vreg(0),
2672 rn: xreg(28),
2673 size: VectorSize::Size32x2,
2674 },
2675 "800F040E",
2676 "dup v0.2s, w28",
2677 ));
2678 insns.push((
2679 Inst::VecDup {
2680 rd: writable_vreg(31),
2681 rn: xreg(5),
2682 size: VectorSize::Size64x2,
2683 },
2684 "BF0C084E",
2685 "dup v31.2d, x5",
2686 ));
2687 insns.push((
2688 Inst::VecDupFromFpu {
2689 rd: writable_vreg(14),
2690 rn: vreg(19),
2691 size: VectorSize::Size32x4,
2692 lane: 0,
2693 },
2694 "6E06044E",
2695 "dup v14.4s, v19.s[0]",
2696 ));
2697 insns.push((
2698 Inst::VecDupFromFpu {
2699 rd: writable_vreg(18),
2700 rn: vreg(10),
2701 size: VectorSize::Size64x2,
2702 lane: 0,
2703 },
2704 "5205084E",
2705 "dup v18.2d, v10.d[0]",
2706 ));
2707 insns.push((
2708 Inst::VecDupFPImm {
2709 rd: writable_vreg(31),
2710 imm: ASIMDFPModImm::maybe_from_u64(1_f32.to_bits() as u64, ScalarSize::Size32).unwrap(),
2711 size: VectorSize::Size32x2,
2712 },
2713 "1FF6030F",
2714 "fmov v31.2s, #1",
2715 ));
2716 insns.push((
2717 Inst::VecDupFPImm {
2718 rd: writable_vreg(0),
2719 imm: ASIMDFPModImm::maybe_from_u64(2_f64.to_bits(), ScalarSize::Size64).unwrap(),
2720 size: VectorSize::Size64x2,
2721 },
2722 "00F4006F",
2723 "fmov v0.2d, #2",
2724 ));
2725 insns.push((
2726 Inst::VecDupImm {
2727 rd: writable_vreg(31),
2728 imm: ASIMDMovModImm::maybe_from_u64(255, ScalarSize::Size8).unwrap(),
2729 invert: false,
2730 size: VectorSize::Size8x16,
2731 },
2732 "FFE7074F",
2733 "movi v31.16b, #255",
2734 ));
2735 insns.push((
2736 Inst::VecDupImm {
2737 rd: writable_vreg(30),
2738 imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size16).unwrap(),
2739 invert: false,
2740 size: VectorSize::Size16x8,
2741 },
2742 "1E84004F",
2743 "movi v30.8h, #0",
2744 ));
2745 insns.push((
2746 Inst::VecDupImm {
2747 rd: writable_vreg(0),
2748 imm: ASIMDMovModImm::zero(ScalarSize::Size16),
2749 invert: true,
2750 size: VectorSize::Size16x4,
2751 },
2752 "0084002F",
2753 "mvni v0.4h, #0",
2754 ));
2755 insns.push((
2756 Inst::VecDupImm {
2757 rd: writable_vreg(0),
2758 imm: ASIMDMovModImm::maybe_from_u64(256, ScalarSize::Size16).unwrap(),
2759 invert: false,
2760 size: VectorSize::Size16x8,
2761 },
2762 "20A4004F",
2763 "movi v0.8h, #1, LSL #8",
2764 ));
2765 insns.push((
2766 Inst::VecDupImm {
2767 rd: writable_vreg(8),
2768 imm: ASIMDMovModImm::maybe_from_u64(2228223, ScalarSize::Size32).unwrap(),
2769 invert: false,
2770 size: VectorSize::Size32x4,
2771 },
2772 "28D4014F",
2773 "movi v8.4s, #33, MSL #16",
2774 ));
2775 insns.push((
2776 Inst::VecDupImm {
2777 rd: writable_vreg(16),
2778 imm: ASIMDMovModImm::maybe_from_u64(35071, ScalarSize::Size32).unwrap(),
2779 invert: true,
2780 size: VectorSize::Size32x2,
2781 },
2782 "10C5042F",
2783 "mvni v16.2s, #136, MSL #8",
2784 ));
2785 insns.push((
2786 Inst::VecDupImm {
2787 rd: writable_vreg(1),
2788 imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size32).unwrap(),
2789 invert: false,
2790 size: VectorSize::Size32x2,
2791 },
2792 "0104000F",
2793 "movi v1.2s, #0",
2794 ));
2795 insns.push((
2796 Inst::VecDupImm {
2797 rd: writable_vreg(24),
2798 imm: ASIMDMovModImm::maybe_from_u64(1107296256, ScalarSize::Size32).unwrap(),
2799 invert: false,
2800 size: VectorSize::Size32x4,
2801 },
2802 "5864024F",
2803 "movi v24.4s, #66, LSL #24",
2804 ));
2805 insns.push((
2806 Inst::VecDupImm {
2807 rd: writable_vreg(8),
2808 imm: ASIMDMovModImm::zero(ScalarSize::Size64),
2809 invert: false,
2810 size: VectorSize::Size64x2,
2811 },
2812 "08E4006F",
2813 "movi v8.2d, #0",
2814 ));
2815 insns.push((
2816 Inst::VecDupImm {
2817 rd: writable_vreg(7),
2818 imm: ASIMDMovModImm::maybe_from_u64(18374687574904995840, ScalarSize::Size64).unwrap(),
2819 invert: false,
2820 size: VectorSize::Size64x2,
2821 },
2822 "87E6046F",
2823 "movi v7.2d, #18374687574904995840",
2824 ));
2825 insns.push((
2826 Inst::VecExtend {
2827 t: VecExtendOp::Sxtl,
2828 rd: writable_vreg(4),
2829 rn: vreg(27),
2830 high_half: false,
2831 lane_size: ScalarSize::Size16,
2832 },
2833 "64A7080F",
2834 "sxtl v4.8h, v27.8b",
2835 ));
2836 insns.push((
2837 Inst::VecExtend {
2838 t: VecExtendOp::Sxtl,
2839 rd: writable_vreg(17),
2840 rn: vreg(19),
2841 high_half: true,
2842 lane_size: ScalarSize::Size32,
2843 },
2844 "71A6104F",
2845 "sxtl2 v17.4s, v19.8h",
2846 ));
2847 insns.push((
2848 Inst::VecExtend {
2849 t: VecExtendOp::Sxtl,
2850 rd: writable_vreg(30),
2851 rn: vreg(6),
2852 high_half: false,
2853 lane_size: ScalarSize::Size64,
2854 },
2855 "DEA4200F",
2856 "sxtl v30.2d, v6.2s",
2857 ));
2858 insns.push((
2859 Inst::VecExtend {
2860 t: VecExtendOp::Uxtl,
2861 rd: writable_vreg(3),
2862 rn: vreg(29),
2863 high_half: true,
2864 lane_size: ScalarSize::Size16,
2865 },
2866 "A3A7086F",
2867 "uxtl2 v3.8h, v29.16b",
2868 ));
2869 insns.push((
2870 Inst::VecExtend {
2871 t: VecExtendOp::Uxtl,
2872 rd: writable_vreg(15),
2873 rn: vreg(12),
2874 high_half: false,
2875 lane_size: ScalarSize::Size32,
2876 },
2877 "8FA5102F",
2878 "uxtl v15.4s, v12.4h",
2879 ));
2880 insns.push((
2881 Inst::VecExtend {
2882 t: VecExtendOp::Uxtl,
2883 rd: writable_vreg(28),
2884 rn: vreg(2),
2885 high_half: true,
2886 lane_size: ScalarSize::Size64,
2887 },
2888 "5CA4206F",
2889 "uxtl2 v28.2d, v2.4s",
2890 ));
2891
2892 insns.push((
2893 Inst::VecMovElement {
2894 rd: writable_vreg(0),
2895 ri: vreg(0),
2896 rn: vreg(31),
2897 dest_idx: 7,
2898 src_idx: 7,
2899 size: VectorSize::Size16x8,
2900 },
2901 "E0771E6E",
2902 "mov v0.h[7], v0.h[7], v31.h[7]",
2903 ));
2904
2905 insns.push((
2906 Inst::VecMovElement {
2907 rd: writable_vreg(31),
2908 ri: vreg(31),
2909 rn: vreg(16),
2910 dest_idx: 1,
2911 src_idx: 0,
2912 size: VectorSize::Size32x2,
2913 },
2914 "1F060C6E",
2915 "mov v31.s[1], v31.s[1], v16.s[0]",
2916 ));
2917
2918 insns.push((
2919 Inst::VecRRLong {
2920 op: VecRRLongOp::Fcvtl16,
2921 rd: writable_vreg(0),
2922 rn: vreg(30),
2923 high_half: false,
2924 },
2925 "C07B210E",
2926 "fcvtl v0.4s, v30.4h",
2927 ));
2928
2929 insns.push((
2930 Inst::VecRRLong {
2931 op: VecRRLongOp::Fcvtl32,
2932 rd: writable_vreg(16),
2933 rn: vreg(1),
2934 high_half: true,
2935 },
2936 "3078614E",
2937 "fcvtl2 v16.2d, v1.4s",
2938 ));
2939
2940 insns.push((
2941 Inst::VecRRLong {
2942 op: VecRRLongOp::Shll8,
2943 rd: writable_vreg(12),
2944 rn: vreg(5),
2945 high_half: false,
2946 },
2947 "AC38212E",
2948 "shll v12.8h, v5.8b, #8",
2949 ));
2950
2951 insns.push((
2952 Inst::VecRRLong {
2953 op: VecRRLongOp::Shll16,
2954 rd: writable_vreg(9),
2955 rn: vreg(1),
2956 high_half: true,
2957 },
2958 "2938616E",
2959 "shll2 v9.4s, v1.8h, #16",
2960 ));
2961
2962 insns.push((
2963 Inst::VecRRLong {
2964 op: VecRRLongOp::Shll32,
2965 rd: writable_vreg(1),
2966 rn: vreg(10),
2967 high_half: false,
2968 },
2969 "4139A12E",
2970 "shll v1.2d, v10.2s, #32",
2971 ));
2972
2973 insns.push((
2974 Inst::VecRRNarrowLow {
2975 op: VecRRNarrowOp::Xtn,
2976 rd: writable_vreg(25),
2977 rn: vreg(17),
2978 lane_size: ScalarSize::Size8,
2979 },
2980 "392A210E",
2981 "xtn v25.8b, v17.8h",
2982 ));
2983
2984 insns.push((
2985 Inst::VecRRNarrowHigh {
2986 op: VecRRNarrowOp::Xtn,
2987 rd: writable_vreg(3),
2988 ri: vreg(3),
2989 rn: vreg(10),
2990 lane_size: ScalarSize::Size16,
2991 },
2992 "4329614E",
2993 "xtn2 v3.8h, v3.8h, v10.4s",
2994 ));
2995
2996 insns.push((
2997 Inst::VecRRNarrowLow {
2998 op: VecRRNarrowOp::Xtn,
2999 rd: writable_vreg(22),
3000 rn: vreg(8),
3001 lane_size: ScalarSize::Size32,
3002 },
3003 "1629A10E",
3004 "xtn v22.2s, v8.2d",
3005 ));
3006
3007 insns.push((
3008 Inst::VecRRNarrowHigh {
3009 op: VecRRNarrowOp::Sqxtn,
3010 rd: writable_vreg(7),
3011 ri: vreg(7),
3012 rn: vreg(22),
3013 lane_size: ScalarSize::Size8,
3014 },
3015 "C74A214E",
3016 "sqxtn2 v7.16b, v7.16b, v22.8h",
3017 ));
3018
3019 insns.push((
3020 Inst::VecRRNarrowHigh {
3021 op: VecRRNarrowOp::Sqxtn,
3022 rd: writable_vreg(31),
3023 ri: vreg(31),
3024 rn: vreg(0),
3025 lane_size: ScalarSize::Size16,
3026 },
3027 "1F48614E",
3028 "sqxtn2 v31.8h, v31.8h, v0.4s",
3029 ));
3030
3031 insns.push((
3032 Inst::VecRRNarrowLow {
3033 op: VecRRNarrowOp::Sqxtn,
3034 rd: writable_vreg(14),
3035 rn: vreg(20),
3036 lane_size: ScalarSize::Size32,
3037 },
3038 "8E4AA10E",
3039 "sqxtn v14.2s, v20.2d",
3040 ));
3041
3042 insns.push((
3043 Inst::VecRRNarrowLow {
3044 op: VecRRNarrowOp::Sqxtun,
3045 rd: writable_vreg(16),
3046 rn: vreg(23),
3047 lane_size: ScalarSize::Size8,
3048 },
3049 "F02A212E",
3050 "sqxtun v16.8b, v23.8h",
3051 ));
3052
3053 insns.push((
3054 Inst::VecRRNarrowHigh {
3055 op: VecRRNarrowOp::Sqxtun,
3056 rd: writable_vreg(28),
3057 ri: vreg(28),
3058 rn: vreg(9),
3059 lane_size: ScalarSize::Size16,
3060 },
3061 "3C29616E",
3062 "sqxtun2 v28.8h, v28.8h, v9.4s",
3063 ));
3064
3065 insns.push((
3066 Inst::VecRRNarrowLow {
3067 op: VecRRNarrowOp::Sqxtun,
3068 rd: writable_vreg(15),
3069 rn: vreg(15),
3070 lane_size: ScalarSize::Size32,
3071 },
3072 "EF29A12E",
3073 "sqxtun v15.2s, v15.2d",
3074 ));
3075
3076 insns.push((
3077 Inst::VecRRNarrowHigh {
3078 op: VecRRNarrowOp::Uqxtn,
3079 rd: writable_vreg(21),
3080 ri: vreg(21),
3081 rn: vreg(4),
3082 lane_size: ScalarSize::Size8,
3083 },
3084 "9548216E",
3085 "uqxtn2 v21.16b, v21.16b, v4.8h",
3086 ));
3087
3088 insns.push((
3089 Inst::VecRRNarrowLow {
3090 op: VecRRNarrowOp::Uqxtn,
3091 rd: writable_vreg(31),
3092 rn: vreg(31),
3093 lane_size: ScalarSize::Size16,
3094 },
3095 "FF4B612E",
3096 "uqxtn v31.4h, v31.4s",
3097 ));
3098
3099 insns.push((
3100 Inst::VecRRNarrowHigh {
3101 op: VecRRNarrowOp::Uqxtn,
3102 rd: writable_vreg(11),
3103 ri: vreg(11),
3104 rn: vreg(12),
3105 lane_size: ScalarSize::Size32,
3106 },
3107 "8B49A16E",
3108 "uqxtn2 v11.4s, v11.4s, v12.2d",
3109 ));
3110
3111 insns.push((
3112 Inst::VecRRNarrowLow {
3113 op: VecRRNarrowOp::Fcvtn,
3114 rd: writable_vreg(0),
3115 rn: vreg(0),
3116 lane_size: ScalarSize::Size16,
3117 },
3118 "0068210E",
3119 "fcvtn v0.4h, v0.4s",
3120 ));
3121
3122 insns.push((
3123 Inst::VecRRNarrowLow {
3124 op: VecRRNarrowOp::Fcvtn,
3125 rd: writable_vreg(2),
3126 rn: vreg(7),
3127 lane_size: ScalarSize::Size32,
3128 },
3129 "E268610E",
3130 "fcvtn v2.2s, v7.2d",
3131 ));
3132
3133 insns.push((
3134 Inst::VecRRNarrowHigh {
3135 op: VecRRNarrowOp::Fcvtn,
3136 rd: writable_vreg(31),
3137 ri: vreg(31),
3138 rn: vreg(30),
3139 lane_size: ScalarSize::Size32,
3140 },
3141 "DF6B614E",
3142 "fcvtn2 v31.4s, v31.4s, v30.2d",
3143 ));
3144
3145 insns.push((
3146 Inst::VecRRPair {
3147 op: VecPairOp::Addp,
3148 rd: writable_vreg(0),
3149 rn: vreg(30),
3150 },
3151 "C0BBF15E",
3152 "addp d0, v30.2d",
3153 ));
3154
3155 insns.push((
3156 Inst::VecRRPairLong {
3157 op: VecRRPairLongOp::Uaddlp8,
3158 rd: writable_vreg(0),
3159 rn: vreg(1),
3160 },
3161 "2028206E",
3162 "uaddlp v0.8h, v1.16b",
3163 ));
3164
3165 insns.push((
3166 Inst::VecRRPairLong {
3167 op: VecRRPairLongOp::Saddlp8,
3168 rd: writable_vreg(3),
3169 rn: vreg(11),
3170 },
3171 "6329204E",
3172 "saddlp v3.8h, v11.16b",
3173 ));
3174
3175 insns.push((
3176 Inst::VecRRPairLong {
3177 op: VecRRPairLongOp::Uaddlp16,
3178 rd: writable_vreg(14),
3179 rn: vreg(23),
3180 },
3181 "EE2A606E",
3182 "uaddlp v14.4s, v23.8h",
3183 ));
3184
3185 insns.push((
3186 Inst::VecRRPairLong {
3187 op: VecRRPairLongOp::Saddlp16,
3188 rd: writable_vreg(29),
3189 rn: vreg(0),
3190 },
3191 "1D28604E",
3192 "saddlp v29.4s, v0.8h",
3193 ));
3194
3195 insns.push((
3196 Inst::VecRRR {
3197 alu_op: VecALUOp::Sqadd,
3198 rd: writable_vreg(1),
3199 rn: vreg(2),
3200 rm: vreg(8),
3201 size: VectorSize::Size8x16,
3202 },
3203 "410C284E",
3204 "sqadd v1.16b, v2.16b, v8.16b",
3205 ));
3206
3207 insns.push((
3208 Inst::VecRRR {
3209 alu_op: VecALUOp::Sqadd,
3210 rd: writable_vreg(1),
3211 rn: vreg(12),
3212 rm: vreg(28),
3213 size: VectorSize::Size16x8,
3214 },
3215 "810D7C4E",
3216 "sqadd v1.8h, v12.8h, v28.8h",
3217 ));
3218
3219 insns.push((
3220 Inst::VecRRR {
3221 alu_op: VecALUOp::Sqadd,
3222 rd: writable_vreg(12),
3223 rn: vreg(2),
3224 rm: vreg(6),
3225 size: VectorSize::Size32x4,
3226 },
3227 "4C0CA64E",
3228 "sqadd v12.4s, v2.4s, v6.4s",
3229 ));
3230
3231 insns.push((
3232 Inst::VecRRR {
3233 alu_op: VecALUOp::Sqadd,
3234 rd: writable_vreg(20),
3235 rn: vreg(7),
3236 rm: vreg(13),
3237 size: VectorSize::Size64x2,
3238 },
3239 "F40CED4E",
3240 "sqadd v20.2d, v7.2d, v13.2d",
3241 ));
3242
3243 insns.push((
3244 Inst::VecRRR {
3245 alu_op: VecALUOp::Sqsub,
3246 rd: writable_vreg(1),
3247 rn: vreg(2),
3248 rm: vreg(8),
3249 size: VectorSize::Size8x16,
3250 },
3251 "412C284E",
3252 "sqsub v1.16b, v2.16b, v8.16b",
3253 ));
3254
3255 insns.push((
3256 Inst::VecRRR {
3257 alu_op: VecALUOp::Sqsub,
3258 rd: writable_vreg(1),
3259 rn: vreg(12),
3260 rm: vreg(28),
3261 size: VectorSize::Size16x8,
3262 },
3263 "812D7C4E",
3264 "sqsub v1.8h, v12.8h, v28.8h",
3265 ));
3266
3267 insns.push((
3268 Inst::VecRRR {
3269 alu_op: VecALUOp::Sqsub,
3270 rd: writable_vreg(12),
3271 rn: vreg(2),
3272 rm: vreg(6),
3273 size: VectorSize::Size32x4,
3274 },
3275 "4C2CA64E",
3276 "sqsub v12.4s, v2.4s, v6.4s",
3277 ));
3278
3279 insns.push((
3280 Inst::VecRRR {
3281 alu_op: VecALUOp::Sqsub,
3282 rd: writable_vreg(20),
3283 rn: vreg(7),
3284 rm: vreg(13),
3285 size: VectorSize::Size64x2,
3286 },
3287 "F42CED4E",
3288 "sqsub v20.2d, v7.2d, v13.2d",
3289 ));
3290
3291 insns.push((
3292 Inst::VecRRR {
3293 alu_op: VecALUOp::Uqadd,
3294 rd: writable_vreg(1),
3295 rn: vreg(2),
3296 rm: vreg(8),
3297 size: VectorSize::Size8x16,
3298 },
3299 "410C286E",
3300 "uqadd v1.16b, v2.16b, v8.16b",
3301 ));
3302
3303 insns.push((
3304 Inst::VecRRR {
3305 alu_op: VecALUOp::Uqadd,
3306 rd: writable_vreg(1),
3307 rn: vreg(12),
3308 rm: vreg(28),
3309 size: VectorSize::Size16x8,
3310 },
3311 "810D7C6E",
3312 "uqadd v1.8h, v12.8h, v28.8h",
3313 ));
3314
3315 insns.push((
3316 Inst::VecRRR {
3317 alu_op: VecALUOp::Uqadd,
3318 rd: writable_vreg(12),
3319 rn: vreg(2),
3320 rm: vreg(6),
3321 size: VectorSize::Size32x4,
3322 },
3323 "4C0CA66E",
3324 "uqadd v12.4s, v2.4s, v6.4s",
3325 ));
3326
3327 insns.push((
3328 Inst::VecRRR {
3329 alu_op: VecALUOp::Uqadd,
3330 rd: writable_vreg(20),
3331 rn: vreg(7),
3332 rm: vreg(13),
3333 size: VectorSize::Size64x2,
3334 },
3335 "F40CED6E",
3336 "uqadd v20.2d, v7.2d, v13.2d",
3337 ));
3338
3339 insns.push((
3340 Inst::VecRRR {
3341 alu_op: VecALUOp::Uqsub,
3342 rd: writable_vreg(1),
3343 rn: vreg(2),
3344 rm: vreg(8),
3345 size: VectorSize::Size8x16,
3346 },
3347 "412C286E",
3348 "uqsub v1.16b, v2.16b, v8.16b",
3349 ));
3350
3351 insns.push((
3352 Inst::VecRRR {
3353 alu_op: VecALUOp::Uqsub,
3354 rd: writable_vreg(1),
3355 rn: vreg(12),
3356 rm: vreg(28),
3357 size: VectorSize::Size16x8,
3358 },
3359 "812D7C6E",
3360 "uqsub v1.8h, v12.8h, v28.8h",
3361 ));
3362
3363 insns.push((
3364 Inst::VecRRR {
3365 alu_op: VecALUOp::Uqsub,
3366 rd: writable_vreg(12),
3367 rn: vreg(2),
3368 rm: vreg(6),
3369 size: VectorSize::Size32x4,
3370 },
3371 "4C2CA66E",
3372 "uqsub v12.4s, v2.4s, v6.4s",
3373 ));
3374
3375 insns.push((
3376 Inst::VecRRR {
3377 alu_op: VecALUOp::Uqsub,
3378 rd: writable_vreg(20),
3379 rn: vreg(7),
3380 rm: vreg(13),
3381 size: VectorSize::Size64x2,
3382 },
3383 "F42CED6E",
3384 "uqsub v20.2d, v7.2d, v13.2d",
3385 ));
3386
3387 insns.push((
3388 Inst::VecRRR {
3389 alu_op: VecALUOp::Cmeq,
3390 rd: writable_vreg(3),
3391 rn: vreg(23),
3392 rm: vreg(24),
3393 size: VectorSize::Size8x16,
3394 },
3395 "E38E386E",
3396 "cmeq v3.16b, v23.16b, v24.16b",
3397 ));
3398
3399 insns.push((
3400 Inst::VecRRR {
3401 alu_op: VecALUOp::Cmgt,
3402 rd: writable_vreg(3),
3403 rn: vreg(23),
3404 rm: vreg(24),
3405 size: VectorSize::Size8x16,
3406 },
3407 "E336384E",
3408 "cmgt v3.16b, v23.16b, v24.16b",
3409 ));
3410
3411 insns.push((
3412 Inst::VecRRR {
3413 alu_op: VecALUOp::Cmge,
3414 rd: writable_vreg(23),
3415 rn: vreg(9),
3416 rm: vreg(12),
3417 size: VectorSize::Size8x16,
3418 },
3419 "373D2C4E",
3420 "cmge v23.16b, v9.16b, v12.16b",
3421 ));
3422
3423 insns.push((
3424 Inst::VecRRR {
3425 alu_op: VecALUOp::Cmhi,
3426 rd: writable_vreg(5),
3427 rn: vreg(1),
3428 rm: vreg(1),
3429 size: VectorSize::Size8x16,
3430 },
3431 "2534216E",
3432 "cmhi v5.16b, v1.16b, v1.16b",
3433 ));
3434
3435 insns.push((
3436 Inst::VecRRR {
3437 alu_op: VecALUOp::Cmhs,
3438 rd: writable_vreg(8),
3439 rn: vreg(2),
3440 rm: vreg(15),
3441 size: VectorSize::Size8x16,
3442 },
3443 "483C2F6E",
3444 "cmhs v8.16b, v2.16b, v15.16b",
3445 ));
3446
3447 insns.push((
3448 Inst::VecRRR {
3449 alu_op: VecALUOp::Cmeq,
3450 rd: writable_vreg(3),
3451 rn: vreg(23),
3452 rm: vreg(24),
3453 size: VectorSize::Size16x8,
3454 },
3455 "E38E786E",
3456 "cmeq v3.8h, v23.8h, v24.8h",
3457 ));
3458
3459 insns.push((
3460 Inst::VecRRR {
3461 alu_op: VecALUOp::Cmgt,
3462 rd: writable_vreg(3),
3463 rn: vreg(23),
3464 rm: vreg(24),
3465 size: VectorSize::Size16x8,
3466 },
3467 "E336784E",
3468 "cmgt v3.8h, v23.8h, v24.8h",
3469 ));
3470
3471 insns.push((
3472 Inst::VecRRR {
3473 alu_op: VecALUOp::Cmge,
3474 rd: writable_vreg(23),
3475 rn: vreg(9),
3476 rm: vreg(12),
3477 size: VectorSize::Size16x8,
3478 },
3479 "373D6C4E",
3480 "cmge v23.8h, v9.8h, v12.8h",
3481 ));
3482
3483 insns.push((
3484 Inst::VecRRR {
3485 alu_op: VecALUOp::Cmhi,
3486 rd: writable_vreg(5),
3487 rn: vreg(1),
3488 rm: vreg(1),
3489 size: VectorSize::Size16x8,
3490 },
3491 "2534616E",
3492 "cmhi v5.8h, v1.8h, v1.8h",
3493 ));
3494
3495 insns.push((
3496 Inst::VecRRR {
3497 alu_op: VecALUOp::Cmhs,
3498 rd: writable_vreg(8),
3499 rn: vreg(2),
3500 rm: vreg(15),
3501 size: VectorSize::Size16x8,
3502 },
3503 "483C6F6E",
3504 "cmhs v8.8h, v2.8h, v15.8h",
3505 ));
3506
3507 insns.push((
3508 Inst::VecRRR {
3509 alu_op: VecALUOp::Cmeq,
3510 rd: writable_vreg(3),
3511 rn: vreg(23),
3512 rm: vreg(24),
3513 size: VectorSize::Size32x4,
3514 },
3515 "E38EB86E",
3516 "cmeq v3.4s, v23.4s, v24.4s",
3517 ));
3518
3519 insns.push((
3520 Inst::VecRRR {
3521 alu_op: VecALUOp::Cmgt,
3522 rd: writable_vreg(3),
3523 rn: vreg(23),
3524 rm: vreg(24),
3525 size: VectorSize::Size32x4,
3526 },
3527 "E336B84E",
3528 "cmgt v3.4s, v23.4s, v24.4s",
3529 ));
3530
3531 insns.push((
3532 Inst::VecRRR {
3533 alu_op: VecALUOp::Cmge,
3534 rd: writable_vreg(23),
3535 rn: vreg(9),
3536 rm: vreg(12),
3537 size: VectorSize::Size32x4,
3538 },
3539 "373DAC4E",
3540 "cmge v23.4s, v9.4s, v12.4s",
3541 ));
3542
3543 insns.push((
3544 Inst::VecRRR {
3545 alu_op: VecALUOp::Cmhi,
3546 rd: writable_vreg(5),
3547 rn: vreg(1),
3548 rm: vreg(1),
3549 size: VectorSize::Size32x4,
3550 },
3551 "2534A16E",
3552 "cmhi v5.4s, v1.4s, v1.4s",
3553 ));
3554
3555 insns.push((
3556 Inst::VecRRR {
3557 alu_op: VecALUOp::Cmhs,
3558 rd: writable_vreg(8),
3559 rn: vreg(2),
3560 rm: vreg(15),
3561 size: VectorSize::Size32x4,
3562 },
3563 "483CAF6E",
3564 "cmhs v8.4s, v2.4s, v15.4s",
3565 ));
3566
3567 insns.push((
3568 Inst::VecRRR {
3569 alu_op: VecALUOp::Fcmeq,
3570 rd: writable_vreg(28),
3571 rn: vreg(12),
3572 rm: vreg(4),
3573 size: VectorSize::Size32x2,
3574 },
3575 "9CE5240E",
3576 "fcmeq v28.2s, v12.2s, v4.2s",
3577 ));
3578
3579 insns.push((
3580 Inst::VecRRR {
3581 alu_op: VecALUOp::Fcmgt,
3582 rd: writable_vreg(3),
3583 rn: vreg(16),
3584 rm: vreg(31),
3585 size: VectorSize::Size64x2,
3586 },
3587 "03E6FF6E",
3588 "fcmgt v3.2d, v16.2d, v31.2d",
3589 ));
3590
3591 insns.push((
3592 Inst::VecRRR {
3593 alu_op: VecALUOp::Fcmge,
3594 rd: writable_vreg(18),
3595 rn: vreg(23),
3596 rm: vreg(0),
3597 size: VectorSize::Size64x2,
3598 },
3599 "F2E6606E",
3600 "fcmge v18.2d, v23.2d, v0.2d",
3601 ));
3602
3603 insns.push((
3604 Inst::VecRRR {
3605 alu_op: VecALUOp::And,
3606 rd: writable_vreg(20),
3607 rn: vreg(19),
3608 rm: vreg(18),
3609 size: VectorSize::Size32x4,
3610 },
3611 "741E324E",
3612 "and v20.16b, v19.16b, v18.16b",
3613 ));
3614
3615 insns.push((
3616 Inst::VecRRR {
3617 alu_op: VecALUOp::Bic,
3618 rd: writable_vreg(8),
3619 rn: vreg(11),
3620 rm: vreg(1),
3621 size: VectorSize::Size8x16,
3622 },
3623 "681D614E",
3624 "bic v8.16b, v11.16b, v1.16b",
3625 ));
3626
3627 insns.push((
3628 Inst::VecRRR {
3629 alu_op: VecALUOp::Orr,
3630 rd: writable_vreg(15),
3631 rn: vreg(2),
3632 rm: vreg(12),
3633 size: VectorSize::Size16x8,
3634 },
3635 "4F1CAC4E",
3636 "orr v15.16b, v2.16b, v12.16b",
3637 ));
3638
3639 insns.push((
3640 Inst::VecRRR {
3641 alu_op: VecALUOp::Eor,
3642 rd: writable_vreg(18),
3643 rn: vreg(3),
3644 rm: vreg(22),
3645 size: VectorSize::Size8x16,
3646 },
3647 "721C366E",
3648 "eor v18.16b, v3.16b, v22.16b",
3649 ));
3650
3651 insns.push((
3652 Inst::VecRRRMod {
3653 alu_op: VecALUModOp::Bsl,
3654 rd: writable_vreg(8),
3655 ri: vreg(8),
3656 rn: vreg(9),
3657 rm: vreg(1),
3658 size: VectorSize::Size8x16,
3659 },
3660 "281D616E",
3661 "bsl v8.16b, v8.16b, v9.16b, v1.16b",
3662 ));
3663
3664 insns.push((
3665 Inst::VecRRR {
3666 alu_op: VecALUOp::Umaxp,
3667 rd: writable_vreg(8),
3668 rn: vreg(12),
3669 rm: vreg(1),
3670 size: VectorSize::Size8x16,
3671 },
3672 "88A5216E",
3673 "umaxp v8.16b, v12.16b, v1.16b",
3674 ));
3675
3676 insns.push((
3677 Inst::VecRRR {
3678 alu_op: VecALUOp::Umaxp,
3679 rd: writable_vreg(1),
3680 rn: vreg(6),
3681 rm: vreg(1),
3682 size: VectorSize::Size16x8,
3683 },
3684 "C1A4616E",
3685 "umaxp v1.8h, v6.8h, v1.8h",
3686 ));
3687
3688 insns.push((
3689 Inst::VecRRR {
3690 alu_op: VecALUOp::Umaxp,
3691 rd: writable_vreg(1),
3692 rn: vreg(20),
3693 rm: vreg(16),
3694 size: VectorSize::Size32x4,
3695 },
3696 "81A6B06E",
3697 "umaxp v1.4s, v20.4s, v16.4s",
3698 ));
3699
3700 insns.push((
3701 Inst::VecRRR {
3702 alu_op: VecALUOp::Add,
3703 rd: writable_vreg(5),
3704 rn: vreg(1),
3705 rm: vreg(1),
3706 size: VectorSize::Size8x16,
3707 },
3708 "2584214E",
3709 "add v5.16b, v1.16b, v1.16b",
3710 ));
3711
3712 insns.push((
3713 Inst::VecRRR {
3714 alu_op: VecALUOp::Add,
3715 rd: writable_vreg(7),
3716 rn: vreg(13),
3717 rm: vreg(2),
3718 size: VectorSize::Size16x8,
3719 },
3720 "A785624E",
3721 "add v7.8h, v13.8h, v2.8h",
3722 ));
3723
3724 insns.push((
3725 Inst::VecRRR {
3726 alu_op: VecALUOp::Add,
3727 rd: writable_vreg(18),
3728 rn: vreg(9),
3729 rm: vreg(6),
3730 size: VectorSize::Size32x4,
3731 },
3732 "3285A64E",
3733 "add v18.4s, v9.4s, v6.4s",
3734 ));
3735
3736 insns.push((
3737 Inst::VecRRR {
3738 alu_op: VecALUOp::Add,
3739 rd: writable_vreg(1),
3740 rn: vreg(3),
3741 rm: vreg(2),
3742 size: VectorSize::Size64x2,
3743 },
3744 "6184E24E",
3745 "add v1.2d, v3.2d, v2.2d",
3746 ));
3747
3748 insns.push((
3749 Inst::VecRRR {
3750 alu_op: VecALUOp::Sub,
3751 rd: writable_vreg(5),
3752 rn: vreg(1),
3753 rm: vreg(1),
3754 size: VectorSize::Size8x16,
3755 },
3756 "2584216E",
3757 "sub v5.16b, v1.16b, v1.16b",
3758 ));
3759
3760 insns.push((
3761 Inst::VecRRR {
3762 alu_op: VecALUOp::Sub,
3763 rd: writable_vreg(7),
3764 rn: vreg(13),
3765 rm: vreg(2),
3766 size: VectorSize::Size16x8,
3767 },
3768 "A785626E",
3769 "sub v7.8h, v13.8h, v2.8h",
3770 ));
3771
3772 insns.push((
3773 Inst::VecRRR {
3774 alu_op: VecALUOp::Sub,
3775 rd: writable_vreg(18),
3776 rn: vreg(9),
3777 rm: vreg(6),
3778 size: VectorSize::Size32x4,
3779 },
3780 "3285A66E",
3781 "sub v18.4s, v9.4s, v6.4s",
3782 ));
3783
3784 insns.push((
3785 Inst::VecRRR {
3786 alu_op: VecALUOp::Sub,
3787 rd: writable_vreg(18),
3788 rn: vreg(0),
3789 rm: vreg(8),
3790 size: VectorSize::Size64x2,
3791 },
3792 "1284E86E",
3793 "sub v18.2d, v0.2d, v8.2d",
3794 ));
3795
3796 insns.push((
3797 Inst::VecRRR {
3798 alu_op: VecALUOp::Mul,
3799 rd: writable_vreg(25),
3800 rn: vreg(9),
3801 rm: vreg(8),
3802 size: VectorSize::Size8x16,
3803 },
3804 "399D284E",
3805 "mul v25.16b, v9.16b, v8.16b",
3806 ));
3807
3808 insns.push((
3809 Inst::VecRRR {
3810 alu_op: VecALUOp::Mul,
3811 rd: writable_vreg(30),
3812 rn: vreg(30),
3813 rm: vreg(12),
3814 size: VectorSize::Size16x8,
3815 },
3816 "DE9F6C4E",
3817 "mul v30.8h, v30.8h, v12.8h",
3818 ));
3819
3820 insns.push((
3821 Inst::VecRRR {
3822 alu_op: VecALUOp::Mul,
3823 rd: writable_vreg(18),
3824 rn: vreg(18),
3825 rm: vreg(18),
3826 size: VectorSize::Size32x4,
3827 },
3828 "529EB24E",
3829 "mul v18.4s, v18.4s, v18.4s",
3830 ));
3831
3832 insns.push((
3833 Inst::VecRRR {
3834 alu_op: VecALUOp::Ushl,
3835 rd: writable_vreg(18),
3836 rn: vreg(18),
3837 rm: vreg(18),
3838 size: VectorSize::Size8x16,
3839 },
3840 "5246326E",
3841 "ushl v18.16b, v18.16b, v18.16b",
3842 ));
3843
3844 insns.push((
3845 Inst::VecRRR {
3846 alu_op: VecALUOp::Ushl,
3847 rd: writable_vreg(18),
3848 rn: vreg(18),
3849 rm: vreg(18),
3850 size: VectorSize::Size16x8,
3851 },
3852 "5246726E",
3853 "ushl v18.8h, v18.8h, v18.8h",
3854 ));
3855
3856 insns.push((
3857 Inst::VecRRR {
3858 alu_op: VecALUOp::Ushl,
3859 rd: writable_vreg(18),
3860 rn: vreg(1),
3861 rm: vreg(21),
3862 size: VectorSize::Size32x4,
3863 },
3864 "3244B56E",
3865 "ushl v18.4s, v1.4s, v21.4s",
3866 ));
3867
3868 insns.push((
3869 Inst::VecRRR {
3870 alu_op: VecALUOp::Ushl,
3871 rd: writable_vreg(5),
3872 rn: vreg(7),
3873 rm: vreg(19),
3874 size: VectorSize::Size64x2,
3875 },
3876 "E544F36E",
3877 "ushl v5.2d, v7.2d, v19.2d",
3878 ));
3879
3880 insns.push((
3881 Inst::VecRRR {
3882 alu_op: VecALUOp::Sshl,
3883 rd: writable_vreg(18),
3884 rn: vreg(18),
3885 rm: vreg(18),
3886 size: VectorSize::Size8x16,
3887 },
3888 "5246324E",
3889 "sshl v18.16b, v18.16b, v18.16b",
3890 ));
3891
3892 insns.push((
3893 Inst::VecRRR {
3894 alu_op: VecALUOp::Sshl,
3895 rd: writable_vreg(30),
3896 rn: vreg(1),
3897 rm: vreg(29),
3898 size: VectorSize::Size16x8,
3899 },
3900 "3E447D4E",
3901 "sshl v30.8h, v1.8h, v29.8h",
3902 ));
3903
3904 insns.push((
3905 Inst::VecRRR {
3906 alu_op: VecALUOp::Sshl,
3907 rd: writable_vreg(8),
3908 rn: vreg(22),
3909 rm: vreg(21),
3910 size: VectorSize::Size32x4,
3911 },
3912 "C846B54E",
3913 "sshl v8.4s, v22.4s, v21.4s",
3914 ));
3915
3916 insns.push((
3917 Inst::VecRRR {
3918 alu_op: VecALUOp::Sshl,
3919 rd: writable_vreg(8),
3920 rn: vreg(22),
3921 rm: vreg(2),
3922 size: VectorSize::Size64x2,
3923 },
3924 "C846E24E",
3925 "sshl v8.2d, v22.2d, v2.2d",
3926 ));
3927
3928 insns.push((
3929 Inst::VecRRR {
3930 alu_op: VecALUOp::Umin,
3931 rd: writable_vreg(0),
3932 rn: vreg(11),
3933 rm: vreg(2),
3934 size: VectorSize::Size8x8,
3935 },
3936 "606D222E",
3937 "umin v0.8b, v11.8b, v2.8b",
3938 ));
3939
3940 insns.push((
3941 Inst::VecRRR {
3942 alu_op: VecALUOp::Umin,
3943 rd: writable_vreg(1),
3944 rn: vreg(12),
3945 rm: vreg(3),
3946 size: VectorSize::Size8x16,
3947 },
3948 "816D236E",
3949 "umin v1.16b, v12.16b, v3.16b",
3950 ));
3951
3952 insns.push((
3953 Inst::VecRRR {
3954 alu_op: VecALUOp::Umin,
3955 rd: writable_vreg(29),
3956 rn: vreg(19),
3957 rm: vreg(9),
3958 size: VectorSize::Size16x4,
3959 },
3960 "7D6E692E",
3961 "umin v29.4h, v19.4h, v9.4h",
3962 ));
3963
3964 insns.push((
3965 Inst::VecRRR {
3966 alu_op: VecALUOp::Umin,
3967 rd: writable_vreg(30),
3968 rn: vreg(20),
3969 rm: vreg(10),
3970 size: VectorSize::Size16x8,
3971 },
3972 "9E6E6A6E",
3973 "umin v30.8h, v20.8h, v10.8h",
3974 ));
3975
3976 insns.push((
3977 Inst::VecRRR {
3978 alu_op: VecALUOp::Umin,
3979 rd: writable_vreg(7),
3980 rn: vreg(21),
3981 rm: vreg(20),
3982 size: VectorSize::Size32x2,
3983 },
3984 "A76EB42E",
3985 "umin v7.2s, v21.2s, v20.2s",
3986 ));
3987
3988 insns.push((
3989 Inst::VecRRR {
3990 alu_op: VecALUOp::Umin,
3991 rd: writable_vreg(8),
3992 rn: vreg(22),
3993 rm: vreg(21),
3994 size: VectorSize::Size32x4,
3995 },
3996 "C86EB56E",
3997 "umin v8.4s, v22.4s, v21.4s",
3998 ));
3999
4000 insns.push((
4001 Inst::VecRRR {
4002 alu_op: VecALUOp::Smin,
4003 rd: writable_vreg(2),
4004 rn: vreg(13),
4005 rm: vreg(4),
4006 size: VectorSize::Size8x8,
4007 },
4008 "A26D240E",
4009 "smin v2.8b, v13.8b, v4.8b",
4010 ));
4011
4012 insns.push((
4013 Inst::VecRRR {
4014 alu_op: VecALUOp::Smin,
4015 rd: writable_vreg(1),
4016 rn: vreg(12),
4017 rm: vreg(3),
4018 size: VectorSize::Size8x16,
4019 },
4020 "816D234E",
4021 "smin v1.16b, v12.16b, v3.16b",
4022 ));
4023
4024 insns.push((
4025 Inst::VecRRR {
4026 alu_op: VecALUOp::Smin,
4027 rd: writable_vreg(3),
4028 rn: vreg(2),
4029 rm: vreg(1),
4030 size: VectorSize::Size16x4,
4031 },
4032 "436C610E",
4033 "smin v3.4h, v2.4h, v1.4h",
4034 ));
4035
4036 insns.push((
4037 Inst::VecRRR {
4038 alu_op: VecALUOp::Smin,
4039 rd: writable_vreg(30),
4040 rn: vreg(20),
4041 rm: vreg(10),
4042 size: VectorSize::Size16x8,
4043 },
4044 "9E6E6A4E",
4045 "smin v30.8h, v20.8h, v10.8h",
4046 ));
4047
4048 insns.push((
4049 Inst::VecRRR {
4050 alu_op: VecALUOp::Smin,
4051 rd: writable_vreg(9),
4052 rn: vreg(22),
4053 rm: vreg(20),
4054 size: VectorSize::Size32x2,
4055 },
4056 "C96EB40E",
4057 "smin v9.2s, v22.2s, v20.2s",
4058 ));
4059
4060 insns.push((
4061 Inst::VecRRR {
4062 alu_op: VecALUOp::Smin,
4063 rd: writable_vreg(8),
4064 rn: vreg(22),
4065 rm: vreg(21),
4066 size: VectorSize::Size32x4,
4067 },
4068 "C86EB54E",
4069 "smin v8.4s, v22.4s, v21.4s",
4070 ));
4071
4072 insns.push((
4073 Inst::VecRRR {
4074 alu_op: VecALUOp::Umax,
4075 rd: writable_vreg(6),
4076 rn: vreg(9),
4077 rm: vreg(8),
4078 size: VectorSize::Size8x8,
4079 },
4080 "2665282E",
4081 "umax v6.8b, v9.8b, v8.8b",
4082 ));
4083
4084 insns.push((
4085 Inst::VecRRR {
4086 alu_op: VecALUOp::Umax,
4087 rd: writable_vreg(5),
4088 rn: vreg(15),
4089 rm: vreg(8),
4090 size: VectorSize::Size8x16,
4091 },
4092 "E565286E",
4093 "umax v5.16b, v15.16b, v8.16b",
4094 ));
4095
4096 insns.push((
4097 Inst::VecRRR {
4098 alu_op: VecALUOp::Umax,
4099 rd: writable_vreg(12),
4100 rn: vreg(14),
4101 rm: vreg(3),
4102 size: VectorSize::Size16x4,
4103 },
4104 "CC65632E",
4105 "umax v12.4h, v14.4h, v3.4h",
4106 ));
4107
4108 insns.push((
4109 Inst::VecRRR {
4110 alu_op: VecALUOp::Umax,
4111 rd: writable_vreg(11),
4112 rn: vreg(13),
4113 rm: vreg(2),
4114 size: VectorSize::Size16x8,
4115 },
4116 "AB65626E",
4117 "umax v11.8h, v13.8h, v2.8h",
4118 ));
4119
4120 insns.push((
4121 Inst::VecRRR {
4122 alu_op: VecALUOp::Umax,
4123 rd: writable_vreg(9),
4124 rn: vreg(13),
4125 rm: vreg(15),
4126 size: VectorSize::Size32x2,
4127 },
4128 "A965AF2E",
4129 "umax v9.2s, v13.2s, v15.2s",
4130 ));
4131
4132 insns.push((
4133 Inst::VecRRR {
4134 alu_op: VecALUOp::Umax,
4135 rd: writable_vreg(8),
4136 rn: vreg(12),
4137 rm: vreg(14),
4138 size: VectorSize::Size32x4,
4139 },
4140 "8865AE6E",
4141 "umax v8.4s, v12.4s, v14.4s",
4142 ));
4143
4144 insns.push((
4145 Inst::VecRRR {
4146 alu_op: VecALUOp::Smax,
4147 rd: writable_vreg(7),
4148 rn: vreg(8),
4149 rm: vreg(9),
4150 size: VectorSize::Size8x8,
4151 },
4152 "0765290E",
4153 "smax v7.8b, v8.8b, v9.8b",
4154 ));
4155
4156 insns.push((
4157 Inst::VecRRR {
4158 alu_op: VecALUOp::Smax,
4159 rd: writable_vreg(6),
4160 rn: vreg(9),
4161 rm: vreg(8),
4162 size: VectorSize::Size8x16,
4163 },
4164 "2665284E",
4165 "smax v6.16b, v9.16b, v8.16b",
4166 ));
4167
4168 insns.push((
4169 Inst::VecRRR {
4170 alu_op: VecALUOp::Smax,
4171 rd: writable_vreg(11),
4172 rn: vreg(12),
4173 rm: vreg(13),
4174 size: VectorSize::Size16x4,
4175 },
4176 "8B656D0E",
4177 "smax v11.4h, v12.4h, v13.4h",
4178 ));
4179
4180 insns.push((
4181 Inst::VecRRR {
4182 alu_op: VecALUOp::Smax,
4183 rd: writable_vreg(11),
4184 rn: vreg(13),
4185 rm: vreg(2),
4186 size: VectorSize::Size16x8,
4187 },
4188 "AB65624E",
4189 "smax v11.8h, v13.8h, v2.8h",
4190 ));
4191
4192 insns.push((
4193 Inst::VecRRR {
4194 alu_op: VecALUOp::Smax,
4195 rd: writable_vreg(14),
4196 rn: vreg(16),
4197 rm: vreg(18),
4198 size: VectorSize::Size32x2,
4199 },
4200 "0E66B20E",
4201 "smax v14.2s, v16.2s, v18.2s",
4202 ));
4203
4204 insns.push((
4205 Inst::VecRRR {
4206 alu_op: VecALUOp::Smax,
4207 rd: writable_vreg(8),
4208 rn: vreg(12),
4209 rm: vreg(14),
4210 size: VectorSize::Size32x4,
4211 },
4212 "8865AE4E",
4213 "smax v8.4s, v12.4s, v14.4s",
4214 ));
4215
4216 insns.push((
4217 Inst::VecRRR {
4218 alu_op: VecALUOp::Urhadd,
4219 rd: writable_vreg(8),
4220 rn: vreg(1),
4221 rm: vreg(3),
4222 size: VectorSize::Size8x8,
4223 },
4224 "2814232E",
4225 "urhadd v8.8b, v1.8b, v3.8b",
4226 ));
4227
4228 insns.push((
4229 Inst::VecRRR {
4230 alu_op: VecALUOp::Urhadd,
4231 rd: writable_vreg(8),
4232 rn: vreg(1),
4233 rm: vreg(3),
4234 size: VectorSize::Size8x16,
4235 },
4236 "2814236E",
4237 "urhadd v8.16b, v1.16b, v3.16b",
4238 ));
4239
4240 insns.push((
4241 Inst::VecRRR {
4242 alu_op: VecALUOp::Urhadd,
4243 rd: writable_vreg(2),
4244 rn: vreg(13),
4245 rm: vreg(6),
4246 size: VectorSize::Size16x4,
4247 },
4248 "A215662E",
4249 "urhadd v2.4h, v13.4h, v6.4h",
4250 ));
4251
4252 insns.push((
4253 Inst::VecRRR {
4254 alu_op: VecALUOp::Urhadd,
4255 rd: writable_vreg(2),
4256 rn: vreg(13),
4257 rm: vreg(6),
4258 size: VectorSize::Size16x8,
4259 },
4260 "A215666E",
4261 "urhadd v2.8h, v13.8h, v6.8h",
4262 ));
4263
4264 insns.push((
4265 Inst::VecRRR {
4266 alu_op: VecALUOp::Urhadd,
4267 rd: writable_vreg(8),
4268 rn: vreg(12),
4269 rm: vreg(14),
4270 size: VectorSize::Size32x2,
4271 },
4272 "8815AE2E",
4273 "urhadd v8.2s, v12.2s, v14.2s",
4274 ));
4275
4276 insns.push((
4277 Inst::VecRRR {
4278 alu_op: VecALUOp::Urhadd,
4279 rd: writable_vreg(8),
4280 rn: vreg(12),
4281 rm: vreg(14),
4282 size: VectorSize::Size32x4,
4283 },
4284 "8815AE6E",
4285 "urhadd v8.4s, v12.4s, v14.4s",
4286 ));
4287
4288 insns.push((
4289 Inst::VecRRR {
4290 alu_op: VecALUOp::Fadd,
4291 rd: writable_vreg(31),
4292 rn: vreg(0),
4293 rm: vreg(16),
4294 size: VectorSize::Size32x4,
4295 },
4296 "1FD4304E",
4297 "fadd v31.4s, v0.4s, v16.4s",
4298 ));
4299
4300 insns.push((
4301 Inst::VecRRR {
4302 alu_op: VecALUOp::Fsub,
4303 rd: writable_vreg(8),
4304 rn: vreg(7),
4305 rm: vreg(15),
4306 size: VectorSize::Size64x2,
4307 },
4308 "E8D4EF4E",
4309 "fsub v8.2d, v7.2d, v15.2d",
4310 ));
4311
4312 insns.push((
4313 Inst::VecRRR {
4314 alu_op: VecALUOp::Fdiv,
4315 rd: writable_vreg(1),
4316 rn: vreg(3),
4317 rm: vreg(4),
4318 size: VectorSize::Size32x4,
4319 },
4320 "61FC246E",
4321 "fdiv v1.4s, v3.4s, v4.4s",
4322 ));
4323
4324 insns.push((
4325 Inst::VecRRR {
4326 alu_op: VecALUOp::Fmax,
4327 rd: writable_vreg(31),
4328 rn: vreg(16),
4329 rm: vreg(0),
4330 size: VectorSize::Size64x2,
4331 },
4332 "1FF6604E",
4333 "fmax v31.2d, v16.2d, v0.2d",
4334 ));
4335
4336 insns.push((
4337 Inst::VecRRR {
4338 alu_op: VecALUOp::Fmin,
4339 rd: writable_vreg(5),
4340 rn: vreg(19),
4341 rm: vreg(26),
4342 size: VectorSize::Size32x4,
4343 },
4344 "65F6BA4E",
4345 "fmin v5.4s, v19.4s, v26.4s",
4346 ));
4347
4348 insns.push((
4349 Inst::VecRRR {
4350 alu_op: VecALUOp::Fmul,
4351 rd: writable_vreg(2),
4352 rn: vreg(0),
4353 rm: vreg(5),
4354 size: VectorSize::Size64x2,
4355 },
4356 "02DC656E",
4357 "fmul v2.2d, v0.2d, v5.2d",
4358 ));
4359
4360 insns.push((
4361 Inst::VecRRRMod {
4362 alu_op: VecALUModOp::Fmla,
4363 rd: writable_vreg(2),
4364 ri: vreg(2),
4365 rn: vreg(0),
4366 rm: vreg(5),
4367 size: VectorSize::Size32x2,
4368 },
4369 "02CC250E",
4370 "fmla v2.2s, v2.2s, v0.2s, v5.2s",
4371 ));
4372
4373 insns.push((
4374 Inst::VecRRRMod {
4375 alu_op: VecALUModOp::Fmla,
4376 rd: writable_vreg(2),
4377 ri: vreg(2),
4378 rn: vreg(0),
4379 rm: vreg(5),
4380 size: VectorSize::Size32x4,
4381 },
4382 "02CC254E",
4383 "fmla v2.4s, v2.4s, v0.4s, v5.4s",
4384 ));
4385
4386 insns.push((
4387 Inst::VecRRRMod {
4388 alu_op: VecALUModOp::Fmla,
4389 rd: writable_vreg(2),
4390 ri: vreg(2),
4391 rn: vreg(0),
4392 rm: vreg(5),
4393 size: VectorSize::Size64x2,
4394 },
4395 "02CC654E",
4396 "fmla v2.2d, v2.2d, v0.2d, v5.2d",
4397 ));
4398
4399 insns.push((
4400 Inst::VecRRR {
4401 alu_op: VecALUOp::Addp,
4402 rd: writable_vreg(16),
4403 rn: vreg(12),
4404 rm: vreg(1),
4405 size: VectorSize::Size8x8,
4406 },
4407 "90BD210E",
4408 "addp v16.8b, v12.8b, v1.8b",
4409 ));
4410
4411 insns.push((
4412 Inst::VecRRR {
4413 alu_op: VecALUOp::Addp,
4414 rd: writable_vreg(16),
4415 rn: vreg(12),
4416 rm: vreg(1),
4417 size: VectorSize::Size8x16,
4418 },
4419 "90BD214E",
4420 "addp v16.16b, v12.16b, v1.16b",
4421 ));
4422
4423 insns.push((
4424 Inst::VecRRR {
4425 alu_op: VecALUOp::Addp,
4426 rd: writable_vreg(8),
4427 rn: vreg(12),
4428 rm: vreg(14),
4429 size: VectorSize::Size32x4,
4430 },
4431 "88BDAE4E",
4432 "addp v8.4s, v12.4s, v14.4s",
4433 ));
4434
4435 insns.push((
4436 Inst::VecRRR {
4437 alu_op: VecALUOp::Addp,
4438 rd: writable_vreg(8),
4439 rn: vreg(12),
4440 rm: vreg(14),
4441 size: VectorSize::Size32x2,
4442 },
4443 "88BDAE0E",
4444 "addp v8.2s, v12.2s, v14.2s",
4445 ));
4446
4447 insns.push((
4448 Inst::VecRRR {
4449 alu_op: VecALUOp::Zip1,
4450 rd: writable_vreg(16),
4451 rn: vreg(12),
4452 rm: vreg(1),
4453 size: VectorSize::Size8x16,
4454 },
4455 "9039014E",
4456 "zip1 v16.16b, v12.16b, v1.16b",
4457 ));
4458
4459 insns.push((
4460 Inst::VecRRR {
4461 alu_op: VecALUOp::Zip1,
4462 rd: writable_vreg(2),
4463 rn: vreg(13),
4464 rm: vreg(6),
4465 size: VectorSize::Size16x8,
4466 },
4467 "A239464E",
4468 "zip1 v2.8h, v13.8h, v6.8h",
4469 ));
4470
4471 insns.push((
4472 Inst::VecRRR {
4473 alu_op: VecALUOp::Zip1,
4474 rd: writable_vreg(8),
4475 rn: vreg(12),
4476 rm: vreg(14),
4477 size: VectorSize::Size32x4,
4478 },
4479 "88398E4E",
4480 "zip1 v8.4s, v12.4s, v14.4s",
4481 ));
4482
4483 insns.push((
4484 Inst::VecRRR {
4485 alu_op: VecALUOp::Zip1,
4486 rd: writable_vreg(9),
4487 rn: vreg(20),
4488 rm: vreg(17),
4489 size: VectorSize::Size64x2,
4490 },
4491 "893AD14E",
4492 "zip1 v9.2d, v20.2d, v17.2d",
4493 ));
4494
4495 insns.push((
4496 Inst::VecRRRLong {
4497 alu_op: VecRRRLongOp::Smull8,
4498 rd: writable_vreg(16),
4499 rn: vreg(12),
4500 rm: vreg(1),
4501 high_half: false,
4502 },
4503 "90C1210E",
4504 "smull v16.8h, v12.8b, v1.8b",
4505 ));
4506
4507 insns.push((
4508 Inst::VecRRRLong {
4509 alu_op: VecRRRLongOp::Umull8,
4510 rd: writable_vreg(15),
4511 rn: vreg(11),
4512 rm: vreg(2),
4513 high_half: false,
4514 },
4515 "6FC1222E",
4516 "umull v15.8h, v11.8b, v2.8b",
4517 ));
4518
4519 insns.push((
4520 Inst::VecRRRLongMod {
4521 alu_op: VecRRRLongModOp::Umlal8,
4522 rd: writable_vreg(4),
4523 ri: vreg(4),
4524 rn: vreg(8),
4525 rm: vreg(16),
4526 high_half: false,
4527 },
4528 "0481302E",
4529 "umlal v4.8h, v4.8h, v8.8b, v16.8b",
4530 ));
4531
4532 insns.push((
4533 Inst::VecRRRLong {
4534 alu_op: VecRRRLongOp::Smull16,
4535 rd: writable_vreg(2),
4536 rn: vreg(13),
4537 rm: vreg(6),
4538 high_half: false,
4539 },
4540 "A2C1660E",
4541 "smull v2.4s, v13.4h, v6.4h",
4542 ));
4543
4544 insns.push((
4545 Inst::VecRRRLong {
4546 alu_op: VecRRRLongOp::Umull16,
4547 rd: writable_vreg(3),
4548 rn: vreg(14),
4549 rm: vreg(7),
4550 high_half: false,
4551 },
4552 "C3C1672E",
4553 "umull v3.4s, v14.4h, v7.4h",
4554 ));
4555
4556 insns.push((
4557 Inst::VecRRRLongMod {
4558 alu_op: VecRRRLongModOp::Umlal16,
4559 rd: writable_vreg(7),
4560 ri: vreg(7),
4561 rn: vreg(14),
4562 rm: vreg(21),
4563 high_half: false,
4564 },
4565 "C781752E",
4566 "umlal v7.4s, v7.4s, v14.4h, v21.4h",
4567 ));
4568
4569 insns.push((
4570 Inst::VecRRRLong {
4571 alu_op: VecRRRLongOp::Smull32,
4572 rd: writable_vreg(8),
4573 rn: vreg(12),
4574 rm: vreg(14),
4575 high_half: false,
4576 },
4577 "88C1AE0E",
4578 "smull v8.2d, v12.2s, v14.2s",
4579 ));
4580
4581 insns.push((
4582 Inst::VecRRRLong {
4583 alu_op: VecRRRLongOp::Umull32,
4584 rd: writable_vreg(9),
4585 rn: vreg(5),
4586 rm: vreg(6),
4587 high_half: false,
4588 },
4589 "A9C0A62E",
4590 "umull v9.2d, v5.2s, v6.2s",
4591 ));
4592
4593 insns.push((
4594 Inst::VecRRRLongMod {
4595 alu_op: VecRRRLongModOp::Umlal32,
4596 rd: writable_vreg(9),
4597 ri: vreg(9),
4598 rn: vreg(20),
4599 rm: vreg(17),
4600 high_half: false,
4601 },
4602 "8982B12E",
4603 "umlal v9.2d, v9.2d, v20.2s, v17.2s",
4604 ));
4605
4606 insns.push((
4607 Inst::VecRRRLong {
4608 alu_op: VecRRRLongOp::Smull8,
4609 rd: writable_vreg(16),
4610 rn: vreg(12),
4611 rm: vreg(1),
4612 high_half: true,
4613 },
4614 "90C1214E",
4615 "smull2 v16.8h, v12.16b, v1.16b",
4616 ));
4617
4618 insns.push((
4619 Inst::VecRRRLong {
4620 alu_op: VecRRRLongOp::Umull8,
4621 rd: writable_vreg(29),
4622 rn: vreg(22),
4623 rm: vreg(10),
4624 high_half: true,
4625 },
4626 "DDC22A6E",
4627 "umull2 v29.8h, v22.16b, v10.16b",
4628 ));
4629
4630 insns.push((
4631 Inst::VecRRRLongMod {
4632 alu_op: VecRRRLongModOp::Umlal8,
4633 rd: writable_vreg(1),
4634 ri: vreg(1),
4635 rn: vreg(5),
4636 rm: vreg(15),
4637 high_half: true,
4638 },
4639 "A1802F6E",
4640 "umlal2 v1.8h, v1.8h, v5.16b, v15.16b",
4641 ));
4642
4643 insns.push((
4644 Inst::VecRRRLong {
4645 alu_op: VecRRRLongOp::Smull16,
4646 rd: writable_vreg(2),
4647 rn: vreg(13),
4648 rm: vreg(6),
4649 high_half: true,
4650 },
4651 "A2C1664E",
4652 "smull2 v2.4s, v13.8h, v6.8h",
4653 ));
4654
4655 insns.push((
4656 Inst::VecRRRLong {
4657 alu_op: VecRRRLongOp::Umull16,
4658 rd: writable_vreg(19),
4659 rn: vreg(18),
4660 rm: vreg(17),
4661 high_half: true,
4662 },
4663 "53C2716E",
4664 "umull2 v19.4s, v18.8h, v17.8h",
4665 ));
4666
4667 insns.push((
4668 Inst::VecRRRLongMod {
4669 alu_op: VecRRRLongModOp::Umlal16,
4670 rd: writable_vreg(11),
4671 ri: vreg(11),
4672 rn: vreg(10),
4673 rm: vreg(12),
4674 high_half: true,
4675 },
4676 "4B816C6E",
4677 "umlal2 v11.4s, v11.4s, v10.8h, v12.8h",
4678 ));
4679
4680 insns.push((
4681 Inst::VecRRRLong {
4682 alu_op: VecRRRLongOp::Smull32,
4683 rd: writable_vreg(8),
4684 rn: vreg(12),
4685 rm: vreg(14),
4686 high_half: true,
4687 },
4688 "88C1AE4E",
4689 "smull2 v8.2d, v12.4s, v14.4s",
4690 ));
4691
4692 insns.push((
4693 Inst::VecRRRLong {
4694 alu_op: VecRRRLongOp::Umull32,
4695 rd: writable_vreg(4),
4696 rn: vreg(12),
4697 rm: vreg(16),
4698 high_half: true,
4699 },
4700 "84C1B06E",
4701 "umull2 v4.2d, v12.4s, v16.4s",
4702 ));
4703
4704 insns.push((
4705 Inst::VecRRRLongMod {
4706 alu_op: VecRRRLongModOp::Umlal32,
4707 rd: writable_vreg(10),
4708 ri: vreg(10),
4709 rn: vreg(29),
4710 rm: vreg(2),
4711 high_half: true,
4712 },
4713 "AA83A26E",
4714 "umlal2 v10.2d, v10.2d, v29.4s, v2.4s",
4715 ));
4716
4717 insns.push((
4718 Inst::VecRRR {
4719 alu_op: VecALUOp::Sqrdmulh,
4720 rd: writable_vreg(31),
4721 rn: vreg(0),
4722 rm: vreg(31),
4723 size: VectorSize::Size16x8,
4724 },
4725 "1FB47F6E",
4726 "sqrdmulh v31.8h, v0.8h, v31.8h",
4727 ));
4728
4729 insns.push((
4730 Inst::VecRRR {
4731 alu_op: VecALUOp::Sqrdmulh,
4732 rd: writable_vreg(7),
4733 rn: vreg(7),
4734 rm: vreg(23),
4735 size: VectorSize::Size32x2,
4736 },
4737 "E7B4B72E",
4738 "sqrdmulh v7.2s, v7.2s, v23.2s",
4739 ));
4740
4741 insns.push((
4742 Inst::VecMisc {
4743 op: VecMisc2::Not,
4744 rd: writable_vreg(20),
4745 rn: vreg(17),
4746 size: VectorSize::Size8x8,
4747 },
4748 "345A202E",
4749 "mvn v20.8b, v17.8b",
4750 ));
4751
4752 insns.push((
4753 Inst::VecMisc {
4754 op: VecMisc2::Not,
4755 rd: writable_vreg(2),
4756 rn: vreg(1),
4757 size: VectorSize::Size32x4,
4758 },
4759 "2258206E",
4760 "mvn v2.16b, v1.16b",
4761 ));
4762
4763 insns.push((
4764 Inst::VecMisc {
4765 op: VecMisc2::Neg,
4766 rd: writable_vreg(3),
4767 rn: vreg(7),
4768 size: VectorSize::Size8x8,
4769 },
4770 "E3B8202E",
4771 "neg v3.8b, v7.8b",
4772 ));
4773
4774 insns.push((
4775 Inst::VecMisc {
4776 op: VecMisc2::Neg,
4777 rd: writable_vreg(8),
4778 rn: vreg(12),
4779 size: VectorSize::Size8x16,
4780 },
4781 "88B9206E",
4782 "neg v8.16b, v12.16b",
4783 ));
4784
4785 insns.push((
4786 Inst::VecMisc {
4787 op: VecMisc2::Neg,
4788 rd: writable_vreg(0),
4789 rn: vreg(31),
4790 size: VectorSize::Size16x8,
4791 },
4792 "E0BB606E",
4793 "neg v0.8h, v31.8h",
4794 ));
4795
4796 insns.push((
4797 Inst::VecMisc {
4798 op: VecMisc2::Neg,
4799 rd: writable_vreg(2),
4800 rn: vreg(3),
4801 size: VectorSize::Size32x4,
4802 },
4803 "62B8A06E",
4804 "neg v2.4s, v3.4s",
4805 ));
4806
4807 insns.push((
4808 Inst::VecMisc {
4809 op: VecMisc2::Neg,
4810 rd: writable_vreg(10),
4811 rn: vreg(8),
4812 size: VectorSize::Size64x2,
4813 },
4814 "0AB9E06E",
4815 "neg v10.2d, v8.2d",
4816 ));
4817
4818 insns.push((
4819 Inst::VecMisc {
4820 op: VecMisc2::Abs,
4821 rd: writable_vreg(3),
4822 rn: vreg(1),
4823 size: VectorSize::Size8x8,
4824 },
4825 "23B8200E",
4826 "abs v3.8b, v1.8b",
4827 ));
4828
4829 insns.push((
4830 Inst::VecMisc {
4831 op: VecMisc2::Abs,
4832 rd: writable_vreg(1),
4833 rn: vreg(1),
4834 size: VectorSize::Size8x16,
4835 },
4836 "21B8204E",
4837 "abs v1.16b, v1.16b",
4838 ));
4839
4840 insns.push((
4841 Inst::VecMisc {
4842 op: VecMisc2::Abs,
4843 rd: writable_vreg(29),
4844 rn: vreg(28),
4845 size: VectorSize::Size16x8,
4846 },
4847 "9DBB604E",
4848 "abs v29.8h, v28.8h",
4849 ));
4850
4851 insns.push((
4852 Inst::VecMisc {
4853 op: VecMisc2::Abs,
4854 rd: writable_vreg(7),
4855 rn: vreg(8),
4856 size: VectorSize::Size32x4,
4857 },
4858 "07B9A04E",
4859 "abs v7.4s, v8.4s",
4860 ));
4861
4862 insns.push((
4863 Inst::VecMisc {
4864 op: VecMisc2::Abs,
4865 rd: writable_vreg(1),
4866 rn: vreg(10),
4867 size: VectorSize::Size64x2,
4868 },
4869 "41B9E04E",
4870 "abs v1.2d, v10.2d",
4871 ));
4872
4873 insns.push((
4874 Inst::VecMisc {
4875 op: VecMisc2::Fabs,
4876 rd: writable_vreg(15),
4877 rn: vreg(16),
4878 size: VectorSize::Size32x2,
4879 },
4880 "0FFAA00E",
4881 "fabs v15.2s, v16.2s",
4882 ));
4883
4884 insns.push((
4885 Inst::VecMisc {
4886 op: VecMisc2::Fabs,
4887 rd: writable_vreg(15),
4888 rn: vreg(16),
4889 size: VectorSize::Size32x4,
4890 },
4891 "0FFAA04E",
4892 "fabs v15.4s, v16.4s",
4893 ));
4894
4895 insns.push((
4896 Inst::VecMisc {
4897 op: VecMisc2::Fabs,
4898 rd: writable_vreg(3),
4899 rn: vreg(22),
4900 size: VectorSize::Size64x2,
4901 },
4902 "C3FAE04E",
4903 "fabs v3.2d, v22.2d",
4904 ));
4905
4906 insns.push((
4907 Inst::VecMisc {
4908 op: VecMisc2::Fneg,
4909 rd: writable_vreg(31),
4910 rn: vreg(0),
4911 size: VectorSize::Size32x2,
4912 },
4913 "1FF8A02E",
4914 "fneg v31.2s, v0.2s",
4915 ));
4916
4917 insns.push((
4918 Inst::VecMisc {
4919 op: VecMisc2::Fneg,
4920 rd: writable_vreg(31),
4921 rn: vreg(0),
4922 size: VectorSize::Size32x4,
4923 },
4924 "1FF8A06E",
4925 "fneg v31.4s, v0.4s",
4926 ));
4927
4928 insns.push((
4929 Inst::VecMisc {
4930 op: VecMisc2::Fneg,
4931 rd: writable_vreg(11),
4932 rn: vreg(6),
4933 size: VectorSize::Size64x2,
4934 },
4935 "CBF8E06E",
4936 "fneg v11.2d, v6.2d",
4937 ));
4938
4939 insns.push((
4940 Inst::VecMisc {
4941 op: VecMisc2::Fsqrt,
4942 rd: writable_vreg(18),
4943 rn: vreg(25),
4944 size: VectorSize::Size32x2,
4945 },
4946 "32FBA12E",
4947 "fsqrt v18.2s, v25.2s",
4948 ));
4949
4950 insns.push((
4951 Inst::VecMisc {
4952 op: VecMisc2::Fsqrt,
4953 rd: writable_vreg(18),
4954 rn: vreg(25),
4955 size: VectorSize::Size32x4,
4956 },
4957 "32FBA16E",
4958 "fsqrt v18.4s, v25.4s",
4959 ));
4960
4961 insns.push((
4962 Inst::VecMisc {
4963 op: VecMisc2::Fsqrt,
4964 rd: writable_vreg(7),
4965 rn: vreg(18),
4966 size: VectorSize::Size64x2,
4967 },
4968 "47FAE16E",
4969 "fsqrt v7.2d, v18.2d",
4970 ));
4971
4972 insns.push((
4973 Inst::VecMisc {
4974 op: VecMisc2::Rev64,
4975 rd: writable_vreg(1),
4976 rn: vreg(10),
4977 size: VectorSize::Size32x4,
4978 },
4979 "4109A04E",
4980 "rev64 v1.4s, v10.4s",
4981 ));
4982
4983 insns.push((
4984 Inst::VecMisc {
4985 op: VecMisc2::Fcvtzs,
4986 rd: writable_vreg(4),
4987 rn: vreg(22),
4988 size: VectorSize::Size32x4,
4989 },
4990 "C4BAA14E",
4991 "fcvtzs v4.4s, v22.4s",
4992 ));
4993
4994 insns.push((
4995 Inst::VecMisc {
4996 op: VecMisc2::Fcvtzs,
4997 rd: writable_vreg(0),
4998 rn: vreg(31),
4999 size: VectorSize::Size64x2,
5000 },
5001 "E0BBE14E",
5002 "fcvtzs v0.2d, v31.2d",
5003 ));
5004
5005 insns.push((
5006 Inst::VecMisc {
5007 op: VecMisc2::Fcvtzu,
5008 rd: writable_vreg(4),
5009 rn: vreg(26),
5010 size: VectorSize::Size32x2,
5011 },
5012 "44BBA12E",
5013 "fcvtzu v4.2s, v26.2s",
5014 ));
5015
5016 insns.push((
5017 Inst::VecMisc {
5018 op: VecMisc2::Fcvtzu,
5019 rd: writable_vreg(29),
5020 rn: vreg(15),
5021 size: VectorSize::Size64x2,
5022 },
5023 "FDB9E16E",
5024 "fcvtzu v29.2d, v15.2d",
5025 ));
5026
5027 insns.push((
5028 Inst::VecMisc {
5029 op: VecMisc2::Scvtf,
5030 rd: writable_vreg(20),
5031 rn: vreg(8),
5032 size: VectorSize::Size32x4,
5033 },
5034 "14D9214E",
5035 "scvtf v20.4s, v8.4s",
5036 ));
5037
5038 insns.push((
5039 Inst::VecMisc {
5040 op: VecMisc2::Ucvtf,
5041 rd: writable_vreg(10),
5042 rn: vreg(19),
5043 size: VectorSize::Size64x2,
5044 },
5045 "6ADA616E",
5046 "ucvtf v10.2d, v19.2d",
5047 ));
5048
5049 insns.push((
5050 Inst::VecMisc {
5051 op: VecMisc2::Frintn,
5052 rd: writable_vreg(20),
5053 rn: vreg(7),
5054 size: VectorSize::Size32x2,
5055 },
5056 "F488210E",
5057 "frintn v20.2s, v7.2s",
5058 ));
5059
5060 insns.push((
5061 Inst::VecMisc {
5062 op: VecMisc2::Frintn,
5063 rd: writable_vreg(11),
5064 rn: vreg(18),
5065 size: VectorSize::Size32x4,
5066 },
5067 "4B8A214E",
5068 "frintn v11.4s, v18.4s",
5069 ));
5070
5071 insns.push((
5072 Inst::VecMisc {
5073 op: VecMisc2::Frintn,
5074 rd: writable_vreg(12),
5075 rn: vreg(17),
5076 size: VectorSize::Size64x2,
5077 },
5078 "2C8A614E",
5079 "frintn v12.2d, v17.2d",
5080 ));
5081
5082 insns.push((
5083 Inst::VecMisc {
5084 op: VecMisc2::Frintz,
5085 rd: writable_vreg(1),
5086 rn: vreg(30),
5087 size: VectorSize::Size32x2,
5088 },
5089 "C19BA10E",
5090 "frintz v1.2s, v30.2s",
5091 ));
5092
5093 insns.push((
5094 Inst::VecMisc {
5095 op: VecMisc2::Frintz,
5096 rd: writable_vreg(11),
5097 rn: vreg(18),
5098 size: VectorSize::Size32x4,
5099 },
5100 "4B9AA14E",
5101 "frintz v11.4s, v18.4s",
5102 ));
5103
5104 insns.push((
5105 Inst::VecMisc {
5106 op: VecMisc2::Frintz,
5107 rd: writable_vreg(12),
5108 rn: vreg(17),
5109 size: VectorSize::Size64x2,
5110 },
5111 "2C9AE14E",
5112 "frintz v12.2d, v17.2d",
5113 ));
5114
5115 insns.push((
5116 Inst::VecMisc {
5117 op: VecMisc2::Frintm,
5118 rd: writable_vreg(15),
5119 rn: vreg(7),
5120 size: VectorSize::Size32x2,
5121 },
5122 "EF98210E",
5123 "frintm v15.2s, v7.2s",
5124 ));
5125
5126 insns.push((
5127 Inst::VecMisc {
5128 op: VecMisc2::Frintm,
5129 rd: writable_vreg(11),
5130 rn: vreg(18),
5131 size: VectorSize::Size32x4,
5132 },
5133 "4B9A214E",
5134 "frintm v11.4s, v18.4s",
5135 ));
5136
5137 insns.push((
5138 Inst::VecMisc {
5139 op: VecMisc2::Frintm,
5140 rd: writable_vreg(12),
5141 rn: vreg(17),
5142 size: VectorSize::Size64x2,
5143 },
5144 "2C9A614E",
5145 "frintm v12.2d, v17.2d",
5146 ));
5147
5148 insns.push((
5149 Inst::VecMisc {
5150 op: VecMisc2::Frintp,
5151 rd: writable_vreg(3),
5152 rn: vreg(4),
5153 size: VectorSize::Size32x2,
5154 },
5155 "8388A10E",
5156 "frintp v3.2s, v4.2s",
5157 ));
5158
5159 insns.push((
5160 Inst::VecMisc {
5161 op: VecMisc2::Frintp,
5162 rd: writable_vreg(11),
5163 rn: vreg(18),
5164 size: VectorSize::Size32x4,
5165 },
5166 "4B8AA14E",
5167 "frintp v11.4s, v18.4s",
5168 ));
5169
5170 insns.push((
5171 Inst::VecMisc {
5172 op: VecMisc2::Frintp,
5173 rd: writable_vreg(12),
5174 rn: vreg(17),
5175 size: VectorSize::Size64x2,
5176 },
5177 "2C8AE14E",
5178 "frintp v12.2d, v17.2d",
5179 ));
5180
5181 insns.push((
5182 Inst::VecMisc {
5183 op: VecMisc2::Cnt,
5184 rd: writable_vreg(23),
5185 rn: vreg(5),
5186 size: VectorSize::Size8x8,
5187 },
5188 "B758200E",
5189 "cnt v23.8b, v5.8b",
5190 ));
5191
5192 insns.push((
5193 Inst::VecMisc {
5194 op: VecMisc2::Fcmeq0,
5195 rd: writable_vreg(5),
5196 rn: vreg(2),
5197 size: VectorSize::Size32x4,
5198 },
5199 "45D8A04E",
5200 "fcmeq v5.4s, v2.4s, #0.0",
5201 ));
5202
5203 insns.push((
5204 Inst::VecMisc {
5205 op: VecMisc2::Fcmge0,
5206 rd: writable_vreg(3),
5207 rn: vreg(1),
5208 size: VectorSize::Size64x2,
5209 },
5210 "23C8E06E",
5211 "fcmge v3.2d, v1.2d, #0.0",
5212 ));
5213
5214 insns.push((
5215 Inst::VecMisc {
5216 op: VecMisc2::Fcmgt0,
5217 rd: writable_vreg(5),
5218 rn: vreg(7),
5219 size: VectorSize::Size32x4,
5220 },
5221 "E5C8A04E",
5222 "fcmgt v5.4s, v7.4s, #0.0",
5223 ));
5224
5225 insns.push((
5226 Inst::VecMisc {
5227 op: VecMisc2::Fcmle0,
5228 rd: writable_vreg(10),
5229 rn: vreg(2),
5230 size: VectorSize::Size32x4,
5231 },
5232 "4AD8A06E",
5233 "fcmle v10.4s, v2.4s, #0.0",
5234 ));
5235
5236 insns.push((
5237 Inst::VecMisc {
5238 op: VecMisc2::Fcmlt0,
5239 rd: writable_vreg(12),
5240 rn: vreg(12),
5241 size: VectorSize::Size64x2,
5242 },
5243 "8CE9E04E",
5244 "fcmlt v12.2d, v12.2d, #0.0",
5245 ));
5246
5247 insns.push((
5248 Inst::VecMisc {
5249 op: VecMisc2::Cmeq0,
5250 rd: writable_vreg(22),
5251 rn: vreg(27),
5252 size: VectorSize::Size16x8,
5253 },
5254 "769B604E",
5255 "cmeq v22.8h, v27.8h, #0",
5256 ));
5257
5258 insns.push((
5259 Inst::VecMisc {
5260 op: VecMisc2::Cmge0,
5261 rd: writable_vreg(12),
5262 rn: vreg(27),
5263 size: VectorSize::Size16x8,
5264 },
5265 "6C8B606E",
5266 "cmge v12.8h, v27.8h, #0",
5267 ));
5268
5269 insns.push((
5270 Inst::VecMisc {
5271 op: VecMisc2::Cmgt0,
5272 rd: writable_vreg(12),
5273 rn: vreg(27),
5274 size: VectorSize::Size8x16,
5275 },
5276 "6C8B204E",
5277 "cmgt v12.16b, v27.16b, #0",
5278 ));
5279
5280 insns.push((
5281 Inst::VecMisc {
5282 op: VecMisc2::Cmle0,
5283 rd: writable_vreg(1),
5284 rn: vreg(27),
5285 size: VectorSize::Size32x4,
5286 },
5287 "619BA06E",
5288 "cmle v1.4s, v27.4s, #0",
5289 ));
5290
5291 insns.push((
5292 Inst::VecMisc {
5293 op: VecMisc2::Cmlt0,
5294 rd: writable_vreg(0),
5295 rn: vreg(7),
5296 size: VectorSize::Size64x2,
5297 },
5298 "E0A8E04E",
5299 "cmlt v0.2d, v7.2d, #0",
5300 ));
5301
5302 insns.push((
5303 Inst::VecLanes {
5304 op: VecLanesOp::Uminv,
5305 rd: writable_vreg(0),
5306 rn: vreg(31),
5307 size: VectorSize::Size8x8,
5308 },
5309 "E0AB312E",
5310 "uminv b0, v31.8b",
5311 ));
5312
5313 insns.push((
5314 Inst::VecLanes {
5315 op: VecLanesOp::Uminv,
5316 rd: writable_vreg(2),
5317 rn: vreg(1),
5318 size: VectorSize::Size8x16,
5319 },
5320 "22A8316E",
5321 "uminv b2, v1.16b",
5322 ));
5323
5324 insns.push((
5325 Inst::VecLanes {
5326 op: VecLanesOp::Uminv,
5327 rd: writable_vreg(3),
5328 rn: vreg(11),
5329 size: VectorSize::Size16x8,
5330 },
5331 "63A9716E",
5332 "uminv h3, v11.8h",
5333 ));
5334
5335 insns.push((
5336 Inst::VecLanes {
5337 op: VecLanesOp::Uminv,
5338 rd: writable_vreg(18),
5339 rn: vreg(4),
5340 size: VectorSize::Size32x4,
5341 },
5342 "92A8B16E",
5343 "uminv s18, v4.4s",
5344 ));
5345
5346 insns.push((
5347 Inst::VecLanes {
5348 op: VecLanesOp::Addv,
5349 rd: writable_vreg(2),
5350 rn: vreg(29),
5351 size: VectorSize::Size8x16,
5352 },
5353 "A2BB314E",
5354 "addv b2, v29.16b",
5355 ));
5356
5357 insns.push((
5358 Inst::VecLanes {
5359 op: VecLanesOp::Addv,
5360 rd: writable_vreg(15),
5361 rn: vreg(7),
5362 size: VectorSize::Size16x4,
5363 },
5364 "EFB8710E",
5365 "addv h15, v7.4h",
5366 ));
5367
5368 insns.push((
5369 Inst::VecLanes {
5370 op: VecLanesOp::Addv,
5371 rd: writable_vreg(3),
5372 rn: vreg(21),
5373 size: VectorSize::Size16x8,
5374 },
5375 "A3BA714E",
5376 "addv h3, v21.8h",
5377 ));
5378
5379 insns.push((
5380 Inst::VecLanes {
5381 op: VecLanesOp::Addv,
5382 rd: writable_vreg(18),
5383 rn: vreg(5),
5384 size: VectorSize::Size32x4,
5385 },
5386 "B2B8B14E",
5387 "addv s18, v5.4s",
5388 ));
5389
5390 insns.push((
5391 Inst::VecShiftImm {
5392 op: VecShiftImmOp::Shl,
5393 rd: writable_vreg(27),
5394 rn: vreg(5),
5395 imm: 7,
5396 size: VectorSize::Size8x16,
5397 },
5398 "BB540F4F",
5399 "shl v27.16b, v5.16b, #7",
5400 ));
5401
5402 insns.push((
5403 Inst::VecShiftImm {
5404 op: VecShiftImmOp::Shl,
5405 rd: writable_vreg(1),
5406 rn: vreg(30),
5407 imm: 0,
5408 size: VectorSize::Size8x16,
5409 },
5410 "C157084F",
5411 "shl v1.16b, v30.16b, #0",
5412 ));
5413
5414 insns.push((
5415 Inst::VecShiftImm {
5416 op: VecShiftImmOp::Sshr,
5417 rd: writable_vreg(26),
5418 rn: vreg(6),
5419 imm: 16,
5420 size: VectorSize::Size16x8,
5421 },
5422 "DA04104F",
5423 "sshr v26.8h, v6.8h, #16",
5424 ));
5425
5426 insns.push((
5427 Inst::VecShiftImm {
5428 op: VecShiftImmOp::Sshr,
5429 rd: writable_vreg(3),
5430 rn: vreg(19),
5431 imm: 1,
5432 size: VectorSize::Size16x8,
5433 },
5434 "63061F4F",
5435 "sshr v3.8h, v19.8h, #1",
5436 ));
5437
5438 insns.push((
5439 Inst::VecShiftImm {
5440 op: VecShiftImmOp::Ushr,
5441 rd: writable_vreg(25),
5442 rn: vreg(6),
5443 imm: 8,
5444 size: VectorSize::Size8x8,
5445 },
5446 "D904082F",
5447 "ushr v25.8b, v6.8b, #8",
5448 ));
5449
5450 insns.push((
5451 Inst::VecShiftImm {
5452 op: VecShiftImmOp::Ushr,
5453 rd: writable_vreg(5),
5454 rn: vreg(21),
5455 imm: 1,
5456 size: VectorSize::Size8x8,
5457 },
5458 "A5060F2F",
5459 "ushr v5.8b, v21.8b, #1",
5460 ));
5461
5462 insns.push((
5463 Inst::VecShiftImm {
5464 op: VecShiftImmOp::Ushr,
5465 rd: writable_vreg(25),
5466 rn: vreg(6),
5467 imm: 8,
5468 size: VectorSize::Size8x16,
5469 },
5470 "D904086F",
5471 "ushr v25.16b, v6.16b, #8",
5472 ));
5473
5474 insns.push((
5475 Inst::VecShiftImm {
5476 op: VecShiftImmOp::Ushr,
5477 rd: writable_vreg(5),
5478 rn: vreg(21),
5479 imm: 1,
5480 size: VectorSize::Size8x16,
5481 },
5482 "A5060F6F",
5483 "ushr v5.16b, v21.16b, #1",
5484 ));
5485
5486 insns.push((
5487 Inst::VecShiftImm {
5488 op: VecShiftImmOp::Ushr,
5489 rd: writable_vreg(25),
5490 rn: vreg(6),
5491 imm: 16,
5492 size: VectorSize::Size16x4,
5493 },
5494 "D904102F",
5495 "ushr v25.4h, v6.4h, #16",
5496 ));
5497
5498 insns.push((
5499 Inst::VecShiftImm {
5500 op: VecShiftImmOp::Ushr,
5501 rd: writable_vreg(5),
5502 rn: vreg(21),
5503 imm: 1,
5504 size: VectorSize::Size16x4,
5505 },
5506 "A5061F2F",
5507 "ushr v5.4h, v21.4h, #1",
5508 ));
5509
5510 insns.push((
5511 Inst::VecShiftImm {
5512 op: VecShiftImmOp::Ushr,
5513 rd: writable_vreg(25),
5514 rn: vreg(6),
5515 imm: 16,
5516 size: VectorSize::Size16x8,
5517 },
5518 "D904106F",
5519 "ushr v25.8h, v6.8h, #16",
5520 ));
5521
5522 insns.push((
5523 Inst::VecShiftImm {
5524 op: VecShiftImmOp::Ushr,
5525 rd: writable_vreg(5),
5526 rn: vreg(21),
5527 imm: 1,
5528 size: VectorSize::Size16x8,
5529 },
5530 "A5061F6F",
5531 "ushr v5.8h, v21.8h, #1",
5532 ));
5533
5534 insns.push((
5535 Inst::VecShiftImm {
5536 op: VecShiftImmOp::Ushr,
5537 rd: writable_vreg(25),
5538 rn: vreg(6),
5539 imm: 32,
5540 size: VectorSize::Size32x2,
5541 },
5542 "D904202F",
5543 "ushr v25.2s, v6.2s, #32",
5544 ));
5545
5546 insns.push((
5547 Inst::VecShiftImm {
5548 op: VecShiftImmOp::Ushr,
5549 rd: writable_vreg(5),
5550 rn: vreg(21),
5551 imm: 1,
5552 size: VectorSize::Size32x2,
5553 },
5554 "A5063F2F",
5555 "ushr v5.2s, v21.2s, #1",
5556 ));
5557
5558 insns.push((
5559 Inst::VecShiftImm {
5560 op: VecShiftImmOp::Ushr,
5561 rd: writable_vreg(25),
5562 rn: vreg(6),
5563 imm: 32,
5564 size: VectorSize::Size32x4,
5565 },
5566 "D904206F",
5567 "ushr v25.4s, v6.4s, #32",
5568 ));
5569
5570 insns.push((
5571 Inst::VecShiftImm {
5572 op: VecShiftImmOp::Ushr,
5573 rd: writable_vreg(5),
5574 rn: vreg(21),
5575 imm: 1,
5576 size: VectorSize::Size32x4,
5577 },
5578 "A5063F6F",
5579 "ushr v5.4s, v21.4s, #1",
5580 ));
5581
5582 insns.push((
5583 Inst::VecShiftImm {
5584 op: VecShiftImmOp::Ushr,
5585 rd: writable_vreg(25),
5586 rn: vreg(6),
5587 imm: 64,
5588 size: VectorSize::Size64x2,
5589 },
5590 "D904406F",
5591 "ushr v25.2d, v6.2d, #64",
5592 ));
5593
5594 insns.push((
5595 Inst::VecShiftImm {
5596 op: VecShiftImmOp::Ushr,
5597 rd: writable_vreg(5),
5598 rn: vreg(21),
5599 imm: 1,
5600 size: VectorSize::Size64x2,
5601 },
5602 "A5067F6F",
5603 "ushr v5.2d, v21.2d, #1",
5604 ));
5605
5606 insns.push((
5607 Inst::VecShiftImm {
5608 op: VecShiftImmOp::Shl,
5609 rd: writable_vreg(22),
5610 rn: vreg(13),
5611 imm: 63,
5612 size: VectorSize::Size64x2,
5613 },
5614 "B6557F4F",
5615 "shl v22.2d, v13.2d, #63",
5616 ));
5617
5618 insns.push((
5619 Inst::VecShiftImm {
5620 op: VecShiftImmOp::Shl,
5621 rd: writable_vreg(23),
5622 rn: vreg(9),
5623 imm: 0,
5624 size: VectorSize::Size64x2,
5625 },
5626 "3755404F",
5627 "shl v23.2d, v9.2d, #0",
5628 ));
5629
5630 insns.push((
5631 Inst::VecExtract {
5632 rd: writable_vreg(1),
5633 rn: vreg(30),
5634 rm: vreg(17),
5635 imm4: 0,
5636 },
5637 "C103116E",
5638 "ext v1.16b, v30.16b, v17.16b, #0",
5639 ));
5640
5641 insns.push((
5642 Inst::VecExtract {
5643 rd: writable_vreg(1),
5644 rn: vreg(30),
5645 rm: vreg(17),
5646 imm4: 8,
5647 },
5648 "C143116E",
5649 "ext v1.16b, v30.16b, v17.16b, #8",
5650 ));
5651
5652 insns.push((
5653 Inst::VecExtract {
5654 rd: writable_vreg(1),
5655 rn: vreg(30),
5656 rm: vreg(17),
5657 imm4: 15,
5658 },
5659 "C17B116E",
5660 "ext v1.16b, v30.16b, v17.16b, #15",
5661 ));
5662
5663 insns.push((
5664 Inst::VecTbl {
5665 rd: writable_vreg(0),
5666 rn: vreg(31),
5667 rm: vreg(16),
5668 },
5669 "E003104E",
5670 "tbl v0.16b, { v31.16b }, v16.16b",
5671 ));
5672
5673 insns.push((
5674 Inst::VecTblExt {
5675 rd: writable_vreg(4),
5676 ri: vreg(4),
5677 rn: vreg(12),
5678 rm: vreg(23),
5679 },
5680 "8411174E",
5681 "tbx v4.16b, v4.16b, { v12.16b }, v23.16b",
5682 ));
5683
5684 insns.push((
5685 Inst::VecTbl2 {
5686 rd: writable_vreg(16),
5687 rn: vreg(31),
5688 rn2: vreg(0),
5689 rm: vreg(26),
5690 },
5691 "F0231A4E",
5692 "tbl v16.16b, { v31.16b, v0.16b }, v26.16b",
5693 ));
5694
5695 insns.push((
5696 Inst::VecTbl2Ext {
5697 rd: writable_vreg(3),
5698 ri: vreg(3),
5699 rn: vreg(11),
5700 rn2: vreg(12),
5701 rm: vreg(19),
5702 },
5703 "6331134E",
5704 "tbx v3.16b, v3.16b, { v11.16b, v12.16b }, v19.16b",
5705 ));
5706
5707 insns.push((
5708 Inst::VecLoadReplicate {
5709 rd: writable_vreg(31),
5710 rn: xreg(0),
5711 size: VectorSize::Size64x2,
5712 flags: MemFlags::trusted(),
5713 },
5714 "1FCC404D",
5715 "ld1r { v31.2d }, [x0]",
5716 ));
5717
5718 insns.push((
5719 Inst::VecLoadReplicate {
5720 rd: writable_vreg(0),
5721 rn: xreg(25),
5722 size: VectorSize::Size8x8,
5723 flags: MemFlags::trusted(),
5724 },
5725 "20C3400D",
5726 "ld1r { v0.8b }, [x25]",
5727 ));
5728
5729 insns.push((
5730 Inst::VecCSel {
5731 rd: writable_vreg(5),
5732 rn: vreg(10),
5733 rm: vreg(19),
5734 cond: Cond::Gt,
5735 },
5736 "6C000054651EB34E02000014451DAA4E",
5737 "vcsel v5.16b, v10.16b, v19.16b, gt (if-then-else diamond)",
5738 ));
5739
5740 insns.push((
5741 Inst::Extend {
5742 rd: writable_xreg(3),
5743 rn: xreg(5),
5744 signed: false,
5745 from_bits: 1,
5746 to_bits: 32,
5747 },
5748 "A3000012",
5749 "and w3, w5, #1",
5750 ));
5751 insns.push((
5752 Inst::Extend {
5753 rd: writable_xreg(3),
5754 rn: xreg(5),
5755 signed: false,
5756 from_bits: 1,
5757 to_bits: 64,
5758 },
5759 "A3000012",
5760 "and w3, w5, #1",
5761 ));
5762 insns.push((
5763 Inst::Extend {
5764 rd: writable_xreg(10),
5765 rn: xreg(21),
5766 signed: true,
5767 from_bits: 1,
5768 to_bits: 32,
5769 },
5770 "AA020013",
5771 "sbfx w10, w21, #0, #1",
5772 ));
5773 insns.push((
5774 Inst::Extend {
5775 rd: writable_xreg(1),
5776 rn: xreg(2),
5777 signed: true,
5778 from_bits: 1,
5779 to_bits: 64,
5780 },
5781 "41004093",
5782 "sbfx x1, x2, #0, #1",
5783 ));
5784 insns.push((
5785 Inst::Extend {
5786 rd: writable_xreg(1),
5787 rn: xreg(2),
5788 signed: false,
5789 from_bits: 8,
5790 to_bits: 32,
5791 },
5792 "411C0053",
5793 "uxtb w1, w2",
5794 ));
5795 insns.push((
5796 Inst::Extend {
5797 rd: writable_xreg(1),
5798 rn: xreg(2),
5799 signed: true,
5800 from_bits: 8,
5801 to_bits: 32,
5802 },
5803 "411C0013",
5804 "sxtb w1, w2",
5805 ));
5806 insns.push((
5807 Inst::Extend {
5808 rd: writable_xreg(1),
5809 rn: xreg(2),
5810 signed: false,
5811 from_bits: 16,
5812 to_bits: 32,
5813 },
5814 "413C0053",
5815 "uxth w1, w2",
5816 ));
5817 insns.push((
5818 Inst::Extend {
5819 rd: writable_xreg(1),
5820 rn: xreg(2),
5821 signed: true,
5822 from_bits: 16,
5823 to_bits: 32,
5824 },
5825 "413C0013",
5826 "sxth w1, w2",
5827 ));
5828 insns.push((
5829 Inst::Extend {
5830 rd: writable_xreg(1),
5831 rn: xreg(2),
5832 signed: false,
5833 from_bits: 8,
5834 to_bits: 64,
5835 },
5836 "411C0053",
5837 "uxtb w1, w2",
5838 ));
5839 insns.push((
5840 Inst::Extend {
5841 rd: writable_xreg(1),
5842 rn: xreg(2),
5843 signed: true,
5844 from_bits: 8,
5845 to_bits: 64,
5846 },
5847 "411C4093",
5848 "sxtb x1, w2",
5849 ));
5850 insns.push((
5851 Inst::Extend {
5852 rd: writable_xreg(1),
5853 rn: xreg(2),
5854 signed: false,
5855 from_bits: 16,
5856 to_bits: 64,
5857 },
5858 "413C0053",
5859 "uxth w1, w2",
5860 ));
5861 insns.push((
5862 Inst::Extend {
5863 rd: writable_xreg(1),
5864 rn: xreg(2),
5865 signed: true,
5866 from_bits: 16,
5867 to_bits: 64,
5868 },
5869 "413C4093",
5870 "sxth x1, w2",
5871 ));
5872 insns.push((
5873 Inst::Extend {
5874 rd: writable_xreg(1),
5875 rn: xreg(2),
5876 signed: false,
5877 from_bits: 32,
5878 to_bits: 64,
5879 },
5880 "E103022A",
5881 "mov w1, w2",
5882 ));
5883 insns.push((
5884 Inst::Extend {
5885 rd: writable_xreg(1),
5886 rn: xreg(2),
5887 signed: true,
5888 from_bits: 32,
5889 to_bits: 64,
5890 },
5891 "417C4093",
5892 "sxtw x1, w2",
5893 ));
5894
5895 insns.push((
5896 Inst::Jump {
5897 dest: BranchTarget::ResolvedOffset(64),
5898 },
5899 "10000014",
5900 "b 64",
5901 ));
5902
5903 insns.push((
5904 Inst::TrapIf {
5905 trap_code: TrapCode::STACK_OVERFLOW,
5906 kind: CondBrKind::NotZero(xreg(8), OperandSize::Size64),
5907 },
5908 "280000B51FC10000",
5909 "cbnz x8, #trap=stk_ovf",
5910 ));
5911 insns.push((
5912 Inst::TrapIf {
5913 trap_code: TrapCode::STACK_OVERFLOW,
5914 kind: CondBrKind::Zero(xreg(8), OperandSize::Size64),
5915 },
5916 "280000B41FC10000",
5917 "cbz x8, #trap=stk_ovf",
5918 ));
5919 insns.push((
5920 Inst::TrapIf {
5921 trap_code: TrapCode::STACK_OVERFLOW,
5922 kind: CondBrKind::Cond(Cond::Ne),
5923 },
5924 "210000541FC10000",
5925 "b.ne #trap=stk_ovf",
5926 ));
5927 insns.push((
5928 Inst::TrapIf {
5929 trap_code: TrapCode::STACK_OVERFLOW,
5930 kind: CondBrKind::Cond(Cond::Eq),
5931 },
5932 "200000541FC10000",
5933 "b.eq #trap=stk_ovf",
5934 ));
5935 insns.push((
5936 Inst::TrapIf {
5937 trap_code: TrapCode::STACK_OVERFLOW,
5938 kind: CondBrKind::Cond(Cond::Lo),
5939 },
5940 "230000541FC10000",
5941 "b.lo #trap=stk_ovf",
5942 ));
5943 insns.push((
5944 Inst::TrapIf {
5945 trap_code: TrapCode::STACK_OVERFLOW,
5946 kind: CondBrKind::Cond(Cond::Hs),
5947 },
5948 "220000541FC10000",
5949 "b.hs #trap=stk_ovf",
5950 ));
5951 insns.push((
5952 Inst::TrapIf {
5953 trap_code: TrapCode::STACK_OVERFLOW,
5954 kind: CondBrKind::Cond(Cond::Pl),
5955 },
5956 "250000541FC10000",
5957 "b.pl #trap=stk_ovf",
5958 ));
5959 insns.push((
5960 Inst::TrapIf {
5961 trap_code: TrapCode::STACK_OVERFLOW,
5962 kind: CondBrKind::Cond(Cond::Mi),
5963 },
5964 "240000541FC10000",
5965 "b.mi #trap=stk_ovf",
5966 ));
5967 insns.push((
5968 Inst::TrapIf {
5969 trap_code: TrapCode::STACK_OVERFLOW,
5970 kind: CondBrKind::Cond(Cond::Vc),
5971 },
5972 "270000541FC10000",
5973 "b.vc #trap=stk_ovf",
5974 ));
5975 insns.push((
5976 Inst::TrapIf {
5977 trap_code: TrapCode::STACK_OVERFLOW,
5978 kind: CondBrKind::Cond(Cond::Vs),
5979 },
5980 "260000541FC10000",
5981 "b.vs #trap=stk_ovf",
5982 ));
5983 insns.push((
5984 Inst::TrapIf {
5985 trap_code: TrapCode::STACK_OVERFLOW,
5986 kind: CondBrKind::Cond(Cond::Ls),
5987 },
5988 "290000541FC10000",
5989 "b.ls #trap=stk_ovf",
5990 ));
5991 insns.push((
5992 Inst::TrapIf {
5993 trap_code: TrapCode::STACK_OVERFLOW,
5994 kind: CondBrKind::Cond(Cond::Hi),
5995 },
5996 "280000541FC10000",
5997 "b.hi #trap=stk_ovf",
5998 ));
5999 insns.push((
6000 Inst::TrapIf {
6001 trap_code: TrapCode::STACK_OVERFLOW,
6002 kind: CondBrKind::Cond(Cond::Lt),
6003 },
6004 "2B0000541FC10000",
6005 "b.lt #trap=stk_ovf",
6006 ));
6007 insns.push((
6008 Inst::TrapIf {
6009 trap_code: TrapCode::STACK_OVERFLOW,
6010 kind: CondBrKind::Cond(Cond::Ge),
6011 },
6012 "2A0000541FC10000",
6013 "b.ge #trap=stk_ovf",
6014 ));
6015 insns.push((
6016 Inst::TrapIf {
6017 trap_code: TrapCode::STACK_OVERFLOW,
6018 kind: CondBrKind::Cond(Cond::Le),
6019 },
6020 "2D0000541FC10000",
6021 "b.le #trap=stk_ovf",
6022 ));
6023 insns.push((
6024 Inst::TrapIf {
6025 trap_code: TrapCode::STACK_OVERFLOW,
6026 kind: CondBrKind::Cond(Cond::Gt),
6027 },
6028 "2C0000541FC10000",
6029 "b.gt #trap=stk_ovf",
6030 ));
6031 insns.push((
6032 Inst::TrapIf {
6033 trap_code: TrapCode::STACK_OVERFLOW,
6034 kind: CondBrKind::Cond(Cond::Nv),
6035 },
6036 "2F0000541FC10000",
6037 "b.nv #trap=stk_ovf",
6038 ));
6039 insns.push((
6040 Inst::TrapIf {
6041 trap_code: TrapCode::STACK_OVERFLOW,
6042 kind: CondBrKind::Cond(Cond::Al),
6043 },
6044 "2E0000541FC10000",
6045 "b.al #trap=stk_ovf",
6046 ));
6047
6048 insns.push((
6049 Inst::CondBr {
6050 taken: BranchTarget::ResolvedOffset(64),
6051 not_taken: BranchTarget::ResolvedOffset(128),
6052 kind: CondBrKind::Cond(Cond::Le),
6053 },
6054 "0D02005420000014",
6055 "b.le 64 ; b 128",
6056 ));
6057
6058 insns.push((
6059 Inst::Call {
6060 info: Box::new(CallInfo::empty(
6061 ExternalName::testcase("test0"),
6062 CallConv::SystemV,
6063 )),
6064 },
6065 "00000094",
6066 "bl 0",
6067 ));
6068
6069 insns.push((
6070 Inst::CallInd {
6071 info: Box::new(CallInfo::empty(xreg(10), CallConv::SystemV)),
6072 },
6073 "40013FD6",
6074 "blr x10",
6075 ));
6076
6077 insns.push((
6078 Inst::IndirectBr {
6079 rn: xreg(3),
6080 targets: vec![],
6081 },
6082 "60001FD6",
6083 "br x3",
6084 ));
6085
6086 insns.push((Inst::Brk, "00003ED4", "brk #0xf000"));
6087
6088 insns.push((
6089 Inst::Adr {
6090 rd: writable_xreg(15),
6091 off: (1 << 20) - 4,
6092 },
6093 "EFFF7F10",
6094 "adr x15, pc+1048572",
6095 ));
6096
6097 insns.push((
6098 Inst::Adrp {
6099 rd: writable_xreg(8),
6100 off: 0,
6101 },
6102 "08000090",
6103 "adrp x8, pc+0",
6104 ));
6105
6106 insns.push((
6107 Inst::Adrp {
6108 rd: writable_xreg(3),
6109 off: 16,
6110 },
6111 "83000090",
6112 "adrp x3, pc+65536",
6113 ));
6114
6115 insns.push((
6116 Inst::FpuMove64 {
6117 rd: writable_vreg(8),
6118 rn: vreg(4),
6119 },
6120 "8840601E",
6121 "fmov d8, d4",
6122 ));
6123
6124 insns.push((
6125 Inst::FpuMove32 {
6126 rd: writable_vreg(8),
6127 rn: vreg(4),
6128 },
6129 "8840201E",
6130 "fmov s8, s4",
6131 ));
6132
6133 insns.push((
6134 Inst::FpuMove128 {
6135 rd: writable_vreg(17),
6136 rn: vreg(26),
6137 },
6138 "511FBA4E",
6139 "mov v17.16b, v26.16b",
6140 ));
6141
6142 insns.push((
6143 Inst::FpuMoveFromVec {
6144 rd: writable_vreg(1),
6145 rn: vreg(30),
6146 idx: 2,
6147 size: VectorSize::Size32x4,
6148 },
6149 "C107145E",
6150 "mov s1, v30.s[2]",
6151 ));
6152
6153 insns.push((
6154 Inst::FpuMoveFromVec {
6155 rd: writable_vreg(23),
6156 rn: vreg(11),
6157 idx: 0,
6158 size: VectorSize::Size64x2,
6159 },
6160 "7705085E",
6161 "mov d23, v11.d[0]",
6162 ));
6163
6164 insns.push((
6165 Inst::FpuExtend {
6166 rd: writable_vreg(31),
6167 rn: vreg(0),
6168 size: ScalarSize::Size32,
6169 },
6170 "1F40201E",
6171 "fmov s31, s0",
6172 ));
6173
6174 insns.push((
6175 Inst::FpuExtend {
6176 rd: writable_vreg(31),
6177 rn: vreg(0),
6178 size: ScalarSize::Size64,
6179 },
6180 "1F40601E",
6181 "fmov d31, d0",
6182 ));
6183
6184 insns.push((
6185 Inst::FpuRR {
6186 fpu_op: FPUOp1::Abs,
6187 size: ScalarSize::Size32,
6188 rd: writable_vreg(15),
6189 rn: vreg(30),
6190 },
6191 "CFC3201E",
6192 "fabs s15, s30",
6193 ));
6194
6195 insns.push((
6196 Inst::FpuRR {
6197 fpu_op: FPUOp1::Abs,
6198 size: ScalarSize::Size64,
6199 rd: writable_vreg(15),
6200 rn: vreg(30),
6201 },
6202 "CFC3601E",
6203 "fabs d15, d30",
6204 ));
6205
6206 insns.push((
6207 Inst::FpuRR {
6208 fpu_op: FPUOp1::Neg,
6209 size: ScalarSize::Size32,
6210 rd: writable_vreg(15),
6211 rn: vreg(30),
6212 },
6213 "CF43211E",
6214 "fneg s15, s30",
6215 ));
6216
6217 insns.push((
6218 Inst::FpuRR {
6219 fpu_op: FPUOp1::Neg,
6220 size: ScalarSize::Size64,
6221 rd: writable_vreg(15),
6222 rn: vreg(30),
6223 },
6224 "CF43611E",
6225 "fneg d15, d30",
6226 ));
6227
6228 insns.push((
6229 Inst::FpuRR {
6230 fpu_op: FPUOp1::Sqrt,
6231 size: ScalarSize::Size32,
6232 rd: writable_vreg(15),
6233 rn: vreg(30),
6234 },
6235 "CFC3211E",
6236 "fsqrt s15, s30",
6237 ));
6238
6239 insns.push((
6240 Inst::FpuRR {
6241 fpu_op: FPUOp1::Sqrt,
6242 size: ScalarSize::Size64,
6243 rd: writable_vreg(15),
6244 rn: vreg(30),
6245 },
6246 "CFC3611E",
6247 "fsqrt d15, d30",
6248 ));
6249
6250 insns.push((
6251 Inst::FpuRR {
6252 fpu_op: FPUOp1::Cvt32To64,
6253 size: ScalarSize::Size32,
6254 rd: writable_vreg(15),
6255 rn: vreg(30),
6256 },
6257 "CFC3221E",
6258 "fcvt d15, s30",
6259 ));
6260
6261 insns.push((
6262 Inst::FpuRR {
6263 fpu_op: FPUOp1::Cvt64To32,
6264 size: ScalarSize::Size64,
6265 rd: writable_vreg(15),
6266 rn: vreg(30),
6267 },
6268 "CF43621E",
6269 "fcvt s15, d30",
6270 ));
6271
6272 insns.push((
6273 Inst::FpuRRR {
6274 fpu_op: FPUOp2::Add,
6275 size: ScalarSize::Size32,
6276 rd: writable_vreg(15),
6277 rn: vreg(30),
6278 rm: vreg(31),
6279 },
6280 "CF2B3F1E",
6281 "fadd s15, s30, s31",
6282 ));
6283
6284 insns.push((
6285 Inst::FpuRRR {
6286 fpu_op: FPUOp2::Add,
6287 size: ScalarSize::Size64,
6288 rd: writable_vreg(15),
6289 rn: vreg(30),
6290 rm: vreg(31),
6291 },
6292 "CF2B7F1E",
6293 "fadd d15, d30, d31",
6294 ));
6295
6296 insns.push((
6297 Inst::FpuRRR {
6298 fpu_op: FPUOp2::Sub,
6299 size: ScalarSize::Size32,
6300 rd: writable_vreg(15),
6301 rn: vreg(30),
6302 rm: vreg(31),
6303 },
6304 "CF3B3F1E",
6305 "fsub s15, s30, s31",
6306 ));
6307
6308 insns.push((
6309 Inst::FpuRRR {
6310 fpu_op: FPUOp2::Sub,
6311 size: ScalarSize::Size64,
6312 rd: writable_vreg(15),
6313 rn: vreg(30),
6314 rm: vreg(31),
6315 },
6316 "CF3B7F1E",
6317 "fsub d15, d30, d31",
6318 ));
6319
6320 insns.push((
6321 Inst::FpuRRR {
6322 fpu_op: FPUOp2::Mul,
6323 size: ScalarSize::Size32,
6324 rd: writable_vreg(15),
6325 rn: vreg(30),
6326 rm: vreg(31),
6327 },
6328 "CF0B3F1E",
6329 "fmul s15, s30, s31",
6330 ));
6331
6332 insns.push((
6333 Inst::FpuRRR {
6334 fpu_op: FPUOp2::Mul,
6335 size: ScalarSize::Size64,
6336 rd: writable_vreg(15),
6337 rn: vreg(30),
6338 rm: vreg(31),
6339 },
6340 "CF0B7F1E",
6341 "fmul d15, d30, d31",
6342 ));
6343
6344 insns.push((
6345 Inst::FpuRRR {
6346 fpu_op: FPUOp2::Div,
6347 size: ScalarSize::Size32,
6348 rd: writable_vreg(15),
6349 rn: vreg(30),
6350 rm: vreg(31),
6351 },
6352 "CF1B3F1E",
6353 "fdiv s15, s30, s31",
6354 ));
6355
6356 insns.push((
6357 Inst::FpuRRR {
6358 fpu_op: FPUOp2::Div,
6359 size: ScalarSize::Size64,
6360 rd: writable_vreg(15),
6361 rn: vreg(30),
6362 rm: vreg(31),
6363 },
6364 "CF1B7F1E",
6365 "fdiv d15, d30, d31",
6366 ));
6367
6368 insns.push((
6369 Inst::FpuRRR {
6370 fpu_op: FPUOp2::Max,
6371 size: ScalarSize::Size32,
6372 rd: writable_vreg(15),
6373 rn: vreg(30),
6374 rm: vreg(31),
6375 },
6376 "CF4B3F1E",
6377 "fmax s15, s30, s31",
6378 ));
6379
6380 insns.push((
6381 Inst::FpuRRR {
6382 fpu_op: FPUOp2::Max,
6383 size: ScalarSize::Size64,
6384 rd: writable_vreg(15),
6385 rn: vreg(30),
6386 rm: vreg(31),
6387 },
6388 "CF4B7F1E",
6389 "fmax d15, d30, d31",
6390 ));
6391
6392 insns.push((
6393 Inst::FpuRRR {
6394 fpu_op: FPUOp2::Min,
6395 size: ScalarSize::Size32,
6396 rd: writable_vreg(15),
6397 rn: vreg(30),
6398 rm: vreg(31),
6399 },
6400 "CF5B3F1E",
6401 "fmin s15, s30, s31",
6402 ));
6403
6404 insns.push((
6405 Inst::FpuRRR {
6406 fpu_op: FPUOp2::Min,
6407 size: ScalarSize::Size64,
6408 rd: writable_vreg(15),
6409 rn: vreg(30),
6410 rm: vreg(31),
6411 },
6412 "CF5B7F1E",
6413 "fmin d15, d30, d31",
6414 ));
6415
6416 insns.push((
6417 Inst::FpuRRRR {
6418 fpu_op: FPUOp3::MAdd,
6419 size: ScalarSize::Size32,
6420 rd: writable_vreg(15),
6421 rn: vreg(30),
6422 rm: vreg(31),
6423 ra: vreg(1),
6424 },
6425 "CF071F1F",
6426 "fmadd s15, s30, s31, s1",
6427 ));
6428
6429 insns.push((
6430 Inst::FpuRRRR {
6431 fpu_op: FPUOp3::MSub,
6432 size: ScalarSize::Size32,
6433 rd: writable_vreg(15),
6434 rn: vreg(30),
6435 rm: vreg(31),
6436 ra: vreg(1),
6437 },
6438 "CF871F1F",
6439 "fmsub s15, s30, s31, s1",
6440 ));
6441
6442 insns.push((
6443 Inst::FpuRRRR {
6444 fpu_op: FPUOp3::MAdd,
6445 size: ScalarSize::Size64,
6446 rd: writable_vreg(15),
6447 rn: vreg(30),
6448 rm: vreg(31),
6449 ra: vreg(1),
6450 },
6451 "CF075F1F",
6452 "fmadd d15, d30, d31, d1",
6453 ));
6454
6455 insns.push((
6456 Inst::FpuRRRR {
6457 fpu_op: FPUOp3::MSub,
6458 size: ScalarSize::Size64,
6459 rd: writable_vreg(15),
6460 rn: vreg(30),
6461 rm: vreg(31),
6462 ra: vreg(1),
6463 },
6464 "CF875F1F",
6465 "fmsub d15, d30, d31, d1",
6466 ));
6467
6468 insns.push((
6469 Inst::FpuRRRR {
6470 fpu_op: FPUOp3::NMAdd,
6471 size: ScalarSize::Size64,
6472 rd: writable_vreg(15),
6473 rn: vreg(30),
6474 rm: vreg(31),
6475 ra: vreg(1),
6476 },
6477 "CF077F1F",
6478 "fnmadd d15, d30, d31, d1",
6479 ));
6480
6481 insns.push((
6482 Inst::FpuRRRR {
6483 fpu_op: FPUOp3::NMSub,
6484 size: ScalarSize::Size64,
6485 rd: writable_vreg(15),
6486 rn: vreg(30),
6487 rm: vreg(31),
6488 ra: vreg(1),
6489 },
6490 "CF877F1F",
6491 "fnmsub d15, d30, d31, d1",
6492 ));
6493
6494 insns.push((
6495 Inst::FpuRRI {
6496 fpu_op: FPUOpRI::UShr32(FPURightShiftImm::maybe_from_u8(32, 32).unwrap()),
6497 rd: writable_vreg(2),
6498 rn: vreg(5),
6499 },
6500 "A204202F",
6501 "ushr v2.2s, v5.2s, #32",
6502 ));
6503
6504 insns.push((
6505 Inst::FpuRRI {
6506 fpu_op: FPUOpRI::UShr64(FPURightShiftImm::maybe_from_u8(63, 64).unwrap()),
6507 rd: writable_vreg(2),
6508 rn: vreg(5),
6509 },
6510 "A204417F",
6511 "ushr d2, d5, #63",
6512 ));
6513
6514 insns.push((
6515 Inst::FpuRRIMod {
6516 fpu_op: FPUOpRIMod::Sli32(FPULeftShiftImm::maybe_from_u8(31, 32).unwrap()),
6517 rd: writable_vreg(4),
6518 ri: vreg(4),
6519 rn: vreg(10),
6520 },
6521 "44553F2F",
6522 "sli v4.2s, v4.2s, v10.2s, #31",
6523 ));
6524
6525 insns.push((
6526 Inst::FpuRRIMod {
6527 fpu_op: FPUOpRIMod::Sli64(FPULeftShiftImm::maybe_from_u8(63, 64).unwrap()),
6528 rd: writable_vreg(4),
6529 ri: vreg(4),
6530 rn: vreg(10),
6531 },
6532 "44557F7F",
6533 "sli d4, d4, d10, #63",
6534 ));
6535
6536 insns.push((
6537 Inst::FpuToInt {
6538 op: FpuToIntOp::F32ToU32,
6539 rd: writable_xreg(1),
6540 rn: vreg(4),
6541 },
6542 "8100391E",
6543 "fcvtzu w1, s4",
6544 ));
6545
6546 insns.push((
6547 Inst::FpuToInt {
6548 op: FpuToIntOp::F32ToU64,
6549 rd: writable_xreg(1),
6550 rn: vreg(4),
6551 },
6552 "8100399E",
6553 "fcvtzu x1, s4",
6554 ));
6555
6556 insns.push((
6557 Inst::FpuToInt {
6558 op: FpuToIntOp::F32ToI32,
6559 rd: writable_xreg(1),
6560 rn: vreg(4),
6561 },
6562 "8100381E",
6563 "fcvtzs w1, s4",
6564 ));
6565
6566 insns.push((
6567 Inst::FpuToInt {
6568 op: FpuToIntOp::F32ToI64,
6569 rd: writable_xreg(1),
6570 rn: vreg(4),
6571 },
6572 "8100389E",
6573 "fcvtzs x1, s4",
6574 ));
6575
6576 insns.push((
6577 Inst::FpuToInt {
6578 op: FpuToIntOp::F64ToU32,
6579 rd: writable_xreg(1),
6580 rn: vreg(4),
6581 },
6582 "8100791E",
6583 "fcvtzu w1, d4",
6584 ));
6585
6586 insns.push((
6587 Inst::FpuToInt {
6588 op: FpuToIntOp::F64ToU64,
6589 rd: writable_xreg(1),
6590 rn: vreg(4),
6591 },
6592 "8100799E",
6593 "fcvtzu x1, d4",
6594 ));
6595
6596 insns.push((
6597 Inst::FpuToInt {
6598 op: FpuToIntOp::F64ToI32,
6599 rd: writable_xreg(1),
6600 rn: vreg(4),
6601 },
6602 "8100781E",
6603 "fcvtzs w1, d4",
6604 ));
6605
6606 insns.push((
6607 Inst::FpuToInt {
6608 op: FpuToIntOp::F64ToI64,
6609 rd: writable_xreg(1),
6610 rn: vreg(4),
6611 },
6612 "8100789E",
6613 "fcvtzs x1, d4",
6614 ));
6615
6616 insns.push((
6617 Inst::IntToFpu {
6618 op: IntToFpuOp::U32ToF32,
6619 rd: writable_vreg(1),
6620 rn: xreg(4),
6621 },
6622 "8100231E",
6623 "ucvtf s1, w4",
6624 ));
6625
6626 insns.push((
6627 Inst::IntToFpu {
6628 op: IntToFpuOp::I32ToF32,
6629 rd: writable_vreg(1),
6630 rn: xreg(4),
6631 },
6632 "8100221E",
6633 "scvtf s1, w4",
6634 ));
6635
6636 insns.push((
6637 Inst::IntToFpu {
6638 op: IntToFpuOp::U32ToF64,
6639 rd: writable_vreg(1),
6640 rn: xreg(4),
6641 },
6642 "8100631E",
6643 "ucvtf d1, w4",
6644 ));
6645
6646 insns.push((
6647 Inst::IntToFpu {
6648 op: IntToFpuOp::I32ToF64,
6649 rd: writable_vreg(1),
6650 rn: xreg(4),
6651 },
6652 "8100621E",
6653 "scvtf d1, w4",
6654 ));
6655
6656 insns.push((
6657 Inst::IntToFpu {
6658 op: IntToFpuOp::U64ToF32,
6659 rd: writable_vreg(1),
6660 rn: xreg(4),
6661 },
6662 "8100239E",
6663 "ucvtf s1, x4",
6664 ));
6665
6666 insns.push((
6667 Inst::IntToFpu {
6668 op: IntToFpuOp::I64ToF32,
6669 rd: writable_vreg(1),
6670 rn: xreg(4),
6671 },
6672 "8100229E",
6673 "scvtf s1, x4",
6674 ));
6675
6676 insns.push((
6677 Inst::IntToFpu {
6678 op: IntToFpuOp::U64ToF64,
6679 rd: writable_vreg(1),
6680 rn: xreg(4),
6681 },
6682 "8100639E",
6683 "ucvtf d1, x4",
6684 ));
6685
6686 insns.push((
6687 Inst::IntToFpu {
6688 op: IntToFpuOp::I64ToF64,
6689 rd: writable_vreg(1),
6690 rn: xreg(4),
6691 },
6692 "8100629E",
6693 "scvtf d1, x4",
6694 ));
6695
6696 insns.push((
6697 Inst::FpuCmp {
6698 size: ScalarSize::Size32,
6699 rn: vreg(23),
6700 rm: vreg(24),
6701 },
6702 "E022381E",
6703 "fcmp s23, s24",
6704 ));
6705
6706 insns.push((
6707 Inst::FpuCmp {
6708 size: ScalarSize::Size64,
6709 rn: vreg(23),
6710 rm: vreg(24),
6711 },
6712 "E022781E",
6713 "fcmp d23, d24",
6714 ));
6715
6716 insns.push((
6717 Inst::FpuLoad16 {
6718 rd: writable_vreg(16),
6719 mem: AMode::RegScaled {
6720 rn: xreg(8),
6721 rm: xreg(9),
6722 },
6723 flags: MemFlags::trusted(),
6724 },
6725 "1079697C",
6726 "ldr h16, [x8, x9, LSL #1]",
6727 ));
6728
6729 insns.push((
6730 Inst::FpuLoad32 {
6731 rd: writable_vreg(16),
6732 mem: AMode::RegScaled {
6733 rn: xreg(8),
6734 rm: xreg(9),
6735 },
6736 flags: MemFlags::trusted(),
6737 },
6738 "107969BC",
6739 "ldr s16, [x8, x9, LSL #2]",
6740 ));
6741
6742 insns.push((
6743 Inst::FpuLoad64 {
6744 rd: writable_vreg(16),
6745 mem: AMode::RegScaled {
6746 rn: xreg(8),
6747 rm: xreg(9),
6748 },
6749 flags: MemFlags::trusted(),
6750 },
6751 "107969FC",
6752 "ldr d16, [x8, x9, LSL #3]",
6753 ));
6754
6755 insns.push((
6756 Inst::FpuLoad128 {
6757 rd: writable_vreg(16),
6758 mem: AMode::RegScaled {
6759 rn: xreg(8),
6760 rm: xreg(9),
6761 },
6762 flags: MemFlags::trusted(),
6763 },
6764 "1079E93C",
6765 "ldr q16, [x8, x9, LSL #4]",
6766 ));
6767
6768 insns.push((
6769 Inst::FpuLoad32 {
6770 rd: writable_vreg(16),
6771 mem: AMode::Label {
6772 label: MemLabel::PCRel(8),
6773 },
6774 flags: MemFlags::trusted(),
6775 },
6776 "5000001C",
6777 "ldr s16, pc+8",
6778 ));
6779
6780 insns.push((
6781 Inst::FpuLoad64 {
6782 rd: writable_vreg(16),
6783 mem: AMode::Label {
6784 label: MemLabel::PCRel(8),
6785 },
6786 flags: MemFlags::trusted(),
6787 },
6788 "5000005C",
6789 "ldr d16, pc+8",
6790 ));
6791
6792 insns.push((
6793 Inst::FpuLoad128 {
6794 rd: writable_vreg(16),
6795 mem: AMode::Label {
6796 label: MemLabel::PCRel(8),
6797 },
6798 flags: MemFlags::trusted(),
6799 },
6800 "5000009C",
6801 "ldr q16, pc+8",
6802 ));
6803
6804 insns.push((
6805 Inst::FpuStore16 {
6806 rd: vreg(16),
6807 mem: AMode::RegScaled {
6808 rn: xreg(8),
6809 rm: xreg(9),
6810 },
6811 flags: MemFlags::trusted(),
6812 },
6813 "1079297C",
6814 "str h16, [x8, x9, LSL #1]",
6815 ));
6816
6817 insns.push((
6818 Inst::FpuStore32 {
6819 rd: vreg(16),
6820 mem: AMode::RegScaled {
6821 rn: xreg(8),
6822 rm: xreg(9),
6823 },
6824 flags: MemFlags::trusted(),
6825 },
6826 "107929BC",
6827 "str s16, [x8, x9, LSL #2]",
6828 ));
6829
6830 insns.push((
6831 Inst::FpuStore64 {
6832 rd: vreg(16),
6833 mem: AMode::RegScaled {
6834 rn: xreg(8),
6835 rm: xreg(9),
6836 },
6837 flags: MemFlags::trusted(),
6838 },
6839 "107929FC",
6840 "str d16, [x8, x9, LSL #3]",
6841 ));
6842
6843 insns.push((
6844 Inst::FpuStore128 {
6845 rd: vreg(16),
6846 mem: AMode::RegScaled {
6847 rn: xreg(8),
6848 rm: xreg(9),
6849 },
6850 flags: MemFlags::trusted(),
6851 },
6852 "1079A93C",
6853 "str q16, [x8, x9, LSL #4]",
6854 ));
6855
6856 insns.push((
6857 Inst::FpuLoadP64 {
6858 rt: writable_vreg(0),
6859 rt2: writable_vreg(31),
6860 mem: PairAMode::SignedOffset {
6861 reg: xreg(0),
6862 simm7: simm7_scaled_zero(F64),
6863 },
6864 flags: MemFlags::trusted(),
6865 },
6866 "007C406D",
6867 "ldp d0, d31, [x0]",
6868 ));
6869
6870 insns.push((
6871 Inst::FpuLoadP64 {
6872 rt: writable_vreg(19),
6873 rt2: writable_vreg(11),
6874 mem: PairAMode::SPPreIndexed {
6875 simm7: SImm7Scaled::maybe_from_i64(-512, F64).unwrap(),
6876 },
6877 flags: MemFlags::trusted(),
6878 },
6879 "F32FE06D",
6880 "ldp d19, d11, [sp, #-512]!",
6881 ));
6882
6883 insns.push((
6884 Inst::FpuLoadP64 {
6885 rt: writable_vreg(7),
6886 rt2: writable_vreg(20),
6887 mem: PairAMode::SPPostIndexed {
6888 simm7: SImm7Scaled::maybe_from_i64(64, F64).unwrap(),
6889 },
6890 flags: MemFlags::trusted(),
6891 },
6892 "E753C46C",
6893 "ldp d7, d20, [sp], #64",
6894 ));
6895
6896 insns.push((
6897 Inst::FpuStoreP64 {
6898 rt: vreg(4),
6899 rt2: vreg(26),
6900 mem: PairAMode::SignedOffset {
6901 reg: stack_reg(),
6902 simm7: SImm7Scaled::maybe_from_i64(504, F64).unwrap(),
6903 },
6904 flags: MemFlags::trusted(),
6905 },
6906 "E4EB1F6D",
6907 "stp d4, d26, [sp, #504]",
6908 ));
6909
6910 insns.push((
6911 Inst::FpuStoreP64 {
6912 rt: vreg(16),
6913 rt2: vreg(8),
6914 mem: PairAMode::SPPreIndexed {
6915 simm7: SImm7Scaled::maybe_from_i64(48, F64).unwrap(),
6916 },
6917 flags: MemFlags::trusted(),
6918 },
6919 "F023836D",
6920 "stp d16, d8, [sp, #48]!",
6921 ));
6922
6923 insns.push((
6924 Inst::FpuStoreP64 {
6925 rt: vreg(5),
6926 rt2: vreg(6),
6927 mem: PairAMode::SPPostIndexed {
6928 simm7: SImm7Scaled::maybe_from_i64(-32, F64).unwrap(),
6929 },
6930 flags: MemFlags::trusted(),
6931 },
6932 "E51BBE6C",
6933 "stp d5, d6, [sp], #-32",
6934 ));
6935
6936 insns.push((
6937 Inst::FpuLoadP128 {
6938 rt: writable_vreg(0),
6939 rt2: writable_vreg(17),
6940 mem: PairAMode::SignedOffset {
6941 reg: xreg(3),
6942 simm7: simm7_scaled_zero(I8X16),
6943 },
6944 flags: MemFlags::trusted(),
6945 },
6946 "604440AD",
6947 "ldp q0, q17, [x3]",
6948 ));
6949
6950 insns.push((
6951 Inst::FpuLoadP128 {
6952 rt: writable_vreg(29),
6953 rt2: writable_vreg(9),
6954 mem: PairAMode::SPPreIndexed {
6955 simm7: SImm7Scaled::maybe_from_i64(-1024, I8X16).unwrap(),
6956 },
6957 flags: MemFlags::trusted(),
6958 },
6959 "FD27E0AD",
6960 "ldp q29, q9, [sp, #-1024]!",
6961 ));
6962
6963 insns.push((
6964 Inst::FpuLoadP128 {
6965 rt: writable_vreg(10),
6966 rt2: writable_vreg(20),
6967 mem: PairAMode::SPPostIndexed {
6968 simm7: SImm7Scaled::maybe_from_i64(256, I8X16).unwrap(),
6969 },
6970 flags: MemFlags::trusted(),
6971 },
6972 "EA53C8AC",
6973 "ldp q10, q20, [sp], #256",
6974 ));
6975
6976 insns.push((
6977 Inst::FpuStoreP128 {
6978 rt: vreg(9),
6979 rt2: vreg(31),
6980 mem: PairAMode::SignedOffset {
6981 reg: stack_reg(),
6982 simm7: SImm7Scaled::maybe_from_i64(1008, I8X16).unwrap(),
6983 },
6984 flags: MemFlags::trusted(),
6985 },
6986 "E9FF1FAD",
6987 "stp q9, q31, [sp, #1008]",
6988 ));
6989
6990 insns.push((
6991 Inst::FpuStoreP128 {
6992 rt: vreg(27),
6993 rt2: vreg(13),
6994 mem: PairAMode::SPPreIndexed {
6995 simm7: SImm7Scaled::maybe_from_i64(-192, I8X16).unwrap(),
6996 },
6997 flags: MemFlags::trusted(),
6998 },
6999 "FB37BAAD",
7000 "stp q27, q13, [sp, #-192]!",
7001 ));
7002
7003 insns.push((
7004 Inst::FpuStoreP128 {
7005 rt: vreg(18),
7006 rt2: vreg(22),
7007 mem: PairAMode::SPPostIndexed {
7008 simm7: SImm7Scaled::maybe_from_i64(304, I8X16).unwrap(),
7009 },
7010 flags: MemFlags::trusted(),
7011 },
7012 "F2DB89AC",
7013 "stp q18, q22, [sp], #304",
7014 ));
7015
7016 insns.push((
7017 Inst::FpuCSel16 {
7018 rd: writable_vreg(1),
7019 rn: vreg(2),
7020 rm: vreg(3),
7021 cond: Cond::Hi,
7022 },
7023 "418CE31E",
7024 "fcsel h1, h2, h3, hi",
7025 ));
7026
7027 insns.push((
7028 Inst::FpuCSel32 {
7029 rd: writable_vreg(1),
7030 rn: vreg(2),
7031 rm: vreg(3),
7032 cond: Cond::Hi,
7033 },
7034 "418C231E",
7035 "fcsel s1, s2, s3, hi",
7036 ));
7037
7038 insns.push((
7039 Inst::FpuCSel64 {
7040 rd: writable_vreg(1),
7041 rn: vreg(2),
7042 rm: vreg(3),
7043 cond: Cond::Eq,
7044 },
7045 "410C631E",
7046 "fcsel d1, d2, d3, eq",
7047 ));
7048
7049 insns.push((
7050 Inst::FpuRound {
7051 rd: writable_vreg(23),
7052 rn: vreg(24),
7053 op: FpuRoundMode::Minus32,
7054 },
7055 "1743251E",
7056 "frintm s23, s24",
7057 ));
7058 insns.push((
7059 Inst::FpuRound {
7060 rd: writable_vreg(23),
7061 rn: vreg(24),
7062 op: FpuRoundMode::Minus64,
7063 },
7064 "1743651E",
7065 "frintm d23, d24",
7066 ));
7067 insns.push((
7068 Inst::FpuRound {
7069 rd: writable_vreg(23),
7070 rn: vreg(24),
7071 op: FpuRoundMode::Plus32,
7072 },
7073 "17C3241E",
7074 "frintp s23, s24",
7075 ));
7076 insns.push((
7077 Inst::FpuRound {
7078 rd: writable_vreg(23),
7079 rn: vreg(24),
7080 op: FpuRoundMode::Plus64,
7081 },
7082 "17C3641E",
7083 "frintp d23, d24",
7084 ));
7085 insns.push((
7086 Inst::FpuRound {
7087 rd: writable_vreg(23),
7088 rn: vreg(24),
7089 op: FpuRoundMode::Zero32,
7090 },
7091 "17C3251E",
7092 "frintz s23, s24",
7093 ));
7094 insns.push((
7095 Inst::FpuRound {
7096 rd: writable_vreg(23),
7097 rn: vreg(24),
7098 op: FpuRoundMode::Zero64,
7099 },
7100 "17C3651E",
7101 "frintz d23, d24",
7102 ));
7103 insns.push((
7104 Inst::FpuRound {
7105 rd: writable_vreg(23),
7106 rn: vreg(24),
7107 op: FpuRoundMode::Nearest32,
7108 },
7109 "1743241E",
7110 "frintn s23, s24",
7111 ));
7112 insns.push((
7113 Inst::FpuRound {
7114 rd: writable_vreg(23),
7115 rn: vreg(24),
7116 op: FpuRoundMode::Nearest64,
7117 },
7118 "1743641E",
7119 "frintn d23, d24",
7120 ));
7121
7122 insns.push((
7123 Inst::AtomicRMWLoop {
7124 ty: I8,
7125 op: AtomicRMWLoopOp::Sub,
7126 flags: MemFlags::trusted(),
7127 addr: xreg(25),
7128 operand: xreg(26),
7129 oldval: writable_xreg(27),
7130 scratch1: writable_xreg(24),
7131 scratch2: writable_xreg(28),
7132 },
7133 "3BFF5F087C031A4B3CFF1808B8FFFFB5",
7134 "atomic_rmw_loop_sub_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7135 ));
7136 insns.push((
7137 Inst::AtomicRMWLoop {
7138 ty: I16,
7139 op: AtomicRMWLoopOp::Eor,
7140 flags: MemFlags::trusted(),
7141 addr: xreg(25),
7142 operand: xreg(26),
7143 oldval: writable_xreg(27),
7144 scratch1: writable_xreg(24),
7145 scratch2: writable_xreg(28),
7146 },
7147 "3BFF5F487C031A4A3CFF1848B8FFFFB5",
7148 "atomic_rmw_loop_eor_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7149 ));
7150 insns.push((
7151 Inst::AtomicRMWLoop {
7152 ty: I8,
7153 op: AtomicRMWLoopOp::Add,
7154 flags: MemFlags::trusted(),
7155 addr: xreg(25),
7156 operand: xreg(26),
7157 oldval: writable_xreg(27),
7158 scratch1: writable_xreg(24),
7159 scratch2: writable_xreg(28),
7160 },
7161 "3BFF5F087C031A0B3CFF1808B8FFFFB5",
7162 "atomic_rmw_loop_add_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7163 ));
7164 insns.push((
7165 Inst::AtomicRMWLoop {
7166 ty: I32,
7167 op: AtomicRMWLoopOp::Orr,
7168 flags: MemFlags::trusted(),
7169 addr: xreg(25),
7170 operand: xreg(26),
7171 oldval: writable_xreg(27),
7172 scratch1: writable_xreg(24),
7173 scratch2: writable_xreg(28),
7174 },
7175 "3BFF5F887C031A2A3CFF1888B8FFFFB5",
7176 "atomic_rmw_loop_orr_32 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7177 ));
7178 insns.push((
7179 Inst::AtomicRMWLoop {
7180 ty: I64,
7181 op: AtomicRMWLoopOp::And,
7182 flags: MemFlags::trusted(),
7183 addr: xreg(25),
7184 operand: xreg(26),
7185 oldval: writable_xreg(27),
7186 scratch1: writable_xreg(24),
7187 scratch2: writable_xreg(28),
7188 },
7189 "3BFF5FC87C031A8A3CFF18C8B8FFFFB5",
7190 "atomic_rmw_loop_and_64 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7191 ));
7192 insns.push((
7193 Inst::AtomicRMWLoop {
7194 ty: I8,
7195 op: AtomicRMWLoopOp::Xchg,
7196 flags: MemFlags::trusted(),
7197 addr: xreg(25),
7198 operand: xreg(26),
7199 oldval: writable_xreg(27),
7200 scratch1: writable_xreg(24),
7201 scratch2: writable_xreg(28),
7202 },
7203 "3BFF5F083AFF1808D8FFFFB5",
7204 "atomic_rmw_loop_xchg_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7205 ));
7206 insns.push((
7207 Inst::AtomicRMWLoop {
7208 ty: I16,
7209 op: AtomicRMWLoopOp::Nand,
7210 flags: MemFlags::trusted(),
7211 addr: xreg(25),
7212 operand: xreg(26),
7213 oldval: writable_xreg(27),
7214 scratch1: writable_xreg(24),
7215 scratch2: writable_xreg(28),
7216 },
7217 "3BFF5F487C031A0AFC033C2A3CFF184898FFFFB5",
7218 "atomic_rmw_loop_nand_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7219 ));
7220 insns.push((
7221 Inst::AtomicRMWLoop {
7222 ty: I16,
7223 op: AtomicRMWLoopOp::Smin,
7224 flags: MemFlags::trusted(),
7225 addr: xreg(25),
7226 operand: xreg(26),
7227 oldval: writable_xreg(27),
7228 scratch1: writable_xreg(24),
7229 scratch2: writable_xreg(28),
7230 },
7231 "3BFF5F487B3F00137FA33A6B7CB39A9A3CFF184878FFFFB5",
7232 "atomic_rmw_loop_smin_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7233 ));
7234 insns.push((
7235 Inst::AtomicRMWLoop {
7236 ty: I32,
7237 op: AtomicRMWLoopOp::Smin,
7238 flags: MemFlags::trusted(),
7239 addr: xreg(25),
7240 operand: xreg(26),
7241 oldval: writable_xreg(27),
7242 scratch1: writable_xreg(24),
7243 scratch2: writable_xreg(28),
7244 },
7245 "3BFF5F887F031A6B7CB39A9A3CFF188898FFFFB5",
7246 "atomic_rmw_loop_smin_32 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7247 ));
7248 insns.push((
7249 Inst::AtomicRMWLoop {
7250 ty: I64,
7251 op: AtomicRMWLoopOp::Smax,
7252 flags: MemFlags::trusted(),
7253 addr: xreg(25),
7254 operand: xreg(26),
7255 oldval: writable_xreg(27),
7256 scratch1: writable_xreg(24),
7257 scratch2: writable_xreg(28),
7258 },
7259 "3BFF5FC87F031AEB7CC39A9A3CFF18C898FFFFB5",
7260 "atomic_rmw_loop_smax_64 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7261 ));
7262 insns.push((
7263 Inst::AtomicRMWLoop {
7264 ty: I8,
7265 op: AtomicRMWLoopOp::Smax,
7266 flags: MemFlags::trusted(),
7267 addr: xreg(25),
7268 operand: xreg(26),
7269 oldval: writable_xreg(27),
7270 scratch1: writable_xreg(24),
7271 scratch2: writable_xreg(28),
7272 },
7273 "3BFF5F087B1F00137F833A6B7CC39A9A3CFF180878FFFFB5",
7274 "atomic_rmw_loop_smax_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7275 ));
7276 insns.push((
7277 Inst::AtomicRMWLoop {
7278 ty: I8,
7279 op: AtomicRMWLoopOp::Umin,
7280 flags: MemFlags::trusted(),
7281 addr: xreg(25),
7282 operand: xreg(26),
7283 oldval: writable_xreg(27),
7284 scratch1: writable_xreg(24),
7285 scratch2: writable_xreg(28),
7286 },
7287 "3BFF5F087F031A6B7C339A9A3CFF180898FFFFB5",
7288 "atomic_rmw_loop_umin_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7289 ));
7290 insns.push((
7291 Inst::AtomicRMWLoop {
7292 ty: I16,
7293 op: AtomicRMWLoopOp::Umax,
7294 flags: MemFlags::trusted(),
7295 addr: xreg(25),
7296 operand: xreg(26),
7297 oldval: writable_xreg(27),
7298 scratch1: writable_xreg(24),
7299 scratch2: writable_xreg(28),
7300 },
7301 "3BFF5F487F031A6B7C839A9A3CFF184898FFFFB5",
7302 "atomic_rmw_loop_umax_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28",
7303 ));
7304
7305 insns.push((
7306 Inst::AtomicRMW {
7307 ty: I8,
7308 op: AtomicRMWOp::Add,
7309 rs: xreg(1),
7310 rt: writable_xreg(2),
7311 rn: xreg(3),
7312 flags: MemFlags::trusted(),
7313 },
7314 "6200E138",
7315 "ldaddalb w1, w2, [x3]",
7316 ));
7317 insns.push((
7318 Inst::AtomicRMW {
7319 ty: I16,
7320 op: AtomicRMWOp::Add,
7321 rs: xreg(4),
7322 rt: writable_xreg(5),
7323 rn: xreg(6),
7324 flags: MemFlags::trusted(),
7325 },
7326 "C500E478",
7327 "ldaddalh w4, w5, [x6]",
7328 ));
7329 insns.push((
7330 Inst::AtomicRMW {
7331 ty: I32,
7332 op: AtomicRMWOp::Add,
7333 rs: xreg(7),
7334 rt: writable_xreg(8),
7335 rn: xreg(9),
7336 flags: MemFlags::trusted(),
7337 },
7338 "2801E7B8",
7339 "ldaddal w7, w8, [x9]",
7340 ));
7341 insns.push((
7342 Inst::AtomicRMW {
7343 ty: I64,
7344 op: AtomicRMWOp::Add,
7345 rs: xreg(10),
7346 rt: writable_xreg(11),
7347 rn: xreg(12),
7348 flags: MemFlags::trusted(),
7349 },
7350 "8B01EAF8",
7351 "ldaddal x10, x11, [x12]",
7352 ));
7353 insns.push((
7354 Inst::AtomicRMW {
7355 ty: I8,
7356 op: AtomicRMWOp::Clr,
7357 rs: xreg(13),
7358 rt: writable_xreg(14),
7359 rn: xreg(15),
7360 flags: MemFlags::trusted(),
7361 },
7362 "EE11ED38",
7363 "ldclralb w13, w14, [x15]",
7364 ));
7365 insns.push((
7366 Inst::AtomicRMW {
7367 ty: I16,
7368 op: AtomicRMWOp::Clr,
7369 rs: xreg(16),
7370 rt: writable_xreg(17),
7371 rn: xreg(18),
7372 flags: MemFlags::trusted(),
7373 },
7374 "5112F078",
7375 "ldclralh w16, w17, [x18]",
7376 ));
7377 insns.push((
7378 Inst::AtomicRMW {
7379 ty: I32,
7380 op: AtomicRMWOp::Clr,
7381 rs: xreg(19),
7382 rt: writable_xreg(20),
7383 rn: xreg(21),
7384 flags: MemFlags::trusted(),
7385 },
7386 "B412F3B8",
7387 "ldclral w19, w20, [x21]",
7388 ));
7389 insns.push((
7390 Inst::AtomicRMW {
7391 ty: I64,
7392 op: AtomicRMWOp::Clr,
7393 rs: xreg(22),
7394 rt: writable_xreg(23),
7395 rn: xreg(24),
7396 flags: MemFlags::trusted(),
7397 },
7398 "1713F6F8",
7399 "ldclral x22, x23, [x24]",
7400 ));
7401 insns.push((
7402 Inst::AtomicRMW {
7403 ty: I8,
7404 op: AtomicRMWOp::Eor,
7405 rs: xreg(25),
7406 rt: writable_xreg(26),
7407 rn: xreg(27),
7408 flags: MemFlags::trusted(),
7409 },
7410 "7A23F938",
7411 "ldeoralb w25, w26, [x27]",
7412 ));
7413 insns.push((
7414 Inst::AtomicRMW {
7415 ty: I16,
7416 op: AtomicRMWOp::Eor,
7417 rs: xreg(28),
7418 rt: writable_xreg(29),
7419 rn: xreg(30),
7420 flags: MemFlags::trusted(),
7421 },
7422 "DD23FC78",
7423 "ldeoralh w28, fp, [lr]",
7424 ));
7425 insns.push((
7426 Inst::AtomicRMW {
7427 ty: I32,
7428 op: AtomicRMWOp::Eor,
7429 rs: xreg(29),
7430 rt: writable_xreg(28),
7431 rn: xreg(27),
7432 flags: MemFlags::trusted(),
7433 },
7434 "7C23FDB8",
7435 "ldeoral fp, w28, [x27]",
7436 ));
7437 insns.push((
7438 Inst::AtomicRMW {
7439 ty: I64,
7440 op: AtomicRMWOp::Eor,
7441 rs: xreg(26),
7442 rt: writable_xreg(25),
7443 rn: xreg(24),
7444 flags: MemFlags::trusted(),
7445 },
7446 "1923FAF8",
7447 "ldeoral x26, x25, [x24]",
7448 ));
7449 insns.push((
7450 Inst::AtomicRMW {
7451 ty: I8,
7452 op: AtomicRMWOp::Set,
7453 rs: xreg(23),
7454 rt: writable_xreg(22),
7455 rn: xreg(21),
7456 flags: MemFlags::trusted(),
7457 },
7458 "B632F738",
7459 "ldsetalb w23, w22, [x21]",
7460 ));
7461 insns.push((
7462 Inst::AtomicRMW {
7463 ty: I16,
7464 op: AtomicRMWOp::Set,
7465 rs: xreg(20),
7466 rt: writable_xreg(19),
7467 rn: xreg(18),
7468 flags: MemFlags::trusted(),
7469 },
7470 "5332F478",
7471 "ldsetalh w20, w19, [x18]",
7472 ));
7473 insns.push((
7474 Inst::AtomicRMW {
7475 ty: I32,
7476 op: AtomicRMWOp::Set,
7477 rs: xreg(17),
7478 rt: writable_xreg(16),
7479 rn: xreg(15),
7480 flags: MemFlags::trusted(),
7481 },
7482 "F031F1B8",
7483 "ldsetal w17, w16, [x15]",
7484 ));
7485 insns.push((
7486 Inst::AtomicRMW {
7487 ty: I64,
7488 op: AtomicRMWOp::Set,
7489 rs: xreg(14),
7490 rt: writable_xreg(13),
7491 rn: xreg(12),
7492 flags: MemFlags::trusted(),
7493 },
7494 "8D31EEF8",
7495 "ldsetal x14, x13, [x12]",
7496 ));
7497 insns.push((
7498 Inst::AtomicRMW {
7499 ty: I8,
7500 op: AtomicRMWOp::Smax,
7501 rs: xreg(11),
7502 rt: writable_xreg(10),
7503 rn: xreg(9),
7504 flags: MemFlags::trusted(),
7505 },
7506 "2A41EB38",
7507 "ldsmaxalb w11, w10, [x9]",
7508 ));
7509 insns.push((
7510 Inst::AtomicRMW {
7511 ty: I16,
7512 op: AtomicRMWOp::Smax,
7513 rs: xreg(8),
7514 rt: writable_xreg(7),
7515 rn: xreg(6),
7516 flags: MemFlags::trusted(),
7517 },
7518 "C740E878",
7519 "ldsmaxalh w8, w7, [x6]",
7520 ));
7521 insns.push((
7522 Inst::AtomicRMW {
7523 ty: I32,
7524 op: AtomicRMWOp::Smax,
7525 rs: xreg(5),
7526 rt: writable_xreg(4),
7527 rn: xreg(3),
7528 flags: MemFlags::trusted(),
7529 },
7530 "6440E5B8",
7531 "ldsmaxal w5, w4, [x3]",
7532 ));
7533 insns.push((
7534 Inst::AtomicRMW {
7535 ty: I64,
7536 op: AtomicRMWOp::Smax,
7537 rs: xreg(2),
7538 rt: writable_xreg(1),
7539 rn: xreg(0),
7540 flags: MemFlags::trusted(),
7541 },
7542 "0140E2F8",
7543 "ldsmaxal x2, x1, [x0]",
7544 ));
7545 insns.push((
7546 Inst::AtomicRMW {
7547 ty: I8,
7548 op: AtomicRMWOp::Smin,
7549 rs: xreg(1),
7550 rt: writable_xreg(2),
7551 rn: xreg(3),
7552 flags: MemFlags::trusted(),
7553 },
7554 "6250E138",
7555 "ldsminalb w1, w2, [x3]",
7556 ));
7557 insns.push((
7558 Inst::AtomicRMW {
7559 ty: I16,
7560 op: AtomicRMWOp::Smin,
7561 rs: xreg(4),
7562 rt: writable_xreg(5),
7563 rn: xreg(6),
7564 flags: MemFlags::trusted(),
7565 },
7566 "C550E478",
7567 "ldsminalh w4, w5, [x6]",
7568 ));
7569 insns.push((
7570 Inst::AtomicRMW {
7571 ty: I32,
7572 op: AtomicRMWOp::Smin,
7573 rs: xreg(7),
7574 rt: writable_xreg(8),
7575 rn: xreg(9),
7576 flags: MemFlags::trusted(),
7577 },
7578 "2851E7B8",
7579 "ldsminal w7, w8, [x9]",
7580 ));
7581 insns.push((
7582 Inst::AtomicRMW {
7583 ty: I64,
7584 op: AtomicRMWOp::Smin,
7585 rs: xreg(10),
7586 rt: writable_xreg(11),
7587 rn: xreg(12),
7588 flags: MemFlags::trusted(),
7589 },
7590 "8B51EAF8",
7591 "ldsminal x10, x11, [x12]",
7592 ));
7593 insns.push((
7594 Inst::AtomicRMW {
7595 ty: I8,
7596 op: AtomicRMWOp::Umax,
7597 rs: xreg(13),
7598 rt: writable_xreg(14),
7599 rn: xreg(15),
7600 flags: MemFlags::trusted(),
7601 },
7602 "EE61ED38",
7603 "ldumaxalb w13, w14, [x15]",
7604 ));
7605 insns.push((
7606 Inst::AtomicRMW {
7607 ty: I16,
7608 op: AtomicRMWOp::Umax,
7609 rs: xreg(16),
7610 rt: writable_xreg(17),
7611 rn: xreg(18),
7612 flags: MemFlags::trusted(),
7613 },
7614 "5162F078",
7615 "ldumaxalh w16, w17, [x18]",
7616 ));
7617 insns.push((
7618 Inst::AtomicRMW {
7619 ty: I32,
7620 op: AtomicRMWOp::Umax,
7621 rs: xreg(19),
7622 rt: writable_xreg(20),
7623 rn: xreg(21),
7624 flags: MemFlags::trusted(),
7625 },
7626 "B462F3B8",
7627 "ldumaxal w19, w20, [x21]",
7628 ));
7629 insns.push((
7630 Inst::AtomicRMW {
7631 ty: I64,
7632 op: AtomicRMWOp::Umax,
7633 rs: xreg(22),
7634 rt: writable_xreg(23),
7635 rn: xreg(24),
7636 flags: MemFlags::trusted(),
7637 },
7638 "1763F6F8",
7639 "ldumaxal x22, x23, [x24]",
7640 ));
7641 insns.push((
7642 Inst::AtomicRMW {
7643 ty: I8,
7644 op: AtomicRMWOp::Umin,
7645 rs: xreg(16),
7646 rt: writable_xreg(17),
7647 rn: xreg(18),
7648 flags: MemFlags::trusted(),
7649 },
7650 "5172F038",
7651 "lduminalb w16, w17, [x18]",
7652 ));
7653 insns.push((
7654 Inst::AtomicRMW {
7655 ty: I16,
7656 op: AtomicRMWOp::Umin,
7657 rs: xreg(19),
7658 rt: writable_xreg(20),
7659 rn: xreg(21),
7660 flags: MemFlags::trusted(),
7661 },
7662 "B472F378",
7663 "lduminalh w19, w20, [x21]",
7664 ));
7665 insns.push((
7666 Inst::AtomicRMW {
7667 ty: I32,
7668 op: AtomicRMWOp::Umin,
7669 rs: xreg(22),
7670 rt: writable_xreg(23),
7671 rn: xreg(24),
7672 flags: MemFlags::trusted(),
7673 },
7674 "1773F6B8",
7675 "lduminal w22, w23, [x24]",
7676 ));
7677 insns.push((
7678 Inst::AtomicRMW {
7679 ty: I64,
7680 op: AtomicRMWOp::Umin,
7681 rs: xreg(25),
7682 rt: writable_xreg(26),
7683 rn: xreg(27),
7684 flags: MemFlags::trusted(),
7685 },
7686 "7A73F9F8",
7687 "lduminal x25, x26, [x27]",
7688 ));
7689 insns.push((
7690 Inst::AtomicRMW {
7691 ty: I8,
7692 op: AtomicRMWOp::Swp,
7693 rs: xreg(28),
7694 rt: writable_xreg(29),
7695 rn: xreg(30),
7696 flags: MemFlags::trusted(),
7697 },
7698 "DD83FC38",
7699 "swpalb w28, fp, [lr]",
7700 ));
7701 insns.push((
7702 Inst::AtomicRMW {
7703 ty: I16,
7704 op: AtomicRMWOp::Swp,
7705 rs: xreg(0),
7706 rt: writable_xreg(1),
7707 rn: xreg(2),
7708 flags: MemFlags::trusted(),
7709 },
7710 "4180E078",
7711 "swpalh w0, w1, [x2]",
7712 ));
7713 insns.push((
7714 Inst::AtomicRMW {
7715 ty: I32,
7716 op: AtomicRMWOp::Swp,
7717 rs: xreg(3),
7718 rt: writable_xreg(4),
7719 rn: xreg(5),
7720 flags: MemFlags::trusted(),
7721 },
7722 "A480E3B8",
7723 "swpal w3, w4, [x5]",
7724 ));
7725 insns.push((
7726 Inst::AtomicRMW {
7727 ty: I64,
7728 op: AtomicRMWOp::Swp,
7729 rs: xreg(6),
7730 rt: writable_xreg(7),
7731 rn: xreg(8),
7732 flags: MemFlags::trusted(),
7733 },
7734 "0781E6F8",
7735 "swpal x6, x7, [x8]",
7736 ));
7737
7738 insns.push((
7739 Inst::AtomicCAS {
7740 rd: writable_xreg(28),
7741 rs: xreg(28),
7742 rt: xreg(20),
7743 rn: xreg(10),
7744 ty: I8,
7745 flags: MemFlags::trusted(),
7746 },
7747 "54FDFC08",
7748 "casalb w28, w28, w20, [x10]",
7749 ));
7750 insns.push((
7751 Inst::AtomicCAS {
7752 rd: writable_xreg(2),
7753 rs: xreg(2),
7754 rt: xreg(19),
7755 rn: xreg(23),
7756 ty: I16,
7757 flags: MemFlags::trusted(),
7758 },
7759 "F3FEE248",
7760 "casalh w2, w2, w19, [x23]",
7761 ));
7762 insns.push((
7763 Inst::AtomicCAS {
7764 rd: writable_xreg(0),
7765 rs: xreg(0),
7766 rt: zero_reg(),
7767 rn: stack_reg(),
7768 ty: I32,
7769 flags: MemFlags::trusted(),
7770 },
7771 "FFFFE088",
7772 "casal w0, w0, wzr, [sp]",
7773 ));
7774 insns.push((
7775 Inst::AtomicCAS {
7776 rd: writable_xreg(7),
7777 rs: xreg(7),
7778 rt: xreg(15),
7779 rn: xreg(27),
7780 ty: I64,
7781 flags: MemFlags::trusted(),
7782 },
7783 "6FFFE7C8",
7784 "casal x7, x7, x15, [x27]",
7785 ));
7786 insns.push((
7787 Inst::AtomicCASLoop {
7788 ty: I8,
7789 flags: MemFlags::trusted(),
7790 addr: xreg(25),
7791 expected: xreg(26),
7792 replacement: xreg(28),
7793 oldval: writable_xreg(27),
7794 scratch: writable_xreg(24),
7795 },
7796 "3BFF5F087F033AEB610000543CFF180898FFFFB5",
7797 "atomic_cas_loop_8 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7798 ));
7799
7800 insns.push((
7801 Inst::AtomicCASLoop {
7802 ty: I16,
7803 flags: MemFlags::trusted(),
7804 addr: xreg(25),
7805 expected: xreg(26),
7806 replacement: xreg(28),
7807 oldval: writable_xreg(27),
7808 scratch: writable_xreg(24),
7809 },
7810 "3BFF5F487F233AEB610000543CFF184898FFFFB5",
7811 "atomic_cas_loop_16 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7812 ));
7813
7814 insns.push((
7815 Inst::AtomicCASLoop {
7816 ty: I32,
7817 flags: MemFlags::trusted(),
7818 addr: xreg(25),
7819 expected: xreg(26),
7820 replacement: xreg(28),
7821 oldval: writable_xreg(27),
7822 scratch: writable_xreg(24),
7823 },
7824 "3BFF5F887F031AEB610000543CFF188898FFFFB5",
7825 "atomic_cas_loop_32 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7826 ));
7827
7828 insns.push((
7829 Inst::AtomicCASLoop {
7830 ty: I64,
7831 flags: MemFlags::trusted(),
7832 addr: xreg(25),
7833 expected: xreg(26),
7834 replacement: xreg(28),
7835 oldval: writable_xreg(27),
7836 scratch: writable_xreg(24),
7837 },
7838 "3BFF5FC87F031AEB610000543CFF18C898FFFFB5",
7839 "atomic_cas_loop_64 addr=x25, expect=x26, replacement=x28, oldval=x27, scratch=x24",
7840 ));
7841
7842 insns.push((
7843 Inst::LoadAcquire {
7844 access_ty: I8,
7845 rt: writable_xreg(7),
7846 rn: xreg(28),
7847 flags: MemFlags::trusted(),
7848 },
7849 "87FFDF08",
7850 "ldarb w7, [x28]",
7851 ));
7852
7853 insns.push((
7854 Inst::LoadAcquire {
7855 access_ty: I16,
7856 rt: writable_xreg(2),
7857 rn: xreg(3),
7858 flags: MemFlags::trusted(),
7859 },
7860 "62FCDF48",
7861 "ldarh w2, [x3]",
7862 ));
7863
7864 insns.push((
7865 Inst::LoadAcquire {
7866 access_ty: I32,
7867 rt: writable_xreg(15),
7868 rn: xreg(0),
7869 flags: MemFlags::trusted(),
7870 },
7871 "0FFCDF88",
7872 "ldar w15, [x0]",
7873 ));
7874
7875 insns.push((
7876 Inst::LoadAcquire {
7877 access_ty: I64,
7878 rt: writable_xreg(28),
7879 rn: xreg(7),
7880 flags: MemFlags::trusted(),
7881 },
7882 "FCFCDFC8",
7883 "ldar x28, [x7]",
7884 ));
7885
7886 insns.push((
7887 Inst::StoreRelease {
7888 access_ty: I8,
7889 rt: xreg(7),
7890 rn: xreg(28),
7891 flags: MemFlags::trusted(),
7892 },
7893 "87FF9F08",
7894 "stlrb w7, [x28]",
7895 ));
7896
7897 insns.push((
7898 Inst::StoreRelease {
7899 access_ty: I16,
7900 rt: xreg(2),
7901 rn: xreg(3),
7902 flags: MemFlags::trusted(),
7903 },
7904 "62FC9F48",
7905 "stlrh w2, [x3]",
7906 ));
7907
7908 insns.push((
7909 Inst::StoreRelease {
7910 access_ty: I32,
7911 rt: xreg(15),
7912 rn: xreg(0),
7913 flags: MemFlags::trusted(),
7914 },
7915 "0FFC9F88",
7916 "stlr w15, [x0]",
7917 ));
7918
7919 insns.push((
7920 Inst::StoreRelease {
7921 access_ty: I64,
7922 rt: xreg(28),
7923 rn: xreg(7),
7924 flags: MemFlags::trusted(),
7925 },
7926 "FCFC9FC8",
7927 "stlr x28, [x7]",
7928 ));
7929
7930 insns.push((Inst::Fence {}, "BF3B03D5", "dmb ish"));
7931
7932 let flags = settings::Flags::new(settings::builder());
7933 let isa_flags = aarch64::settings::Flags::new(&flags, &aarch64::settings::builder());
7934 let emit_info = EmitInfo::new(flags, isa_flags);
7935 for (insn, expected_encoding, expected_printing) in insns {
7936 println!("AArch64: {insn:?}, {expected_encoding}, {expected_printing}");
7937
7938 // Check the printed text is as expected.
7939 let actual_printing = insn.print_with_state(&mut EmitState::default());
7940 assert_eq!(expected_printing, actual_printing);
7941
7942 let mut buffer = MachBuffer::new();
7943 insn.emit(&mut buffer, &emit_info, &mut Default::default());
7944 let buffer = buffer.finish(&Default::default(), &mut Default::default());
7945 let actual_encoding = &buffer.stringify_code_bytes();
7946 assert_eq!(expected_encoding, actual_encoding);
7947 }
7948 }
7949
7950 #[test]
test_cond_invert()7951 fn test_cond_invert() {
7952 for cond in vec![
7953 Cond::Eq,
7954 Cond::Ne,
7955 Cond::Hs,
7956 Cond::Lo,
7957 Cond::Mi,
7958 Cond::Pl,
7959 Cond::Vs,
7960 Cond::Vc,
7961 Cond::Hi,
7962 Cond::Ls,
7963 Cond::Ge,
7964 Cond::Lt,
7965 Cond::Gt,
7966 Cond::Le,
7967 Cond::Al,
7968 Cond::Nv,
7969 ]
7970 .into_iter()
7971 {
7972 assert_eq!(cond.invert().invert(), cond);
7973 }
7974 }
7975