15c0c51a9SNicolas Vasilache //===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===//
25c0c51a9SNicolas Vasilache //
356222a06SMehdi Amini // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions.
456222a06SMehdi Amini // See https://llvm.org/LICENSE.txt for license information.
556222a06SMehdi Amini // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
65c0c51a9SNicolas Vasilache //
756222a06SMehdi Amini //===----------------------------------------------------------------------===//
85c0c51a9SNicolas Vasilache 
965678d93SNicolas Vasilache #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
105c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
115c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
125c0c51a9SNicolas Vasilache #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
1365678d93SNicolas Vasilache #include "mlir/Dialect/StandardOps/Ops.h"
145c0c51a9SNicolas Vasilache #include "mlir/Dialect/VectorOps/VectorOps.h"
155c0c51a9SNicolas Vasilache #include "mlir/IR/Attributes.h"
165c0c51a9SNicolas Vasilache #include "mlir/IR/Builders.h"
175c0c51a9SNicolas Vasilache #include "mlir/IR/MLIRContext.h"
185c0c51a9SNicolas Vasilache #include "mlir/IR/Module.h"
195c0c51a9SNicolas Vasilache #include "mlir/IR/Operation.h"
205c0c51a9SNicolas Vasilache #include "mlir/IR/PatternMatch.h"
215c0c51a9SNicolas Vasilache #include "mlir/IR/StandardTypes.h"
225c0c51a9SNicolas Vasilache #include "mlir/IR/Types.h"
235c0c51a9SNicolas Vasilache #include "mlir/Pass/Pass.h"
245c0c51a9SNicolas Vasilache #include "mlir/Pass/PassManager.h"
255c0c51a9SNicolas Vasilache #include "mlir/Transforms/DialectConversion.h"
265c0c51a9SNicolas Vasilache #include "mlir/Transforms/Passes.h"
275c0c51a9SNicolas Vasilache 
285c0c51a9SNicolas Vasilache #include "llvm/IR/DerivedTypes.h"
295c0c51a9SNicolas Vasilache #include "llvm/IR/Module.h"
305c0c51a9SNicolas Vasilache #include "llvm/IR/Type.h"
315c0c51a9SNicolas Vasilache #include "llvm/Support/Allocator.h"
325c0c51a9SNicolas Vasilache #include "llvm/Support/ErrorHandling.h"
335c0c51a9SNicolas Vasilache 
345c0c51a9SNicolas Vasilache using namespace mlir;
3565678d93SNicolas Vasilache using namespace mlir::vector;
365c0c51a9SNicolas Vasilache 
37df186507SBenjamin Kramer namespace {
38df186507SBenjamin Kramer 
395c0c51a9SNicolas Vasilache template <typename T>
405c0c51a9SNicolas Vasilache static LLVM::LLVMType getPtrToElementType(T containerType,
415c0c51a9SNicolas Vasilache                                           LLVMTypeConverter &lowering) {
425c0c51a9SNicolas Vasilache   return lowering.convertType(containerType.getElementType())
435c0c51a9SNicolas Vasilache       .template cast<LLVM::LLVMType>()
445c0c51a9SNicolas Vasilache       .getPointerTo();
455c0c51a9SNicolas Vasilache }
465c0c51a9SNicolas Vasilache 
479826fe5cSAart Bik // Helper to reduce vector type by one rank at front.
489826fe5cSAart Bik static VectorType reducedVectorTypeFront(VectorType tp) {
499826fe5cSAart Bik   assert((tp.getRank() > 1) && "unlowerable vector type");
509826fe5cSAart Bik   return VectorType::get(tp.getShape().drop_front(), tp.getElementType());
519826fe5cSAart Bik }
529826fe5cSAart Bik 
539826fe5cSAart Bik // Helper to reduce vector type by *all* but one rank at back.
549826fe5cSAart Bik static VectorType reducedVectorTypeBack(VectorType tp) {
559826fe5cSAart Bik   assert((tp.getRank() > 1) && "unlowerable vector type");
569826fe5cSAart Bik   return VectorType::get(tp.getShape().take_back(), tp.getElementType());
579826fe5cSAart Bik }
589826fe5cSAart Bik 
591c81adf3SAart Bik // Helper that picks the proper sequence for inserting.
60e62a6956SRiver Riddle static Value insertOne(ConversionPatternRewriter &rewriter,
61e62a6956SRiver Riddle                        LLVMTypeConverter &lowering, Location loc, Value val1,
62e62a6956SRiver Riddle                        Value val2, Type llvmType, int64_t rank, int64_t pos) {
631c81adf3SAart Bik   if (rank == 1) {
641c81adf3SAart Bik     auto idxType = rewriter.getIndexType();
651c81adf3SAart Bik     auto constant = rewriter.create<LLVM::ConstantOp>(
661c81adf3SAart Bik         loc, lowering.convertType(idxType),
671c81adf3SAart Bik         rewriter.getIntegerAttr(idxType, pos));
681c81adf3SAart Bik     return rewriter.create<LLVM::InsertElementOp>(loc, llvmType, val1, val2,
691c81adf3SAart Bik                                                   constant);
701c81adf3SAart Bik   }
711c81adf3SAart Bik   return rewriter.create<LLVM::InsertValueOp>(loc, llvmType, val1, val2,
721c81adf3SAart Bik                                               rewriter.getI64ArrayAttr(pos));
731c81adf3SAart Bik }
741c81adf3SAart Bik 
752d515e49SNicolas Vasilache // Helper that picks the proper sequence for inserting.
762d515e49SNicolas Vasilache static Value insertOne(PatternRewriter &rewriter, Location loc, Value from,
772d515e49SNicolas Vasilache                        Value into, int64_t offset) {
782d515e49SNicolas Vasilache   auto vectorType = into.getType().cast<VectorType>();
792d515e49SNicolas Vasilache   if (vectorType.getRank() > 1)
802d515e49SNicolas Vasilache     return rewriter.create<InsertOp>(loc, from, into, offset);
812d515e49SNicolas Vasilache   return rewriter.create<vector::InsertElementOp>(
822d515e49SNicolas Vasilache       loc, vectorType, from, into,
832d515e49SNicolas Vasilache       rewriter.create<ConstantIndexOp>(loc, offset));
842d515e49SNicolas Vasilache }
852d515e49SNicolas Vasilache 
861c81adf3SAart Bik // Helper that picks the proper sequence for extracting.
87e62a6956SRiver Riddle static Value extractOne(ConversionPatternRewriter &rewriter,
88e62a6956SRiver Riddle                         LLVMTypeConverter &lowering, Location loc, Value val,
89e62a6956SRiver Riddle                         Type llvmType, int64_t rank, int64_t pos) {
901c81adf3SAart Bik   if (rank == 1) {
911c81adf3SAart Bik     auto idxType = rewriter.getIndexType();
921c81adf3SAart Bik     auto constant = rewriter.create<LLVM::ConstantOp>(
931c81adf3SAart Bik         loc, lowering.convertType(idxType),
941c81adf3SAart Bik         rewriter.getIntegerAttr(idxType, pos));
951c81adf3SAart Bik     return rewriter.create<LLVM::ExtractElementOp>(loc, llvmType, val,
961c81adf3SAart Bik                                                    constant);
971c81adf3SAart Bik   }
981c81adf3SAart Bik   return rewriter.create<LLVM::ExtractValueOp>(loc, llvmType, val,
991c81adf3SAart Bik                                                rewriter.getI64ArrayAttr(pos));
1001c81adf3SAart Bik }
1011c81adf3SAart Bik 
1022d515e49SNicolas Vasilache // Helper that picks the proper sequence for extracting.
1032d515e49SNicolas Vasilache static Value extractOne(PatternRewriter &rewriter, Location loc, Value vector,
1042d515e49SNicolas Vasilache                         int64_t offset) {
1052d515e49SNicolas Vasilache   auto vectorType = vector.getType().cast<VectorType>();
1062d515e49SNicolas Vasilache   if (vectorType.getRank() > 1)
1072d515e49SNicolas Vasilache     return rewriter.create<ExtractOp>(loc, vector, offset);
1082d515e49SNicolas Vasilache   return rewriter.create<vector::ExtractElementOp>(
1092d515e49SNicolas Vasilache       loc, vectorType.getElementType(), vector,
1102d515e49SNicolas Vasilache       rewriter.create<ConstantIndexOp>(loc, offset));
1112d515e49SNicolas Vasilache }
1122d515e49SNicolas Vasilache 
1132d515e49SNicolas Vasilache // Helper that returns a subset of `arrayAttr` as a vector of int64_t.
1142d515e49SNicolas Vasilache // TODO(rriddle): Better support for attribute subtype forwarding + slicing.
1152d515e49SNicolas Vasilache static SmallVector<int64_t, 4> getI64SubArray(ArrayAttr arrayAttr,
1162d515e49SNicolas Vasilache                                               unsigned dropFront = 0,
1172d515e49SNicolas Vasilache                                               unsigned dropBack = 0) {
1182d515e49SNicolas Vasilache   assert(arrayAttr.size() > dropFront + dropBack && "Out of bounds");
1192d515e49SNicolas Vasilache   auto range = arrayAttr.getAsRange<IntegerAttr>();
1202d515e49SNicolas Vasilache   SmallVector<int64_t, 4> res;
1212d515e49SNicolas Vasilache   res.reserve(arrayAttr.size() - dropFront - dropBack);
1222d515e49SNicolas Vasilache   for (auto it = range.begin() + dropFront, eit = range.end() - dropBack;
1232d515e49SNicolas Vasilache        it != eit; ++it)
1242d515e49SNicolas Vasilache     res.push_back((*it).getValue().getSExtValue());
1252d515e49SNicolas Vasilache   return res;
1262d515e49SNicolas Vasilache }
1272d515e49SNicolas Vasilache 
128b36aaeafSAart Bik class VectorBroadcastOpConversion : public LLVMOpLowering {
129b36aaeafSAart Bik public:
130b36aaeafSAart Bik   explicit VectorBroadcastOpConversion(MLIRContext *context,
131b36aaeafSAart Bik                                        LLVMTypeConverter &typeConverter)
132b36aaeafSAart Bik       : LLVMOpLowering(vector::BroadcastOp::getOperationName(), context,
133b36aaeafSAart Bik                        typeConverter) {}
134b36aaeafSAart Bik 
135b36aaeafSAart Bik   PatternMatchResult
136e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
137b36aaeafSAart Bik                   ConversionPatternRewriter &rewriter) const override {
138b36aaeafSAart Bik     auto broadcastOp = cast<vector::BroadcastOp>(op);
139b36aaeafSAart Bik     VectorType dstVectorType = broadcastOp.getVectorType();
140b36aaeafSAart Bik     if (lowering.convertType(dstVectorType) == nullptr)
141b36aaeafSAart Bik       return matchFailure();
142b36aaeafSAart Bik     // Rewrite when the full vector type can be lowered (which
143b36aaeafSAart Bik     // implies all 'reduced' types can be lowered too).
1441c81adf3SAart Bik     auto adaptor = vector::BroadcastOpOperandAdaptor(operands);
145b36aaeafSAart Bik     VectorType srcVectorType =
146b36aaeafSAart Bik         broadcastOp.getSourceType().dyn_cast<VectorType>();
147b36aaeafSAart Bik     rewriter.replaceOp(
1481c81adf3SAart Bik         op, expandRanks(adaptor.source(), // source value to be expanded
149b36aaeafSAart Bik                         op->getLoc(),     // location of original broadcast
150b36aaeafSAart Bik                         srcVectorType, dstVectorType, rewriter));
151b36aaeafSAart Bik     return matchSuccess();
152b36aaeafSAart Bik   }
153b36aaeafSAart Bik 
154b36aaeafSAart Bik private:
155b36aaeafSAart Bik   // Expands the given source value over all the ranks, as defined
156b36aaeafSAart Bik   // by the source and destination type (a null source type denotes
157b36aaeafSAart Bik   // expansion from a scalar value into a vector).
158b36aaeafSAart Bik   //
159b36aaeafSAart Bik   // TODO(ajcbik): consider replacing this one-pattern lowering
160b36aaeafSAart Bik   //               with a two-pattern lowering using other vector
161b36aaeafSAart Bik   //               ops once all insert/extract/shuffle operations
162*fc817b09SKazuaki Ishizaki   //               are available with lowering implementation.
163b36aaeafSAart Bik   //
164e62a6956SRiver Riddle   Value expandRanks(Value value, Location loc, VectorType srcVectorType,
165b36aaeafSAart Bik                     VectorType dstVectorType,
166b36aaeafSAart Bik                     ConversionPatternRewriter &rewriter) const {
167b36aaeafSAart Bik     assert((dstVectorType != nullptr) && "invalid result type in broadcast");
168b36aaeafSAart Bik     // Determine rank of source and destination.
169b36aaeafSAart Bik     int64_t srcRank = srcVectorType ? srcVectorType.getRank() : 0;
170b36aaeafSAart Bik     int64_t dstRank = dstVectorType.getRank();
171b36aaeafSAart Bik     int64_t curDim = dstVectorType.getDimSize(0);
172b36aaeafSAart Bik     if (srcRank < dstRank)
173b36aaeafSAart Bik       // Duplicate this rank.
174b36aaeafSAart Bik       return duplicateOneRank(value, loc, srcVectorType, dstVectorType, dstRank,
175b36aaeafSAart Bik                               curDim, rewriter);
176b36aaeafSAart Bik     // If all trailing dimensions are the same, the broadcast consists of
177b36aaeafSAart Bik     // simply passing through the source value and we are done. Otherwise,
178b36aaeafSAart Bik     // any non-matching dimension forces a stretch along this rank.
179b36aaeafSAart Bik     assert((srcVectorType != nullptr) && (srcRank > 0) &&
180b36aaeafSAart Bik            (srcRank == dstRank) && "invalid rank in broadcast");
181b36aaeafSAart Bik     for (int64_t r = 0; r < dstRank; r++) {
182b36aaeafSAart Bik       if (srcVectorType.getDimSize(r) != dstVectorType.getDimSize(r)) {
183b36aaeafSAart Bik         return stretchOneRank(value, loc, srcVectorType, dstVectorType, dstRank,
184b36aaeafSAart Bik                               curDim, rewriter);
185b36aaeafSAart Bik       }
186b36aaeafSAart Bik     }
187b36aaeafSAart Bik     return value;
188b36aaeafSAart Bik   }
189b36aaeafSAart Bik 
190b36aaeafSAart Bik   // Picks the best way to duplicate a single rank. For the 1-D case, a
191b36aaeafSAart Bik   // single insert-elt/shuffle is the most efficient expansion. For higher
192b36aaeafSAart Bik   // dimensions, however, we need dim x insert-values on a new broadcast
193b36aaeafSAart Bik   // with one less leading dimension, which will be lowered "recursively"
194b36aaeafSAart Bik   // to matching LLVM IR.
195b36aaeafSAart Bik   // For example:
196b36aaeafSAart Bik   //   v = broadcast s : f32 to vector<4x2xf32>
197b36aaeafSAart Bik   // becomes:
198b36aaeafSAart Bik   //   x = broadcast s : f32 to vector<2xf32>
199b36aaeafSAart Bik   //   v = [x,x,x,x]
200b36aaeafSAart Bik   // becomes:
201b36aaeafSAart Bik   //   x = [s,s]
202b36aaeafSAart Bik   //   v = [x,x,x,x]
203e62a6956SRiver Riddle   Value duplicateOneRank(Value value, Location loc, VectorType srcVectorType,
204e62a6956SRiver Riddle                          VectorType dstVectorType, int64_t rank, int64_t dim,
205b36aaeafSAart Bik                          ConversionPatternRewriter &rewriter) const {
206b36aaeafSAart Bik     Type llvmType = lowering.convertType(dstVectorType);
207b36aaeafSAart Bik     assert((llvmType != nullptr) && "unlowerable vector type");
208b36aaeafSAart Bik     if (rank == 1) {
209e62a6956SRiver Riddle       Value undef = rewriter.create<LLVM::UndefOp>(loc, llvmType);
210e62a6956SRiver Riddle       Value expand =
2111c81adf3SAart Bik           insertOne(rewriter, lowering, loc, undef, value, llvmType, rank, 0);
212b36aaeafSAart Bik       SmallVector<int32_t, 4> zeroValues(dim, 0);
213b36aaeafSAart Bik       return rewriter.create<LLVM::ShuffleVectorOp>(
214b36aaeafSAart Bik           loc, expand, undef, rewriter.getI32ArrayAttr(zeroValues));
215b36aaeafSAart Bik     }
216e62a6956SRiver Riddle     Value expand = expandRanks(value, loc, srcVectorType,
2179826fe5cSAart Bik                                reducedVectorTypeFront(dstVectorType), rewriter);
218e62a6956SRiver Riddle     Value result = rewriter.create<LLVM::UndefOp>(loc, llvmType);
219b36aaeafSAart Bik     for (int64_t d = 0; d < dim; ++d) {
2201c81adf3SAart Bik       result =
2211c81adf3SAart Bik           insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d);
222b36aaeafSAart Bik     }
223b36aaeafSAart Bik     return result;
224b36aaeafSAart Bik   }
225b36aaeafSAart Bik 
226b36aaeafSAart Bik   // Picks the best way to stretch a single rank. For the 1-D case, a
227b36aaeafSAart Bik   // single insert-elt/shuffle is the most efficient expansion when at
228b36aaeafSAart Bik   // a stretch. Otherwise, every dimension needs to be expanded
229b36aaeafSAart Bik   // individually and individually inserted in the resulting vector.
230b36aaeafSAart Bik   // For example:
231b36aaeafSAart Bik   //   v = broadcast w : vector<4x1x2xf32> to vector<4x2x2xf32>
232b36aaeafSAart Bik   // becomes:
233b36aaeafSAart Bik   //   a = broadcast w[0] : vector<1x2xf32> to vector<2x2xf32>
234b36aaeafSAart Bik   //   b = broadcast w[1] : vector<1x2xf32> to vector<2x2xf32>
235b36aaeafSAart Bik   //   c = broadcast w[2] : vector<1x2xf32> to vector<2x2xf32>
236b36aaeafSAart Bik   //   d = broadcast w[3] : vector<1x2xf32> to vector<2x2xf32>
237b36aaeafSAart Bik   //   v = [a,b,c,d]
238b36aaeafSAart Bik   // becomes:
239b36aaeafSAart Bik   //   x = broadcast w[0][0] : vector<2xf32> to vector <2x2xf32>
240b36aaeafSAart Bik   //   y = broadcast w[1][0] : vector<2xf32> to vector <2x2xf32>
241b36aaeafSAart Bik   //   a = [x, y]
242b36aaeafSAart Bik   //   etc.
243e62a6956SRiver Riddle   Value stretchOneRank(Value value, Location loc, VectorType srcVectorType,
244e62a6956SRiver Riddle                        VectorType dstVectorType, int64_t rank, int64_t dim,
245b36aaeafSAart Bik                        ConversionPatternRewriter &rewriter) const {
246b36aaeafSAart Bik     Type llvmType = lowering.convertType(dstVectorType);
247b36aaeafSAart Bik     assert((llvmType != nullptr) && "unlowerable vector type");
248e62a6956SRiver Riddle     Value result = rewriter.create<LLVM::UndefOp>(loc, llvmType);
249b36aaeafSAart Bik     bool atStretch = dim != srcVectorType.getDimSize(0);
250b36aaeafSAart Bik     if (rank == 1) {
2511c81adf3SAart Bik       assert(atStretch);
252b36aaeafSAart Bik       Type redLlvmType = lowering.convertType(dstVectorType.getElementType());
253e62a6956SRiver Riddle       Value one =
2541c81adf3SAart Bik           extractOne(rewriter, lowering, loc, value, redLlvmType, rank, 0);
255e62a6956SRiver Riddle       Value expand =
2561c81adf3SAart Bik           insertOne(rewriter, lowering, loc, result, one, llvmType, rank, 0);
257b36aaeafSAart Bik       SmallVector<int32_t, 4> zeroValues(dim, 0);
258b36aaeafSAart Bik       return rewriter.create<LLVM::ShuffleVectorOp>(
259b36aaeafSAart Bik           loc, expand, result, rewriter.getI32ArrayAttr(zeroValues));
260b36aaeafSAart Bik     }
2619826fe5cSAart Bik     VectorType redSrcType = reducedVectorTypeFront(srcVectorType);
2629826fe5cSAart Bik     VectorType redDstType = reducedVectorTypeFront(dstVectorType);
263b36aaeafSAart Bik     Type redLlvmType = lowering.convertType(redSrcType);
264b36aaeafSAart Bik     for (int64_t d = 0; d < dim; ++d) {
265b36aaeafSAart Bik       int64_t pos = atStretch ? 0 : d;
266e62a6956SRiver Riddle       Value one =
2671c81adf3SAart Bik           extractOne(rewriter, lowering, loc, value, redLlvmType, rank, pos);
268e62a6956SRiver Riddle       Value expand = expandRanks(one, loc, redSrcType, redDstType, rewriter);
2691c81adf3SAart Bik       result =
2701c81adf3SAart Bik           insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d);
271b36aaeafSAart Bik     }
272b36aaeafSAart Bik     return result;
273b36aaeafSAart Bik   }
2741c81adf3SAart Bik };
275b36aaeafSAart Bik 
2761c81adf3SAart Bik class VectorShuffleOpConversion : public LLVMOpLowering {
2771c81adf3SAart Bik public:
2781c81adf3SAart Bik   explicit VectorShuffleOpConversion(MLIRContext *context,
2791c81adf3SAart Bik                                      LLVMTypeConverter &typeConverter)
2801c81adf3SAart Bik       : LLVMOpLowering(vector::ShuffleOp::getOperationName(), context,
2811c81adf3SAart Bik                        typeConverter) {}
2821c81adf3SAart Bik 
2831c81adf3SAart Bik   PatternMatchResult
284e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
2851c81adf3SAart Bik                   ConversionPatternRewriter &rewriter) const override {
2861c81adf3SAart Bik     auto loc = op->getLoc();
2871c81adf3SAart Bik     auto adaptor = vector::ShuffleOpOperandAdaptor(operands);
2881c81adf3SAart Bik     auto shuffleOp = cast<vector::ShuffleOp>(op);
2891c81adf3SAart Bik     auto v1Type = shuffleOp.getV1VectorType();
2901c81adf3SAart Bik     auto v2Type = shuffleOp.getV2VectorType();
2911c81adf3SAart Bik     auto vectorType = shuffleOp.getVectorType();
2921c81adf3SAart Bik     Type llvmType = lowering.convertType(vectorType);
2931c81adf3SAart Bik     auto maskArrayAttr = shuffleOp.mask();
2941c81adf3SAart Bik 
2951c81adf3SAart Bik     // Bail if result type cannot be lowered.
2961c81adf3SAart Bik     if (!llvmType)
2971c81adf3SAart Bik       return matchFailure();
2981c81adf3SAart Bik 
2991c81adf3SAart Bik     // Get rank and dimension sizes.
3001c81adf3SAart Bik     int64_t rank = vectorType.getRank();
3011c81adf3SAart Bik     assert(v1Type.getRank() == rank);
3021c81adf3SAart Bik     assert(v2Type.getRank() == rank);
3031c81adf3SAart Bik     int64_t v1Dim = v1Type.getDimSize(0);
3041c81adf3SAart Bik 
3051c81adf3SAart Bik     // For rank 1, where both operands have *exactly* the same vector type,
3061c81adf3SAart Bik     // there is direct shuffle support in LLVM. Use it!
3071c81adf3SAart Bik     if (rank == 1 && v1Type == v2Type) {
308e62a6956SRiver Riddle       Value shuffle = rewriter.create<LLVM::ShuffleVectorOp>(
3091c81adf3SAart Bik           loc, adaptor.v1(), adaptor.v2(), maskArrayAttr);
3101c81adf3SAart Bik       rewriter.replaceOp(op, shuffle);
3111c81adf3SAart Bik       return matchSuccess();
312b36aaeafSAart Bik     }
313b36aaeafSAart Bik 
3141c81adf3SAart Bik     // For all other cases, insert the individual values individually.
315e62a6956SRiver Riddle     Value insert = rewriter.create<LLVM::UndefOp>(loc, llvmType);
3161c81adf3SAart Bik     int64_t insPos = 0;
3171c81adf3SAart Bik     for (auto en : llvm::enumerate(maskArrayAttr)) {
3181c81adf3SAart Bik       int64_t extPos = en.value().cast<IntegerAttr>().getInt();
319e62a6956SRiver Riddle       Value value = adaptor.v1();
3201c81adf3SAart Bik       if (extPos >= v1Dim) {
3211c81adf3SAart Bik         extPos -= v1Dim;
3221c81adf3SAart Bik         value = adaptor.v2();
323b36aaeafSAart Bik       }
324e62a6956SRiver Riddle       Value extract =
3251c81adf3SAart Bik           extractOne(rewriter, lowering, loc, value, llvmType, rank, extPos);
3261c81adf3SAart Bik       insert = insertOne(rewriter, lowering, loc, insert, extract, llvmType,
3271c81adf3SAart Bik                          rank, insPos++);
3281c81adf3SAart Bik     }
3291c81adf3SAart Bik     rewriter.replaceOp(op, insert);
3301c81adf3SAart Bik     return matchSuccess();
331b36aaeafSAart Bik   }
332b36aaeafSAart Bik };
333b36aaeafSAart Bik 
334cd5dab8aSAart Bik class VectorExtractElementOpConversion : public LLVMOpLowering {
335cd5dab8aSAart Bik public:
336cd5dab8aSAart Bik   explicit VectorExtractElementOpConversion(MLIRContext *context,
337cd5dab8aSAart Bik                                             LLVMTypeConverter &typeConverter)
338cd5dab8aSAart Bik       : LLVMOpLowering(vector::ExtractElementOp::getOperationName(), context,
339cd5dab8aSAart Bik                        typeConverter) {}
340cd5dab8aSAart Bik 
341cd5dab8aSAart Bik   PatternMatchResult
342e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
343cd5dab8aSAart Bik                   ConversionPatternRewriter &rewriter) const override {
344cd5dab8aSAart Bik     auto adaptor = vector::ExtractElementOpOperandAdaptor(operands);
345cd5dab8aSAart Bik     auto extractEltOp = cast<vector::ExtractElementOp>(op);
346cd5dab8aSAart Bik     auto vectorType = extractEltOp.getVectorType();
347cd5dab8aSAart Bik     auto llvmType = lowering.convertType(vectorType.getElementType());
348cd5dab8aSAart Bik 
349cd5dab8aSAart Bik     // Bail if result type cannot be lowered.
350cd5dab8aSAart Bik     if (!llvmType)
351cd5dab8aSAart Bik       return matchFailure();
352cd5dab8aSAart Bik 
353cd5dab8aSAart Bik     rewriter.replaceOpWithNewOp<LLVM::ExtractElementOp>(
354cd5dab8aSAart Bik         op, llvmType, adaptor.vector(), adaptor.position());
355cd5dab8aSAart Bik     return matchSuccess();
356cd5dab8aSAart Bik   }
357cd5dab8aSAart Bik };
358cd5dab8aSAart Bik 
3599826fe5cSAart Bik class VectorExtractOpConversion : public LLVMOpLowering {
3605c0c51a9SNicolas Vasilache public:
3619826fe5cSAart Bik   explicit VectorExtractOpConversion(MLIRContext *context,
3625c0c51a9SNicolas Vasilache                                      LLVMTypeConverter &typeConverter)
363d37f2725SAart Bik       : LLVMOpLowering(vector::ExtractOp::getOperationName(), context,
3645c0c51a9SNicolas Vasilache                        typeConverter) {}
3655c0c51a9SNicolas Vasilache 
3665c0c51a9SNicolas Vasilache   PatternMatchResult
367e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
3685c0c51a9SNicolas Vasilache                   ConversionPatternRewriter &rewriter) const override {
3695c0c51a9SNicolas Vasilache     auto loc = op->getLoc();
370d37f2725SAart Bik     auto adaptor = vector::ExtractOpOperandAdaptor(operands);
371d37f2725SAart Bik     auto extractOp = cast<vector::ExtractOp>(op);
3729826fe5cSAart Bik     auto vectorType = extractOp.getVectorType();
3732bdf33ccSRiver Riddle     auto resultType = extractOp.getResult().getType();
3745c0c51a9SNicolas Vasilache     auto llvmResultType = lowering.convertType(resultType);
3755c0c51a9SNicolas Vasilache     auto positionArrayAttr = extractOp.position();
3769826fe5cSAart Bik 
3779826fe5cSAart Bik     // Bail if result type cannot be lowered.
3789826fe5cSAart Bik     if (!llvmResultType)
3799826fe5cSAart Bik       return matchFailure();
3809826fe5cSAart Bik 
3815c0c51a9SNicolas Vasilache     // One-shot extraction of vector from array (only requires extractvalue).
3825c0c51a9SNicolas Vasilache     if (resultType.isa<VectorType>()) {
383e62a6956SRiver Riddle       Value extracted = rewriter.create<LLVM::ExtractValueOp>(
3845c0c51a9SNicolas Vasilache           loc, llvmResultType, adaptor.vector(), positionArrayAttr);
3855c0c51a9SNicolas Vasilache       rewriter.replaceOp(op, extracted);
3865c0c51a9SNicolas Vasilache       return matchSuccess();
3875c0c51a9SNicolas Vasilache     }
3885c0c51a9SNicolas Vasilache 
3899826fe5cSAart Bik     // Potential extraction of 1-D vector from array.
3905c0c51a9SNicolas Vasilache     auto *context = op->getContext();
391e62a6956SRiver Riddle     Value extracted = adaptor.vector();
3925c0c51a9SNicolas Vasilache     auto positionAttrs = positionArrayAttr.getValue();
3935c0c51a9SNicolas Vasilache     if (positionAttrs.size() > 1) {
3949826fe5cSAart Bik       auto oneDVectorType = reducedVectorTypeBack(vectorType);
3955c0c51a9SNicolas Vasilache       auto nMinusOnePositionAttrs =
3965c0c51a9SNicolas Vasilache           ArrayAttr::get(positionAttrs.drop_back(), context);
3975c0c51a9SNicolas Vasilache       extracted = rewriter.create<LLVM::ExtractValueOp>(
3985c0c51a9SNicolas Vasilache           loc, lowering.convertType(oneDVectorType), extracted,
3995c0c51a9SNicolas Vasilache           nMinusOnePositionAttrs);
4005c0c51a9SNicolas Vasilache     }
4015c0c51a9SNicolas Vasilache 
4025c0c51a9SNicolas Vasilache     // Remaining extraction of element from 1-D LLVM vector
4035c0c51a9SNicolas Vasilache     auto position = positionAttrs.back().cast<IntegerAttr>();
4041d47564aSAart Bik     auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect());
4051d47564aSAart Bik     auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position);
4065c0c51a9SNicolas Vasilache     extracted =
4075c0c51a9SNicolas Vasilache         rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant);
4085c0c51a9SNicolas Vasilache     rewriter.replaceOp(op, extracted);
4095c0c51a9SNicolas Vasilache 
4105c0c51a9SNicolas Vasilache     return matchSuccess();
4115c0c51a9SNicolas Vasilache   }
4125c0c51a9SNicolas Vasilache };
4135c0c51a9SNicolas Vasilache 
414cd5dab8aSAart Bik class VectorInsertElementOpConversion : public LLVMOpLowering {
415cd5dab8aSAart Bik public:
416cd5dab8aSAart Bik   explicit VectorInsertElementOpConversion(MLIRContext *context,
417cd5dab8aSAart Bik                                            LLVMTypeConverter &typeConverter)
418cd5dab8aSAart Bik       : LLVMOpLowering(vector::InsertElementOp::getOperationName(), context,
419cd5dab8aSAart Bik                        typeConverter) {}
420cd5dab8aSAart Bik 
421cd5dab8aSAart Bik   PatternMatchResult
422e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
423cd5dab8aSAart Bik                   ConversionPatternRewriter &rewriter) const override {
424cd5dab8aSAart Bik     auto adaptor = vector::InsertElementOpOperandAdaptor(operands);
425cd5dab8aSAart Bik     auto insertEltOp = cast<vector::InsertElementOp>(op);
426cd5dab8aSAart Bik     auto vectorType = insertEltOp.getDestVectorType();
427cd5dab8aSAart Bik     auto llvmType = lowering.convertType(vectorType);
428cd5dab8aSAart Bik 
429cd5dab8aSAart Bik     // Bail if result type cannot be lowered.
430cd5dab8aSAart Bik     if (!llvmType)
431cd5dab8aSAart Bik       return matchFailure();
432cd5dab8aSAart Bik 
433cd5dab8aSAart Bik     rewriter.replaceOpWithNewOp<LLVM::InsertElementOp>(
434cd5dab8aSAart Bik         op, llvmType, adaptor.dest(), adaptor.source(), adaptor.position());
435cd5dab8aSAart Bik     return matchSuccess();
436cd5dab8aSAart Bik   }
437cd5dab8aSAart Bik };
438cd5dab8aSAart Bik 
4399826fe5cSAart Bik class VectorInsertOpConversion : public LLVMOpLowering {
4409826fe5cSAart Bik public:
4419826fe5cSAart Bik   explicit VectorInsertOpConversion(MLIRContext *context,
4429826fe5cSAart Bik                                     LLVMTypeConverter &typeConverter)
4439826fe5cSAart Bik       : LLVMOpLowering(vector::InsertOp::getOperationName(), context,
4449826fe5cSAart Bik                        typeConverter) {}
4459826fe5cSAart Bik 
4469826fe5cSAart Bik   PatternMatchResult
447e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
4489826fe5cSAart Bik                   ConversionPatternRewriter &rewriter) const override {
4499826fe5cSAart Bik     auto loc = op->getLoc();
4509826fe5cSAart Bik     auto adaptor = vector::InsertOpOperandAdaptor(operands);
4519826fe5cSAart Bik     auto insertOp = cast<vector::InsertOp>(op);
4529826fe5cSAart Bik     auto sourceType = insertOp.getSourceType();
4539826fe5cSAart Bik     auto destVectorType = insertOp.getDestVectorType();
4549826fe5cSAart Bik     auto llvmResultType = lowering.convertType(destVectorType);
4559826fe5cSAart Bik     auto positionArrayAttr = insertOp.position();
4569826fe5cSAart Bik 
4579826fe5cSAart Bik     // Bail if result type cannot be lowered.
4589826fe5cSAart Bik     if (!llvmResultType)
4599826fe5cSAart Bik       return matchFailure();
4609826fe5cSAart Bik 
4619826fe5cSAart Bik     // One-shot insertion of a vector into an array (only requires insertvalue).
4629826fe5cSAart Bik     if (sourceType.isa<VectorType>()) {
463e62a6956SRiver Riddle       Value inserted = rewriter.create<LLVM::InsertValueOp>(
4649826fe5cSAart Bik           loc, llvmResultType, adaptor.dest(), adaptor.source(),
4659826fe5cSAart Bik           positionArrayAttr);
4669826fe5cSAart Bik       rewriter.replaceOp(op, inserted);
4679826fe5cSAart Bik       return matchSuccess();
4689826fe5cSAart Bik     }
4699826fe5cSAart Bik 
4709826fe5cSAart Bik     // Potential extraction of 1-D vector from array.
4719826fe5cSAart Bik     auto *context = op->getContext();
472e62a6956SRiver Riddle     Value extracted = adaptor.dest();
4739826fe5cSAart Bik     auto positionAttrs = positionArrayAttr.getValue();
4749826fe5cSAart Bik     auto position = positionAttrs.back().cast<IntegerAttr>();
4759826fe5cSAart Bik     auto oneDVectorType = destVectorType;
4769826fe5cSAart Bik     if (positionAttrs.size() > 1) {
4779826fe5cSAart Bik       oneDVectorType = reducedVectorTypeBack(destVectorType);
4789826fe5cSAart Bik       auto nMinusOnePositionAttrs =
4799826fe5cSAart Bik           ArrayAttr::get(positionAttrs.drop_back(), context);
4809826fe5cSAart Bik       extracted = rewriter.create<LLVM::ExtractValueOp>(
4819826fe5cSAart Bik           loc, lowering.convertType(oneDVectorType), extracted,
4829826fe5cSAart Bik           nMinusOnePositionAttrs);
4839826fe5cSAart Bik     }
4849826fe5cSAart Bik 
4859826fe5cSAart Bik     // Insertion of an element into a 1-D LLVM vector.
4861d47564aSAart Bik     auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect());
4871d47564aSAart Bik     auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position);
488e62a6956SRiver Riddle     Value inserted = rewriter.create<LLVM::InsertElementOp>(
4899826fe5cSAart Bik         loc, lowering.convertType(oneDVectorType), extracted, adaptor.source(),
4909826fe5cSAart Bik         constant);
4919826fe5cSAart Bik 
4929826fe5cSAart Bik     // Potential insertion of resulting 1-D vector into array.
4939826fe5cSAart Bik     if (positionAttrs.size() > 1) {
4949826fe5cSAart Bik       auto nMinusOnePositionAttrs =
4959826fe5cSAart Bik           ArrayAttr::get(positionAttrs.drop_back(), context);
4969826fe5cSAart Bik       inserted = rewriter.create<LLVM::InsertValueOp>(loc, llvmResultType,
4979826fe5cSAart Bik                                                       adaptor.dest(), inserted,
4989826fe5cSAart Bik                                                       nMinusOnePositionAttrs);
4999826fe5cSAart Bik     }
5009826fe5cSAart Bik 
5019826fe5cSAart Bik     rewriter.replaceOp(op, inserted);
5029826fe5cSAart Bik     return matchSuccess();
5039826fe5cSAart Bik   }
5049826fe5cSAart Bik };
5059826fe5cSAart Bik 
5062d515e49SNicolas Vasilache // When ranks are different, InsertStridedSlice needs to extract a properly
5072d515e49SNicolas Vasilache // ranked vector from the destination vector into which to insert. This pattern
5082d515e49SNicolas Vasilache // only takes care of this part and forwards the rest of the conversion to
5092d515e49SNicolas Vasilache // another pattern that converts InsertStridedSlice for operands of the same
5102d515e49SNicolas Vasilache // rank.
5112d515e49SNicolas Vasilache //
5122d515e49SNicolas Vasilache // RewritePattern for InsertStridedSliceOp where source and destination vectors
5132d515e49SNicolas Vasilache // have different ranks. In this case:
5142d515e49SNicolas Vasilache //   1. the proper subvector is extracted from the destination vector
5152d515e49SNicolas Vasilache //   2. a new InsertStridedSlice op is created to insert the source in the
5162d515e49SNicolas Vasilache //   destination subvector
5172d515e49SNicolas Vasilache //   3. the destination subvector is inserted back in the proper place
5182d515e49SNicolas Vasilache //   4. the op is replaced by the result of step 3.
5192d515e49SNicolas Vasilache // The new InsertStridedSlice from step 2. will be picked up by a
5202d515e49SNicolas Vasilache // `VectorInsertStridedSliceOpSameRankRewritePattern`.
5212d515e49SNicolas Vasilache class VectorInsertStridedSliceOpDifferentRankRewritePattern
5222d515e49SNicolas Vasilache     : public OpRewritePattern<InsertStridedSliceOp> {
5232d515e49SNicolas Vasilache public:
5242d515e49SNicolas Vasilache   using OpRewritePattern<InsertStridedSliceOp>::OpRewritePattern;
5252d515e49SNicolas Vasilache 
5262d515e49SNicolas Vasilache   PatternMatchResult matchAndRewrite(InsertStridedSliceOp op,
5272d515e49SNicolas Vasilache                                      PatternRewriter &rewriter) const override {
5282d515e49SNicolas Vasilache     auto srcType = op.getSourceVectorType();
5292d515e49SNicolas Vasilache     auto dstType = op.getDestVectorType();
5302d515e49SNicolas Vasilache 
5312d515e49SNicolas Vasilache     if (op.offsets().getValue().empty())
5322d515e49SNicolas Vasilache       return matchFailure();
5332d515e49SNicolas Vasilache 
5342d515e49SNicolas Vasilache     auto loc = op.getLoc();
5352d515e49SNicolas Vasilache     int64_t rankDiff = dstType.getRank() - srcType.getRank();
5362d515e49SNicolas Vasilache     assert(rankDiff >= 0);
5372d515e49SNicolas Vasilache     if (rankDiff == 0)
5382d515e49SNicolas Vasilache       return matchFailure();
5392d515e49SNicolas Vasilache 
5402d515e49SNicolas Vasilache     int64_t rankRest = dstType.getRank() - rankDiff;
5412d515e49SNicolas Vasilache     // Extract / insert the subvector of matching rank and InsertStridedSlice
5422d515e49SNicolas Vasilache     // on it.
5432d515e49SNicolas Vasilache     Value extracted =
5442d515e49SNicolas Vasilache         rewriter.create<ExtractOp>(loc, op.dest(),
5452d515e49SNicolas Vasilache                                    getI64SubArray(op.offsets(), /*dropFront=*/0,
5462d515e49SNicolas Vasilache                                                   /*dropFront=*/rankRest));
5472d515e49SNicolas Vasilache     // A different pattern will kick in for InsertStridedSlice with matching
5482d515e49SNicolas Vasilache     // ranks.
5492d515e49SNicolas Vasilache     auto stridedSliceInnerOp = rewriter.create<InsertStridedSliceOp>(
5502d515e49SNicolas Vasilache         loc, op.source(), extracted,
5512d515e49SNicolas Vasilache         getI64SubArray(op.offsets(), /*dropFront=*/rankDiff),
5522d515e49SNicolas Vasilache         getI64SubArray(op.strides(), /*dropFront=*/rankDiff));
5532d515e49SNicolas Vasilache     rewriter.replaceOpWithNewOp<InsertOp>(
5542d515e49SNicolas Vasilache         op, stridedSliceInnerOp.getResult(), op.dest(),
5552d515e49SNicolas Vasilache         getI64SubArray(op.offsets(), /*dropFront=*/0,
5562d515e49SNicolas Vasilache                        /*dropFront=*/rankRest));
5572d515e49SNicolas Vasilache     return matchSuccess();
5582d515e49SNicolas Vasilache   }
5592d515e49SNicolas Vasilache };
5602d515e49SNicolas Vasilache 
5612d515e49SNicolas Vasilache // RewritePattern for InsertStridedSliceOp where source and destination vectors
5622d515e49SNicolas Vasilache // have the same rank. In this case, we reduce
5632d515e49SNicolas Vasilache //   1. the proper subvector is extracted from the destination vector
5642d515e49SNicolas Vasilache //   2. a new InsertStridedSlice op is created to insert the source in the
5652d515e49SNicolas Vasilache //   destination subvector
5662d515e49SNicolas Vasilache //   3. the destination subvector is inserted back in the proper place
5672d515e49SNicolas Vasilache //   4. the op is replaced by the result of step 3.
5682d515e49SNicolas Vasilache // The new InsertStridedSlice from step 2. will be picked up by a
5692d515e49SNicolas Vasilache // `VectorInsertStridedSliceOpSameRankRewritePattern`.
5702d515e49SNicolas Vasilache class VectorInsertStridedSliceOpSameRankRewritePattern
5712d515e49SNicolas Vasilache     : public OpRewritePattern<InsertStridedSliceOp> {
5722d515e49SNicolas Vasilache public:
5732d515e49SNicolas Vasilache   using OpRewritePattern<InsertStridedSliceOp>::OpRewritePattern;
5742d515e49SNicolas Vasilache 
5752d515e49SNicolas Vasilache   PatternMatchResult matchAndRewrite(InsertStridedSliceOp op,
5762d515e49SNicolas Vasilache                                      PatternRewriter &rewriter) const override {
5772d515e49SNicolas Vasilache     auto srcType = op.getSourceVectorType();
5782d515e49SNicolas Vasilache     auto dstType = op.getDestVectorType();
5792d515e49SNicolas Vasilache 
5802d515e49SNicolas Vasilache     if (op.offsets().getValue().empty())
5812d515e49SNicolas Vasilache       return matchFailure();
5822d515e49SNicolas Vasilache 
5832d515e49SNicolas Vasilache     int64_t rankDiff = dstType.getRank() - srcType.getRank();
5842d515e49SNicolas Vasilache     assert(rankDiff >= 0);
5852d515e49SNicolas Vasilache     if (rankDiff != 0)
5862d515e49SNicolas Vasilache       return matchFailure();
5872d515e49SNicolas Vasilache 
5882d515e49SNicolas Vasilache     if (srcType == dstType) {
5892d515e49SNicolas Vasilache       rewriter.replaceOp(op, op.source());
5902d515e49SNicolas Vasilache       return matchSuccess();
5912d515e49SNicolas Vasilache     }
5922d515e49SNicolas Vasilache 
5932d515e49SNicolas Vasilache     int64_t offset =
5942d515e49SNicolas Vasilache         op.offsets().getValue().front().cast<IntegerAttr>().getInt();
5952d515e49SNicolas Vasilache     int64_t size = srcType.getShape().front();
5962d515e49SNicolas Vasilache     int64_t stride =
5972d515e49SNicolas Vasilache         op.strides().getValue().front().cast<IntegerAttr>().getInt();
5982d515e49SNicolas Vasilache 
5992d515e49SNicolas Vasilache     auto loc = op.getLoc();
6002d515e49SNicolas Vasilache     Value res = op.dest();
6012d515e49SNicolas Vasilache     // For each slice of the source vector along the most major dimension.
6022d515e49SNicolas Vasilache     for (int64_t off = offset, e = offset + size * stride, idx = 0; off < e;
6032d515e49SNicolas Vasilache          off += stride, ++idx) {
6042d515e49SNicolas Vasilache       // 1. extract the proper subvector (or element) from source
6052d515e49SNicolas Vasilache       Value extractedSource = extractOne(rewriter, loc, op.source(), idx);
6062d515e49SNicolas Vasilache       if (extractedSource.getType().isa<VectorType>()) {
6072d515e49SNicolas Vasilache         // 2. If we have a vector, extract the proper subvector from destination
6082d515e49SNicolas Vasilache         // Otherwise we are at the element level and no need to recurse.
6092d515e49SNicolas Vasilache         Value extractedDest = extractOne(rewriter, loc, op.dest(), off);
6102d515e49SNicolas Vasilache         // 3. Reduce the problem to lowering a new InsertStridedSlice op with
6112d515e49SNicolas Vasilache         // smaller rank.
6122d515e49SNicolas Vasilache         InsertStridedSliceOp insertStridedSliceOp =
6132d515e49SNicolas Vasilache             rewriter.create<InsertStridedSliceOp>(
6142d515e49SNicolas Vasilache                 loc, extractedSource, extractedDest,
6152d515e49SNicolas Vasilache                 getI64SubArray(op.offsets(), /* dropFront=*/1),
6162d515e49SNicolas Vasilache                 getI64SubArray(op.strides(), /* dropFront=*/1));
6172d515e49SNicolas Vasilache         // Call matchAndRewrite recursively from within the pattern. This
6182d515e49SNicolas Vasilache         // circumvents the current limitation that a given pattern cannot
6192d515e49SNicolas Vasilache         // be called multiple times by the PatternRewrite infrastructure (to
6202d515e49SNicolas Vasilache         // avoid infinite recursion, but in this case, infinite recursion
6212d515e49SNicolas Vasilache         // cannot happen because the rank is strictly decreasing).
6222d515e49SNicolas Vasilache         // TODO(rriddle, nicolasvasilache) Implement something like a hook for
6232d515e49SNicolas Vasilache         // a potential function that must decrease and allow the same pattern
6242d515e49SNicolas Vasilache         // multiple times.
6252d515e49SNicolas Vasilache         auto success = matchAndRewrite(insertStridedSliceOp, rewriter);
6262d515e49SNicolas Vasilache         (void)success;
6272d515e49SNicolas Vasilache         assert(success && "Unexpected failure");
6282d515e49SNicolas Vasilache         extractedSource = insertStridedSliceOp;
6292d515e49SNicolas Vasilache       }
6302d515e49SNicolas Vasilache       // 4. Insert the extractedSource into the res vector.
6312d515e49SNicolas Vasilache       res = insertOne(rewriter, loc, extractedSource, res, off);
6322d515e49SNicolas Vasilache     }
6332d515e49SNicolas Vasilache 
6342d515e49SNicolas Vasilache     rewriter.replaceOp(op, res);
6352d515e49SNicolas Vasilache     return matchSuccess();
6362d515e49SNicolas Vasilache   }
6372d515e49SNicolas Vasilache };
6382d515e49SNicolas Vasilache 
6395c0c51a9SNicolas Vasilache class VectorOuterProductOpConversion : public LLVMOpLowering {
6405c0c51a9SNicolas Vasilache public:
6415c0c51a9SNicolas Vasilache   explicit VectorOuterProductOpConversion(MLIRContext *context,
6425c0c51a9SNicolas Vasilache                                           LLVMTypeConverter &typeConverter)
6435c0c51a9SNicolas Vasilache       : LLVMOpLowering(vector::OuterProductOp::getOperationName(), context,
6445c0c51a9SNicolas Vasilache                        typeConverter) {}
6455c0c51a9SNicolas Vasilache 
6465c0c51a9SNicolas Vasilache   PatternMatchResult
647e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
6485c0c51a9SNicolas Vasilache                   ConversionPatternRewriter &rewriter) const override {
6495c0c51a9SNicolas Vasilache     auto loc = op->getLoc();
6505c0c51a9SNicolas Vasilache     auto adaptor = vector::OuterProductOpOperandAdaptor(operands);
6515c0c51a9SNicolas Vasilache     auto *ctx = op->getContext();
6522bdf33ccSRiver Riddle     auto vLHS = adaptor.lhs().getType().cast<LLVM::LLVMType>();
6532bdf33ccSRiver Riddle     auto vRHS = adaptor.rhs().getType().cast<LLVM::LLVMType>();
6545c0c51a9SNicolas Vasilache     auto rankLHS = vLHS.getUnderlyingType()->getVectorNumElements();
6555c0c51a9SNicolas Vasilache     auto rankRHS = vRHS.getUnderlyingType()->getVectorNumElements();
6565c0c51a9SNicolas Vasilache     auto llvmArrayOfVectType = lowering.convertType(
6572bdf33ccSRiver Riddle         cast<vector::OuterProductOp>(op).getResult().getType());
658e62a6956SRiver Riddle     Value desc = rewriter.create<LLVM::UndefOp>(loc, llvmArrayOfVectType);
659e62a6956SRiver Riddle     Value a = adaptor.lhs(), b = adaptor.rhs();
660e62a6956SRiver Riddle     Value acc = adaptor.acc().empty() ? nullptr : adaptor.acc().front();
661e62a6956SRiver Riddle     SmallVector<Value, 8> lhs, accs;
6625c0c51a9SNicolas Vasilache     lhs.reserve(rankLHS);
6635c0c51a9SNicolas Vasilache     accs.reserve(rankLHS);
6645c0c51a9SNicolas Vasilache     for (unsigned d = 0, e = rankLHS; d < e; ++d) {
6655c0c51a9SNicolas Vasilache       // shufflevector explicitly requires i32.
6665c0c51a9SNicolas Vasilache       auto attr = rewriter.getI32IntegerAttr(d);
6675c0c51a9SNicolas Vasilache       SmallVector<Attribute, 4> bcastAttr(rankRHS, attr);
6685c0c51a9SNicolas Vasilache       auto bcastArrayAttr = ArrayAttr::get(bcastAttr, ctx);
669e62a6956SRiver Riddle       Value aD = nullptr, accD = nullptr;
6705c0c51a9SNicolas Vasilache       // 1. Broadcast the element a[d] into vector aD.
6715c0c51a9SNicolas Vasilache       aD = rewriter.create<LLVM::ShuffleVectorOp>(loc, a, a, bcastArrayAttr);
6725c0c51a9SNicolas Vasilache       // 2. If acc is present, extract 1-d vector acc[d] into accD.
6735c0c51a9SNicolas Vasilache       if (acc)
6745c0c51a9SNicolas Vasilache         accD = rewriter.create<LLVM::ExtractValueOp>(
6755c0c51a9SNicolas Vasilache             loc, vRHS, acc, rewriter.getI64ArrayAttr(d));
6765c0c51a9SNicolas Vasilache       // 3. Compute aD outer b (plus accD, if relevant).
677e62a6956SRiver Riddle       Value aOuterbD =
6785c0c51a9SNicolas Vasilache           accD ? rewriter.create<LLVM::FMulAddOp>(loc, vRHS, aD, b, accD)
6795c0c51a9SNicolas Vasilache                      .getResult()
6805c0c51a9SNicolas Vasilache                : rewriter.create<LLVM::FMulOp>(loc, aD, b).getResult();
6815c0c51a9SNicolas Vasilache       // 4. Insert as value `d` in the descriptor.
6825c0c51a9SNicolas Vasilache       desc = rewriter.create<LLVM::InsertValueOp>(loc, llvmArrayOfVectType,
6835c0c51a9SNicolas Vasilache                                                   desc, aOuterbD,
6845c0c51a9SNicolas Vasilache                                                   rewriter.getI64ArrayAttr(d));
6855c0c51a9SNicolas Vasilache     }
6865c0c51a9SNicolas Vasilache     rewriter.replaceOp(op, desc);
6875c0c51a9SNicolas Vasilache     return matchSuccess();
6885c0c51a9SNicolas Vasilache   }
6895c0c51a9SNicolas Vasilache };
6905c0c51a9SNicolas Vasilache 
6915c0c51a9SNicolas Vasilache class VectorTypeCastOpConversion : public LLVMOpLowering {
6925c0c51a9SNicolas Vasilache public:
6935c0c51a9SNicolas Vasilache   explicit VectorTypeCastOpConversion(MLIRContext *context,
6945c0c51a9SNicolas Vasilache                                       LLVMTypeConverter &typeConverter)
6955c0c51a9SNicolas Vasilache       : LLVMOpLowering(vector::TypeCastOp::getOperationName(), context,
6965c0c51a9SNicolas Vasilache                        typeConverter) {}
6975c0c51a9SNicolas Vasilache 
6985c0c51a9SNicolas Vasilache   PatternMatchResult
699e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
7005c0c51a9SNicolas Vasilache                   ConversionPatternRewriter &rewriter) const override {
7015c0c51a9SNicolas Vasilache     auto loc = op->getLoc();
7025c0c51a9SNicolas Vasilache     vector::TypeCastOp castOp = cast<vector::TypeCastOp>(op);
7035c0c51a9SNicolas Vasilache     MemRefType sourceMemRefType =
7042bdf33ccSRiver Riddle         castOp.getOperand().getType().cast<MemRefType>();
7055c0c51a9SNicolas Vasilache     MemRefType targetMemRefType =
7062bdf33ccSRiver Riddle         castOp.getResult().getType().cast<MemRefType>();
7075c0c51a9SNicolas Vasilache 
7085c0c51a9SNicolas Vasilache     // Only static shape casts supported atm.
7095c0c51a9SNicolas Vasilache     if (!sourceMemRefType.hasStaticShape() ||
7105c0c51a9SNicolas Vasilache         !targetMemRefType.hasStaticShape())
7115c0c51a9SNicolas Vasilache       return matchFailure();
7125c0c51a9SNicolas Vasilache 
7135c0c51a9SNicolas Vasilache     auto llvmSourceDescriptorTy =
7142bdf33ccSRiver Riddle         operands[0].getType().dyn_cast<LLVM::LLVMType>();
7155c0c51a9SNicolas Vasilache     if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy())
7165c0c51a9SNicolas Vasilache       return matchFailure();
7175c0c51a9SNicolas Vasilache     MemRefDescriptor sourceMemRef(operands[0]);
7185c0c51a9SNicolas Vasilache 
7195c0c51a9SNicolas Vasilache     auto llvmTargetDescriptorTy = lowering.convertType(targetMemRefType)
7205c0c51a9SNicolas Vasilache                                       .dyn_cast_or_null<LLVM::LLVMType>();
7215c0c51a9SNicolas Vasilache     if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy())
7225c0c51a9SNicolas Vasilache       return matchFailure();
7235c0c51a9SNicolas Vasilache 
7245c0c51a9SNicolas Vasilache     int64_t offset;
7255c0c51a9SNicolas Vasilache     SmallVector<int64_t, 4> strides;
7265c0c51a9SNicolas Vasilache     auto successStrides =
7275c0c51a9SNicolas Vasilache         getStridesAndOffset(sourceMemRefType, strides, offset);
7285c0c51a9SNicolas Vasilache     bool isContiguous = (strides.back() == 1);
7295c0c51a9SNicolas Vasilache     if (isContiguous) {
7305c0c51a9SNicolas Vasilache       auto sizes = sourceMemRefType.getShape();
7315c0c51a9SNicolas Vasilache       for (int index = 0, e = strides.size() - 2; index < e; ++index) {
7325c0c51a9SNicolas Vasilache         if (strides[index] != strides[index + 1] * sizes[index + 1]) {
7335c0c51a9SNicolas Vasilache           isContiguous = false;
7345c0c51a9SNicolas Vasilache           break;
7355c0c51a9SNicolas Vasilache         }
7365c0c51a9SNicolas Vasilache       }
7375c0c51a9SNicolas Vasilache     }
7385c0c51a9SNicolas Vasilache     // Only contiguous source tensors supported atm.
7395c0c51a9SNicolas Vasilache     if (failed(successStrides) || !isContiguous)
7405c0c51a9SNicolas Vasilache       return matchFailure();
7415c0c51a9SNicolas Vasilache 
7425c0c51a9SNicolas Vasilache     auto int64Ty = LLVM::LLVMType::getInt64Ty(lowering.getDialect());
7435c0c51a9SNicolas Vasilache 
7445c0c51a9SNicolas Vasilache     // Create descriptor.
7455c0c51a9SNicolas Vasilache     auto desc = MemRefDescriptor::undef(rewriter, loc, llvmTargetDescriptorTy);
7465c0c51a9SNicolas Vasilache     Type llvmTargetElementTy = desc.getElementType();
7475c0c51a9SNicolas Vasilache     // Set allocated ptr.
748e62a6956SRiver Riddle     Value allocated = sourceMemRef.allocatedPtr(rewriter, loc);
7495c0c51a9SNicolas Vasilache     allocated =
7505c0c51a9SNicolas Vasilache         rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, allocated);
7515c0c51a9SNicolas Vasilache     desc.setAllocatedPtr(rewriter, loc, allocated);
7525c0c51a9SNicolas Vasilache     // Set aligned ptr.
753e62a6956SRiver Riddle     Value ptr = sourceMemRef.alignedPtr(rewriter, loc);
7545c0c51a9SNicolas Vasilache     ptr = rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, ptr);
7555c0c51a9SNicolas Vasilache     desc.setAlignedPtr(rewriter, loc, ptr);
7565c0c51a9SNicolas Vasilache     // Fill offset 0.
7575c0c51a9SNicolas Vasilache     auto attr = rewriter.getIntegerAttr(rewriter.getIndexType(), 0);
7585c0c51a9SNicolas Vasilache     auto zero = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, attr);
7595c0c51a9SNicolas Vasilache     desc.setOffset(rewriter, loc, zero);
7605c0c51a9SNicolas Vasilache 
7615c0c51a9SNicolas Vasilache     // Fill size and stride descriptors in memref.
7625c0c51a9SNicolas Vasilache     for (auto indexedSize : llvm::enumerate(targetMemRefType.getShape())) {
7635c0c51a9SNicolas Vasilache       int64_t index = indexedSize.index();
7645c0c51a9SNicolas Vasilache       auto sizeAttr =
7655c0c51a9SNicolas Vasilache           rewriter.getIntegerAttr(rewriter.getIndexType(), indexedSize.value());
7665c0c51a9SNicolas Vasilache       auto size = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, sizeAttr);
7675c0c51a9SNicolas Vasilache       desc.setSize(rewriter, loc, index, size);
7685c0c51a9SNicolas Vasilache       auto strideAttr =
7695c0c51a9SNicolas Vasilache           rewriter.getIntegerAttr(rewriter.getIndexType(), strides[index]);
7705c0c51a9SNicolas Vasilache       auto stride = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, strideAttr);
7715c0c51a9SNicolas Vasilache       desc.setStride(rewriter, loc, index, stride);
7725c0c51a9SNicolas Vasilache     }
7735c0c51a9SNicolas Vasilache 
7745c0c51a9SNicolas Vasilache     rewriter.replaceOp(op, {desc});
7755c0c51a9SNicolas Vasilache     return matchSuccess();
7765c0c51a9SNicolas Vasilache   }
7775c0c51a9SNicolas Vasilache };
7785c0c51a9SNicolas Vasilache 
779d9b500d3SAart Bik class VectorPrintOpConversion : public LLVMOpLowering {
780d9b500d3SAart Bik public:
781d9b500d3SAart Bik   explicit VectorPrintOpConversion(MLIRContext *context,
782d9b500d3SAart Bik                                    LLVMTypeConverter &typeConverter)
783d9b500d3SAart Bik       : LLVMOpLowering(vector::PrintOp::getOperationName(), context,
784d9b500d3SAart Bik                        typeConverter) {}
785d9b500d3SAart Bik 
786d9b500d3SAart Bik   // Proof-of-concept lowering implementation that relies on a small
787d9b500d3SAart Bik   // runtime support library, which only needs to provide a few
788d9b500d3SAart Bik   // printing methods (single value for all data types, opening/closing
789d9b500d3SAart Bik   // bracket, comma, newline). The lowering fully unrolls a vector
790d9b500d3SAart Bik   // in terms of these elementary printing operations. The advantage
791d9b500d3SAart Bik   // of this approach is that the library can remain unaware of all
792d9b500d3SAart Bik   // low-level implementation details of vectors while still supporting
793d9b500d3SAart Bik   // output of any shaped and dimensioned vector. Due to full unrolling,
794d9b500d3SAart Bik   // this approach is less suited for very large vectors though.
795d9b500d3SAart Bik   //
796d9b500d3SAart Bik   // TODO(ajcbik): rely solely on libc in future? something else?
797d9b500d3SAart Bik   //
798d9b500d3SAart Bik   PatternMatchResult
799e62a6956SRiver Riddle   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
800d9b500d3SAart Bik                   ConversionPatternRewriter &rewriter) const override {
801d9b500d3SAart Bik     auto printOp = cast<vector::PrintOp>(op);
802d9b500d3SAart Bik     auto adaptor = vector::PrintOpOperandAdaptor(operands);
803d9b500d3SAart Bik     Type printType = printOp.getPrintType();
804d9b500d3SAart Bik 
805d9b500d3SAart Bik     if (lowering.convertType(printType) == nullptr)
806d9b500d3SAart Bik       return matchFailure();
807d9b500d3SAart Bik 
808d9b500d3SAart Bik     // Make sure element type has runtime support (currently just Float/Double).
809d9b500d3SAart Bik     VectorType vectorType = printType.dyn_cast<VectorType>();
810d9b500d3SAart Bik     Type eltType = vectorType ? vectorType.getElementType() : printType;
811d9b500d3SAart Bik     int64_t rank = vectorType ? vectorType.getRank() : 0;
812d9b500d3SAart Bik     Operation *printer;
813d9b500d3SAart Bik     if (eltType.isF32())
814d9b500d3SAart Bik       printer = getPrintFloat(op);
815d9b500d3SAart Bik     else if (eltType.isF64())
816d9b500d3SAart Bik       printer = getPrintDouble(op);
817d9b500d3SAart Bik     else
818d9b500d3SAart Bik       return matchFailure();
819d9b500d3SAart Bik 
820d9b500d3SAart Bik     // Unroll vector into elementary print calls.
821d9b500d3SAart Bik     emitRanks(rewriter, op, adaptor.source(), vectorType, printer, rank);
822d9b500d3SAart Bik     emitCall(rewriter, op->getLoc(), getPrintNewline(op));
823d9b500d3SAart Bik     rewriter.eraseOp(op);
824d9b500d3SAart Bik     return matchSuccess();
825d9b500d3SAart Bik   }
826d9b500d3SAart Bik 
827d9b500d3SAart Bik private:
828d9b500d3SAart Bik   void emitRanks(ConversionPatternRewriter &rewriter, Operation *op,
829e62a6956SRiver Riddle                  Value value, VectorType vectorType, Operation *printer,
830d9b500d3SAart Bik                  int64_t rank) const {
831d9b500d3SAart Bik     Location loc = op->getLoc();
832d9b500d3SAart Bik     if (rank == 0) {
833d9b500d3SAart Bik       emitCall(rewriter, loc, printer, value);
834d9b500d3SAart Bik       return;
835d9b500d3SAart Bik     }
836d9b500d3SAart Bik 
837d9b500d3SAart Bik     emitCall(rewriter, loc, getPrintOpen(op));
838d9b500d3SAart Bik     Operation *printComma = getPrintComma(op);
839d9b500d3SAart Bik     int64_t dim = vectorType.getDimSize(0);
840d9b500d3SAart Bik     for (int64_t d = 0; d < dim; ++d) {
841d9b500d3SAart Bik       auto reducedType =
842d9b500d3SAart Bik           rank > 1 ? reducedVectorTypeFront(vectorType) : nullptr;
843d9b500d3SAart Bik       auto llvmType = lowering.convertType(
844d9b500d3SAart Bik           rank > 1 ? reducedType : vectorType.getElementType());
845e62a6956SRiver Riddle       Value nestedVal =
846d9b500d3SAart Bik           extractOne(rewriter, lowering, loc, value, llvmType, rank, d);
847d9b500d3SAart Bik       emitRanks(rewriter, op, nestedVal, reducedType, printer, rank - 1);
848d9b500d3SAart Bik       if (d != dim - 1)
849d9b500d3SAart Bik         emitCall(rewriter, loc, printComma);
850d9b500d3SAart Bik     }
851d9b500d3SAart Bik     emitCall(rewriter, loc, getPrintClose(op));
852d9b500d3SAart Bik   }
853d9b500d3SAart Bik 
854d9b500d3SAart Bik   // Helper to emit a call.
855d9b500d3SAart Bik   static void emitCall(ConversionPatternRewriter &rewriter, Location loc,
856d9b500d3SAart Bik                        Operation *ref, ValueRange params = ValueRange()) {
857d9b500d3SAart Bik     rewriter.create<LLVM::CallOp>(loc, ArrayRef<Type>{},
858d9b500d3SAart Bik                                   rewriter.getSymbolRefAttr(ref), params);
859d9b500d3SAart Bik   }
860d9b500d3SAart Bik 
861d9b500d3SAart Bik   // Helper for printer method declaration (first hit) and lookup.
862d9b500d3SAart Bik   static Operation *getPrint(Operation *op, LLVM::LLVMDialect *dialect,
863d9b500d3SAart Bik                              StringRef name, ArrayRef<LLVM::LLVMType> params) {
864d9b500d3SAart Bik     auto module = op->getParentOfType<ModuleOp>();
865d9b500d3SAart Bik     auto func = module.lookupSymbol<LLVM::LLVMFuncOp>(name);
866d9b500d3SAart Bik     if (func)
867d9b500d3SAart Bik       return func;
868d9b500d3SAart Bik     OpBuilder moduleBuilder(module.getBodyRegion());
869d9b500d3SAart Bik     return moduleBuilder.create<LLVM::LLVMFuncOp>(
870d9b500d3SAart Bik         op->getLoc(), name,
871d9b500d3SAart Bik         LLVM::LLVMType::getFunctionTy(LLVM::LLVMType::getVoidTy(dialect),
872d9b500d3SAart Bik                                       params, /*isVarArg=*/false));
873d9b500d3SAart Bik   }
874d9b500d3SAart Bik 
875d9b500d3SAart Bik   // Helpers for method names.
876d9b500d3SAart Bik   Operation *getPrintFloat(Operation *op) const {
877d9b500d3SAart Bik     LLVM::LLVMDialect *dialect = lowering.getDialect();
878d9b500d3SAart Bik     return getPrint(op, dialect, "print_f32",
879d9b500d3SAart Bik                     LLVM::LLVMType::getFloatTy(dialect));
880d9b500d3SAart Bik   }
881d9b500d3SAart Bik   Operation *getPrintDouble(Operation *op) const {
882d9b500d3SAart Bik     LLVM::LLVMDialect *dialect = lowering.getDialect();
883d9b500d3SAart Bik     return getPrint(op, dialect, "print_f64",
884d9b500d3SAart Bik                     LLVM::LLVMType::getDoubleTy(dialect));
885d9b500d3SAart Bik   }
886d9b500d3SAart Bik   Operation *getPrintOpen(Operation *op) const {
887d9b500d3SAart Bik     return getPrint(op, lowering.getDialect(), "print_open", {});
888d9b500d3SAart Bik   }
889d9b500d3SAart Bik   Operation *getPrintClose(Operation *op) const {
890d9b500d3SAart Bik     return getPrint(op, lowering.getDialect(), "print_close", {});
891d9b500d3SAart Bik   }
892d9b500d3SAart Bik   Operation *getPrintComma(Operation *op) const {
893d9b500d3SAart Bik     return getPrint(op, lowering.getDialect(), "print_comma", {});
894d9b500d3SAart Bik   }
895d9b500d3SAart Bik   Operation *getPrintNewline(Operation *op) const {
896d9b500d3SAart Bik     return getPrint(op, lowering.getDialect(), "print_newline", {});
897d9b500d3SAart Bik   }
898d9b500d3SAart Bik };
899d9b500d3SAart Bik 
90065678d93SNicolas Vasilache /// Progressive lowering of StridedSliceOp to either:
90165678d93SNicolas Vasilache ///   1. extractelement + insertelement for the 1-D case
90265678d93SNicolas Vasilache ///   2. extract + optional strided_slice + insert for the n-D case.
9032d515e49SNicolas Vasilache class VectorStridedSliceOpConversion : public OpRewritePattern<StridedSliceOp> {
90465678d93SNicolas Vasilache public:
90565678d93SNicolas Vasilache   using OpRewritePattern<StridedSliceOp>::OpRewritePattern;
90665678d93SNicolas Vasilache 
90765678d93SNicolas Vasilache   PatternMatchResult matchAndRewrite(StridedSliceOp op,
90865678d93SNicolas Vasilache                                      PatternRewriter &rewriter) const override {
90965678d93SNicolas Vasilache     auto dstType = op.getResult().getType().cast<VectorType>();
91065678d93SNicolas Vasilache 
91165678d93SNicolas Vasilache     assert(!op.offsets().getValue().empty() && "Unexpected empty offsets");
91265678d93SNicolas Vasilache 
91365678d93SNicolas Vasilache     int64_t offset =
91465678d93SNicolas Vasilache         op.offsets().getValue().front().cast<IntegerAttr>().getInt();
91565678d93SNicolas Vasilache     int64_t size = op.sizes().getValue().front().cast<IntegerAttr>().getInt();
91665678d93SNicolas Vasilache     int64_t stride =
91765678d93SNicolas Vasilache         op.strides().getValue().front().cast<IntegerAttr>().getInt();
91865678d93SNicolas Vasilache 
91965678d93SNicolas Vasilache     auto loc = op.getLoc();
92065678d93SNicolas Vasilache     auto elemType = dstType.getElementType();
92165678d93SNicolas Vasilache     assert(elemType.isIntOrIndexOrFloat());
92265678d93SNicolas Vasilache     Value zero = rewriter.create<ConstantOp>(loc, elemType,
92365678d93SNicolas Vasilache                                              rewriter.getZeroAttr(elemType));
92465678d93SNicolas Vasilache     Value res = rewriter.create<SplatOp>(loc, dstType, zero);
92565678d93SNicolas Vasilache     for (int64_t off = offset, e = offset + size * stride, idx = 0; off < e;
92665678d93SNicolas Vasilache          off += stride, ++idx) {
92765678d93SNicolas Vasilache       Value extracted = extractOne(rewriter, loc, op.vector(), off);
92865678d93SNicolas Vasilache       if (op.offsets().getValue().size() > 1) {
92965678d93SNicolas Vasilache         StridedSliceOp stridedSliceOp = rewriter.create<StridedSliceOp>(
93065678d93SNicolas Vasilache             loc, extracted, getI64SubArray(op.offsets(), /* dropFront=*/1),
93165678d93SNicolas Vasilache             getI64SubArray(op.sizes(), /* dropFront=*/1),
93265678d93SNicolas Vasilache             getI64SubArray(op.strides(), /* dropFront=*/1));
93365678d93SNicolas Vasilache         // Call matchAndRewrite recursively from within the pattern. This
93465678d93SNicolas Vasilache         // circumvents the current limitation that a given pattern cannot
93565678d93SNicolas Vasilache         // be called multiple times by the PatternRewrite infrastructure (to
93665678d93SNicolas Vasilache         // avoid infinite recursion, but in this case, infinite recursion
93765678d93SNicolas Vasilache         // cannot happen because the rank is strictly decreasing).
93865678d93SNicolas Vasilache         // TODO(rriddle, nicolasvasilache) Implement something like a hook for
93965678d93SNicolas Vasilache         // a potential function that must decrease and allow the same pattern
94065678d93SNicolas Vasilache         // multiple times.
94165678d93SNicolas Vasilache         auto success = matchAndRewrite(stridedSliceOp, rewriter);
94265678d93SNicolas Vasilache         (void)success;
94365678d93SNicolas Vasilache         assert(success && "Unexpected failure");
94465678d93SNicolas Vasilache         extracted = stridedSliceOp;
94565678d93SNicolas Vasilache       }
94665678d93SNicolas Vasilache       res = insertOne(rewriter, loc, extracted, res, idx);
94765678d93SNicolas Vasilache     }
94865678d93SNicolas Vasilache     rewriter.replaceOp(op, {res});
94965678d93SNicolas Vasilache     return matchSuccess();
95065678d93SNicolas Vasilache   }
95165678d93SNicolas Vasilache };
95265678d93SNicolas Vasilache 
953df186507SBenjamin Kramer } // namespace
954df186507SBenjamin Kramer 
9555c0c51a9SNicolas Vasilache /// Populate the given list with patterns that convert from Vector to LLVM.
9565c0c51a9SNicolas Vasilache void mlir::populateVectorToLLVMConversionPatterns(
9575c0c51a9SNicolas Vasilache     LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
95865678d93SNicolas Vasilache   MLIRContext *ctx = converter.getDialect()->getContext();
9592d515e49SNicolas Vasilache   patterns.insert<VectorInsertStridedSliceOpDifferentRankRewritePattern,
9602d515e49SNicolas Vasilache                   VectorInsertStridedSliceOpSameRankRewritePattern,
9612d515e49SNicolas Vasilache                   VectorStridedSliceOpConversion>(ctx);
9621c81adf3SAart Bik   patterns.insert<VectorBroadcastOpConversion, VectorShuffleOpConversion,
963cd5dab8aSAart Bik                   VectorExtractElementOpConversion, VectorExtractOpConversion,
964cd5dab8aSAart Bik                   VectorInsertElementOpConversion, VectorInsertOpConversion,
965d9b500d3SAart Bik                   VectorOuterProductOpConversion, VectorTypeCastOpConversion,
96665678d93SNicolas Vasilache                   VectorPrintOpConversion>(ctx, converter);
9675c0c51a9SNicolas Vasilache }
9685c0c51a9SNicolas Vasilache 
9695c0c51a9SNicolas Vasilache namespace {
9705c0c51a9SNicolas Vasilache struct LowerVectorToLLVMPass : public ModulePass<LowerVectorToLLVMPass> {
9715c0c51a9SNicolas Vasilache   void runOnModule() override;
9725c0c51a9SNicolas Vasilache };
9735c0c51a9SNicolas Vasilache } // namespace
9745c0c51a9SNicolas Vasilache 
9755c0c51a9SNicolas Vasilache void LowerVectorToLLVMPass::runOnModule() {
9765c0c51a9SNicolas Vasilache   // Convert to the LLVM IR dialect using the converter defined above.
9775c0c51a9SNicolas Vasilache   OwningRewritePatternList patterns;
9785c0c51a9SNicolas Vasilache   LLVMTypeConverter converter(&getContext());
9795c0c51a9SNicolas Vasilache   populateVectorToLLVMConversionPatterns(converter, patterns);
9805c0c51a9SNicolas Vasilache   populateStdToLLVMConversionPatterns(converter, patterns);
9815c0c51a9SNicolas Vasilache 
9825c0c51a9SNicolas Vasilache   ConversionTarget target(getContext());
9835c0c51a9SNicolas Vasilache   target.addLegalDialect<LLVM::LLVMDialect>();
9845c0c51a9SNicolas Vasilache   target.addDynamicallyLegalOp<FuncOp>(
9855c0c51a9SNicolas Vasilache       [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); });
9865c0c51a9SNicolas Vasilache   if (failed(
9875c0c51a9SNicolas Vasilache           applyPartialConversion(getModule(), target, patterns, &converter))) {
9885c0c51a9SNicolas Vasilache     signalPassFailure();
9895c0c51a9SNicolas Vasilache   }
9905c0c51a9SNicolas Vasilache }
9915c0c51a9SNicolas Vasilache 
9925c0c51a9SNicolas Vasilache OpPassBase<ModuleOp> *mlir::createLowerVectorToLLVMPass() {
9935c0c51a9SNicolas Vasilache   return new LowerVectorToLLVMPass();
9945c0c51a9SNicolas Vasilache }
9955c0c51a9SNicolas Vasilache 
9965c0c51a9SNicolas Vasilache static PassRegistration<LowerVectorToLLVMPass>
9975c0c51a9SNicolas Vasilache     pass("convert-vector-to-llvm",
9985c0c51a9SNicolas Vasilache          "Lower the operations from the vector dialect into the LLVM dialect");
999