15c0c51a9SNicolas Vasilache //===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===// 25c0c51a9SNicolas Vasilache // 356222a06SMehdi Amini // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions. 456222a06SMehdi Amini // See https://llvm.org/LICENSE.txt for license information. 556222a06SMehdi Amini // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65c0c51a9SNicolas Vasilache // 756222a06SMehdi Amini //===----------------------------------------------------------------------===// 85c0c51a9SNicolas Vasilache 95c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 105c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h" 115c0c51a9SNicolas Vasilache #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 125c0c51a9SNicolas Vasilache #include "mlir/Dialect/LLVMIR/LLVMDialect.h" 135c0c51a9SNicolas Vasilache #include "mlir/Dialect/VectorOps/VectorOps.h" 145c0c51a9SNicolas Vasilache #include "mlir/IR/Attributes.h" 155c0c51a9SNicolas Vasilache #include "mlir/IR/Builders.h" 165c0c51a9SNicolas Vasilache #include "mlir/IR/MLIRContext.h" 175c0c51a9SNicolas Vasilache #include "mlir/IR/Module.h" 185c0c51a9SNicolas Vasilache #include "mlir/IR/Operation.h" 195c0c51a9SNicolas Vasilache #include "mlir/IR/PatternMatch.h" 205c0c51a9SNicolas Vasilache #include "mlir/IR/StandardTypes.h" 215c0c51a9SNicolas Vasilache #include "mlir/IR/Types.h" 225c0c51a9SNicolas Vasilache #include "mlir/Pass/Pass.h" 235c0c51a9SNicolas Vasilache #include "mlir/Pass/PassManager.h" 245c0c51a9SNicolas Vasilache #include "mlir/Transforms/DialectConversion.h" 255c0c51a9SNicolas Vasilache #include "mlir/Transforms/Passes.h" 265c0c51a9SNicolas Vasilache 275c0c51a9SNicolas Vasilache #include "llvm/IR/DerivedTypes.h" 285c0c51a9SNicolas Vasilache #include "llvm/IR/Module.h" 295c0c51a9SNicolas Vasilache #include "llvm/IR/Type.h" 305c0c51a9SNicolas Vasilache #include "llvm/Support/Allocator.h" 315c0c51a9SNicolas Vasilache #include "llvm/Support/ErrorHandling.h" 325c0c51a9SNicolas Vasilache 335c0c51a9SNicolas Vasilache using namespace mlir; 345c0c51a9SNicolas Vasilache 355c0c51a9SNicolas Vasilache template <typename T> 365c0c51a9SNicolas Vasilache static LLVM::LLVMType getPtrToElementType(T containerType, 375c0c51a9SNicolas Vasilache LLVMTypeConverter &lowering) { 385c0c51a9SNicolas Vasilache return lowering.convertType(containerType.getElementType()) 395c0c51a9SNicolas Vasilache .template cast<LLVM::LLVMType>() 405c0c51a9SNicolas Vasilache .getPointerTo(); 415c0c51a9SNicolas Vasilache } 425c0c51a9SNicolas Vasilache 439826fe5cSAart Bik // Helper to reduce vector type by one rank at front. 449826fe5cSAart Bik static VectorType reducedVectorTypeFront(VectorType tp) { 459826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 469826fe5cSAart Bik return VectorType::get(tp.getShape().drop_front(), tp.getElementType()); 479826fe5cSAart Bik } 489826fe5cSAart Bik 499826fe5cSAart Bik // Helper to reduce vector type by *all* but one rank at back. 509826fe5cSAart Bik static VectorType reducedVectorTypeBack(VectorType tp) { 519826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 529826fe5cSAart Bik return VectorType::get(tp.getShape().take_back(), tp.getElementType()); 539826fe5cSAart Bik } 549826fe5cSAart Bik 551c81adf3SAart Bik // Helper that picks the proper sequence for inserting. 56*e62a6956SRiver Riddle static Value insertOne(ConversionPatternRewriter &rewriter, 57*e62a6956SRiver Riddle LLVMTypeConverter &lowering, Location loc, Value val1, 58*e62a6956SRiver Riddle Value val2, Type llvmType, int64_t rank, int64_t pos) { 591c81adf3SAart Bik if (rank == 1) { 601c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 611c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 621c81adf3SAart Bik loc, lowering.convertType(idxType), 631c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 641c81adf3SAart Bik return rewriter.create<LLVM::InsertElementOp>(loc, llvmType, val1, val2, 651c81adf3SAart Bik constant); 661c81adf3SAart Bik } 671c81adf3SAart Bik return rewriter.create<LLVM::InsertValueOp>(loc, llvmType, val1, val2, 681c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 691c81adf3SAart Bik } 701c81adf3SAart Bik 711c81adf3SAart Bik // Helper that picks the proper sequence for extracting. 72*e62a6956SRiver Riddle static Value extractOne(ConversionPatternRewriter &rewriter, 73*e62a6956SRiver Riddle LLVMTypeConverter &lowering, Location loc, Value val, 74*e62a6956SRiver Riddle Type llvmType, int64_t rank, int64_t pos) { 751c81adf3SAart Bik if (rank == 1) { 761c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 771c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 781c81adf3SAart Bik loc, lowering.convertType(idxType), 791c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 801c81adf3SAart Bik return rewriter.create<LLVM::ExtractElementOp>(loc, llvmType, val, 811c81adf3SAart Bik constant); 821c81adf3SAart Bik } 831c81adf3SAart Bik return rewriter.create<LLVM::ExtractValueOp>(loc, llvmType, val, 841c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 851c81adf3SAart Bik } 861c81adf3SAart Bik 87b36aaeafSAart Bik class VectorBroadcastOpConversion : public LLVMOpLowering { 88b36aaeafSAart Bik public: 89b36aaeafSAart Bik explicit VectorBroadcastOpConversion(MLIRContext *context, 90b36aaeafSAart Bik LLVMTypeConverter &typeConverter) 91b36aaeafSAart Bik : LLVMOpLowering(vector::BroadcastOp::getOperationName(), context, 92b36aaeafSAart Bik typeConverter) {} 93b36aaeafSAart Bik 94b36aaeafSAart Bik PatternMatchResult 95*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 96b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const override { 97b36aaeafSAart Bik auto broadcastOp = cast<vector::BroadcastOp>(op); 98b36aaeafSAart Bik VectorType dstVectorType = broadcastOp.getVectorType(); 99b36aaeafSAart Bik if (lowering.convertType(dstVectorType) == nullptr) 100b36aaeafSAart Bik return matchFailure(); 101b36aaeafSAart Bik // Rewrite when the full vector type can be lowered (which 102b36aaeafSAart Bik // implies all 'reduced' types can be lowered too). 1031c81adf3SAart Bik auto adaptor = vector::BroadcastOpOperandAdaptor(operands); 104b36aaeafSAart Bik VectorType srcVectorType = 105b36aaeafSAart Bik broadcastOp.getSourceType().dyn_cast<VectorType>(); 106b36aaeafSAart Bik rewriter.replaceOp( 1071c81adf3SAart Bik op, expandRanks(adaptor.source(), // source value to be expanded 108b36aaeafSAart Bik op->getLoc(), // location of original broadcast 109b36aaeafSAart Bik srcVectorType, dstVectorType, rewriter)); 110b36aaeafSAart Bik return matchSuccess(); 111b36aaeafSAart Bik } 112b36aaeafSAart Bik 113b36aaeafSAart Bik private: 114b36aaeafSAart Bik // Expands the given source value over all the ranks, as defined 115b36aaeafSAart Bik // by the source and destination type (a null source type denotes 116b36aaeafSAart Bik // expansion from a scalar value into a vector). 117b36aaeafSAart Bik // 118b36aaeafSAart Bik // TODO(ajcbik): consider replacing this one-pattern lowering 119b36aaeafSAart Bik // with a two-pattern lowering using other vector 120b36aaeafSAart Bik // ops once all insert/extract/shuffle operations 121b36aaeafSAart Bik // are available with lowering implemention. 122b36aaeafSAart Bik // 123*e62a6956SRiver Riddle Value expandRanks(Value value, Location loc, VectorType srcVectorType, 124b36aaeafSAart Bik VectorType dstVectorType, 125b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 126b36aaeafSAart Bik assert((dstVectorType != nullptr) && "invalid result type in broadcast"); 127b36aaeafSAart Bik // Determine rank of source and destination. 128b36aaeafSAart Bik int64_t srcRank = srcVectorType ? srcVectorType.getRank() : 0; 129b36aaeafSAart Bik int64_t dstRank = dstVectorType.getRank(); 130b36aaeafSAart Bik int64_t curDim = dstVectorType.getDimSize(0); 131b36aaeafSAart Bik if (srcRank < dstRank) 132b36aaeafSAart Bik // Duplicate this rank. 133b36aaeafSAart Bik return duplicateOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 134b36aaeafSAart Bik curDim, rewriter); 135b36aaeafSAart Bik // If all trailing dimensions are the same, the broadcast consists of 136b36aaeafSAart Bik // simply passing through the source value and we are done. Otherwise, 137b36aaeafSAart Bik // any non-matching dimension forces a stretch along this rank. 138b36aaeafSAart Bik assert((srcVectorType != nullptr) && (srcRank > 0) && 139b36aaeafSAart Bik (srcRank == dstRank) && "invalid rank in broadcast"); 140b36aaeafSAart Bik for (int64_t r = 0; r < dstRank; r++) { 141b36aaeafSAart Bik if (srcVectorType.getDimSize(r) != dstVectorType.getDimSize(r)) { 142b36aaeafSAart Bik return stretchOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 143b36aaeafSAart Bik curDim, rewriter); 144b36aaeafSAart Bik } 145b36aaeafSAart Bik } 146b36aaeafSAart Bik return value; 147b36aaeafSAart Bik } 148b36aaeafSAart Bik 149b36aaeafSAart Bik // Picks the best way to duplicate a single rank. For the 1-D case, a 150b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion. For higher 151b36aaeafSAart Bik // dimensions, however, we need dim x insert-values on a new broadcast 152b36aaeafSAart Bik // with one less leading dimension, which will be lowered "recursively" 153b36aaeafSAart Bik // to matching LLVM IR. 154b36aaeafSAart Bik // For example: 155b36aaeafSAart Bik // v = broadcast s : f32 to vector<4x2xf32> 156b36aaeafSAart Bik // becomes: 157b36aaeafSAart Bik // x = broadcast s : f32 to vector<2xf32> 158b36aaeafSAart Bik // v = [x,x,x,x] 159b36aaeafSAart Bik // becomes: 160b36aaeafSAart Bik // x = [s,s] 161b36aaeafSAart Bik // v = [x,x,x,x] 162*e62a6956SRiver Riddle Value duplicateOneRank(Value value, Location loc, VectorType srcVectorType, 163*e62a6956SRiver Riddle VectorType dstVectorType, int64_t rank, int64_t dim, 164b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 165b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 166b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 167b36aaeafSAart Bik if (rank == 1) { 168*e62a6956SRiver Riddle Value undef = rewriter.create<LLVM::UndefOp>(loc, llvmType); 169*e62a6956SRiver Riddle Value expand = 1701c81adf3SAart Bik insertOne(rewriter, lowering, loc, undef, value, llvmType, rank, 0); 171b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 172b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 173b36aaeafSAart Bik loc, expand, undef, rewriter.getI32ArrayAttr(zeroValues)); 174b36aaeafSAart Bik } 175*e62a6956SRiver Riddle Value expand = expandRanks(value, loc, srcVectorType, 1769826fe5cSAart Bik reducedVectorTypeFront(dstVectorType), rewriter); 177*e62a6956SRiver Riddle Value result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 178b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 1791c81adf3SAart Bik result = 1801c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 181b36aaeafSAart Bik } 182b36aaeafSAart Bik return result; 183b36aaeafSAart Bik } 184b36aaeafSAart Bik 185b36aaeafSAart Bik // Picks the best way to stretch a single rank. For the 1-D case, a 186b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion when at 187b36aaeafSAart Bik // a stretch. Otherwise, every dimension needs to be expanded 188b36aaeafSAart Bik // individually and individually inserted in the resulting vector. 189b36aaeafSAart Bik // For example: 190b36aaeafSAart Bik // v = broadcast w : vector<4x1x2xf32> to vector<4x2x2xf32> 191b36aaeafSAart Bik // becomes: 192b36aaeafSAart Bik // a = broadcast w[0] : vector<1x2xf32> to vector<2x2xf32> 193b36aaeafSAart Bik // b = broadcast w[1] : vector<1x2xf32> to vector<2x2xf32> 194b36aaeafSAart Bik // c = broadcast w[2] : vector<1x2xf32> to vector<2x2xf32> 195b36aaeafSAart Bik // d = broadcast w[3] : vector<1x2xf32> to vector<2x2xf32> 196b36aaeafSAart Bik // v = [a,b,c,d] 197b36aaeafSAart Bik // becomes: 198b36aaeafSAart Bik // x = broadcast w[0][0] : vector<2xf32> to vector <2x2xf32> 199b36aaeafSAart Bik // y = broadcast w[1][0] : vector<2xf32> to vector <2x2xf32> 200b36aaeafSAart Bik // a = [x, y] 201b36aaeafSAart Bik // etc. 202*e62a6956SRiver Riddle Value stretchOneRank(Value value, Location loc, VectorType srcVectorType, 203*e62a6956SRiver Riddle VectorType dstVectorType, int64_t rank, int64_t dim, 204b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 205b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 206b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 207*e62a6956SRiver Riddle Value result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 208b36aaeafSAart Bik bool atStretch = dim != srcVectorType.getDimSize(0); 209b36aaeafSAart Bik if (rank == 1) { 2101c81adf3SAart Bik assert(atStretch); 211b36aaeafSAart Bik Type redLlvmType = lowering.convertType(dstVectorType.getElementType()); 212*e62a6956SRiver Riddle Value one = 2131c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, 0); 214*e62a6956SRiver Riddle Value expand = 2151c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, one, llvmType, rank, 0); 216b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 217b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 218b36aaeafSAart Bik loc, expand, result, rewriter.getI32ArrayAttr(zeroValues)); 219b36aaeafSAart Bik } 2209826fe5cSAart Bik VectorType redSrcType = reducedVectorTypeFront(srcVectorType); 2219826fe5cSAart Bik VectorType redDstType = reducedVectorTypeFront(dstVectorType); 222b36aaeafSAart Bik Type redLlvmType = lowering.convertType(redSrcType); 223b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 224b36aaeafSAart Bik int64_t pos = atStretch ? 0 : d; 225*e62a6956SRiver Riddle Value one = 2261c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, pos); 227*e62a6956SRiver Riddle Value expand = expandRanks(one, loc, redSrcType, redDstType, rewriter); 2281c81adf3SAart Bik result = 2291c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 230b36aaeafSAart Bik } 231b36aaeafSAart Bik return result; 232b36aaeafSAart Bik } 2331c81adf3SAart Bik }; 234b36aaeafSAart Bik 2351c81adf3SAart Bik class VectorShuffleOpConversion : public LLVMOpLowering { 2361c81adf3SAart Bik public: 2371c81adf3SAart Bik explicit VectorShuffleOpConversion(MLIRContext *context, 2381c81adf3SAart Bik LLVMTypeConverter &typeConverter) 2391c81adf3SAart Bik : LLVMOpLowering(vector::ShuffleOp::getOperationName(), context, 2401c81adf3SAart Bik typeConverter) {} 2411c81adf3SAart Bik 2421c81adf3SAart Bik PatternMatchResult 243*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 2441c81adf3SAart Bik ConversionPatternRewriter &rewriter) const override { 2451c81adf3SAart Bik auto loc = op->getLoc(); 2461c81adf3SAart Bik auto adaptor = vector::ShuffleOpOperandAdaptor(operands); 2471c81adf3SAart Bik auto shuffleOp = cast<vector::ShuffleOp>(op); 2481c81adf3SAart Bik auto v1Type = shuffleOp.getV1VectorType(); 2491c81adf3SAart Bik auto v2Type = shuffleOp.getV2VectorType(); 2501c81adf3SAart Bik auto vectorType = shuffleOp.getVectorType(); 2511c81adf3SAart Bik Type llvmType = lowering.convertType(vectorType); 2521c81adf3SAart Bik auto maskArrayAttr = shuffleOp.mask(); 2531c81adf3SAart Bik 2541c81adf3SAart Bik // Bail if result type cannot be lowered. 2551c81adf3SAart Bik if (!llvmType) 2561c81adf3SAart Bik return matchFailure(); 2571c81adf3SAart Bik 2581c81adf3SAart Bik // Get rank and dimension sizes. 2591c81adf3SAart Bik int64_t rank = vectorType.getRank(); 2601c81adf3SAart Bik assert(v1Type.getRank() == rank); 2611c81adf3SAart Bik assert(v2Type.getRank() == rank); 2621c81adf3SAart Bik int64_t v1Dim = v1Type.getDimSize(0); 2631c81adf3SAart Bik 2641c81adf3SAart Bik // For rank 1, where both operands have *exactly* the same vector type, 2651c81adf3SAart Bik // there is direct shuffle support in LLVM. Use it! 2661c81adf3SAart Bik if (rank == 1 && v1Type == v2Type) { 267*e62a6956SRiver Riddle Value shuffle = rewriter.create<LLVM::ShuffleVectorOp>( 2681c81adf3SAart Bik loc, adaptor.v1(), adaptor.v2(), maskArrayAttr); 2691c81adf3SAart Bik rewriter.replaceOp(op, shuffle); 2701c81adf3SAart Bik return matchSuccess(); 271b36aaeafSAart Bik } 272b36aaeafSAart Bik 2731c81adf3SAart Bik // For all other cases, insert the individual values individually. 274*e62a6956SRiver Riddle Value insert = rewriter.create<LLVM::UndefOp>(loc, llvmType); 2751c81adf3SAart Bik int64_t insPos = 0; 2761c81adf3SAart Bik for (auto en : llvm::enumerate(maskArrayAttr)) { 2771c81adf3SAart Bik int64_t extPos = en.value().cast<IntegerAttr>().getInt(); 278*e62a6956SRiver Riddle Value value = adaptor.v1(); 2791c81adf3SAart Bik if (extPos >= v1Dim) { 2801c81adf3SAart Bik extPos -= v1Dim; 2811c81adf3SAart Bik value = adaptor.v2(); 282b36aaeafSAart Bik } 283*e62a6956SRiver Riddle Value extract = 2841c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, extPos); 2851c81adf3SAart Bik insert = insertOne(rewriter, lowering, loc, insert, extract, llvmType, 2861c81adf3SAart Bik rank, insPos++); 2871c81adf3SAart Bik } 2881c81adf3SAart Bik rewriter.replaceOp(op, insert); 2891c81adf3SAart Bik return matchSuccess(); 290b36aaeafSAart Bik } 291b36aaeafSAart Bik }; 292b36aaeafSAart Bik 293cd5dab8aSAart Bik class VectorExtractElementOpConversion : public LLVMOpLowering { 294cd5dab8aSAart Bik public: 295cd5dab8aSAart Bik explicit VectorExtractElementOpConversion(MLIRContext *context, 296cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 297cd5dab8aSAart Bik : LLVMOpLowering(vector::ExtractElementOp::getOperationName(), context, 298cd5dab8aSAart Bik typeConverter) {} 299cd5dab8aSAart Bik 300cd5dab8aSAart Bik PatternMatchResult 301*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 302cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 303cd5dab8aSAart Bik auto adaptor = vector::ExtractElementOpOperandAdaptor(operands); 304cd5dab8aSAart Bik auto extractEltOp = cast<vector::ExtractElementOp>(op); 305cd5dab8aSAart Bik auto vectorType = extractEltOp.getVectorType(); 306cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType.getElementType()); 307cd5dab8aSAart Bik 308cd5dab8aSAart Bik // Bail if result type cannot be lowered. 309cd5dab8aSAart Bik if (!llvmType) 310cd5dab8aSAart Bik return matchFailure(); 311cd5dab8aSAart Bik 312cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::ExtractElementOp>( 313cd5dab8aSAart Bik op, llvmType, adaptor.vector(), adaptor.position()); 314cd5dab8aSAart Bik return matchSuccess(); 315cd5dab8aSAart Bik } 316cd5dab8aSAart Bik }; 317cd5dab8aSAart Bik 3189826fe5cSAart Bik class VectorExtractOpConversion : public LLVMOpLowering { 3195c0c51a9SNicolas Vasilache public: 3209826fe5cSAart Bik explicit VectorExtractOpConversion(MLIRContext *context, 3215c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 322d37f2725SAart Bik : LLVMOpLowering(vector::ExtractOp::getOperationName(), context, 3235c0c51a9SNicolas Vasilache typeConverter) {} 3245c0c51a9SNicolas Vasilache 3255c0c51a9SNicolas Vasilache PatternMatchResult 326*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 3275c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 3285c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 329d37f2725SAart Bik auto adaptor = vector::ExtractOpOperandAdaptor(operands); 330d37f2725SAart Bik auto extractOp = cast<vector::ExtractOp>(op); 3319826fe5cSAart Bik auto vectorType = extractOp.getVectorType(); 3325c0c51a9SNicolas Vasilache auto resultType = extractOp.getResult()->getType(); 3335c0c51a9SNicolas Vasilache auto llvmResultType = lowering.convertType(resultType); 3345c0c51a9SNicolas Vasilache auto positionArrayAttr = extractOp.position(); 3359826fe5cSAart Bik 3369826fe5cSAart Bik // Bail if result type cannot be lowered. 3379826fe5cSAart Bik if (!llvmResultType) 3389826fe5cSAart Bik return matchFailure(); 3399826fe5cSAart Bik 3405c0c51a9SNicolas Vasilache // One-shot extraction of vector from array (only requires extractvalue). 3415c0c51a9SNicolas Vasilache if (resultType.isa<VectorType>()) { 342*e62a6956SRiver Riddle Value extracted = rewriter.create<LLVM::ExtractValueOp>( 3435c0c51a9SNicolas Vasilache loc, llvmResultType, adaptor.vector(), positionArrayAttr); 3445c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3455c0c51a9SNicolas Vasilache return matchSuccess(); 3465c0c51a9SNicolas Vasilache } 3475c0c51a9SNicolas Vasilache 3489826fe5cSAart Bik // Potential extraction of 1-D vector from array. 3495c0c51a9SNicolas Vasilache auto *context = op->getContext(); 350*e62a6956SRiver Riddle Value extracted = adaptor.vector(); 3515c0c51a9SNicolas Vasilache auto positionAttrs = positionArrayAttr.getValue(); 3525c0c51a9SNicolas Vasilache if (positionAttrs.size() > 1) { 3539826fe5cSAart Bik auto oneDVectorType = reducedVectorTypeBack(vectorType); 3545c0c51a9SNicolas Vasilache auto nMinusOnePositionAttrs = 3555c0c51a9SNicolas Vasilache ArrayAttr::get(positionAttrs.drop_back(), context); 3565c0c51a9SNicolas Vasilache extracted = rewriter.create<LLVM::ExtractValueOp>( 3575c0c51a9SNicolas Vasilache loc, lowering.convertType(oneDVectorType), extracted, 3585c0c51a9SNicolas Vasilache nMinusOnePositionAttrs); 3595c0c51a9SNicolas Vasilache } 3605c0c51a9SNicolas Vasilache 3615c0c51a9SNicolas Vasilache // Remaining extraction of element from 1-D LLVM vector 3625c0c51a9SNicolas Vasilache auto position = positionAttrs.back().cast<IntegerAttr>(); 3631d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 3641d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 3655c0c51a9SNicolas Vasilache extracted = 3665c0c51a9SNicolas Vasilache rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant); 3675c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3685c0c51a9SNicolas Vasilache 3695c0c51a9SNicolas Vasilache return matchSuccess(); 3705c0c51a9SNicolas Vasilache } 3715c0c51a9SNicolas Vasilache }; 3725c0c51a9SNicolas Vasilache 373cd5dab8aSAart Bik class VectorInsertElementOpConversion : public LLVMOpLowering { 374cd5dab8aSAart Bik public: 375cd5dab8aSAart Bik explicit VectorInsertElementOpConversion(MLIRContext *context, 376cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 377cd5dab8aSAart Bik : LLVMOpLowering(vector::InsertElementOp::getOperationName(), context, 378cd5dab8aSAart Bik typeConverter) {} 379cd5dab8aSAart Bik 380cd5dab8aSAart Bik PatternMatchResult 381*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 382cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 383cd5dab8aSAart Bik auto adaptor = vector::InsertElementOpOperandAdaptor(operands); 384cd5dab8aSAart Bik auto insertEltOp = cast<vector::InsertElementOp>(op); 385cd5dab8aSAart Bik auto vectorType = insertEltOp.getDestVectorType(); 386cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType); 387cd5dab8aSAart Bik 388cd5dab8aSAart Bik // Bail if result type cannot be lowered. 389cd5dab8aSAart Bik if (!llvmType) 390cd5dab8aSAart Bik return matchFailure(); 391cd5dab8aSAart Bik 392cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::InsertElementOp>( 393cd5dab8aSAart Bik op, llvmType, adaptor.dest(), adaptor.source(), adaptor.position()); 394cd5dab8aSAart Bik return matchSuccess(); 395cd5dab8aSAart Bik } 396cd5dab8aSAart Bik }; 397cd5dab8aSAart Bik 3989826fe5cSAart Bik class VectorInsertOpConversion : public LLVMOpLowering { 3999826fe5cSAart Bik public: 4009826fe5cSAart Bik explicit VectorInsertOpConversion(MLIRContext *context, 4019826fe5cSAart Bik LLVMTypeConverter &typeConverter) 4029826fe5cSAart Bik : LLVMOpLowering(vector::InsertOp::getOperationName(), context, 4039826fe5cSAart Bik typeConverter) {} 4049826fe5cSAart Bik 4059826fe5cSAart Bik PatternMatchResult 406*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 4079826fe5cSAart Bik ConversionPatternRewriter &rewriter) const override { 4089826fe5cSAart Bik auto loc = op->getLoc(); 4099826fe5cSAart Bik auto adaptor = vector::InsertOpOperandAdaptor(operands); 4109826fe5cSAart Bik auto insertOp = cast<vector::InsertOp>(op); 4119826fe5cSAart Bik auto sourceType = insertOp.getSourceType(); 4129826fe5cSAart Bik auto destVectorType = insertOp.getDestVectorType(); 4139826fe5cSAart Bik auto llvmResultType = lowering.convertType(destVectorType); 4149826fe5cSAart Bik auto positionArrayAttr = insertOp.position(); 4159826fe5cSAart Bik 4169826fe5cSAart Bik // Bail if result type cannot be lowered. 4179826fe5cSAart Bik if (!llvmResultType) 4189826fe5cSAart Bik return matchFailure(); 4199826fe5cSAart Bik 4209826fe5cSAart Bik // One-shot insertion of a vector into an array (only requires insertvalue). 4219826fe5cSAart Bik if (sourceType.isa<VectorType>()) { 422*e62a6956SRiver Riddle Value inserted = rewriter.create<LLVM::InsertValueOp>( 4239826fe5cSAart Bik loc, llvmResultType, adaptor.dest(), adaptor.source(), 4249826fe5cSAart Bik positionArrayAttr); 4259826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4269826fe5cSAart Bik return matchSuccess(); 4279826fe5cSAart Bik } 4289826fe5cSAart Bik 4299826fe5cSAart Bik // Potential extraction of 1-D vector from array. 4309826fe5cSAart Bik auto *context = op->getContext(); 431*e62a6956SRiver Riddle Value extracted = adaptor.dest(); 4329826fe5cSAart Bik auto positionAttrs = positionArrayAttr.getValue(); 4339826fe5cSAart Bik auto position = positionAttrs.back().cast<IntegerAttr>(); 4349826fe5cSAart Bik auto oneDVectorType = destVectorType; 4359826fe5cSAart Bik if (positionAttrs.size() > 1) { 4369826fe5cSAart Bik oneDVectorType = reducedVectorTypeBack(destVectorType); 4379826fe5cSAart Bik auto nMinusOnePositionAttrs = 4389826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4399826fe5cSAart Bik extracted = rewriter.create<LLVM::ExtractValueOp>( 4409826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, 4419826fe5cSAart Bik nMinusOnePositionAttrs); 4429826fe5cSAart Bik } 4439826fe5cSAart Bik 4449826fe5cSAart Bik // Insertion of an element into a 1-D LLVM vector. 4451d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 4461d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 447*e62a6956SRiver Riddle Value inserted = rewriter.create<LLVM::InsertElementOp>( 4489826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, adaptor.source(), 4499826fe5cSAart Bik constant); 4509826fe5cSAart Bik 4519826fe5cSAart Bik // Potential insertion of resulting 1-D vector into array. 4529826fe5cSAart Bik if (positionAttrs.size() > 1) { 4539826fe5cSAart Bik auto nMinusOnePositionAttrs = 4549826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4559826fe5cSAart Bik inserted = rewriter.create<LLVM::InsertValueOp>(loc, llvmResultType, 4569826fe5cSAart Bik adaptor.dest(), inserted, 4579826fe5cSAart Bik nMinusOnePositionAttrs); 4589826fe5cSAart Bik } 4599826fe5cSAart Bik 4609826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4619826fe5cSAart Bik return matchSuccess(); 4629826fe5cSAart Bik } 4639826fe5cSAart Bik }; 4649826fe5cSAart Bik 4655c0c51a9SNicolas Vasilache class VectorOuterProductOpConversion : public LLVMOpLowering { 4665c0c51a9SNicolas Vasilache public: 4675c0c51a9SNicolas Vasilache explicit VectorOuterProductOpConversion(MLIRContext *context, 4685c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 4695c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::OuterProductOp::getOperationName(), context, 4705c0c51a9SNicolas Vasilache typeConverter) {} 4715c0c51a9SNicolas Vasilache 4725c0c51a9SNicolas Vasilache PatternMatchResult 473*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 4745c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 4755c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 4765c0c51a9SNicolas Vasilache auto adaptor = vector::OuterProductOpOperandAdaptor(operands); 4775c0c51a9SNicolas Vasilache auto *ctx = op->getContext(); 4785c0c51a9SNicolas Vasilache auto vLHS = adaptor.lhs()->getType().cast<LLVM::LLVMType>(); 4795c0c51a9SNicolas Vasilache auto vRHS = adaptor.rhs()->getType().cast<LLVM::LLVMType>(); 4805c0c51a9SNicolas Vasilache auto rankLHS = vLHS.getUnderlyingType()->getVectorNumElements(); 4815c0c51a9SNicolas Vasilache auto rankRHS = vRHS.getUnderlyingType()->getVectorNumElements(); 4825c0c51a9SNicolas Vasilache auto llvmArrayOfVectType = lowering.convertType( 4835c0c51a9SNicolas Vasilache cast<vector::OuterProductOp>(op).getResult()->getType()); 484*e62a6956SRiver Riddle Value desc = rewriter.create<LLVM::UndefOp>(loc, llvmArrayOfVectType); 485*e62a6956SRiver Riddle Value a = adaptor.lhs(), b = adaptor.rhs(); 486*e62a6956SRiver Riddle Value acc = adaptor.acc().empty() ? nullptr : adaptor.acc().front(); 487*e62a6956SRiver Riddle SmallVector<Value, 8> lhs, accs; 4885c0c51a9SNicolas Vasilache lhs.reserve(rankLHS); 4895c0c51a9SNicolas Vasilache accs.reserve(rankLHS); 4905c0c51a9SNicolas Vasilache for (unsigned d = 0, e = rankLHS; d < e; ++d) { 4915c0c51a9SNicolas Vasilache // shufflevector explicitly requires i32. 4925c0c51a9SNicolas Vasilache auto attr = rewriter.getI32IntegerAttr(d); 4935c0c51a9SNicolas Vasilache SmallVector<Attribute, 4> bcastAttr(rankRHS, attr); 4945c0c51a9SNicolas Vasilache auto bcastArrayAttr = ArrayAttr::get(bcastAttr, ctx); 495*e62a6956SRiver Riddle Value aD = nullptr, accD = nullptr; 4965c0c51a9SNicolas Vasilache // 1. Broadcast the element a[d] into vector aD. 4975c0c51a9SNicolas Vasilache aD = rewriter.create<LLVM::ShuffleVectorOp>(loc, a, a, bcastArrayAttr); 4985c0c51a9SNicolas Vasilache // 2. If acc is present, extract 1-d vector acc[d] into accD. 4995c0c51a9SNicolas Vasilache if (acc) 5005c0c51a9SNicolas Vasilache accD = rewriter.create<LLVM::ExtractValueOp>( 5015c0c51a9SNicolas Vasilache loc, vRHS, acc, rewriter.getI64ArrayAttr(d)); 5025c0c51a9SNicolas Vasilache // 3. Compute aD outer b (plus accD, if relevant). 503*e62a6956SRiver Riddle Value aOuterbD = 5045c0c51a9SNicolas Vasilache accD ? rewriter.create<LLVM::FMulAddOp>(loc, vRHS, aD, b, accD) 5055c0c51a9SNicolas Vasilache .getResult() 5065c0c51a9SNicolas Vasilache : rewriter.create<LLVM::FMulOp>(loc, aD, b).getResult(); 5075c0c51a9SNicolas Vasilache // 4. Insert as value `d` in the descriptor. 5085c0c51a9SNicolas Vasilache desc = rewriter.create<LLVM::InsertValueOp>(loc, llvmArrayOfVectType, 5095c0c51a9SNicolas Vasilache desc, aOuterbD, 5105c0c51a9SNicolas Vasilache rewriter.getI64ArrayAttr(d)); 5115c0c51a9SNicolas Vasilache } 5125c0c51a9SNicolas Vasilache rewriter.replaceOp(op, desc); 5135c0c51a9SNicolas Vasilache return matchSuccess(); 5145c0c51a9SNicolas Vasilache } 5155c0c51a9SNicolas Vasilache }; 5165c0c51a9SNicolas Vasilache 5175c0c51a9SNicolas Vasilache class VectorTypeCastOpConversion : public LLVMOpLowering { 5185c0c51a9SNicolas Vasilache public: 5195c0c51a9SNicolas Vasilache explicit VectorTypeCastOpConversion(MLIRContext *context, 5205c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 5215c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::TypeCastOp::getOperationName(), context, 5225c0c51a9SNicolas Vasilache typeConverter) {} 5235c0c51a9SNicolas Vasilache 5245c0c51a9SNicolas Vasilache PatternMatchResult 525*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 5265c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 5275c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 5285c0c51a9SNicolas Vasilache vector::TypeCastOp castOp = cast<vector::TypeCastOp>(op); 5295c0c51a9SNicolas Vasilache MemRefType sourceMemRefType = 5305c0c51a9SNicolas Vasilache castOp.getOperand()->getType().cast<MemRefType>(); 5315c0c51a9SNicolas Vasilache MemRefType targetMemRefType = 5325c0c51a9SNicolas Vasilache castOp.getResult()->getType().cast<MemRefType>(); 5335c0c51a9SNicolas Vasilache 5345c0c51a9SNicolas Vasilache // Only static shape casts supported atm. 5355c0c51a9SNicolas Vasilache if (!sourceMemRefType.hasStaticShape() || 5365c0c51a9SNicolas Vasilache !targetMemRefType.hasStaticShape()) 5375c0c51a9SNicolas Vasilache return matchFailure(); 5385c0c51a9SNicolas Vasilache 5395c0c51a9SNicolas Vasilache auto llvmSourceDescriptorTy = 5405c0c51a9SNicolas Vasilache operands[0]->getType().dyn_cast<LLVM::LLVMType>(); 5415c0c51a9SNicolas Vasilache if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy()) 5425c0c51a9SNicolas Vasilache return matchFailure(); 5435c0c51a9SNicolas Vasilache MemRefDescriptor sourceMemRef(operands[0]); 5445c0c51a9SNicolas Vasilache 5455c0c51a9SNicolas Vasilache auto llvmTargetDescriptorTy = lowering.convertType(targetMemRefType) 5465c0c51a9SNicolas Vasilache .dyn_cast_or_null<LLVM::LLVMType>(); 5475c0c51a9SNicolas Vasilache if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy()) 5485c0c51a9SNicolas Vasilache return matchFailure(); 5495c0c51a9SNicolas Vasilache 5505c0c51a9SNicolas Vasilache int64_t offset; 5515c0c51a9SNicolas Vasilache SmallVector<int64_t, 4> strides; 5525c0c51a9SNicolas Vasilache auto successStrides = 5535c0c51a9SNicolas Vasilache getStridesAndOffset(sourceMemRefType, strides, offset); 5545c0c51a9SNicolas Vasilache bool isContiguous = (strides.back() == 1); 5555c0c51a9SNicolas Vasilache if (isContiguous) { 5565c0c51a9SNicolas Vasilache auto sizes = sourceMemRefType.getShape(); 5575c0c51a9SNicolas Vasilache for (int index = 0, e = strides.size() - 2; index < e; ++index) { 5585c0c51a9SNicolas Vasilache if (strides[index] != strides[index + 1] * sizes[index + 1]) { 5595c0c51a9SNicolas Vasilache isContiguous = false; 5605c0c51a9SNicolas Vasilache break; 5615c0c51a9SNicolas Vasilache } 5625c0c51a9SNicolas Vasilache } 5635c0c51a9SNicolas Vasilache } 5645c0c51a9SNicolas Vasilache // Only contiguous source tensors supported atm. 5655c0c51a9SNicolas Vasilache if (failed(successStrides) || !isContiguous) 5665c0c51a9SNicolas Vasilache return matchFailure(); 5675c0c51a9SNicolas Vasilache 5685c0c51a9SNicolas Vasilache auto int64Ty = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 5695c0c51a9SNicolas Vasilache 5705c0c51a9SNicolas Vasilache // Create descriptor. 5715c0c51a9SNicolas Vasilache auto desc = MemRefDescriptor::undef(rewriter, loc, llvmTargetDescriptorTy); 5725c0c51a9SNicolas Vasilache Type llvmTargetElementTy = desc.getElementType(); 5735c0c51a9SNicolas Vasilache // Set allocated ptr. 574*e62a6956SRiver Riddle Value allocated = sourceMemRef.allocatedPtr(rewriter, loc); 5755c0c51a9SNicolas Vasilache allocated = 5765c0c51a9SNicolas Vasilache rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, allocated); 5775c0c51a9SNicolas Vasilache desc.setAllocatedPtr(rewriter, loc, allocated); 5785c0c51a9SNicolas Vasilache // Set aligned ptr. 579*e62a6956SRiver Riddle Value ptr = sourceMemRef.alignedPtr(rewriter, loc); 5805c0c51a9SNicolas Vasilache ptr = rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, ptr); 5815c0c51a9SNicolas Vasilache desc.setAlignedPtr(rewriter, loc, ptr); 5825c0c51a9SNicolas Vasilache // Fill offset 0. 5835c0c51a9SNicolas Vasilache auto attr = rewriter.getIntegerAttr(rewriter.getIndexType(), 0); 5845c0c51a9SNicolas Vasilache auto zero = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, attr); 5855c0c51a9SNicolas Vasilache desc.setOffset(rewriter, loc, zero); 5865c0c51a9SNicolas Vasilache 5875c0c51a9SNicolas Vasilache // Fill size and stride descriptors in memref. 5885c0c51a9SNicolas Vasilache for (auto indexedSize : llvm::enumerate(targetMemRefType.getShape())) { 5895c0c51a9SNicolas Vasilache int64_t index = indexedSize.index(); 5905c0c51a9SNicolas Vasilache auto sizeAttr = 5915c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), indexedSize.value()); 5925c0c51a9SNicolas Vasilache auto size = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, sizeAttr); 5935c0c51a9SNicolas Vasilache desc.setSize(rewriter, loc, index, size); 5945c0c51a9SNicolas Vasilache auto strideAttr = 5955c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), strides[index]); 5965c0c51a9SNicolas Vasilache auto stride = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, strideAttr); 5975c0c51a9SNicolas Vasilache desc.setStride(rewriter, loc, index, stride); 5985c0c51a9SNicolas Vasilache } 5995c0c51a9SNicolas Vasilache 6005c0c51a9SNicolas Vasilache rewriter.replaceOp(op, {desc}); 6015c0c51a9SNicolas Vasilache return matchSuccess(); 6025c0c51a9SNicolas Vasilache } 6035c0c51a9SNicolas Vasilache }; 6045c0c51a9SNicolas Vasilache 605d9b500d3SAart Bik class VectorPrintOpConversion : public LLVMOpLowering { 606d9b500d3SAart Bik public: 607d9b500d3SAart Bik explicit VectorPrintOpConversion(MLIRContext *context, 608d9b500d3SAart Bik LLVMTypeConverter &typeConverter) 609d9b500d3SAart Bik : LLVMOpLowering(vector::PrintOp::getOperationName(), context, 610d9b500d3SAart Bik typeConverter) {} 611d9b500d3SAart Bik 612d9b500d3SAart Bik // Proof-of-concept lowering implementation that relies on a small 613d9b500d3SAart Bik // runtime support library, which only needs to provide a few 614d9b500d3SAart Bik // printing methods (single value for all data types, opening/closing 615d9b500d3SAart Bik // bracket, comma, newline). The lowering fully unrolls a vector 616d9b500d3SAart Bik // in terms of these elementary printing operations. The advantage 617d9b500d3SAart Bik // of this approach is that the library can remain unaware of all 618d9b500d3SAart Bik // low-level implementation details of vectors while still supporting 619d9b500d3SAart Bik // output of any shaped and dimensioned vector. Due to full unrolling, 620d9b500d3SAart Bik // this approach is less suited for very large vectors though. 621d9b500d3SAart Bik // 622d9b500d3SAart Bik // TODO(ajcbik): rely solely on libc in future? something else? 623d9b500d3SAart Bik // 624d9b500d3SAart Bik PatternMatchResult 625*e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 626d9b500d3SAart Bik ConversionPatternRewriter &rewriter) const override { 627d9b500d3SAart Bik auto printOp = cast<vector::PrintOp>(op); 628d9b500d3SAart Bik auto adaptor = vector::PrintOpOperandAdaptor(operands); 629d9b500d3SAart Bik Type printType = printOp.getPrintType(); 630d9b500d3SAart Bik 631d9b500d3SAart Bik if (lowering.convertType(printType) == nullptr) 632d9b500d3SAart Bik return matchFailure(); 633d9b500d3SAart Bik 634d9b500d3SAart Bik // Make sure element type has runtime support (currently just Float/Double). 635d9b500d3SAart Bik VectorType vectorType = printType.dyn_cast<VectorType>(); 636d9b500d3SAart Bik Type eltType = vectorType ? vectorType.getElementType() : printType; 637d9b500d3SAart Bik int64_t rank = vectorType ? vectorType.getRank() : 0; 638d9b500d3SAart Bik Operation *printer; 639d9b500d3SAart Bik if (eltType.isF32()) 640d9b500d3SAart Bik printer = getPrintFloat(op); 641d9b500d3SAart Bik else if (eltType.isF64()) 642d9b500d3SAart Bik printer = getPrintDouble(op); 643d9b500d3SAart Bik else 644d9b500d3SAart Bik return matchFailure(); 645d9b500d3SAart Bik 646d9b500d3SAart Bik // Unroll vector into elementary print calls. 647d9b500d3SAart Bik emitRanks(rewriter, op, adaptor.source(), vectorType, printer, rank); 648d9b500d3SAart Bik emitCall(rewriter, op->getLoc(), getPrintNewline(op)); 649d9b500d3SAart Bik rewriter.eraseOp(op); 650d9b500d3SAart Bik return matchSuccess(); 651d9b500d3SAart Bik } 652d9b500d3SAart Bik 653d9b500d3SAart Bik private: 654d9b500d3SAart Bik void emitRanks(ConversionPatternRewriter &rewriter, Operation *op, 655*e62a6956SRiver Riddle Value value, VectorType vectorType, Operation *printer, 656d9b500d3SAart Bik int64_t rank) const { 657d9b500d3SAart Bik Location loc = op->getLoc(); 658d9b500d3SAart Bik if (rank == 0) { 659d9b500d3SAart Bik emitCall(rewriter, loc, printer, value); 660d9b500d3SAart Bik return; 661d9b500d3SAart Bik } 662d9b500d3SAart Bik 663d9b500d3SAart Bik emitCall(rewriter, loc, getPrintOpen(op)); 664d9b500d3SAart Bik Operation *printComma = getPrintComma(op); 665d9b500d3SAart Bik int64_t dim = vectorType.getDimSize(0); 666d9b500d3SAart Bik for (int64_t d = 0; d < dim; ++d) { 667d9b500d3SAart Bik auto reducedType = 668d9b500d3SAart Bik rank > 1 ? reducedVectorTypeFront(vectorType) : nullptr; 669d9b500d3SAart Bik auto llvmType = lowering.convertType( 670d9b500d3SAart Bik rank > 1 ? reducedType : vectorType.getElementType()); 671*e62a6956SRiver Riddle Value nestedVal = 672d9b500d3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, d); 673d9b500d3SAart Bik emitRanks(rewriter, op, nestedVal, reducedType, printer, rank - 1); 674d9b500d3SAart Bik if (d != dim - 1) 675d9b500d3SAart Bik emitCall(rewriter, loc, printComma); 676d9b500d3SAart Bik } 677d9b500d3SAart Bik emitCall(rewriter, loc, getPrintClose(op)); 678d9b500d3SAart Bik } 679d9b500d3SAart Bik 680d9b500d3SAart Bik // Helper to emit a call. 681d9b500d3SAart Bik static void emitCall(ConversionPatternRewriter &rewriter, Location loc, 682d9b500d3SAart Bik Operation *ref, ValueRange params = ValueRange()) { 683d9b500d3SAart Bik rewriter.create<LLVM::CallOp>(loc, ArrayRef<Type>{}, 684d9b500d3SAart Bik rewriter.getSymbolRefAttr(ref), params); 685d9b500d3SAart Bik } 686d9b500d3SAart Bik 687d9b500d3SAart Bik // Helper for printer method declaration (first hit) and lookup. 688d9b500d3SAart Bik static Operation *getPrint(Operation *op, LLVM::LLVMDialect *dialect, 689d9b500d3SAart Bik StringRef name, ArrayRef<LLVM::LLVMType> params) { 690d9b500d3SAart Bik auto module = op->getParentOfType<ModuleOp>(); 691d9b500d3SAart Bik auto func = module.lookupSymbol<LLVM::LLVMFuncOp>(name); 692d9b500d3SAart Bik if (func) 693d9b500d3SAart Bik return func; 694d9b500d3SAart Bik OpBuilder moduleBuilder(module.getBodyRegion()); 695d9b500d3SAart Bik return moduleBuilder.create<LLVM::LLVMFuncOp>( 696d9b500d3SAart Bik op->getLoc(), name, 697d9b500d3SAart Bik LLVM::LLVMType::getFunctionTy(LLVM::LLVMType::getVoidTy(dialect), 698d9b500d3SAart Bik params, /*isVarArg=*/false)); 699d9b500d3SAart Bik } 700d9b500d3SAart Bik 701d9b500d3SAart Bik // Helpers for method names. 702d9b500d3SAart Bik Operation *getPrintFloat(Operation *op) const { 703d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 704d9b500d3SAart Bik return getPrint(op, dialect, "print_f32", 705d9b500d3SAart Bik LLVM::LLVMType::getFloatTy(dialect)); 706d9b500d3SAart Bik } 707d9b500d3SAart Bik Operation *getPrintDouble(Operation *op) const { 708d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 709d9b500d3SAart Bik return getPrint(op, dialect, "print_f64", 710d9b500d3SAart Bik LLVM::LLVMType::getDoubleTy(dialect)); 711d9b500d3SAart Bik } 712d9b500d3SAart Bik Operation *getPrintOpen(Operation *op) const { 713d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_open", {}); 714d9b500d3SAart Bik } 715d9b500d3SAart Bik Operation *getPrintClose(Operation *op) const { 716d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_close", {}); 717d9b500d3SAart Bik } 718d9b500d3SAart Bik Operation *getPrintComma(Operation *op) const { 719d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_comma", {}); 720d9b500d3SAart Bik } 721d9b500d3SAart Bik Operation *getPrintNewline(Operation *op) const { 722d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_newline", {}); 723d9b500d3SAart Bik } 724d9b500d3SAart Bik }; 725d9b500d3SAart Bik 7265c0c51a9SNicolas Vasilache /// Populate the given list with patterns that convert from Vector to LLVM. 7275c0c51a9SNicolas Vasilache void mlir::populateVectorToLLVMConversionPatterns( 7285c0c51a9SNicolas Vasilache LLVMTypeConverter &converter, OwningRewritePatternList &patterns) { 7291c81adf3SAart Bik patterns.insert<VectorBroadcastOpConversion, VectorShuffleOpConversion, 730cd5dab8aSAart Bik VectorExtractElementOpConversion, VectorExtractOpConversion, 731cd5dab8aSAart Bik VectorInsertElementOpConversion, VectorInsertOpConversion, 732d9b500d3SAart Bik VectorOuterProductOpConversion, VectorTypeCastOpConversion, 733d9b500d3SAart Bik VectorPrintOpConversion>(converter.getDialect()->getContext(), 734d9b500d3SAart Bik converter); 7355c0c51a9SNicolas Vasilache } 7365c0c51a9SNicolas Vasilache 7375c0c51a9SNicolas Vasilache namespace { 7385c0c51a9SNicolas Vasilache struct LowerVectorToLLVMPass : public ModulePass<LowerVectorToLLVMPass> { 7395c0c51a9SNicolas Vasilache void runOnModule() override; 7405c0c51a9SNicolas Vasilache }; 7415c0c51a9SNicolas Vasilache } // namespace 7425c0c51a9SNicolas Vasilache 7435c0c51a9SNicolas Vasilache void LowerVectorToLLVMPass::runOnModule() { 7445c0c51a9SNicolas Vasilache // Convert to the LLVM IR dialect using the converter defined above. 7455c0c51a9SNicolas Vasilache OwningRewritePatternList patterns; 7465c0c51a9SNicolas Vasilache LLVMTypeConverter converter(&getContext()); 7475c0c51a9SNicolas Vasilache populateVectorToLLVMConversionPatterns(converter, patterns); 7485c0c51a9SNicolas Vasilache populateStdToLLVMConversionPatterns(converter, patterns); 7495c0c51a9SNicolas Vasilache 7505c0c51a9SNicolas Vasilache ConversionTarget target(getContext()); 7515c0c51a9SNicolas Vasilache target.addLegalDialect<LLVM::LLVMDialect>(); 7525c0c51a9SNicolas Vasilache target.addDynamicallyLegalOp<FuncOp>( 7535c0c51a9SNicolas Vasilache [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); }); 7545c0c51a9SNicolas Vasilache if (failed( 7555c0c51a9SNicolas Vasilache applyPartialConversion(getModule(), target, patterns, &converter))) { 7565c0c51a9SNicolas Vasilache signalPassFailure(); 7575c0c51a9SNicolas Vasilache } 7585c0c51a9SNicolas Vasilache } 7595c0c51a9SNicolas Vasilache 7605c0c51a9SNicolas Vasilache OpPassBase<ModuleOp> *mlir::createLowerVectorToLLVMPass() { 7615c0c51a9SNicolas Vasilache return new LowerVectorToLLVMPass(); 7625c0c51a9SNicolas Vasilache } 7635c0c51a9SNicolas Vasilache 7645c0c51a9SNicolas Vasilache static PassRegistration<LowerVectorToLLVMPass> 7655c0c51a9SNicolas Vasilache pass("convert-vector-to-llvm", 7665c0c51a9SNicolas Vasilache "Lower the operations from the vector dialect into the LLVM dialect"); 767