15c0c51a9SNicolas Vasilache //===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===// 25c0c51a9SNicolas Vasilache // 356222a06SMehdi Amini // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions. 456222a06SMehdi Amini // See https://llvm.org/LICENSE.txt for license information. 556222a06SMehdi Amini // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65c0c51a9SNicolas Vasilache // 756222a06SMehdi Amini //===----------------------------------------------------------------------===// 85c0c51a9SNicolas Vasilache 9*65678d93SNicolas Vasilache #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 105c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 115c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h" 125c0c51a9SNicolas Vasilache #include "mlir/Dialect/LLVMIR/LLVMDialect.h" 13*65678d93SNicolas Vasilache #include "mlir/Dialect/StandardOps/Ops.h" 145c0c51a9SNicolas Vasilache #include "mlir/Dialect/VectorOps/VectorOps.h" 155c0c51a9SNicolas Vasilache #include "mlir/IR/Attributes.h" 165c0c51a9SNicolas Vasilache #include "mlir/IR/Builders.h" 175c0c51a9SNicolas Vasilache #include "mlir/IR/MLIRContext.h" 185c0c51a9SNicolas Vasilache #include "mlir/IR/Module.h" 195c0c51a9SNicolas Vasilache #include "mlir/IR/Operation.h" 205c0c51a9SNicolas Vasilache #include "mlir/IR/PatternMatch.h" 215c0c51a9SNicolas Vasilache #include "mlir/IR/StandardTypes.h" 225c0c51a9SNicolas Vasilache #include "mlir/IR/Types.h" 235c0c51a9SNicolas Vasilache #include "mlir/Pass/Pass.h" 245c0c51a9SNicolas Vasilache #include "mlir/Pass/PassManager.h" 255c0c51a9SNicolas Vasilache #include "mlir/Transforms/DialectConversion.h" 265c0c51a9SNicolas Vasilache #include "mlir/Transforms/Passes.h" 275c0c51a9SNicolas Vasilache 285c0c51a9SNicolas Vasilache #include "llvm/IR/DerivedTypes.h" 295c0c51a9SNicolas Vasilache #include "llvm/IR/Module.h" 305c0c51a9SNicolas Vasilache #include "llvm/IR/Type.h" 315c0c51a9SNicolas Vasilache #include "llvm/Support/Allocator.h" 325c0c51a9SNicolas Vasilache #include "llvm/Support/ErrorHandling.h" 335c0c51a9SNicolas Vasilache 345c0c51a9SNicolas Vasilache using namespace mlir; 35*65678d93SNicolas Vasilache using namespace mlir::vector; 365c0c51a9SNicolas Vasilache 375c0c51a9SNicolas Vasilache template <typename T> 385c0c51a9SNicolas Vasilache static LLVM::LLVMType getPtrToElementType(T containerType, 395c0c51a9SNicolas Vasilache LLVMTypeConverter &lowering) { 405c0c51a9SNicolas Vasilache return lowering.convertType(containerType.getElementType()) 415c0c51a9SNicolas Vasilache .template cast<LLVM::LLVMType>() 425c0c51a9SNicolas Vasilache .getPointerTo(); 435c0c51a9SNicolas Vasilache } 445c0c51a9SNicolas Vasilache 459826fe5cSAart Bik // Helper to reduce vector type by one rank at front. 469826fe5cSAart Bik static VectorType reducedVectorTypeFront(VectorType tp) { 479826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 489826fe5cSAart Bik return VectorType::get(tp.getShape().drop_front(), tp.getElementType()); 499826fe5cSAart Bik } 509826fe5cSAart Bik 519826fe5cSAart Bik // Helper to reduce vector type by *all* but one rank at back. 529826fe5cSAart Bik static VectorType reducedVectorTypeBack(VectorType tp) { 539826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 549826fe5cSAart Bik return VectorType::get(tp.getShape().take_back(), tp.getElementType()); 559826fe5cSAart Bik } 569826fe5cSAart Bik 571c81adf3SAart Bik // Helper that picks the proper sequence for inserting. 58e62a6956SRiver Riddle static Value insertOne(ConversionPatternRewriter &rewriter, 59e62a6956SRiver Riddle LLVMTypeConverter &lowering, Location loc, Value val1, 60e62a6956SRiver Riddle Value val2, Type llvmType, int64_t rank, int64_t pos) { 611c81adf3SAart Bik if (rank == 1) { 621c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 631c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 641c81adf3SAart Bik loc, lowering.convertType(idxType), 651c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 661c81adf3SAart Bik return rewriter.create<LLVM::InsertElementOp>(loc, llvmType, val1, val2, 671c81adf3SAart Bik constant); 681c81adf3SAart Bik } 691c81adf3SAart Bik return rewriter.create<LLVM::InsertValueOp>(loc, llvmType, val1, val2, 701c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 711c81adf3SAart Bik } 721c81adf3SAart Bik 731c81adf3SAart Bik // Helper that picks the proper sequence for extracting. 74e62a6956SRiver Riddle static Value extractOne(ConversionPatternRewriter &rewriter, 75e62a6956SRiver Riddle LLVMTypeConverter &lowering, Location loc, Value val, 76e62a6956SRiver Riddle Type llvmType, int64_t rank, int64_t pos) { 771c81adf3SAart Bik if (rank == 1) { 781c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 791c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 801c81adf3SAart Bik loc, lowering.convertType(idxType), 811c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 821c81adf3SAart Bik return rewriter.create<LLVM::ExtractElementOp>(loc, llvmType, val, 831c81adf3SAart Bik constant); 841c81adf3SAart Bik } 851c81adf3SAart Bik return rewriter.create<LLVM::ExtractValueOp>(loc, llvmType, val, 861c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 871c81adf3SAart Bik } 881c81adf3SAart Bik 89b36aaeafSAart Bik class VectorBroadcastOpConversion : public LLVMOpLowering { 90b36aaeafSAart Bik public: 91b36aaeafSAart Bik explicit VectorBroadcastOpConversion(MLIRContext *context, 92b36aaeafSAart Bik LLVMTypeConverter &typeConverter) 93b36aaeafSAart Bik : LLVMOpLowering(vector::BroadcastOp::getOperationName(), context, 94b36aaeafSAart Bik typeConverter) {} 95b36aaeafSAart Bik 96b36aaeafSAart Bik PatternMatchResult 97e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 98b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const override { 99b36aaeafSAart Bik auto broadcastOp = cast<vector::BroadcastOp>(op); 100b36aaeafSAart Bik VectorType dstVectorType = broadcastOp.getVectorType(); 101b36aaeafSAart Bik if (lowering.convertType(dstVectorType) == nullptr) 102b36aaeafSAart Bik return matchFailure(); 103b36aaeafSAart Bik // Rewrite when the full vector type can be lowered (which 104b36aaeafSAart Bik // implies all 'reduced' types can be lowered too). 1051c81adf3SAart Bik auto adaptor = vector::BroadcastOpOperandAdaptor(operands); 106b36aaeafSAart Bik VectorType srcVectorType = 107b36aaeafSAart Bik broadcastOp.getSourceType().dyn_cast<VectorType>(); 108b36aaeafSAart Bik rewriter.replaceOp( 1091c81adf3SAart Bik op, expandRanks(adaptor.source(), // source value to be expanded 110b36aaeafSAart Bik op->getLoc(), // location of original broadcast 111b36aaeafSAart Bik srcVectorType, dstVectorType, rewriter)); 112b36aaeafSAart Bik return matchSuccess(); 113b36aaeafSAart Bik } 114b36aaeafSAart Bik 115b36aaeafSAart Bik private: 116b36aaeafSAart Bik // Expands the given source value over all the ranks, as defined 117b36aaeafSAart Bik // by the source and destination type (a null source type denotes 118b36aaeafSAart Bik // expansion from a scalar value into a vector). 119b36aaeafSAart Bik // 120b36aaeafSAart Bik // TODO(ajcbik): consider replacing this one-pattern lowering 121b36aaeafSAart Bik // with a two-pattern lowering using other vector 122b36aaeafSAart Bik // ops once all insert/extract/shuffle operations 123b36aaeafSAart Bik // are available with lowering implemention. 124b36aaeafSAart Bik // 125e62a6956SRiver Riddle Value expandRanks(Value value, Location loc, VectorType srcVectorType, 126b36aaeafSAart Bik VectorType dstVectorType, 127b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 128b36aaeafSAart Bik assert((dstVectorType != nullptr) && "invalid result type in broadcast"); 129b36aaeafSAart Bik // Determine rank of source and destination. 130b36aaeafSAart Bik int64_t srcRank = srcVectorType ? srcVectorType.getRank() : 0; 131b36aaeafSAart Bik int64_t dstRank = dstVectorType.getRank(); 132b36aaeafSAart Bik int64_t curDim = dstVectorType.getDimSize(0); 133b36aaeafSAart Bik if (srcRank < dstRank) 134b36aaeafSAart Bik // Duplicate this rank. 135b36aaeafSAart Bik return duplicateOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 136b36aaeafSAart Bik curDim, rewriter); 137b36aaeafSAart Bik // If all trailing dimensions are the same, the broadcast consists of 138b36aaeafSAart Bik // simply passing through the source value and we are done. Otherwise, 139b36aaeafSAart Bik // any non-matching dimension forces a stretch along this rank. 140b36aaeafSAart Bik assert((srcVectorType != nullptr) && (srcRank > 0) && 141b36aaeafSAart Bik (srcRank == dstRank) && "invalid rank in broadcast"); 142b36aaeafSAart Bik for (int64_t r = 0; r < dstRank; r++) { 143b36aaeafSAart Bik if (srcVectorType.getDimSize(r) != dstVectorType.getDimSize(r)) { 144b36aaeafSAart Bik return stretchOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 145b36aaeafSAart Bik curDim, rewriter); 146b36aaeafSAart Bik } 147b36aaeafSAart Bik } 148b36aaeafSAart Bik return value; 149b36aaeafSAart Bik } 150b36aaeafSAart Bik 151b36aaeafSAart Bik // Picks the best way to duplicate a single rank. For the 1-D case, a 152b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion. For higher 153b36aaeafSAart Bik // dimensions, however, we need dim x insert-values on a new broadcast 154b36aaeafSAart Bik // with one less leading dimension, which will be lowered "recursively" 155b36aaeafSAart Bik // to matching LLVM IR. 156b36aaeafSAart Bik // For example: 157b36aaeafSAart Bik // v = broadcast s : f32 to vector<4x2xf32> 158b36aaeafSAart Bik // becomes: 159b36aaeafSAart Bik // x = broadcast s : f32 to vector<2xf32> 160b36aaeafSAart Bik // v = [x,x,x,x] 161b36aaeafSAart Bik // becomes: 162b36aaeafSAart Bik // x = [s,s] 163b36aaeafSAart Bik // v = [x,x,x,x] 164e62a6956SRiver Riddle Value duplicateOneRank(Value value, Location loc, VectorType srcVectorType, 165e62a6956SRiver Riddle VectorType dstVectorType, int64_t rank, int64_t dim, 166b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 167b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 168b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 169b36aaeafSAart Bik if (rank == 1) { 170e62a6956SRiver Riddle Value undef = rewriter.create<LLVM::UndefOp>(loc, llvmType); 171e62a6956SRiver Riddle Value expand = 1721c81adf3SAart Bik insertOne(rewriter, lowering, loc, undef, value, llvmType, rank, 0); 173b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 174b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 175b36aaeafSAart Bik loc, expand, undef, rewriter.getI32ArrayAttr(zeroValues)); 176b36aaeafSAart Bik } 177e62a6956SRiver Riddle Value expand = expandRanks(value, loc, srcVectorType, 1789826fe5cSAart Bik reducedVectorTypeFront(dstVectorType), rewriter); 179e62a6956SRiver Riddle Value result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 180b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 1811c81adf3SAart Bik result = 1821c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 183b36aaeafSAart Bik } 184b36aaeafSAart Bik return result; 185b36aaeafSAart Bik } 186b36aaeafSAart Bik 187b36aaeafSAart Bik // Picks the best way to stretch a single rank. For the 1-D case, a 188b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion when at 189b36aaeafSAart Bik // a stretch. Otherwise, every dimension needs to be expanded 190b36aaeafSAart Bik // individually and individually inserted in the resulting vector. 191b36aaeafSAart Bik // For example: 192b36aaeafSAart Bik // v = broadcast w : vector<4x1x2xf32> to vector<4x2x2xf32> 193b36aaeafSAart Bik // becomes: 194b36aaeafSAart Bik // a = broadcast w[0] : vector<1x2xf32> to vector<2x2xf32> 195b36aaeafSAart Bik // b = broadcast w[1] : vector<1x2xf32> to vector<2x2xf32> 196b36aaeafSAart Bik // c = broadcast w[2] : vector<1x2xf32> to vector<2x2xf32> 197b36aaeafSAart Bik // d = broadcast w[3] : vector<1x2xf32> to vector<2x2xf32> 198b36aaeafSAart Bik // v = [a,b,c,d] 199b36aaeafSAart Bik // becomes: 200b36aaeafSAart Bik // x = broadcast w[0][0] : vector<2xf32> to vector <2x2xf32> 201b36aaeafSAart Bik // y = broadcast w[1][0] : vector<2xf32> to vector <2x2xf32> 202b36aaeafSAart Bik // a = [x, y] 203b36aaeafSAart Bik // etc. 204e62a6956SRiver Riddle Value stretchOneRank(Value value, Location loc, VectorType srcVectorType, 205e62a6956SRiver Riddle VectorType dstVectorType, int64_t rank, int64_t dim, 206b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 207b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 208b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 209e62a6956SRiver Riddle Value result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 210b36aaeafSAart Bik bool atStretch = dim != srcVectorType.getDimSize(0); 211b36aaeafSAart Bik if (rank == 1) { 2121c81adf3SAart Bik assert(atStretch); 213b36aaeafSAart Bik Type redLlvmType = lowering.convertType(dstVectorType.getElementType()); 214e62a6956SRiver Riddle Value one = 2151c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, 0); 216e62a6956SRiver Riddle Value expand = 2171c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, one, llvmType, rank, 0); 218b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 219b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 220b36aaeafSAart Bik loc, expand, result, rewriter.getI32ArrayAttr(zeroValues)); 221b36aaeafSAart Bik } 2229826fe5cSAart Bik VectorType redSrcType = reducedVectorTypeFront(srcVectorType); 2239826fe5cSAart Bik VectorType redDstType = reducedVectorTypeFront(dstVectorType); 224b36aaeafSAart Bik Type redLlvmType = lowering.convertType(redSrcType); 225b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 226b36aaeafSAart Bik int64_t pos = atStretch ? 0 : d; 227e62a6956SRiver Riddle Value one = 2281c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, pos); 229e62a6956SRiver Riddle Value expand = expandRanks(one, loc, redSrcType, redDstType, rewriter); 2301c81adf3SAart Bik result = 2311c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 232b36aaeafSAart Bik } 233b36aaeafSAart Bik return result; 234b36aaeafSAart Bik } 2351c81adf3SAart Bik }; 236b36aaeafSAart Bik 2371c81adf3SAart Bik class VectorShuffleOpConversion : public LLVMOpLowering { 2381c81adf3SAart Bik public: 2391c81adf3SAart Bik explicit VectorShuffleOpConversion(MLIRContext *context, 2401c81adf3SAart Bik LLVMTypeConverter &typeConverter) 2411c81adf3SAart Bik : LLVMOpLowering(vector::ShuffleOp::getOperationName(), context, 2421c81adf3SAart Bik typeConverter) {} 2431c81adf3SAart Bik 2441c81adf3SAart Bik PatternMatchResult 245e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 2461c81adf3SAart Bik ConversionPatternRewriter &rewriter) const override { 2471c81adf3SAart Bik auto loc = op->getLoc(); 2481c81adf3SAart Bik auto adaptor = vector::ShuffleOpOperandAdaptor(operands); 2491c81adf3SAart Bik auto shuffleOp = cast<vector::ShuffleOp>(op); 2501c81adf3SAart Bik auto v1Type = shuffleOp.getV1VectorType(); 2511c81adf3SAart Bik auto v2Type = shuffleOp.getV2VectorType(); 2521c81adf3SAart Bik auto vectorType = shuffleOp.getVectorType(); 2531c81adf3SAart Bik Type llvmType = lowering.convertType(vectorType); 2541c81adf3SAart Bik auto maskArrayAttr = shuffleOp.mask(); 2551c81adf3SAart Bik 2561c81adf3SAart Bik // Bail if result type cannot be lowered. 2571c81adf3SAart Bik if (!llvmType) 2581c81adf3SAart Bik return matchFailure(); 2591c81adf3SAart Bik 2601c81adf3SAart Bik // Get rank and dimension sizes. 2611c81adf3SAart Bik int64_t rank = vectorType.getRank(); 2621c81adf3SAart Bik assert(v1Type.getRank() == rank); 2631c81adf3SAart Bik assert(v2Type.getRank() == rank); 2641c81adf3SAart Bik int64_t v1Dim = v1Type.getDimSize(0); 2651c81adf3SAart Bik 2661c81adf3SAart Bik // For rank 1, where both operands have *exactly* the same vector type, 2671c81adf3SAart Bik // there is direct shuffle support in LLVM. Use it! 2681c81adf3SAart Bik if (rank == 1 && v1Type == v2Type) { 269e62a6956SRiver Riddle Value shuffle = rewriter.create<LLVM::ShuffleVectorOp>( 2701c81adf3SAart Bik loc, adaptor.v1(), adaptor.v2(), maskArrayAttr); 2711c81adf3SAart Bik rewriter.replaceOp(op, shuffle); 2721c81adf3SAart Bik return matchSuccess(); 273b36aaeafSAart Bik } 274b36aaeafSAart Bik 2751c81adf3SAart Bik // For all other cases, insert the individual values individually. 276e62a6956SRiver Riddle Value insert = rewriter.create<LLVM::UndefOp>(loc, llvmType); 2771c81adf3SAart Bik int64_t insPos = 0; 2781c81adf3SAart Bik for (auto en : llvm::enumerate(maskArrayAttr)) { 2791c81adf3SAart Bik int64_t extPos = en.value().cast<IntegerAttr>().getInt(); 280e62a6956SRiver Riddle Value value = adaptor.v1(); 2811c81adf3SAart Bik if (extPos >= v1Dim) { 2821c81adf3SAart Bik extPos -= v1Dim; 2831c81adf3SAart Bik value = adaptor.v2(); 284b36aaeafSAart Bik } 285e62a6956SRiver Riddle Value extract = 2861c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, extPos); 2871c81adf3SAart Bik insert = insertOne(rewriter, lowering, loc, insert, extract, llvmType, 2881c81adf3SAart Bik rank, insPos++); 2891c81adf3SAart Bik } 2901c81adf3SAart Bik rewriter.replaceOp(op, insert); 2911c81adf3SAart Bik return matchSuccess(); 292b36aaeafSAart Bik } 293b36aaeafSAart Bik }; 294b36aaeafSAart Bik 295cd5dab8aSAart Bik class VectorExtractElementOpConversion : public LLVMOpLowering { 296cd5dab8aSAart Bik public: 297cd5dab8aSAart Bik explicit VectorExtractElementOpConversion(MLIRContext *context, 298cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 299cd5dab8aSAart Bik : LLVMOpLowering(vector::ExtractElementOp::getOperationName(), context, 300cd5dab8aSAart Bik typeConverter) {} 301cd5dab8aSAart Bik 302cd5dab8aSAart Bik PatternMatchResult 303e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 304cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 305cd5dab8aSAart Bik auto adaptor = vector::ExtractElementOpOperandAdaptor(operands); 306cd5dab8aSAart Bik auto extractEltOp = cast<vector::ExtractElementOp>(op); 307cd5dab8aSAart Bik auto vectorType = extractEltOp.getVectorType(); 308cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType.getElementType()); 309cd5dab8aSAart Bik 310cd5dab8aSAart Bik // Bail if result type cannot be lowered. 311cd5dab8aSAart Bik if (!llvmType) 312cd5dab8aSAart Bik return matchFailure(); 313cd5dab8aSAart Bik 314cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::ExtractElementOp>( 315cd5dab8aSAart Bik op, llvmType, adaptor.vector(), adaptor.position()); 316cd5dab8aSAart Bik return matchSuccess(); 317cd5dab8aSAart Bik } 318cd5dab8aSAart Bik }; 319cd5dab8aSAart Bik 3209826fe5cSAart Bik class VectorExtractOpConversion : public LLVMOpLowering { 3215c0c51a9SNicolas Vasilache public: 3229826fe5cSAart Bik explicit VectorExtractOpConversion(MLIRContext *context, 3235c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 324d37f2725SAart Bik : LLVMOpLowering(vector::ExtractOp::getOperationName(), context, 3255c0c51a9SNicolas Vasilache typeConverter) {} 3265c0c51a9SNicolas Vasilache 3275c0c51a9SNicolas Vasilache PatternMatchResult 328e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 3295c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 3305c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 331d37f2725SAart Bik auto adaptor = vector::ExtractOpOperandAdaptor(operands); 332d37f2725SAart Bik auto extractOp = cast<vector::ExtractOp>(op); 3339826fe5cSAart Bik auto vectorType = extractOp.getVectorType(); 3345c0c51a9SNicolas Vasilache auto resultType = extractOp.getResult()->getType(); 3355c0c51a9SNicolas Vasilache auto llvmResultType = lowering.convertType(resultType); 3365c0c51a9SNicolas Vasilache auto positionArrayAttr = extractOp.position(); 3379826fe5cSAart Bik 3389826fe5cSAart Bik // Bail if result type cannot be lowered. 3399826fe5cSAart Bik if (!llvmResultType) 3409826fe5cSAart Bik return matchFailure(); 3419826fe5cSAart Bik 3425c0c51a9SNicolas Vasilache // One-shot extraction of vector from array (only requires extractvalue). 3435c0c51a9SNicolas Vasilache if (resultType.isa<VectorType>()) { 344e62a6956SRiver Riddle Value extracted = rewriter.create<LLVM::ExtractValueOp>( 3455c0c51a9SNicolas Vasilache loc, llvmResultType, adaptor.vector(), positionArrayAttr); 3465c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3475c0c51a9SNicolas Vasilache return matchSuccess(); 3485c0c51a9SNicolas Vasilache } 3495c0c51a9SNicolas Vasilache 3509826fe5cSAart Bik // Potential extraction of 1-D vector from array. 3515c0c51a9SNicolas Vasilache auto *context = op->getContext(); 352e62a6956SRiver Riddle Value extracted = adaptor.vector(); 3535c0c51a9SNicolas Vasilache auto positionAttrs = positionArrayAttr.getValue(); 3545c0c51a9SNicolas Vasilache if (positionAttrs.size() > 1) { 3559826fe5cSAart Bik auto oneDVectorType = reducedVectorTypeBack(vectorType); 3565c0c51a9SNicolas Vasilache auto nMinusOnePositionAttrs = 3575c0c51a9SNicolas Vasilache ArrayAttr::get(positionAttrs.drop_back(), context); 3585c0c51a9SNicolas Vasilache extracted = rewriter.create<LLVM::ExtractValueOp>( 3595c0c51a9SNicolas Vasilache loc, lowering.convertType(oneDVectorType), extracted, 3605c0c51a9SNicolas Vasilache nMinusOnePositionAttrs); 3615c0c51a9SNicolas Vasilache } 3625c0c51a9SNicolas Vasilache 3635c0c51a9SNicolas Vasilache // Remaining extraction of element from 1-D LLVM vector 3645c0c51a9SNicolas Vasilache auto position = positionAttrs.back().cast<IntegerAttr>(); 3651d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 3661d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 3675c0c51a9SNicolas Vasilache extracted = 3685c0c51a9SNicolas Vasilache rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant); 3695c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3705c0c51a9SNicolas Vasilache 3715c0c51a9SNicolas Vasilache return matchSuccess(); 3725c0c51a9SNicolas Vasilache } 3735c0c51a9SNicolas Vasilache }; 3745c0c51a9SNicolas Vasilache 375cd5dab8aSAart Bik class VectorInsertElementOpConversion : public LLVMOpLowering { 376cd5dab8aSAart Bik public: 377cd5dab8aSAart Bik explicit VectorInsertElementOpConversion(MLIRContext *context, 378cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 379cd5dab8aSAart Bik : LLVMOpLowering(vector::InsertElementOp::getOperationName(), context, 380cd5dab8aSAart Bik typeConverter) {} 381cd5dab8aSAart Bik 382cd5dab8aSAart Bik PatternMatchResult 383e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 384cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 385cd5dab8aSAart Bik auto adaptor = vector::InsertElementOpOperandAdaptor(operands); 386cd5dab8aSAart Bik auto insertEltOp = cast<vector::InsertElementOp>(op); 387cd5dab8aSAart Bik auto vectorType = insertEltOp.getDestVectorType(); 388cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType); 389cd5dab8aSAart Bik 390cd5dab8aSAart Bik // Bail if result type cannot be lowered. 391cd5dab8aSAart Bik if (!llvmType) 392cd5dab8aSAart Bik return matchFailure(); 393cd5dab8aSAart Bik 394cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::InsertElementOp>( 395cd5dab8aSAart Bik op, llvmType, adaptor.dest(), adaptor.source(), adaptor.position()); 396cd5dab8aSAart Bik return matchSuccess(); 397cd5dab8aSAart Bik } 398cd5dab8aSAart Bik }; 399cd5dab8aSAart Bik 4009826fe5cSAart Bik class VectorInsertOpConversion : public LLVMOpLowering { 4019826fe5cSAart Bik public: 4029826fe5cSAart Bik explicit VectorInsertOpConversion(MLIRContext *context, 4039826fe5cSAart Bik LLVMTypeConverter &typeConverter) 4049826fe5cSAart Bik : LLVMOpLowering(vector::InsertOp::getOperationName(), context, 4059826fe5cSAart Bik typeConverter) {} 4069826fe5cSAart Bik 4079826fe5cSAart Bik PatternMatchResult 408e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 4099826fe5cSAart Bik ConversionPatternRewriter &rewriter) const override { 4109826fe5cSAart Bik auto loc = op->getLoc(); 4119826fe5cSAart Bik auto adaptor = vector::InsertOpOperandAdaptor(operands); 4129826fe5cSAart Bik auto insertOp = cast<vector::InsertOp>(op); 4139826fe5cSAart Bik auto sourceType = insertOp.getSourceType(); 4149826fe5cSAart Bik auto destVectorType = insertOp.getDestVectorType(); 4159826fe5cSAart Bik auto llvmResultType = lowering.convertType(destVectorType); 4169826fe5cSAart Bik auto positionArrayAttr = insertOp.position(); 4179826fe5cSAart Bik 4189826fe5cSAart Bik // Bail if result type cannot be lowered. 4199826fe5cSAart Bik if (!llvmResultType) 4209826fe5cSAart Bik return matchFailure(); 4219826fe5cSAart Bik 4229826fe5cSAart Bik // One-shot insertion of a vector into an array (only requires insertvalue). 4239826fe5cSAart Bik if (sourceType.isa<VectorType>()) { 424e62a6956SRiver Riddle Value inserted = rewriter.create<LLVM::InsertValueOp>( 4259826fe5cSAart Bik loc, llvmResultType, adaptor.dest(), adaptor.source(), 4269826fe5cSAart Bik positionArrayAttr); 4279826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4289826fe5cSAart Bik return matchSuccess(); 4299826fe5cSAart Bik } 4309826fe5cSAart Bik 4319826fe5cSAart Bik // Potential extraction of 1-D vector from array. 4329826fe5cSAart Bik auto *context = op->getContext(); 433e62a6956SRiver Riddle Value extracted = adaptor.dest(); 4349826fe5cSAart Bik auto positionAttrs = positionArrayAttr.getValue(); 4359826fe5cSAart Bik auto position = positionAttrs.back().cast<IntegerAttr>(); 4369826fe5cSAart Bik auto oneDVectorType = destVectorType; 4379826fe5cSAart Bik if (positionAttrs.size() > 1) { 4389826fe5cSAart Bik oneDVectorType = reducedVectorTypeBack(destVectorType); 4399826fe5cSAart Bik auto nMinusOnePositionAttrs = 4409826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4419826fe5cSAart Bik extracted = rewriter.create<LLVM::ExtractValueOp>( 4429826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, 4439826fe5cSAart Bik nMinusOnePositionAttrs); 4449826fe5cSAart Bik } 4459826fe5cSAart Bik 4469826fe5cSAart Bik // Insertion of an element into a 1-D LLVM vector. 4471d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 4481d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 449e62a6956SRiver Riddle Value inserted = rewriter.create<LLVM::InsertElementOp>( 4509826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, adaptor.source(), 4519826fe5cSAart Bik constant); 4529826fe5cSAart Bik 4539826fe5cSAart Bik // Potential insertion of resulting 1-D vector into array. 4549826fe5cSAart Bik if (positionAttrs.size() > 1) { 4559826fe5cSAart Bik auto nMinusOnePositionAttrs = 4569826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4579826fe5cSAart Bik inserted = rewriter.create<LLVM::InsertValueOp>(loc, llvmResultType, 4589826fe5cSAart Bik adaptor.dest(), inserted, 4599826fe5cSAart Bik nMinusOnePositionAttrs); 4609826fe5cSAart Bik } 4619826fe5cSAart Bik 4629826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4639826fe5cSAart Bik return matchSuccess(); 4649826fe5cSAart Bik } 4659826fe5cSAart Bik }; 4669826fe5cSAart Bik 4675c0c51a9SNicolas Vasilache class VectorOuterProductOpConversion : public LLVMOpLowering { 4685c0c51a9SNicolas Vasilache public: 4695c0c51a9SNicolas Vasilache explicit VectorOuterProductOpConversion(MLIRContext *context, 4705c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 4715c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::OuterProductOp::getOperationName(), context, 4725c0c51a9SNicolas Vasilache typeConverter) {} 4735c0c51a9SNicolas Vasilache 4745c0c51a9SNicolas Vasilache PatternMatchResult 475e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 4765c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 4775c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 4785c0c51a9SNicolas Vasilache auto adaptor = vector::OuterProductOpOperandAdaptor(operands); 4795c0c51a9SNicolas Vasilache auto *ctx = op->getContext(); 4805c0c51a9SNicolas Vasilache auto vLHS = adaptor.lhs()->getType().cast<LLVM::LLVMType>(); 4815c0c51a9SNicolas Vasilache auto vRHS = adaptor.rhs()->getType().cast<LLVM::LLVMType>(); 4825c0c51a9SNicolas Vasilache auto rankLHS = vLHS.getUnderlyingType()->getVectorNumElements(); 4835c0c51a9SNicolas Vasilache auto rankRHS = vRHS.getUnderlyingType()->getVectorNumElements(); 4845c0c51a9SNicolas Vasilache auto llvmArrayOfVectType = lowering.convertType( 4855c0c51a9SNicolas Vasilache cast<vector::OuterProductOp>(op).getResult()->getType()); 486e62a6956SRiver Riddle Value desc = rewriter.create<LLVM::UndefOp>(loc, llvmArrayOfVectType); 487e62a6956SRiver Riddle Value a = adaptor.lhs(), b = adaptor.rhs(); 488e62a6956SRiver Riddle Value acc = adaptor.acc().empty() ? nullptr : adaptor.acc().front(); 489e62a6956SRiver Riddle SmallVector<Value, 8> lhs, accs; 4905c0c51a9SNicolas Vasilache lhs.reserve(rankLHS); 4915c0c51a9SNicolas Vasilache accs.reserve(rankLHS); 4925c0c51a9SNicolas Vasilache for (unsigned d = 0, e = rankLHS; d < e; ++d) { 4935c0c51a9SNicolas Vasilache // shufflevector explicitly requires i32. 4945c0c51a9SNicolas Vasilache auto attr = rewriter.getI32IntegerAttr(d); 4955c0c51a9SNicolas Vasilache SmallVector<Attribute, 4> bcastAttr(rankRHS, attr); 4965c0c51a9SNicolas Vasilache auto bcastArrayAttr = ArrayAttr::get(bcastAttr, ctx); 497e62a6956SRiver Riddle Value aD = nullptr, accD = nullptr; 4985c0c51a9SNicolas Vasilache // 1. Broadcast the element a[d] into vector aD. 4995c0c51a9SNicolas Vasilache aD = rewriter.create<LLVM::ShuffleVectorOp>(loc, a, a, bcastArrayAttr); 5005c0c51a9SNicolas Vasilache // 2. If acc is present, extract 1-d vector acc[d] into accD. 5015c0c51a9SNicolas Vasilache if (acc) 5025c0c51a9SNicolas Vasilache accD = rewriter.create<LLVM::ExtractValueOp>( 5035c0c51a9SNicolas Vasilache loc, vRHS, acc, rewriter.getI64ArrayAttr(d)); 5045c0c51a9SNicolas Vasilache // 3. Compute aD outer b (plus accD, if relevant). 505e62a6956SRiver Riddle Value aOuterbD = 5065c0c51a9SNicolas Vasilache accD ? rewriter.create<LLVM::FMulAddOp>(loc, vRHS, aD, b, accD) 5075c0c51a9SNicolas Vasilache .getResult() 5085c0c51a9SNicolas Vasilache : rewriter.create<LLVM::FMulOp>(loc, aD, b).getResult(); 5095c0c51a9SNicolas Vasilache // 4. Insert as value `d` in the descriptor. 5105c0c51a9SNicolas Vasilache desc = rewriter.create<LLVM::InsertValueOp>(loc, llvmArrayOfVectType, 5115c0c51a9SNicolas Vasilache desc, aOuterbD, 5125c0c51a9SNicolas Vasilache rewriter.getI64ArrayAttr(d)); 5135c0c51a9SNicolas Vasilache } 5145c0c51a9SNicolas Vasilache rewriter.replaceOp(op, desc); 5155c0c51a9SNicolas Vasilache return matchSuccess(); 5165c0c51a9SNicolas Vasilache } 5175c0c51a9SNicolas Vasilache }; 5185c0c51a9SNicolas Vasilache 5195c0c51a9SNicolas Vasilache class VectorTypeCastOpConversion : public LLVMOpLowering { 5205c0c51a9SNicolas Vasilache public: 5215c0c51a9SNicolas Vasilache explicit VectorTypeCastOpConversion(MLIRContext *context, 5225c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 5235c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::TypeCastOp::getOperationName(), context, 5245c0c51a9SNicolas Vasilache typeConverter) {} 5255c0c51a9SNicolas Vasilache 5265c0c51a9SNicolas Vasilache PatternMatchResult 527e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 5285c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 5295c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 5305c0c51a9SNicolas Vasilache vector::TypeCastOp castOp = cast<vector::TypeCastOp>(op); 5315c0c51a9SNicolas Vasilache MemRefType sourceMemRefType = 5325c0c51a9SNicolas Vasilache castOp.getOperand()->getType().cast<MemRefType>(); 5335c0c51a9SNicolas Vasilache MemRefType targetMemRefType = 5345c0c51a9SNicolas Vasilache castOp.getResult()->getType().cast<MemRefType>(); 5355c0c51a9SNicolas Vasilache 5365c0c51a9SNicolas Vasilache // Only static shape casts supported atm. 5375c0c51a9SNicolas Vasilache if (!sourceMemRefType.hasStaticShape() || 5385c0c51a9SNicolas Vasilache !targetMemRefType.hasStaticShape()) 5395c0c51a9SNicolas Vasilache return matchFailure(); 5405c0c51a9SNicolas Vasilache 5415c0c51a9SNicolas Vasilache auto llvmSourceDescriptorTy = 5425c0c51a9SNicolas Vasilache operands[0]->getType().dyn_cast<LLVM::LLVMType>(); 5435c0c51a9SNicolas Vasilache if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy()) 5445c0c51a9SNicolas Vasilache return matchFailure(); 5455c0c51a9SNicolas Vasilache MemRefDescriptor sourceMemRef(operands[0]); 5465c0c51a9SNicolas Vasilache 5475c0c51a9SNicolas Vasilache auto llvmTargetDescriptorTy = lowering.convertType(targetMemRefType) 5485c0c51a9SNicolas Vasilache .dyn_cast_or_null<LLVM::LLVMType>(); 5495c0c51a9SNicolas Vasilache if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy()) 5505c0c51a9SNicolas Vasilache return matchFailure(); 5515c0c51a9SNicolas Vasilache 5525c0c51a9SNicolas Vasilache int64_t offset; 5535c0c51a9SNicolas Vasilache SmallVector<int64_t, 4> strides; 5545c0c51a9SNicolas Vasilache auto successStrides = 5555c0c51a9SNicolas Vasilache getStridesAndOffset(sourceMemRefType, strides, offset); 5565c0c51a9SNicolas Vasilache bool isContiguous = (strides.back() == 1); 5575c0c51a9SNicolas Vasilache if (isContiguous) { 5585c0c51a9SNicolas Vasilache auto sizes = sourceMemRefType.getShape(); 5595c0c51a9SNicolas Vasilache for (int index = 0, e = strides.size() - 2; index < e; ++index) { 5605c0c51a9SNicolas Vasilache if (strides[index] != strides[index + 1] * sizes[index + 1]) { 5615c0c51a9SNicolas Vasilache isContiguous = false; 5625c0c51a9SNicolas Vasilache break; 5635c0c51a9SNicolas Vasilache } 5645c0c51a9SNicolas Vasilache } 5655c0c51a9SNicolas Vasilache } 5665c0c51a9SNicolas Vasilache // Only contiguous source tensors supported atm. 5675c0c51a9SNicolas Vasilache if (failed(successStrides) || !isContiguous) 5685c0c51a9SNicolas Vasilache return matchFailure(); 5695c0c51a9SNicolas Vasilache 5705c0c51a9SNicolas Vasilache auto int64Ty = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 5715c0c51a9SNicolas Vasilache 5725c0c51a9SNicolas Vasilache // Create descriptor. 5735c0c51a9SNicolas Vasilache auto desc = MemRefDescriptor::undef(rewriter, loc, llvmTargetDescriptorTy); 5745c0c51a9SNicolas Vasilache Type llvmTargetElementTy = desc.getElementType(); 5755c0c51a9SNicolas Vasilache // Set allocated ptr. 576e62a6956SRiver Riddle Value allocated = sourceMemRef.allocatedPtr(rewriter, loc); 5775c0c51a9SNicolas Vasilache allocated = 5785c0c51a9SNicolas Vasilache rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, allocated); 5795c0c51a9SNicolas Vasilache desc.setAllocatedPtr(rewriter, loc, allocated); 5805c0c51a9SNicolas Vasilache // Set aligned ptr. 581e62a6956SRiver Riddle Value ptr = sourceMemRef.alignedPtr(rewriter, loc); 5825c0c51a9SNicolas Vasilache ptr = rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, ptr); 5835c0c51a9SNicolas Vasilache desc.setAlignedPtr(rewriter, loc, ptr); 5845c0c51a9SNicolas Vasilache // Fill offset 0. 5855c0c51a9SNicolas Vasilache auto attr = rewriter.getIntegerAttr(rewriter.getIndexType(), 0); 5865c0c51a9SNicolas Vasilache auto zero = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, attr); 5875c0c51a9SNicolas Vasilache desc.setOffset(rewriter, loc, zero); 5885c0c51a9SNicolas Vasilache 5895c0c51a9SNicolas Vasilache // Fill size and stride descriptors in memref. 5905c0c51a9SNicolas Vasilache for (auto indexedSize : llvm::enumerate(targetMemRefType.getShape())) { 5915c0c51a9SNicolas Vasilache int64_t index = indexedSize.index(); 5925c0c51a9SNicolas Vasilache auto sizeAttr = 5935c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), indexedSize.value()); 5945c0c51a9SNicolas Vasilache auto size = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, sizeAttr); 5955c0c51a9SNicolas Vasilache desc.setSize(rewriter, loc, index, size); 5965c0c51a9SNicolas Vasilache auto strideAttr = 5975c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), strides[index]); 5985c0c51a9SNicolas Vasilache auto stride = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, strideAttr); 5995c0c51a9SNicolas Vasilache desc.setStride(rewriter, loc, index, stride); 6005c0c51a9SNicolas Vasilache } 6015c0c51a9SNicolas Vasilache 6025c0c51a9SNicolas Vasilache rewriter.replaceOp(op, {desc}); 6035c0c51a9SNicolas Vasilache return matchSuccess(); 6045c0c51a9SNicolas Vasilache } 6055c0c51a9SNicolas Vasilache }; 6065c0c51a9SNicolas Vasilache 607d9b500d3SAart Bik class VectorPrintOpConversion : public LLVMOpLowering { 608d9b500d3SAart Bik public: 609d9b500d3SAart Bik explicit VectorPrintOpConversion(MLIRContext *context, 610d9b500d3SAart Bik LLVMTypeConverter &typeConverter) 611d9b500d3SAart Bik : LLVMOpLowering(vector::PrintOp::getOperationName(), context, 612d9b500d3SAart Bik typeConverter) {} 613d9b500d3SAart Bik 614d9b500d3SAart Bik // Proof-of-concept lowering implementation that relies on a small 615d9b500d3SAart Bik // runtime support library, which only needs to provide a few 616d9b500d3SAart Bik // printing methods (single value for all data types, opening/closing 617d9b500d3SAart Bik // bracket, comma, newline). The lowering fully unrolls a vector 618d9b500d3SAart Bik // in terms of these elementary printing operations. The advantage 619d9b500d3SAart Bik // of this approach is that the library can remain unaware of all 620d9b500d3SAart Bik // low-level implementation details of vectors while still supporting 621d9b500d3SAart Bik // output of any shaped and dimensioned vector. Due to full unrolling, 622d9b500d3SAart Bik // this approach is less suited for very large vectors though. 623d9b500d3SAart Bik // 624d9b500d3SAart Bik // TODO(ajcbik): rely solely on libc in future? something else? 625d9b500d3SAart Bik // 626d9b500d3SAart Bik PatternMatchResult 627e62a6956SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<Value> operands, 628d9b500d3SAart Bik ConversionPatternRewriter &rewriter) const override { 629d9b500d3SAart Bik auto printOp = cast<vector::PrintOp>(op); 630d9b500d3SAart Bik auto adaptor = vector::PrintOpOperandAdaptor(operands); 631d9b500d3SAart Bik Type printType = printOp.getPrintType(); 632d9b500d3SAart Bik 633d9b500d3SAart Bik if (lowering.convertType(printType) == nullptr) 634d9b500d3SAart Bik return matchFailure(); 635d9b500d3SAart Bik 636d9b500d3SAart Bik // Make sure element type has runtime support (currently just Float/Double). 637d9b500d3SAart Bik VectorType vectorType = printType.dyn_cast<VectorType>(); 638d9b500d3SAart Bik Type eltType = vectorType ? vectorType.getElementType() : printType; 639d9b500d3SAart Bik int64_t rank = vectorType ? vectorType.getRank() : 0; 640d9b500d3SAart Bik Operation *printer; 641d9b500d3SAart Bik if (eltType.isF32()) 642d9b500d3SAart Bik printer = getPrintFloat(op); 643d9b500d3SAart Bik else if (eltType.isF64()) 644d9b500d3SAart Bik printer = getPrintDouble(op); 645d9b500d3SAart Bik else 646d9b500d3SAart Bik return matchFailure(); 647d9b500d3SAart Bik 648d9b500d3SAart Bik // Unroll vector into elementary print calls. 649d9b500d3SAart Bik emitRanks(rewriter, op, adaptor.source(), vectorType, printer, rank); 650d9b500d3SAart Bik emitCall(rewriter, op->getLoc(), getPrintNewline(op)); 651d9b500d3SAart Bik rewriter.eraseOp(op); 652d9b500d3SAart Bik return matchSuccess(); 653d9b500d3SAart Bik } 654d9b500d3SAart Bik 655d9b500d3SAart Bik private: 656d9b500d3SAart Bik void emitRanks(ConversionPatternRewriter &rewriter, Operation *op, 657e62a6956SRiver Riddle Value value, VectorType vectorType, Operation *printer, 658d9b500d3SAart Bik int64_t rank) const { 659d9b500d3SAart Bik Location loc = op->getLoc(); 660d9b500d3SAart Bik if (rank == 0) { 661d9b500d3SAart Bik emitCall(rewriter, loc, printer, value); 662d9b500d3SAart Bik return; 663d9b500d3SAart Bik } 664d9b500d3SAart Bik 665d9b500d3SAart Bik emitCall(rewriter, loc, getPrintOpen(op)); 666d9b500d3SAart Bik Operation *printComma = getPrintComma(op); 667d9b500d3SAart Bik int64_t dim = vectorType.getDimSize(0); 668d9b500d3SAart Bik for (int64_t d = 0; d < dim; ++d) { 669d9b500d3SAart Bik auto reducedType = 670d9b500d3SAart Bik rank > 1 ? reducedVectorTypeFront(vectorType) : nullptr; 671d9b500d3SAart Bik auto llvmType = lowering.convertType( 672d9b500d3SAart Bik rank > 1 ? reducedType : vectorType.getElementType()); 673e62a6956SRiver Riddle Value nestedVal = 674d9b500d3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, d); 675d9b500d3SAart Bik emitRanks(rewriter, op, nestedVal, reducedType, printer, rank - 1); 676d9b500d3SAart Bik if (d != dim - 1) 677d9b500d3SAart Bik emitCall(rewriter, loc, printComma); 678d9b500d3SAart Bik } 679d9b500d3SAart Bik emitCall(rewriter, loc, getPrintClose(op)); 680d9b500d3SAart Bik } 681d9b500d3SAart Bik 682d9b500d3SAart Bik // Helper to emit a call. 683d9b500d3SAart Bik static void emitCall(ConversionPatternRewriter &rewriter, Location loc, 684d9b500d3SAart Bik Operation *ref, ValueRange params = ValueRange()) { 685d9b500d3SAart Bik rewriter.create<LLVM::CallOp>(loc, ArrayRef<Type>{}, 686d9b500d3SAart Bik rewriter.getSymbolRefAttr(ref), params); 687d9b500d3SAart Bik } 688d9b500d3SAart Bik 689d9b500d3SAart Bik // Helper for printer method declaration (first hit) and lookup. 690d9b500d3SAart Bik static Operation *getPrint(Operation *op, LLVM::LLVMDialect *dialect, 691d9b500d3SAart Bik StringRef name, ArrayRef<LLVM::LLVMType> params) { 692d9b500d3SAart Bik auto module = op->getParentOfType<ModuleOp>(); 693d9b500d3SAart Bik auto func = module.lookupSymbol<LLVM::LLVMFuncOp>(name); 694d9b500d3SAart Bik if (func) 695d9b500d3SAart Bik return func; 696d9b500d3SAart Bik OpBuilder moduleBuilder(module.getBodyRegion()); 697d9b500d3SAart Bik return moduleBuilder.create<LLVM::LLVMFuncOp>( 698d9b500d3SAart Bik op->getLoc(), name, 699d9b500d3SAart Bik LLVM::LLVMType::getFunctionTy(LLVM::LLVMType::getVoidTy(dialect), 700d9b500d3SAart Bik params, /*isVarArg=*/false)); 701d9b500d3SAart Bik } 702d9b500d3SAart Bik 703d9b500d3SAart Bik // Helpers for method names. 704d9b500d3SAart Bik Operation *getPrintFloat(Operation *op) const { 705d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 706d9b500d3SAart Bik return getPrint(op, dialect, "print_f32", 707d9b500d3SAart Bik LLVM::LLVMType::getFloatTy(dialect)); 708d9b500d3SAart Bik } 709d9b500d3SAart Bik Operation *getPrintDouble(Operation *op) const { 710d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 711d9b500d3SAart Bik return getPrint(op, dialect, "print_f64", 712d9b500d3SAart Bik LLVM::LLVMType::getDoubleTy(dialect)); 713d9b500d3SAart Bik } 714d9b500d3SAart Bik Operation *getPrintOpen(Operation *op) const { 715d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_open", {}); 716d9b500d3SAart Bik } 717d9b500d3SAart Bik Operation *getPrintClose(Operation *op) const { 718d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_close", {}); 719d9b500d3SAart Bik } 720d9b500d3SAart Bik Operation *getPrintComma(Operation *op) const { 721d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_comma", {}); 722d9b500d3SAart Bik } 723d9b500d3SAart Bik Operation *getPrintNewline(Operation *op) const { 724d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_newline", {}); 725d9b500d3SAart Bik } 726d9b500d3SAart Bik }; 727d9b500d3SAart Bik 728*65678d93SNicolas Vasilache // TODO(rriddle): Better support for attribute subtype forwarding + slicing. 729*65678d93SNicolas Vasilache static SmallVector<int64_t, 4> getI64SubArray(ArrayAttr arrayAttr, 730*65678d93SNicolas Vasilache unsigned dropFront = 0, 731*65678d93SNicolas Vasilache unsigned dropBack = 0) { 732*65678d93SNicolas Vasilache assert(arrayAttr.size() > dropFront + dropBack && "Out of bounds"); 733*65678d93SNicolas Vasilache auto range = arrayAttr.getAsRange<IntegerAttr>(); 734*65678d93SNicolas Vasilache SmallVector<int64_t, 4> res; 735*65678d93SNicolas Vasilache res.reserve(arrayAttr.size() - dropFront - dropBack); 736*65678d93SNicolas Vasilache for (auto it = range.begin() + dropFront, eit = range.end() - dropBack; 737*65678d93SNicolas Vasilache it != eit; ++it) 738*65678d93SNicolas Vasilache res.push_back((*it).getValue().getSExtValue()); 739*65678d93SNicolas Vasilache return res; 740*65678d93SNicolas Vasilache } 741*65678d93SNicolas Vasilache 742*65678d93SNicolas Vasilache /// Emit the proper `ExtractOp` or `ExtractElementOp` depending on the rank 743*65678d93SNicolas Vasilache /// of `vector`. 744*65678d93SNicolas Vasilache static Value extractOne(PatternRewriter &rewriter, Location loc, Value vector, 745*65678d93SNicolas Vasilache int64_t offset) { 746*65678d93SNicolas Vasilache auto vectorType = vector.getType().cast<VectorType>(); 747*65678d93SNicolas Vasilache if (vectorType.getRank() > 1) 748*65678d93SNicolas Vasilache return rewriter.create<ExtractOp>(loc, vector, offset); 749*65678d93SNicolas Vasilache return rewriter.create<vector::ExtractElementOp>( 750*65678d93SNicolas Vasilache loc, vectorType.getElementType(), vector, 751*65678d93SNicolas Vasilache rewriter.create<ConstantIndexOp>(loc, offset)); 752*65678d93SNicolas Vasilache } 753*65678d93SNicolas Vasilache 754*65678d93SNicolas Vasilache /// Emit the proper `InsertOp` or `InsertElementOp` depending on the rank 755*65678d93SNicolas Vasilache /// of `vector`. 756*65678d93SNicolas Vasilache static Value insertOne(PatternRewriter &rewriter, Location loc, Value from, 757*65678d93SNicolas Vasilache Value into, int64_t offset) { 758*65678d93SNicolas Vasilache auto vectorType = into.getType().cast<VectorType>(); 759*65678d93SNicolas Vasilache if (vectorType.getRank() > 1) 760*65678d93SNicolas Vasilache return rewriter.create<InsertOp>(loc, from, into, offset); 761*65678d93SNicolas Vasilache return rewriter.create<vector::InsertElementOp>( 762*65678d93SNicolas Vasilache loc, vectorType, from, into, 763*65678d93SNicolas Vasilache rewriter.create<ConstantIndexOp>(loc, offset)); 764*65678d93SNicolas Vasilache } 765*65678d93SNicolas Vasilache 766*65678d93SNicolas Vasilache /// Progressive lowering of StridedSliceOp to either: 767*65678d93SNicolas Vasilache /// 1. extractelement + insertelement for the 1-D case 768*65678d93SNicolas Vasilache /// 2. extract + optional strided_slice + insert for the n-D case. 769*65678d93SNicolas Vasilache class VectorStridedSliceOpRewritePattern 770*65678d93SNicolas Vasilache : public OpRewritePattern<StridedSliceOp> { 771*65678d93SNicolas Vasilache public: 772*65678d93SNicolas Vasilache using OpRewritePattern<StridedSliceOp>::OpRewritePattern; 773*65678d93SNicolas Vasilache 774*65678d93SNicolas Vasilache PatternMatchResult matchAndRewrite(StridedSliceOp op, 775*65678d93SNicolas Vasilache PatternRewriter &rewriter) const override { 776*65678d93SNicolas Vasilache auto dstType = op.getResult().getType().cast<VectorType>(); 777*65678d93SNicolas Vasilache 778*65678d93SNicolas Vasilache assert(!op.offsets().getValue().empty() && "Unexpected empty offsets"); 779*65678d93SNicolas Vasilache 780*65678d93SNicolas Vasilache int64_t offset = 781*65678d93SNicolas Vasilache op.offsets().getValue().front().cast<IntegerAttr>().getInt(); 782*65678d93SNicolas Vasilache int64_t size = op.sizes().getValue().front().cast<IntegerAttr>().getInt(); 783*65678d93SNicolas Vasilache int64_t stride = 784*65678d93SNicolas Vasilache op.strides().getValue().front().cast<IntegerAttr>().getInt(); 785*65678d93SNicolas Vasilache 786*65678d93SNicolas Vasilache auto loc = op.getLoc(); 787*65678d93SNicolas Vasilache auto elemType = dstType.getElementType(); 788*65678d93SNicolas Vasilache assert(elemType.isIntOrIndexOrFloat()); 789*65678d93SNicolas Vasilache Value zero = rewriter.create<ConstantOp>(loc, elemType, 790*65678d93SNicolas Vasilache rewriter.getZeroAttr(elemType)); 791*65678d93SNicolas Vasilache Value res = rewriter.create<SplatOp>(loc, dstType, zero); 792*65678d93SNicolas Vasilache for (int64_t off = offset, e = offset + size * stride, idx = 0; off < e; 793*65678d93SNicolas Vasilache off += stride, ++idx) { 794*65678d93SNicolas Vasilache Value extracted = extractOne(rewriter, loc, op.vector(), off); 795*65678d93SNicolas Vasilache if (op.offsets().getValue().size() > 1) { 796*65678d93SNicolas Vasilache StridedSliceOp stridedSliceOp = rewriter.create<StridedSliceOp>( 797*65678d93SNicolas Vasilache loc, extracted, getI64SubArray(op.offsets(), /* dropFront=*/1), 798*65678d93SNicolas Vasilache getI64SubArray(op.sizes(), /* dropFront=*/1), 799*65678d93SNicolas Vasilache getI64SubArray(op.strides(), /* dropFront=*/1)); 800*65678d93SNicolas Vasilache // Call matchAndRewrite recursively from within the pattern. This 801*65678d93SNicolas Vasilache // circumvents the current limitation that a given pattern cannot 802*65678d93SNicolas Vasilache // be called multiple times by the PatternRewrite infrastructure (to 803*65678d93SNicolas Vasilache // avoid infinite recursion, but in this case, infinite recursion 804*65678d93SNicolas Vasilache // cannot happen because the rank is strictly decreasing). 805*65678d93SNicolas Vasilache // TODO(rriddle, nicolasvasilache) Implement something like a hook for 806*65678d93SNicolas Vasilache // a potential function that must decrease and allow the same pattern 807*65678d93SNicolas Vasilache // multiple times. 808*65678d93SNicolas Vasilache auto success = matchAndRewrite(stridedSliceOp, rewriter); 809*65678d93SNicolas Vasilache (void)success; 810*65678d93SNicolas Vasilache assert(success && "Unexpected failure"); 811*65678d93SNicolas Vasilache extracted = stridedSliceOp; 812*65678d93SNicolas Vasilache } 813*65678d93SNicolas Vasilache res = insertOne(rewriter, loc, extracted, res, idx); 814*65678d93SNicolas Vasilache } 815*65678d93SNicolas Vasilache rewriter.replaceOp(op, {res}); 816*65678d93SNicolas Vasilache return matchSuccess(); 817*65678d93SNicolas Vasilache } 818*65678d93SNicolas Vasilache }; 819*65678d93SNicolas Vasilache 8205c0c51a9SNicolas Vasilache /// Populate the given list with patterns that convert from Vector to LLVM. 8215c0c51a9SNicolas Vasilache void mlir::populateVectorToLLVMConversionPatterns( 8225c0c51a9SNicolas Vasilache LLVMTypeConverter &converter, OwningRewritePatternList &patterns) { 823*65678d93SNicolas Vasilache MLIRContext *ctx = converter.getDialect()->getContext(); 824*65678d93SNicolas Vasilache patterns.insert<VectorStridedSliceOpRewritePattern>(ctx); 8251c81adf3SAart Bik patterns.insert<VectorBroadcastOpConversion, VectorShuffleOpConversion, 826cd5dab8aSAart Bik VectorExtractElementOpConversion, VectorExtractOpConversion, 827cd5dab8aSAart Bik VectorInsertElementOpConversion, VectorInsertOpConversion, 828d9b500d3SAart Bik VectorOuterProductOpConversion, VectorTypeCastOpConversion, 829*65678d93SNicolas Vasilache VectorPrintOpConversion>(ctx, converter); 8305c0c51a9SNicolas Vasilache } 8315c0c51a9SNicolas Vasilache 8325c0c51a9SNicolas Vasilache namespace { 8335c0c51a9SNicolas Vasilache struct LowerVectorToLLVMPass : public ModulePass<LowerVectorToLLVMPass> { 8345c0c51a9SNicolas Vasilache void runOnModule() override; 8355c0c51a9SNicolas Vasilache }; 8365c0c51a9SNicolas Vasilache } // namespace 8375c0c51a9SNicolas Vasilache 8385c0c51a9SNicolas Vasilache void LowerVectorToLLVMPass::runOnModule() { 8395c0c51a9SNicolas Vasilache // Convert to the LLVM IR dialect using the converter defined above. 8405c0c51a9SNicolas Vasilache OwningRewritePatternList patterns; 8415c0c51a9SNicolas Vasilache LLVMTypeConverter converter(&getContext()); 8425c0c51a9SNicolas Vasilache populateVectorToLLVMConversionPatterns(converter, patterns); 8435c0c51a9SNicolas Vasilache populateStdToLLVMConversionPatterns(converter, patterns); 8445c0c51a9SNicolas Vasilache 8455c0c51a9SNicolas Vasilache ConversionTarget target(getContext()); 8465c0c51a9SNicolas Vasilache target.addLegalDialect<LLVM::LLVMDialect>(); 8475c0c51a9SNicolas Vasilache target.addDynamicallyLegalOp<FuncOp>( 8485c0c51a9SNicolas Vasilache [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); }); 8495c0c51a9SNicolas Vasilache if (failed( 8505c0c51a9SNicolas Vasilache applyPartialConversion(getModule(), target, patterns, &converter))) { 8515c0c51a9SNicolas Vasilache signalPassFailure(); 8525c0c51a9SNicolas Vasilache } 8535c0c51a9SNicolas Vasilache } 8545c0c51a9SNicolas Vasilache 8555c0c51a9SNicolas Vasilache OpPassBase<ModuleOp> *mlir::createLowerVectorToLLVMPass() { 8565c0c51a9SNicolas Vasilache return new LowerVectorToLLVMPass(); 8575c0c51a9SNicolas Vasilache } 8585c0c51a9SNicolas Vasilache 8595c0c51a9SNicolas Vasilache static PassRegistration<LowerVectorToLLVMPass> 8605c0c51a9SNicolas Vasilache pass("convert-vector-to-llvm", 8615c0c51a9SNicolas Vasilache "Lower the operations from the vector dialect into the LLVM dialect"); 862