15c0c51a9SNicolas Vasilache //===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===// 25c0c51a9SNicolas Vasilache // 3*56222a06SMehdi Amini // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions. 4*56222a06SMehdi Amini // See https://llvm.org/LICENSE.txt for license information. 5*56222a06SMehdi Amini // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 65c0c51a9SNicolas Vasilache // 7*56222a06SMehdi Amini //===----------------------------------------------------------------------===// 85c0c51a9SNicolas Vasilache 95c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 105c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h" 115c0c51a9SNicolas Vasilache #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 125c0c51a9SNicolas Vasilache #include "mlir/Dialect/LLVMIR/LLVMDialect.h" 135c0c51a9SNicolas Vasilache #include "mlir/Dialect/VectorOps/VectorOps.h" 145c0c51a9SNicolas Vasilache #include "mlir/IR/Attributes.h" 155c0c51a9SNicolas Vasilache #include "mlir/IR/Builders.h" 165c0c51a9SNicolas Vasilache #include "mlir/IR/MLIRContext.h" 175c0c51a9SNicolas Vasilache #include "mlir/IR/Module.h" 185c0c51a9SNicolas Vasilache #include "mlir/IR/Operation.h" 195c0c51a9SNicolas Vasilache #include "mlir/IR/PatternMatch.h" 205c0c51a9SNicolas Vasilache #include "mlir/IR/StandardTypes.h" 215c0c51a9SNicolas Vasilache #include "mlir/IR/Types.h" 225c0c51a9SNicolas Vasilache #include "mlir/Pass/Pass.h" 235c0c51a9SNicolas Vasilache #include "mlir/Pass/PassManager.h" 245c0c51a9SNicolas Vasilache #include "mlir/Transforms/DialectConversion.h" 255c0c51a9SNicolas Vasilache #include "mlir/Transforms/Passes.h" 265c0c51a9SNicolas Vasilache 275c0c51a9SNicolas Vasilache #include "llvm/IR/DerivedTypes.h" 285c0c51a9SNicolas Vasilache #include "llvm/IR/Module.h" 295c0c51a9SNicolas Vasilache #include "llvm/IR/Type.h" 305c0c51a9SNicolas Vasilache #include "llvm/Support/Allocator.h" 315c0c51a9SNicolas Vasilache #include "llvm/Support/ErrorHandling.h" 325c0c51a9SNicolas Vasilache 335c0c51a9SNicolas Vasilache using namespace mlir; 345c0c51a9SNicolas Vasilache 355c0c51a9SNicolas Vasilache template <typename T> 365c0c51a9SNicolas Vasilache static LLVM::LLVMType getPtrToElementType(T containerType, 375c0c51a9SNicolas Vasilache LLVMTypeConverter &lowering) { 385c0c51a9SNicolas Vasilache return lowering.convertType(containerType.getElementType()) 395c0c51a9SNicolas Vasilache .template cast<LLVM::LLVMType>() 405c0c51a9SNicolas Vasilache .getPointerTo(); 415c0c51a9SNicolas Vasilache } 425c0c51a9SNicolas Vasilache 439826fe5cSAart Bik // Helper to reduce vector type by one rank at front. 449826fe5cSAart Bik static VectorType reducedVectorTypeFront(VectorType tp) { 459826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 469826fe5cSAart Bik return VectorType::get(tp.getShape().drop_front(), tp.getElementType()); 479826fe5cSAart Bik } 489826fe5cSAart Bik 499826fe5cSAart Bik // Helper to reduce vector type by *all* but one rank at back. 509826fe5cSAart Bik static VectorType reducedVectorTypeBack(VectorType tp) { 519826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 529826fe5cSAart Bik return VectorType::get(tp.getShape().take_back(), tp.getElementType()); 539826fe5cSAart Bik } 549826fe5cSAart Bik 551c81adf3SAart Bik // Helper that picks the proper sequence for inserting. 5635807bc4SRiver Riddle static ValuePtr insertOne(ConversionPatternRewriter &rewriter, 5735807bc4SRiver Riddle LLVMTypeConverter &lowering, Location loc, 5835807bc4SRiver Riddle ValuePtr val1, ValuePtr val2, Type llvmType, 5935807bc4SRiver Riddle int64_t rank, int64_t pos) { 601c81adf3SAart Bik if (rank == 1) { 611c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 621c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 631c81adf3SAart Bik loc, lowering.convertType(idxType), 641c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 651c81adf3SAart Bik return rewriter.create<LLVM::InsertElementOp>(loc, llvmType, val1, val2, 661c81adf3SAart Bik constant); 671c81adf3SAart Bik } 681c81adf3SAart Bik return rewriter.create<LLVM::InsertValueOp>(loc, llvmType, val1, val2, 691c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 701c81adf3SAart Bik } 711c81adf3SAart Bik 721c81adf3SAart Bik // Helper that picks the proper sequence for extracting. 7335807bc4SRiver Riddle static ValuePtr extractOne(ConversionPatternRewriter &rewriter, 7435807bc4SRiver Riddle LLVMTypeConverter &lowering, Location loc, 7535807bc4SRiver Riddle ValuePtr val, Type llvmType, int64_t rank, 7635807bc4SRiver Riddle int64_t pos) { 771c81adf3SAart Bik if (rank == 1) { 781c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 791c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 801c81adf3SAart Bik loc, lowering.convertType(idxType), 811c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 821c81adf3SAart Bik return rewriter.create<LLVM::ExtractElementOp>(loc, llvmType, val, 831c81adf3SAart Bik constant); 841c81adf3SAart Bik } 851c81adf3SAart Bik return rewriter.create<LLVM::ExtractValueOp>(loc, llvmType, val, 861c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 871c81adf3SAart Bik } 881c81adf3SAart Bik 89b36aaeafSAart Bik class VectorBroadcastOpConversion : public LLVMOpLowering { 90b36aaeafSAart Bik public: 91b36aaeafSAart Bik explicit VectorBroadcastOpConversion(MLIRContext *context, 92b36aaeafSAart Bik LLVMTypeConverter &typeConverter) 93b36aaeafSAart Bik : LLVMOpLowering(vector::BroadcastOp::getOperationName(), context, 94b36aaeafSAart Bik typeConverter) {} 95b36aaeafSAart Bik 96b36aaeafSAart Bik PatternMatchResult 9735807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 98b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const override { 99b36aaeafSAart Bik auto broadcastOp = cast<vector::BroadcastOp>(op); 100b36aaeafSAart Bik VectorType dstVectorType = broadcastOp.getVectorType(); 101b36aaeafSAart Bik if (lowering.convertType(dstVectorType) == nullptr) 102b36aaeafSAart Bik return matchFailure(); 103b36aaeafSAart Bik // Rewrite when the full vector type can be lowered (which 104b36aaeafSAart Bik // implies all 'reduced' types can be lowered too). 1051c81adf3SAart Bik auto adaptor = vector::BroadcastOpOperandAdaptor(operands); 106b36aaeafSAart Bik VectorType srcVectorType = 107b36aaeafSAart Bik broadcastOp.getSourceType().dyn_cast<VectorType>(); 108b36aaeafSAart Bik rewriter.replaceOp( 1091c81adf3SAart Bik op, expandRanks(adaptor.source(), // source value to be expanded 110b36aaeafSAart Bik op->getLoc(), // location of original broadcast 111b36aaeafSAart Bik srcVectorType, dstVectorType, rewriter)); 112b36aaeafSAart Bik return matchSuccess(); 113b36aaeafSAart Bik } 114b36aaeafSAart Bik 115b36aaeafSAart Bik private: 116b36aaeafSAart Bik // Expands the given source value over all the ranks, as defined 117b36aaeafSAart Bik // by the source and destination type (a null source type denotes 118b36aaeafSAart Bik // expansion from a scalar value into a vector). 119b36aaeafSAart Bik // 120b36aaeafSAart Bik // TODO(ajcbik): consider replacing this one-pattern lowering 121b36aaeafSAart Bik // with a two-pattern lowering using other vector 122b36aaeafSAart Bik // ops once all insert/extract/shuffle operations 123b36aaeafSAart Bik // are available with lowering implemention. 124b36aaeafSAart Bik // 12535807bc4SRiver Riddle ValuePtr expandRanks(ValuePtr value, Location loc, VectorType srcVectorType, 126b36aaeafSAart Bik VectorType dstVectorType, 127b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 128b36aaeafSAart Bik assert((dstVectorType != nullptr) && "invalid result type in broadcast"); 129b36aaeafSAart Bik // Determine rank of source and destination. 130b36aaeafSAart Bik int64_t srcRank = srcVectorType ? srcVectorType.getRank() : 0; 131b36aaeafSAart Bik int64_t dstRank = dstVectorType.getRank(); 132b36aaeafSAart Bik int64_t curDim = dstVectorType.getDimSize(0); 133b36aaeafSAart Bik if (srcRank < dstRank) 134b36aaeafSAart Bik // Duplicate this rank. 135b36aaeafSAart Bik return duplicateOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 136b36aaeafSAart Bik curDim, rewriter); 137b36aaeafSAart Bik // If all trailing dimensions are the same, the broadcast consists of 138b36aaeafSAart Bik // simply passing through the source value and we are done. Otherwise, 139b36aaeafSAart Bik // any non-matching dimension forces a stretch along this rank. 140b36aaeafSAart Bik assert((srcVectorType != nullptr) && (srcRank > 0) && 141b36aaeafSAart Bik (srcRank == dstRank) && "invalid rank in broadcast"); 142b36aaeafSAart Bik for (int64_t r = 0; r < dstRank; r++) { 143b36aaeafSAart Bik if (srcVectorType.getDimSize(r) != dstVectorType.getDimSize(r)) { 144b36aaeafSAart Bik return stretchOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 145b36aaeafSAart Bik curDim, rewriter); 146b36aaeafSAart Bik } 147b36aaeafSAart Bik } 148b36aaeafSAart Bik return value; 149b36aaeafSAart Bik } 150b36aaeafSAart Bik 151b36aaeafSAart Bik // Picks the best way to duplicate a single rank. For the 1-D case, a 152b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion. For higher 153b36aaeafSAart Bik // dimensions, however, we need dim x insert-values on a new broadcast 154b36aaeafSAart Bik // with one less leading dimension, which will be lowered "recursively" 155b36aaeafSAart Bik // to matching LLVM IR. 156b36aaeafSAart Bik // For example: 157b36aaeafSAart Bik // v = broadcast s : f32 to vector<4x2xf32> 158b36aaeafSAart Bik // becomes: 159b36aaeafSAart Bik // x = broadcast s : f32 to vector<2xf32> 160b36aaeafSAart Bik // v = [x,x,x,x] 161b36aaeafSAart Bik // becomes: 162b36aaeafSAart Bik // x = [s,s] 163b36aaeafSAart Bik // v = [x,x,x,x] 16435807bc4SRiver Riddle ValuePtr duplicateOneRank(ValuePtr value, Location loc, 16535807bc4SRiver Riddle VectorType srcVectorType, VectorType dstVectorType, 16635807bc4SRiver Riddle int64_t rank, int64_t dim, 167b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 168b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 169b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 170b36aaeafSAart Bik if (rank == 1) { 17135807bc4SRiver Riddle ValuePtr undef = rewriter.create<LLVM::UndefOp>(loc, llvmType); 17235807bc4SRiver Riddle ValuePtr expand = 1731c81adf3SAart Bik insertOne(rewriter, lowering, loc, undef, value, llvmType, rank, 0); 174b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 175b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 176b36aaeafSAart Bik loc, expand, undef, rewriter.getI32ArrayAttr(zeroValues)); 177b36aaeafSAart Bik } 17835807bc4SRiver Riddle ValuePtr expand = 1799826fe5cSAart Bik expandRanks(value, loc, srcVectorType, 1809826fe5cSAart Bik reducedVectorTypeFront(dstVectorType), rewriter); 18135807bc4SRiver Riddle ValuePtr result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 182b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 1831c81adf3SAart Bik result = 1841c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 185b36aaeafSAart Bik } 186b36aaeafSAart Bik return result; 187b36aaeafSAart Bik } 188b36aaeafSAart Bik 189b36aaeafSAart Bik // Picks the best way to stretch a single rank. For the 1-D case, a 190b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion when at 191b36aaeafSAart Bik // a stretch. Otherwise, every dimension needs to be expanded 192b36aaeafSAart Bik // individually and individually inserted in the resulting vector. 193b36aaeafSAart Bik // For example: 194b36aaeafSAart Bik // v = broadcast w : vector<4x1x2xf32> to vector<4x2x2xf32> 195b36aaeafSAart Bik // becomes: 196b36aaeafSAart Bik // a = broadcast w[0] : vector<1x2xf32> to vector<2x2xf32> 197b36aaeafSAart Bik // b = broadcast w[1] : vector<1x2xf32> to vector<2x2xf32> 198b36aaeafSAart Bik // c = broadcast w[2] : vector<1x2xf32> to vector<2x2xf32> 199b36aaeafSAart Bik // d = broadcast w[3] : vector<1x2xf32> to vector<2x2xf32> 200b36aaeafSAart Bik // v = [a,b,c,d] 201b36aaeafSAart Bik // becomes: 202b36aaeafSAart Bik // x = broadcast w[0][0] : vector<2xf32> to vector <2x2xf32> 203b36aaeafSAart Bik // y = broadcast w[1][0] : vector<2xf32> to vector <2x2xf32> 204b36aaeafSAart Bik // a = [x, y] 205b36aaeafSAart Bik // etc. 20635807bc4SRiver Riddle ValuePtr stretchOneRank(ValuePtr value, Location loc, 20735807bc4SRiver Riddle VectorType srcVectorType, VectorType dstVectorType, 20835807bc4SRiver Riddle int64_t rank, int64_t dim, 209b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 210b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 211b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 21235807bc4SRiver Riddle ValuePtr result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 213b36aaeafSAart Bik bool atStretch = dim != srcVectorType.getDimSize(0); 214b36aaeafSAart Bik if (rank == 1) { 2151c81adf3SAart Bik assert(atStretch); 216b36aaeafSAart Bik Type redLlvmType = lowering.convertType(dstVectorType.getElementType()); 21735807bc4SRiver Riddle ValuePtr one = 2181c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, 0); 21935807bc4SRiver Riddle ValuePtr expand = 2201c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, one, llvmType, rank, 0); 221b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 222b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 223b36aaeafSAart Bik loc, expand, result, rewriter.getI32ArrayAttr(zeroValues)); 224b36aaeafSAart Bik } 2259826fe5cSAart Bik VectorType redSrcType = reducedVectorTypeFront(srcVectorType); 2269826fe5cSAart Bik VectorType redDstType = reducedVectorTypeFront(dstVectorType); 227b36aaeafSAart Bik Type redLlvmType = lowering.convertType(redSrcType); 228b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 229b36aaeafSAart Bik int64_t pos = atStretch ? 0 : d; 23035807bc4SRiver Riddle ValuePtr one = 2311c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, pos); 23235807bc4SRiver Riddle ValuePtr expand = expandRanks(one, loc, redSrcType, redDstType, rewriter); 2331c81adf3SAart Bik result = 2341c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 235b36aaeafSAart Bik } 236b36aaeafSAart Bik return result; 237b36aaeafSAart Bik } 2381c81adf3SAart Bik }; 239b36aaeafSAart Bik 2401c81adf3SAart Bik class VectorShuffleOpConversion : public LLVMOpLowering { 2411c81adf3SAart Bik public: 2421c81adf3SAart Bik explicit VectorShuffleOpConversion(MLIRContext *context, 2431c81adf3SAart Bik LLVMTypeConverter &typeConverter) 2441c81adf3SAart Bik : LLVMOpLowering(vector::ShuffleOp::getOperationName(), context, 2451c81adf3SAart Bik typeConverter) {} 2461c81adf3SAart Bik 2471c81adf3SAart Bik PatternMatchResult 24835807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 2491c81adf3SAart Bik ConversionPatternRewriter &rewriter) const override { 2501c81adf3SAart Bik auto loc = op->getLoc(); 2511c81adf3SAart Bik auto adaptor = vector::ShuffleOpOperandAdaptor(operands); 2521c81adf3SAart Bik auto shuffleOp = cast<vector::ShuffleOp>(op); 2531c81adf3SAart Bik auto v1Type = shuffleOp.getV1VectorType(); 2541c81adf3SAart Bik auto v2Type = shuffleOp.getV2VectorType(); 2551c81adf3SAart Bik auto vectorType = shuffleOp.getVectorType(); 2561c81adf3SAart Bik Type llvmType = lowering.convertType(vectorType); 2571c81adf3SAart Bik auto maskArrayAttr = shuffleOp.mask(); 2581c81adf3SAart Bik 2591c81adf3SAart Bik // Bail if result type cannot be lowered. 2601c81adf3SAart Bik if (!llvmType) 2611c81adf3SAart Bik return matchFailure(); 2621c81adf3SAart Bik 2631c81adf3SAart Bik // Get rank and dimension sizes. 2641c81adf3SAart Bik int64_t rank = vectorType.getRank(); 2651c81adf3SAart Bik assert(v1Type.getRank() == rank); 2661c81adf3SAart Bik assert(v2Type.getRank() == rank); 2671c81adf3SAart Bik int64_t v1Dim = v1Type.getDimSize(0); 2681c81adf3SAart Bik 2691c81adf3SAart Bik // For rank 1, where both operands have *exactly* the same vector type, 2701c81adf3SAart Bik // there is direct shuffle support in LLVM. Use it! 2711c81adf3SAart Bik if (rank == 1 && v1Type == v2Type) { 27235807bc4SRiver Riddle ValuePtr shuffle = rewriter.create<LLVM::ShuffleVectorOp>( 2731c81adf3SAart Bik loc, adaptor.v1(), adaptor.v2(), maskArrayAttr); 2741c81adf3SAart Bik rewriter.replaceOp(op, shuffle); 2751c81adf3SAart Bik return matchSuccess(); 276b36aaeafSAart Bik } 277b36aaeafSAart Bik 2781c81adf3SAart Bik // For all other cases, insert the individual values individually. 27935807bc4SRiver Riddle ValuePtr insert = rewriter.create<LLVM::UndefOp>(loc, llvmType); 2801c81adf3SAart Bik int64_t insPos = 0; 2811c81adf3SAart Bik for (auto en : llvm::enumerate(maskArrayAttr)) { 2821c81adf3SAart Bik int64_t extPos = en.value().cast<IntegerAttr>().getInt(); 28335807bc4SRiver Riddle ValuePtr value = adaptor.v1(); 2841c81adf3SAart Bik if (extPos >= v1Dim) { 2851c81adf3SAart Bik extPos -= v1Dim; 2861c81adf3SAart Bik value = adaptor.v2(); 287b36aaeafSAart Bik } 28835807bc4SRiver Riddle ValuePtr extract = 2891c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, extPos); 2901c81adf3SAart Bik insert = insertOne(rewriter, lowering, loc, insert, extract, llvmType, 2911c81adf3SAart Bik rank, insPos++); 2921c81adf3SAart Bik } 2931c81adf3SAart Bik rewriter.replaceOp(op, insert); 2941c81adf3SAart Bik return matchSuccess(); 295b36aaeafSAart Bik } 296b36aaeafSAart Bik }; 297b36aaeafSAart Bik 298cd5dab8aSAart Bik class VectorExtractElementOpConversion : public LLVMOpLowering { 299cd5dab8aSAart Bik public: 300cd5dab8aSAart Bik explicit VectorExtractElementOpConversion(MLIRContext *context, 301cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 302cd5dab8aSAart Bik : LLVMOpLowering(vector::ExtractElementOp::getOperationName(), context, 303cd5dab8aSAart Bik typeConverter) {} 304cd5dab8aSAart Bik 305cd5dab8aSAart Bik PatternMatchResult 30635807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 307cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 308cd5dab8aSAart Bik auto adaptor = vector::ExtractElementOpOperandAdaptor(operands); 309cd5dab8aSAart Bik auto extractEltOp = cast<vector::ExtractElementOp>(op); 310cd5dab8aSAart Bik auto vectorType = extractEltOp.getVectorType(); 311cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType.getElementType()); 312cd5dab8aSAart Bik 313cd5dab8aSAart Bik // Bail if result type cannot be lowered. 314cd5dab8aSAart Bik if (!llvmType) 315cd5dab8aSAart Bik return matchFailure(); 316cd5dab8aSAart Bik 317cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::ExtractElementOp>( 318cd5dab8aSAart Bik op, llvmType, adaptor.vector(), adaptor.position()); 319cd5dab8aSAart Bik return matchSuccess(); 320cd5dab8aSAart Bik } 321cd5dab8aSAart Bik }; 322cd5dab8aSAart Bik 3239826fe5cSAart Bik class VectorExtractOpConversion : public LLVMOpLowering { 3245c0c51a9SNicolas Vasilache public: 3259826fe5cSAart Bik explicit VectorExtractOpConversion(MLIRContext *context, 3265c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 327d37f2725SAart Bik : LLVMOpLowering(vector::ExtractOp::getOperationName(), context, 3285c0c51a9SNicolas Vasilache typeConverter) {} 3295c0c51a9SNicolas Vasilache 3305c0c51a9SNicolas Vasilache PatternMatchResult 33135807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 3325c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 3335c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 334d37f2725SAart Bik auto adaptor = vector::ExtractOpOperandAdaptor(operands); 335d37f2725SAart Bik auto extractOp = cast<vector::ExtractOp>(op); 3369826fe5cSAart Bik auto vectorType = extractOp.getVectorType(); 3375c0c51a9SNicolas Vasilache auto resultType = extractOp.getResult()->getType(); 3385c0c51a9SNicolas Vasilache auto llvmResultType = lowering.convertType(resultType); 3395c0c51a9SNicolas Vasilache auto positionArrayAttr = extractOp.position(); 3409826fe5cSAart Bik 3419826fe5cSAart Bik // Bail if result type cannot be lowered. 3429826fe5cSAart Bik if (!llvmResultType) 3439826fe5cSAart Bik return matchFailure(); 3449826fe5cSAart Bik 3455c0c51a9SNicolas Vasilache // One-shot extraction of vector from array (only requires extractvalue). 3465c0c51a9SNicolas Vasilache if (resultType.isa<VectorType>()) { 34735807bc4SRiver Riddle ValuePtr extracted = rewriter.create<LLVM::ExtractValueOp>( 3485c0c51a9SNicolas Vasilache loc, llvmResultType, adaptor.vector(), positionArrayAttr); 3495c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3505c0c51a9SNicolas Vasilache return matchSuccess(); 3515c0c51a9SNicolas Vasilache } 3525c0c51a9SNicolas Vasilache 3539826fe5cSAart Bik // Potential extraction of 1-D vector from array. 3545c0c51a9SNicolas Vasilache auto *context = op->getContext(); 35535807bc4SRiver Riddle ValuePtr extracted = adaptor.vector(); 3565c0c51a9SNicolas Vasilache auto positionAttrs = positionArrayAttr.getValue(); 3575c0c51a9SNicolas Vasilache if (positionAttrs.size() > 1) { 3589826fe5cSAart Bik auto oneDVectorType = reducedVectorTypeBack(vectorType); 3595c0c51a9SNicolas Vasilache auto nMinusOnePositionAttrs = 3605c0c51a9SNicolas Vasilache ArrayAttr::get(positionAttrs.drop_back(), context); 3615c0c51a9SNicolas Vasilache extracted = rewriter.create<LLVM::ExtractValueOp>( 3625c0c51a9SNicolas Vasilache loc, lowering.convertType(oneDVectorType), extracted, 3635c0c51a9SNicolas Vasilache nMinusOnePositionAttrs); 3645c0c51a9SNicolas Vasilache } 3655c0c51a9SNicolas Vasilache 3665c0c51a9SNicolas Vasilache // Remaining extraction of element from 1-D LLVM vector 3675c0c51a9SNicolas Vasilache auto position = positionAttrs.back().cast<IntegerAttr>(); 3681d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 3691d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 3705c0c51a9SNicolas Vasilache extracted = 3715c0c51a9SNicolas Vasilache rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant); 3725c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3735c0c51a9SNicolas Vasilache 3745c0c51a9SNicolas Vasilache return matchSuccess(); 3755c0c51a9SNicolas Vasilache } 3765c0c51a9SNicolas Vasilache }; 3775c0c51a9SNicolas Vasilache 378cd5dab8aSAart Bik class VectorInsertElementOpConversion : public LLVMOpLowering { 379cd5dab8aSAart Bik public: 380cd5dab8aSAart Bik explicit VectorInsertElementOpConversion(MLIRContext *context, 381cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 382cd5dab8aSAart Bik : LLVMOpLowering(vector::InsertElementOp::getOperationName(), context, 383cd5dab8aSAart Bik typeConverter) {} 384cd5dab8aSAart Bik 385cd5dab8aSAart Bik PatternMatchResult 38635807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 387cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 388cd5dab8aSAart Bik auto adaptor = vector::InsertElementOpOperandAdaptor(operands); 389cd5dab8aSAart Bik auto insertEltOp = cast<vector::InsertElementOp>(op); 390cd5dab8aSAart Bik auto vectorType = insertEltOp.getDestVectorType(); 391cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType); 392cd5dab8aSAart Bik 393cd5dab8aSAart Bik // Bail if result type cannot be lowered. 394cd5dab8aSAart Bik if (!llvmType) 395cd5dab8aSAart Bik return matchFailure(); 396cd5dab8aSAart Bik 397cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::InsertElementOp>( 398cd5dab8aSAart Bik op, llvmType, adaptor.dest(), adaptor.source(), adaptor.position()); 399cd5dab8aSAart Bik return matchSuccess(); 400cd5dab8aSAart Bik } 401cd5dab8aSAart Bik }; 402cd5dab8aSAart Bik 4039826fe5cSAart Bik class VectorInsertOpConversion : public LLVMOpLowering { 4049826fe5cSAart Bik public: 4059826fe5cSAart Bik explicit VectorInsertOpConversion(MLIRContext *context, 4069826fe5cSAart Bik LLVMTypeConverter &typeConverter) 4079826fe5cSAart Bik : LLVMOpLowering(vector::InsertOp::getOperationName(), context, 4089826fe5cSAart Bik typeConverter) {} 4099826fe5cSAart Bik 4109826fe5cSAart Bik PatternMatchResult 41135807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 4129826fe5cSAart Bik ConversionPatternRewriter &rewriter) const override { 4139826fe5cSAart Bik auto loc = op->getLoc(); 4149826fe5cSAart Bik auto adaptor = vector::InsertOpOperandAdaptor(operands); 4159826fe5cSAart Bik auto insertOp = cast<vector::InsertOp>(op); 4169826fe5cSAart Bik auto sourceType = insertOp.getSourceType(); 4179826fe5cSAart Bik auto destVectorType = insertOp.getDestVectorType(); 4189826fe5cSAart Bik auto llvmResultType = lowering.convertType(destVectorType); 4199826fe5cSAart Bik auto positionArrayAttr = insertOp.position(); 4209826fe5cSAart Bik 4219826fe5cSAart Bik // Bail if result type cannot be lowered. 4229826fe5cSAart Bik if (!llvmResultType) 4239826fe5cSAart Bik return matchFailure(); 4249826fe5cSAart Bik 4259826fe5cSAart Bik // One-shot insertion of a vector into an array (only requires insertvalue). 4269826fe5cSAart Bik if (sourceType.isa<VectorType>()) { 42735807bc4SRiver Riddle ValuePtr inserted = rewriter.create<LLVM::InsertValueOp>( 4289826fe5cSAart Bik loc, llvmResultType, adaptor.dest(), adaptor.source(), 4299826fe5cSAart Bik positionArrayAttr); 4309826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4319826fe5cSAart Bik return matchSuccess(); 4329826fe5cSAart Bik } 4339826fe5cSAart Bik 4349826fe5cSAart Bik // Potential extraction of 1-D vector from array. 4359826fe5cSAart Bik auto *context = op->getContext(); 43635807bc4SRiver Riddle ValuePtr extracted = adaptor.dest(); 4379826fe5cSAart Bik auto positionAttrs = positionArrayAttr.getValue(); 4389826fe5cSAart Bik auto position = positionAttrs.back().cast<IntegerAttr>(); 4399826fe5cSAart Bik auto oneDVectorType = destVectorType; 4409826fe5cSAart Bik if (positionAttrs.size() > 1) { 4419826fe5cSAart Bik oneDVectorType = reducedVectorTypeBack(destVectorType); 4429826fe5cSAart Bik auto nMinusOnePositionAttrs = 4439826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4449826fe5cSAart Bik extracted = rewriter.create<LLVM::ExtractValueOp>( 4459826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, 4469826fe5cSAart Bik nMinusOnePositionAttrs); 4479826fe5cSAart Bik } 4489826fe5cSAart Bik 4499826fe5cSAart Bik // Insertion of an element into a 1-D LLVM vector. 4501d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 4511d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 45235807bc4SRiver Riddle ValuePtr inserted = rewriter.create<LLVM::InsertElementOp>( 4539826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, adaptor.source(), 4549826fe5cSAart Bik constant); 4559826fe5cSAart Bik 4569826fe5cSAart Bik // Potential insertion of resulting 1-D vector into array. 4579826fe5cSAart Bik if (positionAttrs.size() > 1) { 4589826fe5cSAart Bik auto nMinusOnePositionAttrs = 4599826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4609826fe5cSAart Bik inserted = rewriter.create<LLVM::InsertValueOp>(loc, llvmResultType, 4619826fe5cSAart Bik adaptor.dest(), inserted, 4629826fe5cSAart Bik nMinusOnePositionAttrs); 4639826fe5cSAart Bik } 4649826fe5cSAart Bik 4659826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4669826fe5cSAart Bik return matchSuccess(); 4679826fe5cSAart Bik } 4689826fe5cSAart Bik }; 4699826fe5cSAart Bik 4705c0c51a9SNicolas Vasilache class VectorOuterProductOpConversion : public LLVMOpLowering { 4715c0c51a9SNicolas Vasilache public: 4725c0c51a9SNicolas Vasilache explicit VectorOuterProductOpConversion(MLIRContext *context, 4735c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 4745c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::OuterProductOp::getOperationName(), context, 4755c0c51a9SNicolas Vasilache typeConverter) {} 4765c0c51a9SNicolas Vasilache 4775c0c51a9SNicolas Vasilache PatternMatchResult 47835807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 4795c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 4805c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 4815c0c51a9SNicolas Vasilache auto adaptor = vector::OuterProductOpOperandAdaptor(operands); 4825c0c51a9SNicolas Vasilache auto *ctx = op->getContext(); 4835c0c51a9SNicolas Vasilache auto vLHS = adaptor.lhs()->getType().cast<LLVM::LLVMType>(); 4845c0c51a9SNicolas Vasilache auto vRHS = adaptor.rhs()->getType().cast<LLVM::LLVMType>(); 4855c0c51a9SNicolas Vasilache auto rankLHS = vLHS.getUnderlyingType()->getVectorNumElements(); 4865c0c51a9SNicolas Vasilache auto rankRHS = vRHS.getUnderlyingType()->getVectorNumElements(); 4875c0c51a9SNicolas Vasilache auto llvmArrayOfVectType = lowering.convertType( 4885c0c51a9SNicolas Vasilache cast<vector::OuterProductOp>(op).getResult()->getType()); 48935807bc4SRiver Riddle ValuePtr desc = rewriter.create<LLVM::UndefOp>(loc, llvmArrayOfVectType); 49035807bc4SRiver Riddle ValuePtr a = adaptor.lhs(), b = adaptor.rhs(); 49135807bc4SRiver Riddle ValuePtr acc = adaptor.acc().empty() ? nullptr : adaptor.acc().front(); 49235807bc4SRiver Riddle SmallVector<ValuePtr, 8> lhs, accs; 4935c0c51a9SNicolas Vasilache lhs.reserve(rankLHS); 4945c0c51a9SNicolas Vasilache accs.reserve(rankLHS); 4955c0c51a9SNicolas Vasilache for (unsigned d = 0, e = rankLHS; d < e; ++d) { 4965c0c51a9SNicolas Vasilache // shufflevector explicitly requires i32. 4975c0c51a9SNicolas Vasilache auto attr = rewriter.getI32IntegerAttr(d); 4985c0c51a9SNicolas Vasilache SmallVector<Attribute, 4> bcastAttr(rankRHS, attr); 4995c0c51a9SNicolas Vasilache auto bcastArrayAttr = ArrayAttr::get(bcastAttr, ctx); 50035807bc4SRiver Riddle ValuePtr aD = nullptr, accD = nullptr; 5015c0c51a9SNicolas Vasilache // 1. Broadcast the element a[d] into vector aD. 5025c0c51a9SNicolas Vasilache aD = rewriter.create<LLVM::ShuffleVectorOp>(loc, a, a, bcastArrayAttr); 5035c0c51a9SNicolas Vasilache // 2. If acc is present, extract 1-d vector acc[d] into accD. 5045c0c51a9SNicolas Vasilache if (acc) 5055c0c51a9SNicolas Vasilache accD = rewriter.create<LLVM::ExtractValueOp>( 5065c0c51a9SNicolas Vasilache loc, vRHS, acc, rewriter.getI64ArrayAttr(d)); 5075c0c51a9SNicolas Vasilache // 3. Compute aD outer b (plus accD, if relevant). 50835807bc4SRiver Riddle ValuePtr aOuterbD = 5095c0c51a9SNicolas Vasilache accD ? rewriter.create<LLVM::FMulAddOp>(loc, vRHS, aD, b, accD) 5105c0c51a9SNicolas Vasilache .getResult() 5115c0c51a9SNicolas Vasilache : rewriter.create<LLVM::FMulOp>(loc, aD, b).getResult(); 5125c0c51a9SNicolas Vasilache // 4. Insert as value `d` in the descriptor. 5135c0c51a9SNicolas Vasilache desc = rewriter.create<LLVM::InsertValueOp>(loc, llvmArrayOfVectType, 5145c0c51a9SNicolas Vasilache desc, aOuterbD, 5155c0c51a9SNicolas Vasilache rewriter.getI64ArrayAttr(d)); 5165c0c51a9SNicolas Vasilache } 5175c0c51a9SNicolas Vasilache rewriter.replaceOp(op, desc); 5185c0c51a9SNicolas Vasilache return matchSuccess(); 5195c0c51a9SNicolas Vasilache } 5205c0c51a9SNicolas Vasilache }; 5215c0c51a9SNicolas Vasilache 5225c0c51a9SNicolas Vasilache class VectorTypeCastOpConversion : public LLVMOpLowering { 5235c0c51a9SNicolas Vasilache public: 5245c0c51a9SNicolas Vasilache explicit VectorTypeCastOpConversion(MLIRContext *context, 5255c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 5265c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::TypeCastOp::getOperationName(), context, 5275c0c51a9SNicolas Vasilache typeConverter) {} 5285c0c51a9SNicolas Vasilache 5295c0c51a9SNicolas Vasilache PatternMatchResult 53035807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 5315c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 5325c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 5335c0c51a9SNicolas Vasilache vector::TypeCastOp castOp = cast<vector::TypeCastOp>(op); 5345c0c51a9SNicolas Vasilache MemRefType sourceMemRefType = 5355c0c51a9SNicolas Vasilache castOp.getOperand()->getType().cast<MemRefType>(); 5365c0c51a9SNicolas Vasilache MemRefType targetMemRefType = 5375c0c51a9SNicolas Vasilache castOp.getResult()->getType().cast<MemRefType>(); 5385c0c51a9SNicolas Vasilache 5395c0c51a9SNicolas Vasilache // Only static shape casts supported atm. 5405c0c51a9SNicolas Vasilache if (!sourceMemRefType.hasStaticShape() || 5415c0c51a9SNicolas Vasilache !targetMemRefType.hasStaticShape()) 5425c0c51a9SNicolas Vasilache return matchFailure(); 5435c0c51a9SNicolas Vasilache 5445c0c51a9SNicolas Vasilache auto llvmSourceDescriptorTy = 5455c0c51a9SNicolas Vasilache operands[0]->getType().dyn_cast<LLVM::LLVMType>(); 5465c0c51a9SNicolas Vasilache if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy()) 5475c0c51a9SNicolas Vasilache return matchFailure(); 5485c0c51a9SNicolas Vasilache MemRefDescriptor sourceMemRef(operands[0]); 5495c0c51a9SNicolas Vasilache 5505c0c51a9SNicolas Vasilache auto llvmTargetDescriptorTy = lowering.convertType(targetMemRefType) 5515c0c51a9SNicolas Vasilache .dyn_cast_or_null<LLVM::LLVMType>(); 5525c0c51a9SNicolas Vasilache if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy()) 5535c0c51a9SNicolas Vasilache return matchFailure(); 5545c0c51a9SNicolas Vasilache 5555c0c51a9SNicolas Vasilache int64_t offset; 5565c0c51a9SNicolas Vasilache SmallVector<int64_t, 4> strides; 5575c0c51a9SNicolas Vasilache auto successStrides = 5585c0c51a9SNicolas Vasilache getStridesAndOffset(sourceMemRefType, strides, offset); 5595c0c51a9SNicolas Vasilache bool isContiguous = (strides.back() == 1); 5605c0c51a9SNicolas Vasilache if (isContiguous) { 5615c0c51a9SNicolas Vasilache auto sizes = sourceMemRefType.getShape(); 5625c0c51a9SNicolas Vasilache for (int index = 0, e = strides.size() - 2; index < e; ++index) { 5635c0c51a9SNicolas Vasilache if (strides[index] != strides[index + 1] * sizes[index + 1]) { 5645c0c51a9SNicolas Vasilache isContiguous = false; 5655c0c51a9SNicolas Vasilache break; 5665c0c51a9SNicolas Vasilache } 5675c0c51a9SNicolas Vasilache } 5685c0c51a9SNicolas Vasilache } 5695c0c51a9SNicolas Vasilache // Only contiguous source tensors supported atm. 5705c0c51a9SNicolas Vasilache if (failed(successStrides) || !isContiguous) 5715c0c51a9SNicolas Vasilache return matchFailure(); 5725c0c51a9SNicolas Vasilache 5735c0c51a9SNicolas Vasilache auto int64Ty = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 5745c0c51a9SNicolas Vasilache 5755c0c51a9SNicolas Vasilache // Create descriptor. 5765c0c51a9SNicolas Vasilache auto desc = MemRefDescriptor::undef(rewriter, loc, llvmTargetDescriptorTy); 5775c0c51a9SNicolas Vasilache Type llvmTargetElementTy = desc.getElementType(); 5785c0c51a9SNicolas Vasilache // Set allocated ptr. 57935807bc4SRiver Riddle ValuePtr allocated = sourceMemRef.allocatedPtr(rewriter, loc); 5805c0c51a9SNicolas Vasilache allocated = 5815c0c51a9SNicolas Vasilache rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, allocated); 5825c0c51a9SNicolas Vasilache desc.setAllocatedPtr(rewriter, loc, allocated); 5835c0c51a9SNicolas Vasilache // Set aligned ptr. 58435807bc4SRiver Riddle ValuePtr ptr = sourceMemRef.alignedPtr(rewriter, loc); 5855c0c51a9SNicolas Vasilache ptr = rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, ptr); 5865c0c51a9SNicolas Vasilache desc.setAlignedPtr(rewriter, loc, ptr); 5875c0c51a9SNicolas Vasilache // Fill offset 0. 5885c0c51a9SNicolas Vasilache auto attr = rewriter.getIntegerAttr(rewriter.getIndexType(), 0); 5895c0c51a9SNicolas Vasilache auto zero = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, attr); 5905c0c51a9SNicolas Vasilache desc.setOffset(rewriter, loc, zero); 5915c0c51a9SNicolas Vasilache 5925c0c51a9SNicolas Vasilache // Fill size and stride descriptors in memref. 5935c0c51a9SNicolas Vasilache for (auto indexedSize : llvm::enumerate(targetMemRefType.getShape())) { 5945c0c51a9SNicolas Vasilache int64_t index = indexedSize.index(); 5955c0c51a9SNicolas Vasilache auto sizeAttr = 5965c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), indexedSize.value()); 5975c0c51a9SNicolas Vasilache auto size = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, sizeAttr); 5985c0c51a9SNicolas Vasilache desc.setSize(rewriter, loc, index, size); 5995c0c51a9SNicolas Vasilache auto strideAttr = 6005c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), strides[index]); 6015c0c51a9SNicolas Vasilache auto stride = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, strideAttr); 6025c0c51a9SNicolas Vasilache desc.setStride(rewriter, loc, index, stride); 6035c0c51a9SNicolas Vasilache } 6045c0c51a9SNicolas Vasilache 6055c0c51a9SNicolas Vasilache rewriter.replaceOp(op, {desc}); 6065c0c51a9SNicolas Vasilache return matchSuccess(); 6075c0c51a9SNicolas Vasilache } 6085c0c51a9SNicolas Vasilache }; 6095c0c51a9SNicolas Vasilache 610d9b500d3SAart Bik class VectorPrintOpConversion : public LLVMOpLowering { 611d9b500d3SAart Bik public: 612d9b500d3SAart Bik explicit VectorPrintOpConversion(MLIRContext *context, 613d9b500d3SAart Bik LLVMTypeConverter &typeConverter) 614d9b500d3SAart Bik : LLVMOpLowering(vector::PrintOp::getOperationName(), context, 615d9b500d3SAart Bik typeConverter) {} 616d9b500d3SAart Bik 617d9b500d3SAart Bik // Proof-of-concept lowering implementation that relies on a small 618d9b500d3SAart Bik // runtime support library, which only needs to provide a few 619d9b500d3SAart Bik // printing methods (single value for all data types, opening/closing 620d9b500d3SAart Bik // bracket, comma, newline). The lowering fully unrolls a vector 621d9b500d3SAart Bik // in terms of these elementary printing operations. The advantage 622d9b500d3SAart Bik // of this approach is that the library can remain unaware of all 623d9b500d3SAart Bik // low-level implementation details of vectors while still supporting 624d9b500d3SAart Bik // output of any shaped and dimensioned vector. Due to full unrolling, 625d9b500d3SAart Bik // this approach is less suited for very large vectors though. 626d9b500d3SAart Bik // 627d9b500d3SAart Bik // TODO(ajcbik): rely solely on libc in future? something else? 628d9b500d3SAart Bik // 629d9b500d3SAart Bik PatternMatchResult 63035807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 631d9b500d3SAart Bik ConversionPatternRewriter &rewriter) const override { 632d9b500d3SAart Bik auto printOp = cast<vector::PrintOp>(op); 633d9b500d3SAart Bik auto adaptor = vector::PrintOpOperandAdaptor(operands); 634d9b500d3SAart Bik Type printType = printOp.getPrintType(); 635d9b500d3SAart Bik 636d9b500d3SAart Bik if (lowering.convertType(printType) == nullptr) 637d9b500d3SAart Bik return matchFailure(); 638d9b500d3SAart Bik 639d9b500d3SAart Bik // Make sure element type has runtime support (currently just Float/Double). 640d9b500d3SAart Bik VectorType vectorType = printType.dyn_cast<VectorType>(); 641d9b500d3SAart Bik Type eltType = vectorType ? vectorType.getElementType() : printType; 642d9b500d3SAart Bik int64_t rank = vectorType ? vectorType.getRank() : 0; 643d9b500d3SAart Bik Operation *printer; 644d9b500d3SAart Bik if (eltType.isF32()) 645d9b500d3SAart Bik printer = getPrintFloat(op); 646d9b500d3SAart Bik else if (eltType.isF64()) 647d9b500d3SAart Bik printer = getPrintDouble(op); 648d9b500d3SAart Bik else 649d9b500d3SAart Bik return matchFailure(); 650d9b500d3SAart Bik 651d9b500d3SAart Bik // Unroll vector into elementary print calls. 652d9b500d3SAart Bik emitRanks(rewriter, op, adaptor.source(), vectorType, printer, rank); 653d9b500d3SAart Bik emitCall(rewriter, op->getLoc(), getPrintNewline(op)); 654d9b500d3SAart Bik rewriter.eraseOp(op); 655d9b500d3SAart Bik return matchSuccess(); 656d9b500d3SAart Bik } 657d9b500d3SAart Bik 658d9b500d3SAart Bik private: 659d9b500d3SAart Bik void emitRanks(ConversionPatternRewriter &rewriter, Operation *op, 66035807bc4SRiver Riddle ValuePtr value, VectorType vectorType, Operation *printer, 661d9b500d3SAart Bik int64_t rank) const { 662d9b500d3SAart Bik Location loc = op->getLoc(); 663d9b500d3SAart Bik if (rank == 0) { 664d9b500d3SAart Bik emitCall(rewriter, loc, printer, value); 665d9b500d3SAart Bik return; 666d9b500d3SAart Bik } 667d9b500d3SAart Bik 668d9b500d3SAart Bik emitCall(rewriter, loc, getPrintOpen(op)); 669d9b500d3SAart Bik Operation *printComma = getPrintComma(op); 670d9b500d3SAart Bik int64_t dim = vectorType.getDimSize(0); 671d9b500d3SAart Bik for (int64_t d = 0; d < dim; ++d) { 672d9b500d3SAart Bik auto reducedType = 673d9b500d3SAart Bik rank > 1 ? reducedVectorTypeFront(vectorType) : nullptr; 674d9b500d3SAart Bik auto llvmType = lowering.convertType( 675d9b500d3SAart Bik rank > 1 ? reducedType : vectorType.getElementType()); 67635807bc4SRiver Riddle ValuePtr nestedVal = 677d9b500d3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, d); 678d9b500d3SAart Bik emitRanks(rewriter, op, nestedVal, reducedType, printer, rank - 1); 679d9b500d3SAart Bik if (d != dim - 1) 680d9b500d3SAart Bik emitCall(rewriter, loc, printComma); 681d9b500d3SAart Bik } 682d9b500d3SAart Bik emitCall(rewriter, loc, getPrintClose(op)); 683d9b500d3SAart Bik } 684d9b500d3SAart Bik 685d9b500d3SAart Bik // Helper to emit a call. 686d9b500d3SAart Bik static void emitCall(ConversionPatternRewriter &rewriter, Location loc, 687d9b500d3SAart Bik Operation *ref, ValueRange params = ValueRange()) { 688d9b500d3SAart Bik rewriter.create<LLVM::CallOp>(loc, ArrayRef<Type>{}, 689d9b500d3SAart Bik rewriter.getSymbolRefAttr(ref), params); 690d9b500d3SAart Bik } 691d9b500d3SAart Bik 692d9b500d3SAart Bik // Helper for printer method declaration (first hit) and lookup. 693d9b500d3SAart Bik static Operation *getPrint(Operation *op, LLVM::LLVMDialect *dialect, 694d9b500d3SAart Bik StringRef name, ArrayRef<LLVM::LLVMType> params) { 695d9b500d3SAart Bik auto module = op->getParentOfType<ModuleOp>(); 696d9b500d3SAart Bik auto func = module.lookupSymbol<LLVM::LLVMFuncOp>(name); 697d9b500d3SAart Bik if (func) 698d9b500d3SAart Bik return func; 699d9b500d3SAart Bik OpBuilder moduleBuilder(module.getBodyRegion()); 700d9b500d3SAart Bik return moduleBuilder.create<LLVM::LLVMFuncOp>( 701d9b500d3SAart Bik op->getLoc(), name, 702d9b500d3SAart Bik LLVM::LLVMType::getFunctionTy(LLVM::LLVMType::getVoidTy(dialect), 703d9b500d3SAart Bik params, /*isVarArg=*/false)); 704d9b500d3SAart Bik } 705d9b500d3SAart Bik 706d9b500d3SAart Bik // Helpers for method names. 707d9b500d3SAart Bik Operation *getPrintFloat(Operation *op) const { 708d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 709d9b500d3SAart Bik return getPrint(op, dialect, "print_f32", 710d9b500d3SAart Bik LLVM::LLVMType::getFloatTy(dialect)); 711d9b500d3SAart Bik } 712d9b500d3SAart Bik Operation *getPrintDouble(Operation *op) const { 713d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 714d9b500d3SAart Bik return getPrint(op, dialect, "print_f64", 715d9b500d3SAart Bik LLVM::LLVMType::getDoubleTy(dialect)); 716d9b500d3SAart Bik } 717d9b500d3SAart Bik Operation *getPrintOpen(Operation *op) const { 718d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_open", {}); 719d9b500d3SAart Bik } 720d9b500d3SAart Bik Operation *getPrintClose(Operation *op) const { 721d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_close", {}); 722d9b500d3SAart Bik } 723d9b500d3SAart Bik Operation *getPrintComma(Operation *op) const { 724d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_comma", {}); 725d9b500d3SAart Bik } 726d9b500d3SAart Bik Operation *getPrintNewline(Operation *op) const { 727d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_newline", {}); 728d9b500d3SAart Bik } 729d9b500d3SAart Bik }; 730d9b500d3SAart Bik 7315c0c51a9SNicolas Vasilache /// Populate the given list with patterns that convert from Vector to LLVM. 7325c0c51a9SNicolas Vasilache void mlir::populateVectorToLLVMConversionPatterns( 7335c0c51a9SNicolas Vasilache LLVMTypeConverter &converter, OwningRewritePatternList &patterns) { 7341c81adf3SAart Bik patterns.insert<VectorBroadcastOpConversion, VectorShuffleOpConversion, 735cd5dab8aSAart Bik VectorExtractElementOpConversion, VectorExtractOpConversion, 736cd5dab8aSAart Bik VectorInsertElementOpConversion, VectorInsertOpConversion, 737d9b500d3SAart Bik VectorOuterProductOpConversion, VectorTypeCastOpConversion, 738d9b500d3SAart Bik VectorPrintOpConversion>(converter.getDialect()->getContext(), 739d9b500d3SAart Bik converter); 7405c0c51a9SNicolas Vasilache } 7415c0c51a9SNicolas Vasilache 7425c0c51a9SNicolas Vasilache namespace { 7435c0c51a9SNicolas Vasilache struct LowerVectorToLLVMPass : public ModulePass<LowerVectorToLLVMPass> { 7445c0c51a9SNicolas Vasilache void runOnModule() override; 7455c0c51a9SNicolas Vasilache }; 7465c0c51a9SNicolas Vasilache } // namespace 7475c0c51a9SNicolas Vasilache 7485c0c51a9SNicolas Vasilache void LowerVectorToLLVMPass::runOnModule() { 7495c0c51a9SNicolas Vasilache // Convert to the LLVM IR dialect using the converter defined above. 7505c0c51a9SNicolas Vasilache OwningRewritePatternList patterns; 7515c0c51a9SNicolas Vasilache LLVMTypeConverter converter(&getContext()); 7525c0c51a9SNicolas Vasilache populateVectorToLLVMConversionPatterns(converter, patterns); 7535c0c51a9SNicolas Vasilache populateStdToLLVMConversionPatterns(converter, patterns); 7545c0c51a9SNicolas Vasilache 7555c0c51a9SNicolas Vasilache ConversionTarget target(getContext()); 7565c0c51a9SNicolas Vasilache target.addLegalDialect<LLVM::LLVMDialect>(); 7575c0c51a9SNicolas Vasilache target.addDynamicallyLegalOp<FuncOp>( 7585c0c51a9SNicolas Vasilache [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); }); 7595c0c51a9SNicolas Vasilache if (failed( 7605c0c51a9SNicolas Vasilache applyPartialConversion(getModule(), target, patterns, &converter))) { 7615c0c51a9SNicolas Vasilache signalPassFailure(); 7625c0c51a9SNicolas Vasilache } 7635c0c51a9SNicolas Vasilache } 7645c0c51a9SNicolas Vasilache 7655c0c51a9SNicolas Vasilache OpPassBase<ModuleOp> *mlir::createLowerVectorToLLVMPass() { 7665c0c51a9SNicolas Vasilache return new LowerVectorToLLVMPass(); 7675c0c51a9SNicolas Vasilache } 7685c0c51a9SNicolas Vasilache 7695c0c51a9SNicolas Vasilache static PassRegistration<LowerVectorToLLVMPass> 7705c0c51a9SNicolas Vasilache pass("convert-vector-to-llvm", 7715c0c51a9SNicolas Vasilache "Lower the operations from the vector dialect into the LLVM dialect"); 772