15c0c51a9SNicolas Vasilache //===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===// 25c0c51a9SNicolas Vasilache // 35c0c51a9SNicolas Vasilache // Copyright 2019 The MLIR Authors. 45c0c51a9SNicolas Vasilache // 55c0c51a9SNicolas Vasilache // Licensed under the Apache License, Version 2.0 (the "License"); 65c0c51a9SNicolas Vasilache // you may not use this file except in compliance with the License. 75c0c51a9SNicolas Vasilache // You may obtain a copy of the License at 85c0c51a9SNicolas Vasilache // 95c0c51a9SNicolas Vasilache // http://www.apache.org/licenses/LICENSE-2.0 105c0c51a9SNicolas Vasilache // 115c0c51a9SNicolas Vasilache // Unless required by applicable law or agreed to in writing, software 125c0c51a9SNicolas Vasilache // distributed under the License is distributed on an "AS IS" BASIS, 135c0c51a9SNicolas Vasilache // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 145c0c51a9SNicolas Vasilache // See the License for the specific language governing permissions and 155c0c51a9SNicolas Vasilache // limitations under the License. 165c0c51a9SNicolas Vasilache // ============================================================================= 175c0c51a9SNicolas Vasilache 185c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 195c0c51a9SNicolas Vasilache #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h" 205c0c51a9SNicolas Vasilache #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 215c0c51a9SNicolas Vasilache #include "mlir/Dialect/LLVMIR/LLVMDialect.h" 225c0c51a9SNicolas Vasilache #include "mlir/Dialect/VectorOps/VectorOps.h" 235c0c51a9SNicolas Vasilache #include "mlir/IR/Attributes.h" 245c0c51a9SNicolas Vasilache #include "mlir/IR/Builders.h" 255c0c51a9SNicolas Vasilache #include "mlir/IR/MLIRContext.h" 265c0c51a9SNicolas Vasilache #include "mlir/IR/Module.h" 275c0c51a9SNicolas Vasilache #include "mlir/IR/Operation.h" 285c0c51a9SNicolas Vasilache #include "mlir/IR/PatternMatch.h" 295c0c51a9SNicolas Vasilache #include "mlir/IR/StandardTypes.h" 305c0c51a9SNicolas Vasilache #include "mlir/IR/Types.h" 315c0c51a9SNicolas Vasilache #include "mlir/Pass/Pass.h" 325c0c51a9SNicolas Vasilache #include "mlir/Pass/PassManager.h" 335c0c51a9SNicolas Vasilache #include "mlir/Transforms/DialectConversion.h" 345c0c51a9SNicolas Vasilache #include "mlir/Transforms/Passes.h" 355c0c51a9SNicolas Vasilache 365c0c51a9SNicolas Vasilache #include "llvm/IR/DerivedTypes.h" 375c0c51a9SNicolas Vasilache #include "llvm/IR/Module.h" 385c0c51a9SNicolas Vasilache #include "llvm/IR/Type.h" 395c0c51a9SNicolas Vasilache #include "llvm/Support/Allocator.h" 405c0c51a9SNicolas Vasilache #include "llvm/Support/ErrorHandling.h" 415c0c51a9SNicolas Vasilache 425c0c51a9SNicolas Vasilache using namespace mlir; 435c0c51a9SNicolas Vasilache 445c0c51a9SNicolas Vasilache template <typename T> 455c0c51a9SNicolas Vasilache static LLVM::LLVMType getPtrToElementType(T containerType, 465c0c51a9SNicolas Vasilache LLVMTypeConverter &lowering) { 475c0c51a9SNicolas Vasilache return lowering.convertType(containerType.getElementType()) 485c0c51a9SNicolas Vasilache .template cast<LLVM::LLVMType>() 495c0c51a9SNicolas Vasilache .getPointerTo(); 505c0c51a9SNicolas Vasilache } 515c0c51a9SNicolas Vasilache 529826fe5cSAart Bik // Helper to reduce vector type by one rank at front. 539826fe5cSAart Bik static VectorType reducedVectorTypeFront(VectorType tp) { 549826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 559826fe5cSAart Bik return VectorType::get(tp.getShape().drop_front(), tp.getElementType()); 569826fe5cSAart Bik } 579826fe5cSAart Bik 589826fe5cSAart Bik // Helper to reduce vector type by *all* but one rank at back. 599826fe5cSAart Bik static VectorType reducedVectorTypeBack(VectorType tp) { 609826fe5cSAart Bik assert((tp.getRank() > 1) && "unlowerable vector type"); 619826fe5cSAart Bik return VectorType::get(tp.getShape().take_back(), tp.getElementType()); 629826fe5cSAart Bik } 639826fe5cSAart Bik 641c81adf3SAart Bik // Helper that picks the proper sequence for inserting. 65*35807bc4SRiver Riddle static ValuePtr insertOne(ConversionPatternRewriter &rewriter, 66*35807bc4SRiver Riddle LLVMTypeConverter &lowering, Location loc, 67*35807bc4SRiver Riddle ValuePtr val1, ValuePtr val2, Type llvmType, 68*35807bc4SRiver Riddle int64_t rank, int64_t pos) { 691c81adf3SAart Bik if (rank == 1) { 701c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 711c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 721c81adf3SAart Bik loc, lowering.convertType(idxType), 731c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 741c81adf3SAart Bik return rewriter.create<LLVM::InsertElementOp>(loc, llvmType, val1, val2, 751c81adf3SAart Bik constant); 761c81adf3SAart Bik } 771c81adf3SAart Bik return rewriter.create<LLVM::InsertValueOp>(loc, llvmType, val1, val2, 781c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 791c81adf3SAart Bik } 801c81adf3SAart Bik 811c81adf3SAart Bik // Helper that picks the proper sequence for extracting. 82*35807bc4SRiver Riddle static ValuePtr extractOne(ConversionPatternRewriter &rewriter, 83*35807bc4SRiver Riddle LLVMTypeConverter &lowering, Location loc, 84*35807bc4SRiver Riddle ValuePtr val, Type llvmType, int64_t rank, 85*35807bc4SRiver Riddle int64_t pos) { 861c81adf3SAart Bik if (rank == 1) { 871c81adf3SAart Bik auto idxType = rewriter.getIndexType(); 881c81adf3SAart Bik auto constant = rewriter.create<LLVM::ConstantOp>( 891c81adf3SAart Bik loc, lowering.convertType(idxType), 901c81adf3SAart Bik rewriter.getIntegerAttr(idxType, pos)); 911c81adf3SAart Bik return rewriter.create<LLVM::ExtractElementOp>(loc, llvmType, val, 921c81adf3SAart Bik constant); 931c81adf3SAart Bik } 941c81adf3SAart Bik return rewriter.create<LLVM::ExtractValueOp>(loc, llvmType, val, 951c81adf3SAart Bik rewriter.getI64ArrayAttr(pos)); 961c81adf3SAart Bik } 971c81adf3SAart Bik 98b36aaeafSAart Bik class VectorBroadcastOpConversion : public LLVMOpLowering { 99b36aaeafSAart Bik public: 100b36aaeafSAart Bik explicit VectorBroadcastOpConversion(MLIRContext *context, 101b36aaeafSAart Bik LLVMTypeConverter &typeConverter) 102b36aaeafSAart Bik : LLVMOpLowering(vector::BroadcastOp::getOperationName(), context, 103b36aaeafSAart Bik typeConverter) {} 104b36aaeafSAart Bik 105b36aaeafSAart Bik PatternMatchResult 106*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 107b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const override { 108b36aaeafSAart Bik auto broadcastOp = cast<vector::BroadcastOp>(op); 109b36aaeafSAart Bik VectorType dstVectorType = broadcastOp.getVectorType(); 110b36aaeafSAart Bik if (lowering.convertType(dstVectorType) == nullptr) 111b36aaeafSAart Bik return matchFailure(); 112b36aaeafSAart Bik // Rewrite when the full vector type can be lowered (which 113b36aaeafSAart Bik // implies all 'reduced' types can be lowered too). 1141c81adf3SAart Bik auto adaptor = vector::BroadcastOpOperandAdaptor(operands); 115b36aaeafSAart Bik VectorType srcVectorType = 116b36aaeafSAart Bik broadcastOp.getSourceType().dyn_cast<VectorType>(); 117b36aaeafSAart Bik rewriter.replaceOp( 1181c81adf3SAart Bik op, expandRanks(adaptor.source(), // source value to be expanded 119b36aaeafSAart Bik op->getLoc(), // location of original broadcast 120b36aaeafSAart Bik srcVectorType, dstVectorType, rewriter)); 121b36aaeafSAart Bik return matchSuccess(); 122b36aaeafSAart Bik } 123b36aaeafSAart Bik 124b36aaeafSAart Bik private: 125b36aaeafSAart Bik // Expands the given source value over all the ranks, as defined 126b36aaeafSAart Bik // by the source and destination type (a null source type denotes 127b36aaeafSAart Bik // expansion from a scalar value into a vector). 128b36aaeafSAart Bik // 129b36aaeafSAart Bik // TODO(ajcbik): consider replacing this one-pattern lowering 130b36aaeafSAart Bik // with a two-pattern lowering using other vector 131b36aaeafSAart Bik // ops once all insert/extract/shuffle operations 132b36aaeafSAart Bik // are available with lowering implemention. 133b36aaeafSAart Bik // 134*35807bc4SRiver Riddle ValuePtr expandRanks(ValuePtr value, Location loc, VectorType srcVectorType, 135b36aaeafSAart Bik VectorType dstVectorType, 136b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 137b36aaeafSAart Bik assert((dstVectorType != nullptr) && "invalid result type in broadcast"); 138b36aaeafSAart Bik // Determine rank of source and destination. 139b36aaeafSAart Bik int64_t srcRank = srcVectorType ? srcVectorType.getRank() : 0; 140b36aaeafSAart Bik int64_t dstRank = dstVectorType.getRank(); 141b36aaeafSAart Bik int64_t curDim = dstVectorType.getDimSize(0); 142b36aaeafSAart Bik if (srcRank < dstRank) 143b36aaeafSAart Bik // Duplicate this rank. 144b36aaeafSAart Bik return duplicateOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 145b36aaeafSAart Bik curDim, rewriter); 146b36aaeafSAart Bik // If all trailing dimensions are the same, the broadcast consists of 147b36aaeafSAart Bik // simply passing through the source value and we are done. Otherwise, 148b36aaeafSAart Bik // any non-matching dimension forces a stretch along this rank. 149b36aaeafSAart Bik assert((srcVectorType != nullptr) && (srcRank > 0) && 150b36aaeafSAart Bik (srcRank == dstRank) && "invalid rank in broadcast"); 151b36aaeafSAart Bik for (int64_t r = 0; r < dstRank; r++) { 152b36aaeafSAart Bik if (srcVectorType.getDimSize(r) != dstVectorType.getDimSize(r)) { 153b36aaeafSAart Bik return stretchOneRank(value, loc, srcVectorType, dstVectorType, dstRank, 154b36aaeafSAart Bik curDim, rewriter); 155b36aaeafSAart Bik } 156b36aaeafSAart Bik } 157b36aaeafSAart Bik return value; 158b36aaeafSAart Bik } 159b36aaeafSAart Bik 160b36aaeafSAart Bik // Picks the best way to duplicate a single rank. For the 1-D case, a 161b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion. For higher 162b36aaeafSAart Bik // dimensions, however, we need dim x insert-values on a new broadcast 163b36aaeafSAart Bik // with one less leading dimension, which will be lowered "recursively" 164b36aaeafSAart Bik // to matching LLVM IR. 165b36aaeafSAart Bik // For example: 166b36aaeafSAart Bik // v = broadcast s : f32 to vector<4x2xf32> 167b36aaeafSAart Bik // becomes: 168b36aaeafSAart Bik // x = broadcast s : f32 to vector<2xf32> 169b36aaeafSAart Bik // v = [x,x,x,x] 170b36aaeafSAart Bik // becomes: 171b36aaeafSAart Bik // x = [s,s] 172b36aaeafSAart Bik // v = [x,x,x,x] 173*35807bc4SRiver Riddle ValuePtr duplicateOneRank(ValuePtr value, Location loc, 174*35807bc4SRiver Riddle VectorType srcVectorType, VectorType dstVectorType, 175*35807bc4SRiver Riddle int64_t rank, int64_t dim, 176b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 177b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 178b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 179b36aaeafSAart Bik if (rank == 1) { 180*35807bc4SRiver Riddle ValuePtr undef = rewriter.create<LLVM::UndefOp>(loc, llvmType); 181*35807bc4SRiver Riddle ValuePtr expand = 1821c81adf3SAart Bik insertOne(rewriter, lowering, loc, undef, value, llvmType, rank, 0); 183b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 184b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 185b36aaeafSAart Bik loc, expand, undef, rewriter.getI32ArrayAttr(zeroValues)); 186b36aaeafSAart Bik } 187*35807bc4SRiver Riddle ValuePtr expand = 1889826fe5cSAart Bik expandRanks(value, loc, srcVectorType, 1899826fe5cSAart Bik reducedVectorTypeFront(dstVectorType), rewriter); 190*35807bc4SRiver Riddle ValuePtr result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 191b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 1921c81adf3SAart Bik result = 1931c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 194b36aaeafSAart Bik } 195b36aaeafSAart Bik return result; 196b36aaeafSAart Bik } 197b36aaeafSAart Bik 198b36aaeafSAart Bik // Picks the best way to stretch a single rank. For the 1-D case, a 199b36aaeafSAart Bik // single insert-elt/shuffle is the most efficient expansion when at 200b36aaeafSAart Bik // a stretch. Otherwise, every dimension needs to be expanded 201b36aaeafSAart Bik // individually and individually inserted in the resulting vector. 202b36aaeafSAart Bik // For example: 203b36aaeafSAart Bik // v = broadcast w : vector<4x1x2xf32> to vector<4x2x2xf32> 204b36aaeafSAart Bik // becomes: 205b36aaeafSAart Bik // a = broadcast w[0] : vector<1x2xf32> to vector<2x2xf32> 206b36aaeafSAart Bik // b = broadcast w[1] : vector<1x2xf32> to vector<2x2xf32> 207b36aaeafSAart Bik // c = broadcast w[2] : vector<1x2xf32> to vector<2x2xf32> 208b36aaeafSAart Bik // d = broadcast w[3] : vector<1x2xf32> to vector<2x2xf32> 209b36aaeafSAart Bik // v = [a,b,c,d] 210b36aaeafSAart Bik // becomes: 211b36aaeafSAart Bik // x = broadcast w[0][0] : vector<2xf32> to vector <2x2xf32> 212b36aaeafSAart Bik // y = broadcast w[1][0] : vector<2xf32> to vector <2x2xf32> 213b36aaeafSAart Bik // a = [x, y] 214b36aaeafSAart Bik // etc. 215*35807bc4SRiver Riddle ValuePtr stretchOneRank(ValuePtr value, Location loc, 216*35807bc4SRiver Riddle VectorType srcVectorType, VectorType dstVectorType, 217*35807bc4SRiver Riddle int64_t rank, int64_t dim, 218b36aaeafSAart Bik ConversionPatternRewriter &rewriter) const { 219b36aaeafSAart Bik Type llvmType = lowering.convertType(dstVectorType); 220b36aaeafSAart Bik assert((llvmType != nullptr) && "unlowerable vector type"); 221*35807bc4SRiver Riddle ValuePtr result = rewriter.create<LLVM::UndefOp>(loc, llvmType); 222b36aaeafSAart Bik bool atStretch = dim != srcVectorType.getDimSize(0); 223b36aaeafSAart Bik if (rank == 1) { 2241c81adf3SAart Bik assert(atStretch); 225b36aaeafSAart Bik Type redLlvmType = lowering.convertType(dstVectorType.getElementType()); 226*35807bc4SRiver Riddle ValuePtr one = 2271c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, 0); 228*35807bc4SRiver Riddle ValuePtr expand = 2291c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, one, llvmType, rank, 0); 230b36aaeafSAart Bik SmallVector<int32_t, 4> zeroValues(dim, 0); 231b36aaeafSAart Bik return rewriter.create<LLVM::ShuffleVectorOp>( 232b36aaeafSAart Bik loc, expand, result, rewriter.getI32ArrayAttr(zeroValues)); 233b36aaeafSAart Bik } 2349826fe5cSAart Bik VectorType redSrcType = reducedVectorTypeFront(srcVectorType); 2359826fe5cSAart Bik VectorType redDstType = reducedVectorTypeFront(dstVectorType); 236b36aaeafSAart Bik Type redLlvmType = lowering.convertType(redSrcType); 237b36aaeafSAart Bik for (int64_t d = 0; d < dim; ++d) { 238b36aaeafSAart Bik int64_t pos = atStretch ? 0 : d; 239*35807bc4SRiver Riddle ValuePtr one = 2401c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, redLlvmType, rank, pos); 241*35807bc4SRiver Riddle ValuePtr expand = expandRanks(one, loc, redSrcType, redDstType, rewriter); 2421c81adf3SAart Bik result = 2431c81adf3SAart Bik insertOne(rewriter, lowering, loc, result, expand, llvmType, rank, d); 244b36aaeafSAart Bik } 245b36aaeafSAart Bik return result; 246b36aaeafSAart Bik } 2471c81adf3SAart Bik }; 248b36aaeafSAart Bik 2491c81adf3SAart Bik class VectorShuffleOpConversion : public LLVMOpLowering { 2501c81adf3SAart Bik public: 2511c81adf3SAart Bik explicit VectorShuffleOpConversion(MLIRContext *context, 2521c81adf3SAart Bik LLVMTypeConverter &typeConverter) 2531c81adf3SAart Bik : LLVMOpLowering(vector::ShuffleOp::getOperationName(), context, 2541c81adf3SAart Bik typeConverter) {} 2551c81adf3SAart Bik 2561c81adf3SAart Bik PatternMatchResult 257*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 2581c81adf3SAart Bik ConversionPatternRewriter &rewriter) const override { 2591c81adf3SAart Bik auto loc = op->getLoc(); 2601c81adf3SAart Bik auto adaptor = vector::ShuffleOpOperandAdaptor(operands); 2611c81adf3SAart Bik auto shuffleOp = cast<vector::ShuffleOp>(op); 2621c81adf3SAart Bik auto v1Type = shuffleOp.getV1VectorType(); 2631c81adf3SAart Bik auto v2Type = shuffleOp.getV2VectorType(); 2641c81adf3SAart Bik auto vectorType = shuffleOp.getVectorType(); 2651c81adf3SAart Bik Type llvmType = lowering.convertType(vectorType); 2661c81adf3SAart Bik auto maskArrayAttr = shuffleOp.mask(); 2671c81adf3SAart Bik 2681c81adf3SAart Bik // Bail if result type cannot be lowered. 2691c81adf3SAart Bik if (!llvmType) 2701c81adf3SAart Bik return matchFailure(); 2711c81adf3SAart Bik 2721c81adf3SAart Bik // Get rank and dimension sizes. 2731c81adf3SAart Bik int64_t rank = vectorType.getRank(); 2741c81adf3SAart Bik assert(v1Type.getRank() == rank); 2751c81adf3SAart Bik assert(v2Type.getRank() == rank); 2761c81adf3SAart Bik int64_t v1Dim = v1Type.getDimSize(0); 2771c81adf3SAart Bik 2781c81adf3SAart Bik // For rank 1, where both operands have *exactly* the same vector type, 2791c81adf3SAart Bik // there is direct shuffle support in LLVM. Use it! 2801c81adf3SAart Bik if (rank == 1 && v1Type == v2Type) { 281*35807bc4SRiver Riddle ValuePtr shuffle = rewriter.create<LLVM::ShuffleVectorOp>( 2821c81adf3SAart Bik loc, adaptor.v1(), adaptor.v2(), maskArrayAttr); 2831c81adf3SAart Bik rewriter.replaceOp(op, shuffle); 2841c81adf3SAart Bik return matchSuccess(); 285b36aaeafSAart Bik } 286b36aaeafSAart Bik 2871c81adf3SAart Bik // For all other cases, insert the individual values individually. 288*35807bc4SRiver Riddle ValuePtr insert = rewriter.create<LLVM::UndefOp>(loc, llvmType); 2891c81adf3SAart Bik int64_t insPos = 0; 2901c81adf3SAart Bik for (auto en : llvm::enumerate(maskArrayAttr)) { 2911c81adf3SAart Bik int64_t extPos = en.value().cast<IntegerAttr>().getInt(); 292*35807bc4SRiver Riddle ValuePtr value = adaptor.v1(); 2931c81adf3SAart Bik if (extPos >= v1Dim) { 2941c81adf3SAart Bik extPos -= v1Dim; 2951c81adf3SAart Bik value = adaptor.v2(); 296b36aaeafSAart Bik } 297*35807bc4SRiver Riddle ValuePtr extract = 2981c81adf3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, extPos); 2991c81adf3SAart Bik insert = insertOne(rewriter, lowering, loc, insert, extract, llvmType, 3001c81adf3SAart Bik rank, insPos++); 3011c81adf3SAart Bik } 3021c81adf3SAart Bik rewriter.replaceOp(op, insert); 3031c81adf3SAart Bik return matchSuccess(); 304b36aaeafSAart Bik } 305b36aaeafSAart Bik }; 306b36aaeafSAart Bik 307cd5dab8aSAart Bik class VectorExtractElementOpConversion : public LLVMOpLowering { 308cd5dab8aSAart Bik public: 309cd5dab8aSAart Bik explicit VectorExtractElementOpConversion(MLIRContext *context, 310cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 311cd5dab8aSAart Bik : LLVMOpLowering(vector::ExtractElementOp::getOperationName(), context, 312cd5dab8aSAart Bik typeConverter) {} 313cd5dab8aSAart Bik 314cd5dab8aSAart Bik PatternMatchResult 315*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 316cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 317cd5dab8aSAart Bik auto adaptor = vector::ExtractElementOpOperandAdaptor(operands); 318cd5dab8aSAart Bik auto extractEltOp = cast<vector::ExtractElementOp>(op); 319cd5dab8aSAart Bik auto vectorType = extractEltOp.getVectorType(); 320cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType.getElementType()); 321cd5dab8aSAart Bik 322cd5dab8aSAart Bik // Bail if result type cannot be lowered. 323cd5dab8aSAart Bik if (!llvmType) 324cd5dab8aSAart Bik return matchFailure(); 325cd5dab8aSAart Bik 326cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::ExtractElementOp>( 327cd5dab8aSAart Bik op, llvmType, adaptor.vector(), adaptor.position()); 328cd5dab8aSAart Bik return matchSuccess(); 329cd5dab8aSAart Bik } 330cd5dab8aSAart Bik }; 331cd5dab8aSAart Bik 3329826fe5cSAart Bik class VectorExtractOpConversion : public LLVMOpLowering { 3335c0c51a9SNicolas Vasilache public: 3349826fe5cSAart Bik explicit VectorExtractOpConversion(MLIRContext *context, 3355c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 336d37f2725SAart Bik : LLVMOpLowering(vector::ExtractOp::getOperationName(), context, 3375c0c51a9SNicolas Vasilache typeConverter) {} 3385c0c51a9SNicolas Vasilache 3395c0c51a9SNicolas Vasilache PatternMatchResult 340*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 3415c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 3425c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 343d37f2725SAart Bik auto adaptor = vector::ExtractOpOperandAdaptor(operands); 344d37f2725SAart Bik auto extractOp = cast<vector::ExtractOp>(op); 3459826fe5cSAart Bik auto vectorType = extractOp.getVectorType(); 3465c0c51a9SNicolas Vasilache auto resultType = extractOp.getResult()->getType(); 3475c0c51a9SNicolas Vasilache auto llvmResultType = lowering.convertType(resultType); 3485c0c51a9SNicolas Vasilache auto positionArrayAttr = extractOp.position(); 3499826fe5cSAart Bik 3509826fe5cSAart Bik // Bail if result type cannot be lowered. 3519826fe5cSAart Bik if (!llvmResultType) 3529826fe5cSAart Bik return matchFailure(); 3539826fe5cSAart Bik 3545c0c51a9SNicolas Vasilache // One-shot extraction of vector from array (only requires extractvalue). 3555c0c51a9SNicolas Vasilache if (resultType.isa<VectorType>()) { 356*35807bc4SRiver Riddle ValuePtr extracted = rewriter.create<LLVM::ExtractValueOp>( 3575c0c51a9SNicolas Vasilache loc, llvmResultType, adaptor.vector(), positionArrayAttr); 3585c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3595c0c51a9SNicolas Vasilache return matchSuccess(); 3605c0c51a9SNicolas Vasilache } 3615c0c51a9SNicolas Vasilache 3629826fe5cSAart Bik // Potential extraction of 1-D vector from array. 3635c0c51a9SNicolas Vasilache auto *context = op->getContext(); 364*35807bc4SRiver Riddle ValuePtr extracted = adaptor.vector(); 3655c0c51a9SNicolas Vasilache auto positionAttrs = positionArrayAttr.getValue(); 3665c0c51a9SNicolas Vasilache if (positionAttrs.size() > 1) { 3679826fe5cSAart Bik auto oneDVectorType = reducedVectorTypeBack(vectorType); 3685c0c51a9SNicolas Vasilache auto nMinusOnePositionAttrs = 3695c0c51a9SNicolas Vasilache ArrayAttr::get(positionAttrs.drop_back(), context); 3705c0c51a9SNicolas Vasilache extracted = rewriter.create<LLVM::ExtractValueOp>( 3715c0c51a9SNicolas Vasilache loc, lowering.convertType(oneDVectorType), extracted, 3725c0c51a9SNicolas Vasilache nMinusOnePositionAttrs); 3735c0c51a9SNicolas Vasilache } 3745c0c51a9SNicolas Vasilache 3755c0c51a9SNicolas Vasilache // Remaining extraction of element from 1-D LLVM vector 3765c0c51a9SNicolas Vasilache auto position = positionAttrs.back().cast<IntegerAttr>(); 3771d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 3781d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 3795c0c51a9SNicolas Vasilache extracted = 3805c0c51a9SNicolas Vasilache rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant); 3815c0c51a9SNicolas Vasilache rewriter.replaceOp(op, extracted); 3825c0c51a9SNicolas Vasilache 3835c0c51a9SNicolas Vasilache return matchSuccess(); 3845c0c51a9SNicolas Vasilache } 3855c0c51a9SNicolas Vasilache }; 3865c0c51a9SNicolas Vasilache 387cd5dab8aSAart Bik class VectorInsertElementOpConversion : public LLVMOpLowering { 388cd5dab8aSAart Bik public: 389cd5dab8aSAart Bik explicit VectorInsertElementOpConversion(MLIRContext *context, 390cd5dab8aSAart Bik LLVMTypeConverter &typeConverter) 391cd5dab8aSAart Bik : LLVMOpLowering(vector::InsertElementOp::getOperationName(), context, 392cd5dab8aSAart Bik typeConverter) {} 393cd5dab8aSAart Bik 394cd5dab8aSAart Bik PatternMatchResult 395*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 396cd5dab8aSAart Bik ConversionPatternRewriter &rewriter) const override { 397cd5dab8aSAart Bik auto adaptor = vector::InsertElementOpOperandAdaptor(operands); 398cd5dab8aSAart Bik auto insertEltOp = cast<vector::InsertElementOp>(op); 399cd5dab8aSAart Bik auto vectorType = insertEltOp.getDestVectorType(); 400cd5dab8aSAart Bik auto llvmType = lowering.convertType(vectorType); 401cd5dab8aSAart Bik 402cd5dab8aSAart Bik // Bail if result type cannot be lowered. 403cd5dab8aSAart Bik if (!llvmType) 404cd5dab8aSAart Bik return matchFailure(); 405cd5dab8aSAart Bik 406cd5dab8aSAart Bik rewriter.replaceOpWithNewOp<LLVM::InsertElementOp>( 407cd5dab8aSAart Bik op, llvmType, adaptor.dest(), adaptor.source(), adaptor.position()); 408cd5dab8aSAart Bik return matchSuccess(); 409cd5dab8aSAart Bik } 410cd5dab8aSAart Bik }; 411cd5dab8aSAart Bik 4129826fe5cSAart Bik class VectorInsertOpConversion : public LLVMOpLowering { 4139826fe5cSAart Bik public: 4149826fe5cSAart Bik explicit VectorInsertOpConversion(MLIRContext *context, 4159826fe5cSAart Bik LLVMTypeConverter &typeConverter) 4169826fe5cSAart Bik : LLVMOpLowering(vector::InsertOp::getOperationName(), context, 4179826fe5cSAart Bik typeConverter) {} 4189826fe5cSAart Bik 4199826fe5cSAart Bik PatternMatchResult 420*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 4219826fe5cSAart Bik ConversionPatternRewriter &rewriter) const override { 4229826fe5cSAart Bik auto loc = op->getLoc(); 4239826fe5cSAart Bik auto adaptor = vector::InsertOpOperandAdaptor(operands); 4249826fe5cSAart Bik auto insertOp = cast<vector::InsertOp>(op); 4259826fe5cSAart Bik auto sourceType = insertOp.getSourceType(); 4269826fe5cSAart Bik auto destVectorType = insertOp.getDestVectorType(); 4279826fe5cSAart Bik auto llvmResultType = lowering.convertType(destVectorType); 4289826fe5cSAart Bik auto positionArrayAttr = insertOp.position(); 4299826fe5cSAart Bik 4309826fe5cSAart Bik // Bail if result type cannot be lowered. 4319826fe5cSAart Bik if (!llvmResultType) 4329826fe5cSAart Bik return matchFailure(); 4339826fe5cSAart Bik 4349826fe5cSAart Bik // One-shot insertion of a vector into an array (only requires insertvalue). 4359826fe5cSAart Bik if (sourceType.isa<VectorType>()) { 436*35807bc4SRiver Riddle ValuePtr inserted = rewriter.create<LLVM::InsertValueOp>( 4379826fe5cSAart Bik loc, llvmResultType, adaptor.dest(), adaptor.source(), 4389826fe5cSAart Bik positionArrayAttr); 4399826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4409826fe5cSAart Bik return matchSuccess(); 4419826fe5cSAart Bik } 4429826fe5cSAart Bik 4439826fe5cSAart Bik // Potential extraction of 1-D vector from array. 4449826fe5cSAart Bik auto *context = op->getContext(); 445*35807bc4SRiver Riddle ValuePtr extracted = adaptor.dest(); 4469826fe5cSAart Bik auto positionAttrs = positionArrayAttr.getValue(); 4479826fe5cSAart Bik auto position = positionAttrs.back().cast<IntegerAttr>(); 4489826fe5cSAart Bik auto oneDVectorType = destVectorType; 4499826fe5cSAart Bik if (positionAttrs.size() > 1) { 4509826fe5cSAart Bik oneDVectorType = reducedVectorTypeBack(destVectorType); 4519826fe5cSAart Bik auto nMinusOnePositionAttrs = 4529826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4539826fe5cSAart Bik extracted = rewriter.create<LLVM::ExtractValueOp>( 4549826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, 4559826fe5cSAart Bik nMinusOnePositionAttrs); 4569826fe5cSAart Bik } 4579826fe5cSAart Bik 4589826fe5cSAart Bik // Insertion of an element into a 1-D LLVM vector. 4591d47564aSAart Bik auto i64Type = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 4601d47564aSAart Bik auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position); 461*35807bc4SRiver Riddle ValuePtr inserted = rewriter.create<LLVM::InsertElementOp>( 4629826fe5cSAart Bik loc, lowering.convertType(oneDVectorType), extracted, adaptor.source(), 4639826fe5cSAart Bik constant); 4649826fe5cSAart Bik 4659826fe5cSAart Bik // Potential insertion of resulting 1-D vector into array. 4669826fe5cSAart Bik if (positionAttrs.size() > 1) { 4679826fe5cSAart Bik auto nMinusOnePositionAttrs = 4689826fe5cSAart Bik ArrayAttr::get(positionAttrs.drop_back(), context); 4699826fe5cSAart Bik inserted = rewriter.create<LLVM::InsertValueOp>(loc, llvmResultType, 4709826fe5cSAart Bik adaptor.dest(), inserted, 4719826fe5cSAart Bik nMinusOnePositionAttrs); 4729826fe5cSAart Bik } 4739826fe5cSAart Bik 4749826fe5cSAart Bik rewriter.replaceOp(op, inserted); 4759826fe5cSAart Bik return matchSuccess(); 4769826fe5cSAart Bik } 4779826fe5cSAart Bik }; 4789826fe5cSAart Bik 4795c0c51a9SNicolas Vasilache class VectorOuterProductOpConversion : public LLVMOpLowering { 4805c0c51a9SNicolas Vasilache public: 4815c0c51a9SNicolas Vasilache explicit VectorOuterProductOpConversion(MLIRContext *context, 4825c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 4835c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::OuterProductOp::getOperationName(), context, 4845c0c51a9SNicolas Vasilache typeConverter) {} 4855c0c51a9SNicolas Vasilache 4865c0c51a9SNicolas Vasilache PatternMatchResult 487*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 4885c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 4895c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 4905c0c51a9SNicolas Vasilache auto adaptor = vector::OuterProductOpOperandAdaptor(operands); 4915c0c51a9SNicolas Vasilache auto *ctx = op->getContext(); 4925c0c51a9SNicolas Vasilache auto vLHS = adaptor.lhs()->getType().cast<LLVM::LLVMType>(); 4935c0c51a9SNicolas Vasilache auto vRHS = adaptor.rhs()->getType().cast<LLVM::LLVMType>(); 4945c0c51a9SNicolas Vasilache auto rankLHS = vLHS.getUnderlyingType()->getVectorNumElements(); 4955c0c51a9SNicolas Vasilache auto rankRHS = vRHS.getUnderlyingType()->getVectorNumElements(); 4965c0c51a9SNicolas Vasilache auto llvmArrayOfVectType = lowering.convertType( 4975c0c51a9SNicolas Vasilache cast<vector::OuterProductOp>(op).getResult()->getType()); 498*35807bc4SRiver Riddle ValuePtr desc = rewriter.create<LLVM::UndefOp>(loc, llvmArrayOfVectType); 499*35807bc4SRiver Riddle ValuePtr a = adaptor.lhs(), b = adaptor.rhs(); 500*35807bc4SRiver Riddle ValuePtr acc = adaptor.acc().empty() ? nullptr : adaptor.acc().front(); 501*35807bc4SRiver Riddle SmallVector<ValuePtr, 8> lhs, accs; 5025c0c51a9SNicolas Vasilache lhs.reserve(rankLHS); 5035c0c51a9SNicolas Vasilache accs.reserve(rankLHS); 5045c0c51a9SNicolas Vasilache for (unsigned d = 0, e = rankLHS; d < e; ++d) { 5055c0c51a9SNicolas Vasilache // shufflevector explicitly requires i32. 5065c0c51a9SNicolas Vasilache auto attr = rewriter.getI32IntegerAttr(d); 5075c0c51a9SNicolas Vasilache SmallVector<Attribute, 4> bcastAttr(rankRHS, attr); 5085c0c51a9SNicolas Vasilache auto bcastArrayAttr = ArrayAttr::get(bcastAttr, ctx); 509*35807bc4SRiver Riddle ValuePtr aD = nullptr, accD = nullptr; 5105c0c51a9SNicolas Vasilache // 1. Broadcast the element a[d] into vector aD. 5115c0c51a9SNicolas Vasilache aD = rewriter.create<LLVM::ShuffleVectorOp>(loc, a, a, bcastArrayAttr); 5125c0c51a9SNicolas Vasilache // 2. If acc is present, extract 1-d vector acc[d] into accD. 5135c0c51a9SNicolas Vasilache if (acc) 5145c0c51a9SNicolas Vasilache accD = rewriter.create<LLVM::ExtractValueOp>( 5155c0c51a9SNicolas Vasilache loc, vRHS, acc, rewriter.getI64ArrayAttr(d)); 5165c0c51a9SNicolas Vasilache // 3. Compute aD outer b (plus accD, if relevant). 517*35807bc4SRiver Riddle ValuePtr aOuterbD = 5185c0c51a9SNicolas Vasilache accD ? rewriter.create<LLVM::FMulAddOp>(loc, vRHS, aD, b, accD) 5195c0c51a9SNicolas Vasilache .getResult() 5205c0c51a9SNicolas Vasilache : rewriter.create<LLVM::FMulOp>(loc, aD, b).getResult(); 5215c0c51a9SNicolas Vasilache // 4. Insert as value `d` in the descriptor. 5225c0c51a9SNicolas Vasilache desc = rewriter.create<LLVM::InsertValueOp>(loc, llvmArrayOfVectType, 5235c0c51a9SNicolas Vasilache desc, aOuterbD, 5245c0c51a9SNicolas Vasilache rewriter.getI64ArrayAttr(d)); 5255c0c51a9SNicolas Vasilache } 5265c0c51a9SNicolas Vasilache rewriter.replaceOp(op, desc); 5275c0c51a9SNicolas Vasilache return matchSuccess(); 5285c0c51a9SNicolas Vasilache } 5295c0c51a9SNicolas Vasilache }; 5305c0c51a9SNicolas Vasilache 5315c0c51a9SNicolas Vasilache class VectorTypeCastOpConversion : public LLVMOpLowering { 5325c0c51a9SNicolas Vasilache public: 5335c0c51a9SNicolas Vasilache explicit VectorTypeCastOpConversion(MLIRContext *context, 5345c0c51a9SNicolas Vasilache LLVMTypeConverter &typeConverter) 5355c0c51a9SNicolas Vasilache : LLVMOpLowering(vector::TypeCastOp::getOperationName(), context, 5365c0c51a9SNicolas Vasilache typeConverter) {} 5375c0c51a9SNicolas Vasilache 5385c0c51a9SNicolas Vasilache PatternMatchResult 539*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 5405c0c51a9SNicolas Vasilache ConversionPatternRewriter &rewriter) const override { 5415c0c51a9SNicolas Vasilache auto loc = op->getLoc(); 5425c0c51a9SNicolas Vasilache vector::TypeCastOp castOp = cast<vector::TypeCastOp>(op); 5435c0c51a9SNicolas Vasilache MemRefType sourceMemRefType = 5445c0c51a9SNicolas Vasilache castOp.getOperand()->getType().cast<MemRefType>(); 5455c0c51a9SNicolas Vasilache MemRefType targetMemRefType = 5465c0c51a9SNicolas Vasilache castOp.getResult()->getType().cast<MemRefType>(); 5475c0c51a9SNicolas Vasilache 5485c0c51a9SNicolas Vasilache // Only static shape casts supported atm. 5495c0c51a9SNicolas Vasilache if (!sourceMemRefType.hasStaticShape() || 5505c0c51a9SNicolas Vasilache !targetMemRefType.hasStaticShape()) 5515c0c51a9SNicolas Vasilache return matchFailure(); 5525c0c51a9SNicolas Vasilache 5535c0c51a9SNicolas Vasilache auto llvmSourceDescriptorTy = 5545c0c51a9SNicolas Vasilache operands[0]->getType().dyn_cast<LLVM::LLVMType>(); 5555c0c51a9SNicolas Vasilache if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy()) 5565c0c51a9SNicolas Vasilache return matchFailure(); 5575c0c51a9SNicolas Vasilache MemRefDescriptor sourceMemRef(operands[0]); 5585c0c51a9SNicolas Vasilache 5595c0c51a9SNicolas Vasilache auto llvmTargetDescriptorTy = lowering.convertType(targetMemRefType) 5605c0c51a9SNicolas Vasilache .dyn_cast_or_null<LLVM::LLVMType>(); 5615c0c51a9SNicolas Vasilache if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy()) 5625c0c51a9SNicolas Vasilache return matchFailure(); 5635c0c51a9SNicolas Vasilache 5645c0c51a9SNicolas Vasilache int64_t offset; 5655c0c51a9SNicolas Vasilache SmallVector<int64_t, 4> strides; 5665c0c51a9SNicolas Vasilache auto successStrides = 5675c0c51a9SNicolas Vasilache getStridesAndOffset(sourceMemRefType, strides, offset); 5685c0c51a9SNicolas Vasilache bool isContiguous = (strides.back() == 1); 5695c0c51a9SNicolas Vasilache if (isContiguous) { 5705c0c51a9SNicolas Vasilache auto sizes = sourceMemRefType.getShape(); 5715c0c51a9SNicolas Vasilache for (int index = 0, e = strides.size() - 2; index < e; ++index) { 5725c0c51a9SNicolas Vasilache if (strides[index] != strides[index + 1] * sizes[index + 1]) { 5735c0c51a9SNicolas Vasilache isContiguous = false; 5745c0c51a9SNicolas Vasilache break; 5755c0c51a9SNicolas Vasilache } 5765c0c51a9SNicolas Vasilache } 5775c0c51a9SNicolas Vasilache } 5785c0c51a9SNicolas Vasilache // Only contiguous source tensors supported atm. 5795c0c51a9SNicolas Vasilache if (failed(successStrides) || !isContiguous) 5805c0c51a9SNicolas Vasilache return matchFailure(); 5815c0c51a9SNicolas Vasilache 5825c0c51a9SNicolas Vasilache auto int64Ty = LLVM::LLVMType::getInt64Ty(lowering.getDialect()); 5835c0c51a9SNicolas Vasilache 5845c0c51a9SNicolas Vasilache // Create descriptor. 5855c0c51a9SNicolas Vasilache auto desc = MemRefDescriptor::undef(rewriter, loc, llvmTargetDescriptorTy); 5865c0c51a9SNicolas Vasilache Type llvmTargetElementTy = desc.getElementType(); 5875c0c51a9SNicolas Vasilache // Set allocated ptr. 588*35807bc4SRiver Riddle ValuePtr allocated = sourceMemRef.allocatedPtr(rewriter, loc); 5895c0c51a9SNicolas Vasilache allocated = 5905c0c51a9SNicolas Vasilache rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, allocated); 5915c0c51a9SNicolas Vasilache desc.setAllocatedPtr(rewriter, loc, allocated); 5925c0c51a9SNicolas Vasilache // Set aligned ptr. 593*35807bc4SRiver Riddle ValuePtr ptr = sourceMemRef.alignedPtr(rewriter, loc); 5945c0c51a9SNicolas Vasilache ptr = rewriter.create<LLVM::BitcastOp>(loc, llvmTargetElementTy, ptr); 5955c0c51a9SNicolas Vasilache desc.setAlignedPtr(rewriter, loc, ptr); 5965c0c51a9SNicolas Vasilache // Fill offset 0. 5975c0c51a9SNicolas Vasilache auto attr = rewriter.getIntegerAttr(rewriter.getIndexType(), 0); 5985c0c51a9SNicolas Vasilache auto zero = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, attr); 5995c0c51a9SNicolas Vasilache desc.setOffset(rewriter, loc, zero); 6005c0c51a9SNicolas Vasilache 6015c0c51a9SNicolas Vasilache // Fill size and stride descriptors in memref. 6025c0c51a9SNicolas Vasilache for (auto indexedSize : llvm::enumerate(targetMemRefType.getShape())) { 6035c0c51a9SNicolas Vasilache int64_t index = indexedSize.index(); 6045c0c51a9SNicolas Vasilache auto sizeAttr = 6055c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), indexedSize.value()); 6065c0c51a9SNicolas Vasilache auto size = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, sizeAttr); 6075c0c51a9SNicolas Vasilache desc.setSize(rewriter, loc, index, size); 6085c0c51a9SNicolas Vasilache auto strideAttr = 6095c0c51a9SNicolas Vasilache rewriter.getIntegerAttr(rewriter.getIndexType(), strides[index]); 6105c0c51a9SNicolas Vasilache auto stride = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, strideAttr); 6115c0c51a9SNicolas Vasilache desc.setStride(rewriter, loc, index, stride); 6125c0c51a9SNicolas Vasilache } 6135c0c51a9SNicolas Vasilache 6145c0c51a9SNicolas Vasilache rewriter.replaceOp(op, {desc}); 6155c0c51a9SNicolas Vasilache return matchSuccess(); 6165c0c51a9SNicolas Vasilache } 6175c0c51a9SNicolas Vasilache }; 6185c0c51a9SNicolas Vasilache 619d9b500d3SAart Bik class VectorPrintOpConversion : public LLVMOpLowering { 620d9b500d3SAart Bik public: 621d9b500d3SAart Bik explicit VectorPrintOpConversion(MLIRContext *context, 622d9b500d3SAart Bik LLVMTypeConverter &typeConverter) 623d9b500d3SAart Bik : LLVMOpLowering(vector::PrintOp::getOperationName(), context, 624d9b500d3SAart Bik typeConverter) {} 625d9b500d3SAart Bik 626d9b500d3SAart Bik // Proof-of-concept lowering implementation that relies on a small 627d9b500d3SAart Bik // runtime support library, which only needs to provide a few 628d9b500d3SAart Bik // printing methods (single value for all data types, opening/closing 629d9b500d3SAart Bik // bracket, comma, newline). The lowering fully unrolls a vector 630d9b500d3SAart Bik // in terms of these elementary printing operations. The advantage 631d9b500d3SAart Bik // of this approach is that the library can remain unaware of all 632d9b500d3SAart Bik // low-level implementation details of vectors while still supporting 633d9b500d3SAart Bik // output of any shaped and dimensioned vector. Due to full unrolling, 634d9b500d3SAart Bik // this approach is less suited for very large vectors though. 635d9b500d3SAart Bik // 636d9b500d3SAart Bik // TODO(ajcbik): rely solely on libc in future? something else? 637d9b500d3SAart Bik // 638d9b500d3SAart Bik PatternMatchResult 639*35807bc4SRiver Riddle matchAndRewrite(Operation *op, ArrayRef<ValuePtr> operands, 640d9b500d3SAart Bik ConversionPatternRewriter &rewriter) const override { 641d9b500d3SAart Bik auto printOp = cast<vector::PrintOp>(op); 642d9b500d3SAart Bik auto adaptor = vector::PrintOpOperandAdaptor(operands); 643d9b500d3SAart Bik Type printType = printOp.getPrintType(); 644d9b500d3SAart Bik 645d9b500d3SAart Bik if (lowering.convertType(printType) == nullptr) 646d9b500d3SAart Bik return matchFailure(); 647d9b500d3SAart Bik 648d9b500d3SAart Bik // Make sure element type has runtime support (currently just Float/Double). 649d9b500d3SAart Bik VectorType vectorType = printType.dyn_cast<VectorType>(); 650d9b500d3SAart Bik Type eltType = vectorType ? vectorType.getElementType() : printType; 651d9b500d3SAart Bik int64_t rank = vectorType ? vectorType.getRank() : 0; 652d9b500d3SAart Bik Operation *printer; 653d9b500d3SAart Bik if (eltType.isF32()) 654d9b500d3SAart Bik printer = getPrintFloat(op); 655d9b500d3SAart Bik else if (eltType.isF64()) 656d9b500d3SAart Bik printer = getPrintDouble(op); 657d9b500d3SAart Bik else 658d9b500d3SAart Bik return matchFailure(); 659d9b500d3SAart Bik 660d9b500d3SAart Bik // Unroll vector into elementary print calls. 661d9b500d3SAart Bik emitRanks(rewriter, op, adaptor.source(), vectorType, printer, rank); 662d9b500d3SAart Bik emitCall(rewriter, op->getLoc(), getPrintNewline(op)); 663d9b500d3SAart Bik rewriter.eraseOp(op); 664d9b500d3SAart Bik return matchSuccess(); 665d9b500d3SAart Bik } 666d9b500d3SAart Bik 667d9b500d3SAart Bik private: 668d9b500d3SAart Bik void emitRanks(ConversionPatternRewriter &rewriter, Operation *op, 669*35807bc4SRiver Riddle ValuePtr value, VectorType vectorType, Operation *printer, 670d9b500d3SAart Bik int64_t rank) const { 671d9b500d3SAart Bik Location loc = op->getLoc(); 672d9b500d3SAart Bik if (rank == 0) { 673d9b500d3SAart Bik emitCall(rewriter, loc, printer, value); 674d9b500d3SAart Bik return; 675d9b500d3SAart Bik } 676d9b500d3SAart Bik 677d9b500d3SAart Bik emitCall(rewriter, loc, getPrintOpen(op)); 678d9b500d3SAart Bik Operation *printComma = getPrintComma(op); 679d9b500d3SAart Bik int64_t dim = vectorType.getDimSize(0); 680d9b500d3SAart Bik for (int64_t d = 0; d < dim; ++d) { 681d9b500d3SAart Bik auto reducedType = 682d9b500d3SAart Bik rank > 1 ? reducedVectorTypeFront(vectorType) : nullptr; 683d9b500d3SAart Bik auto llvmType = lowering.convertType( 684d9b500d3SAart Bik rank > 1 ? reducedType : vectorType.getElementType()); 685*35807bc4SRiver Riddle ValuePtr nestedVal = 686d9b500d3SAart Bik extractOne(rewriter, lowering, loc, value, llvmType, rank, d); 687d9b500d3SAart Bik emitRanks(rewriter, op, nestedVal, reducedType, printer, rank - 1); 688d9b500d3SAart Bik if (d != dim - 1) 689d9b500d3SAart Bik emitCall(rewriter, loc, printComma); 690d9b500d3SAart Bik } 691d9b500d3SAart Bik emitCall(rewriter, loc, getPrintClose(op)); 692d9b500d3SAart Bik } 693d9b500d3SAart Bik 694d9b500d3SAart Bik // Helper to emit a call. 695d9b500d3SAart Bik static void emitCall(ConversionPatternRewriter &rewriter, Location loc, 696d9b500d3SAart Bik Operation *ref, ValueRange params = ValueRange()) { 697d9b500d3SAart Bik rewriter.create<LLVM::CallOp>(loc, ArrayRef<Type>{}, 698d9b500d3SAart Bik rewriter.getSymbolRefAttr(ref), params); 699d9b500d3SAart Bik } 700d9b500d3SAart Bik 701d9b500d3SAart Bik // Helper for printer method declaration (first hit) and lookup. 702d9b500d3SAart Bik static Operation *getPrint(Operation *op, LLVM::LLVMDialect *dialect, 703d9b500d3SAart Bik StringRef name, ArrayRef<LLVM::LLVMType> params) { 704d9b500d3SAart Bik auto module = op->getParentOfType<ModuleOp>(); 705d9b500d3SAart Bik auto func = module.lookupSymbol<LLVM::LLVMFuncOp>(name); 706d9b500d3SAart Bik if (func) 707d9b500d3SAart Bik return func; 708d9b500d3SAart Bik OpBuilder moduleBuilder(module.getBodyRegion()); 709d9b500d3SAart Bik return moduleBuilder.create<LLVM::LLVMFuncOp>( 710d9b500d3SAart Bik op->getLoc(), name, 711d9b500d3SAart Bik LLVM::LLVMType::getFunctionTy(LLVM::LLVMType::getVoidTy(dialect), 712d9b500d3SAart Bik params, /*isVarArg=*/false)); 713d9b500d3SAart Bik } 714d9b500d3SAart Bik 715d9b500d3SAart Bik // Helpers for method names. 716d9b500d3SAart Bik Operation *getPrintFloat(Operation *op) const { 717d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 718d9b500d3SAart Bik return getPrint(op, dialect, "print_f32", 719d9b500d3SAart Bik LLVM::LLVMType::getFloatTy(dialect)); 720d9b500d3SAart Bik } 721d9b500d3SAart Bik Operation *getPrintDouble(Operation *op) const { 722d9b500d3SAart Bik LLVM::LLVMDialect *dialect = lowering.getDialect(); 723d9b500d3SAart Bik return getPrint(op, dialect, "print_f64", 724d9b500d3SAart Bik LLVM::LLVMType::getDoubleTy(dialect)); 725d9b500d3SAart Bik } 726d9b500d3SAart Bik Operation *getPrintOpen(Operation *op) const { 727d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_open", {}); 728d9b500d3SAart Bik } 729d9b500d3SAart Bik Operation *getPrintClose(Operation *op) const { 730d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_close", {}); 731d9b500d3SAart Bik } 732d9b500d3SAart Bik Operation *getPrintComma(Operation *op) const { 733d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_comma", {}); 734d9b500d3SAart Bik } 735d9b500d3SAart Bik Operation *getPrintNewline(Operation *op) const { 736d9b500d3SAart Bik return getPrint(op, lowering.getDialect(), "print_newline", {}); 737d9b500d3SAart Bik } 738d9b500d3SAart Bik }; 739d9b500d3SAart Bik 7405c0c51a9SNicolas Vasilache /// Populate the given list with patterns that convert from Vector to LLVM. 7415c0c51a9SNicolas Vasilache void mlir::populateVectorToLLVMConversionPatterns( 7425c0c51a9SNicolas Vasilache LLVMTypeConverter &converter, OwningRewritePatternList &patterns) { 7431c81adf3SAart Bik patterns.insert<VectorBroadcastOpConversion, VectorShuffleOpConversion, 744cd5dab8aSAart Bik VectorExtractElementOpConversion, VectorExtractOpConversion, 745cd5dab8aSAart Bik VectorInsertElementOpConversion, VectorInsertOpConversion, 746d9b500d3SAart Bik VectorOuterProductOpConversion, VectorTypeCastOpConversion, 747d9b500d3SAart Bik VectorPrintOpConversion>(converter.getDialect()->getContext(), 748d9b500d3SAart Bik converter); 7495c0c51a9SNicolas Vasilache } 7505c0c51a9SNicolas Vasilache 7515c0c51a9SNicolas Vasilache namespace { 7525c0c51a9SNicolas Vasilache struct LowerVectorToLLVMPass : public ModulePass<LowerVectorToLLVMPass> { 7535c0c51a9SNicolas Vasilache void runOnModule() override; 7545c0c51a9SNicolas Vasilache }; 7555c0c51a9SNicolas Vasilache } // namespace 7565c0c51a9SNicolas Vasilache 7575c0c51a9SNicolas Vasilache void LowerVectorToLLVMPass::runOnModule() { 7585c0c51a9SNicolas Vasilache // Convert to the LLVM IR dialect using the converter defined above. 7595c0c51a9SNicolas Vasilache OwningRewritePatternList patterns; 7605c0c51a9SNicolas Vasilache LLVMTypeConverter converter(&getContext()); 7615c0c51a9SNicolas Vasilache populateVectorToLLVMConversionPatterns(converter, patterns); 7625c0c51a9SNicolas Vasilache populateStdToLLVMConversionPatterns(converter, patterns); 7635c0c51a9SNicolas Vasilache 7645c0c51a9SNicolas Vasilache ConversionTarget target(getContext()); 7655c0c51a9SNicolas Vasilache target.addLegalDialect<LLVM::LLVMDialect>(); 7665c0c51a9SNicolas Vasilache target.addDynamicallyLegalOp<FuncOp>( 7675c0c51a9SNicolas Vasilache [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); }); 7685c0c51a9SNicolas Vasilache if (failed( 7695c0c51a9SNicolas Vasilache applyPartialConversion(getModule(), target, patterns, &converter))) { 7705c0c51a9SNicolas Vasilache signalPassFailure(); 7715c0c51a9SNicolas Vasilache } 7725c0c51a9SNicolas Vasilache } 7735c0c51a9SNicolas Vasilache 7745c0c51a9SNicolas Vasilache OpPassBase<ModuleOp> *mlir::createLowerVectorToLLVMPass() { 7755c0c51a9SNicolas Vasilache return new LowerVectorToLLVMPass(); 7765c0c51a9SNicolas Vasilache } 7775c0c51a9SNicolas Vasilache 7785c0c51a9SNicolas Vasilache static PassRegistration<LowerVectorToLLVMPass> 7795c0c51a9SNicolas Vasilache pass("convert-vector-to-llvm", 7805c0c51a9SNicolas Vasilache "Lower the operations from the vector dialect into the LLVM dialect"); 781