1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, TF = 17
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 using namespace X86Disassembler;
123 
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
126 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 ///   0b11.
128 ///
129 /// @param form - The form of the instruction.
130 /// @return     - true if the form implies that a ModR/M byte is required, false
131 ///               otherwise.
132 static bool needsModRMForDecode(uint8_t form) {
133   if (form == X86Local::MRMDestReg    ||
134      form == X86Local::MRMDestMem    ||
135      form == X86Local::MRMSrcReg     ||
136      form == X86Local::MRMSrcMem     ||
137      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
139     return true;
140   else
141     return false;
142 }
143 
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 ///   the ModR/M byte to be 0b11.
146 ///
147 /// @param form - The form of the instruction.
148 /// @return     - true if the form implies that Mod must be 0b11, false
149 ///               otherwise.
150 static bool isRegFormat(uint8_t form) {
151   if (form == X86Local::MRMDestReg ||
152      form == X86Local::MRMSrcReg  ||
153      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
154     return true;
155   else
156     return false;
157 }
158 
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 ///   Useful for switch statements and the like.
161 ///
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return     - The field, with the first bit in the BitsInit as the lowest
164 ///               order bit.
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166   int width = init.getNumBits();
167 
168   assert(width <= 8 && "Field is too large for uint8_t!");
169 
170   int     index;
171   uint8_t mask = 0x01;
172 
173   uint8_t ret = 0;
174 
175   for (index = 0; index < width; index++) {
176     if (static_cast<BitInit*>(init.getBit(index))->getValue())
177       ret |= mask;
178 
179     mask <<= 1;
180   }
181 
182   return ret;
183 }
184 
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 ///   name of the field.
187 ///
188 /// @param rec  - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return     - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192   BitsInit* bits = rec->getValueAsBitsInit(name);
193   return byteFromBitsInit(*bits);
194 }
195 
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197                                      const CodeGenInstruction &insn,
198                                      InstrUID uid) {
199   UID = uid;
200 
201   Rec = insn.TheDef;
202   Name = Rec->getName();
203   Spec = &tables.specForUID(UID);
204 
205   if (!Rec->isSubClassOf("X86Inst")) {
206     ShouldBeEmitted = false;
207     return;
208   }
209 
210   Prefix   = byteFromRec(Rec, "Prefix");
211   Opcode   = byteFromRec(Rec, "Opcode");
212   Form     = byteFromRec(Rec, "FormBits");
213   SegOvr   = byteFromRec(Rec, "SegOvrBits");
214 
215   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
216   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
217   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
218   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
219   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
220   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
221   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
222 
223   Name      = Rec->getName();
224   AsmString = Rec->getValueAsString("AsmString");
225 
226   Operands = &insn.Operands.OperandList;
227 
228   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
229                      (Name.find("CRC32") != Name.npos);
230   HasFROperands    = hasFROperands();
231   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
232 
233   // Check for 64-bit inst which does not require REX
234   Is64Bit = false;
235   // FIXME: Is there some better way to check for In64BitMode?
236   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
237   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
238     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
239       Is64Bit = true;
240       break;
241     }
242   }
243   // FIXME: These instructions aren't marked as 64-bit in any way
244   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
245              Rec->getName() == "MASKMOVDQU64" ||
246              Rec->getName() == "POPFS64" ||
247              Rec->getName() == "POPGS64" ||
248              Rec->getName() == "PUSHFS64" ||
249              Rec->getName() == "PUSHGS64" ||
250              Rec->getName() == "REX64_PREFIX" ||
251              Rec->getName().find("VMREAD64") != Name.npos ||
252              Rec->getName().find("VMWRITE64") != Name.npos ||
253              Rec->getName().find("MOV64") != Name.npos ||
254              Rec->getName().find("PUSH64") != Name.npos ||
255              Rec->getName().find("POP64") != Name.npos;
256 
257   ShouldBeEmitted  = true;
258 }
259 
260 void RecognizableInstr::processInstr(DisassemblerTables &tables,
261 	const CodeGenInstruction &insn,
262                                    InstrUID uid)
263 {
264   // Ignore "asm parser only" instructions.
265   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
266     return;
267 
268   RecognizableInstr recogInstr(tables, insn, uid);
269 
270   recogInstr.emitInstructionSpecifier(tables);
271 
272   if (recogInstr.shouldBeEmitted())
273     recogInstr.emitDecodePath(tables);
274 }
275 
276 InstructionContext RecognizableInstr::insnContext() const {
277   InstructionContext insnContext;
278 
279   if (HasVEX_4VPrefix || HasVEXPrefix) {
280     if (HasOpSizePrefix && HasVEX_LPrefix)
281       insnContext = IC_VEX_L_OPSIZE;
282     else if (HasOpSizePrefix && HasVEX_WPrefix)
283       insnContext = IC_VEX_W_OPSIZE;
284     else if (HasOpSizePrefix)
285       insnContext = IC_VEX_OPSIZE;
286     else if (HasVEX_LPrefix && Prefix == X86Local::XS)
287       insnContext = IC_VEX_L_XS;
288     else if (HasVEX_LPrefix && Prefix == X86Local::XD)
289       insnContext = IC_VEX_L_XD;
290     else if (HasVEX_WPrefix && Prefix == X86Local::XS)
291       insnContext = IC_VEX_W_XS;
292     else if (HasVEX_WPrefix && Prefix == X86Local::XD)
293       insnContext = IC_VEX_W_XD;
294     else if (HasVEX_WPrefix)
295       insnContext = IC_VEX_W;
296     else if (HasVEX_LPrefix)
297       insnContext = IC_VEX_L;
298     else if (Prefix == X86Local::XD)
299       insnContext = IC_VEX_XD;
300     else if (Prefix == X86Local::XS)
301       insnContext = IC_VEX_XS;
302     else
303       insnContext = IC_VEX;
304   } else if (Is64Bit || HasREX_WPrefix) {
305     if (HasREX_WPrefix && HasOpSizePrefix)
306       insnContext = IC_64BIT_REXW_OPSIZE;
307     else if (HasOpSizePrefix)
308       insnContext = IC_64BIT_OPSIZE;
309     else if (HasREX_WPrefix && Prefix == X86Local::XS)
310       insnContext = IC_64BIT_REXW_XS;
311     else if (HasREX_WPrefix && Prefix == X86Local::XD)
312       insnContext = IC_64BIT_REXW_XD;
313     else if (Prefix == X86Local::XD)
314       insnContext = IC_64BIT_XD;
315     else if (Prefix == X86Local::XS)
316       insnContext = IC_64BIT_XS;
317     else if (HasREX_WPrefix)
318       insnContext = IC_64BIT_REXW;
319     else
320       insnContext = IC_64BIT;
321   } else {
322     if (HasOpSizePrefix && Prefix == X86Local::TF)
323       insnContext = IC_XD;
324     else if (HasOpSizePrefix)
325       insnContext = IC_OPSIZE;
326     else if (Prefix == X86Local::XD)
327       insnContext = IC_XD;
328     else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
329       insnContext = IC_XS;
330     else
331       insnContext = IC;
332   }
333 
334   return insnContext;
335 }
336 
337 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
338   ///////////////////
339   // FILTER_STRONG
340   //
341 
342   // Filter out intrinsics
343 
344   if (!Rec->isSubClassOf("X86Inst"))
345     return FILTER_STRONG;
346 
347   if (Form == X86Local::Pseudo ||
348       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
349     return FILTER_STRONG;
350 
351   if (Form == X86Local::MRMInitReg)
352     return FILTER_STRONG;
353 
354 
355   // TEMPORARY pending bug fixes
356 
357   if (Name.find("VMOVDQU") != Name.npos ||
358       Name.find("VMOVDQA") != Name.npos ||
359       Name.find("VROUND") != Name.npos)
360     return FILTER_STRONG;
361 
362   // Filter out artificial instructions
363 
364   if (Name.find("TAILJMP") != Name.npos    ||
365       Name.find("_Int") != Name.npos       ||
366       Name.find("_int") != Name.npos       ||
367       Name.find("Int_") != Name.npos       ||
368       Name.find("_NOREX") != Name.npos     ||
369       Name.find("_TC") != Name.npos        ||
370       Name.find("EH_RETURN") != Name.npos  ||
371       Name.find("V_SET") != Name.npos      ||
372       Name.find("LOCK_") != Name.npos      ||
373       Name.find("WIN") != Name.npos        ||
374       Name.find("_AVX") != Name.npos       ||
375       Name.find("2SDL") != Name.npos)
376     return FILTER_STRONG;
377 
378   // Filter out instructions with segment override prefixes.
379   // They're too messy to handle now and we'll special case them if needed.
380 
381   if (SegOvr)
382     return FILTER_STRONG;
383 
384   // Filter out instructions that can't be printed.
385 
386   if (AsmString.size() == 0)
387     return FILTER_STRONG;
388 
389   // Filter out instructions with subreg operands.
390 
391   if (AsmString.find("subreg") != AsmString.npos)
392     return FILTER_STRONG;
393 
394   /////////////////
395   // FILTER_WEAK
396   //
397 
398 
399   // Filter out instructions with a LOCK prefix;
400   //   prefer forms that do not have the prefix
401   if (HasLockPrefix)
402     return FILTER_WEAK;
403 
404   // Filter out alternate forms of AVX instructions
405   if (Name.find("_alt") != Name.npos ||
406       Name.find("XrYr") != Name.npos ||
407       Name.find("r64r") != Name.npos ||
408       Name.find("_64mr") != Name.npos ||
409       Name.find("Xrr") != Name.npos ||
410       Name.find("rr64") != Name.npos)
411     return FILTER_WEAK;
412 
413   if (Name == "VMASKMOVDQU64"  ||
414       Name == "VEXTRACTPSrr64" ||
415       Name == "VMOVQd64rr"     ||
416       Name == "VMOVQs64rr")
417     return FILTER_WEAK;
418 
419   // Special cases.
420 
421   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
422     return FILTER_WEAK;
423   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
424     return FILTER_WEAK;
425 
426   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
427     return FILTER_WEAK;
428   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
429     return FILTER_WEAK;
430   if (Name.find("Fs") != Name.npos)
431     return FILTER_WEAK;
432   if (Name == "MOVLPDrr"          ||
433       Name == "MOVLPSrr"          ||
434       Name == "PUSHFQ"            ||
435       Name == "BSF16rr"           ||
436       Name == "BSF16rm"           ||
437       Name == "BSR16rr"           ||
438       Name == "BSR16rm"           ||
439       Name == "MOVSX16rm8"        ||
440       Name == "MOVSX16rr8"        ||
441       Name == "MOVZX16rm8"        ||
442       Name == "MOVZX16rr8"        ||
443       Name == "PUSH32i16"         ||
444       Name == "PUSH64i16"         ||
445       Name == "MOVPQI2QImr"       ||
446       Name == "VMOVPQI2QImr"      ||
447       Name == "MOVSDmr"           ||
448       Name == "MOVSDrm"           ||
449       Name == "MOVSSmr"           ||
450       Name == "MOVSSrm"           ||
451       Name == "MMX_MOVD64rrv164"  ||
452       Name == "CRC32m16"          ||
453       Name == "MOV64ri64i32"      ||
454       Name == "CRC32r16")
455     return FILTER_WEAK;
456 
457   if (HasFROperands && Name.find("MOV") != Name.npos &&
458      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
459       (Name.find("to") != Name.npos)))
460     return FILTER_WEAK;
461 
462   return FILTER_NORMAL;
463 }
464 
465 bool RecognizableInstr::hasFROperands() const {
466   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
467   unsigned numOperands = OperandList.size();
468 
469   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
470     const std::string &recName = OperandList[operandIndex].Rec->getName();
471 
472     if (recName.find("FR") != recName.npos)
473       return true;
474   }
475   return false;
476 }
477 
478 bool RecognizableInstr::has256BitOperands() const {
479   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
480   unsigned numOperands = OperandList.size();
481 
482   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
483     const std::string &recName = OperandList[operandIndex].Rec->getName();
484 
485     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
486       return true;
487     }
488   }
489   return false;
490 }
491 
492 void RecognizableInstr::handleOperand(
493   bool optional,
494   unsigned &operandIndex,
495   unsigned &physicalOperandIndex,
496   unsigned &numPhysicalOperands,
497   unsigned *operandMapping,
498   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
499   if (optional) {
500     if (physicalOperandIndex >= numPhysicalOperands)
501       return;
502   } else {
503     assert(physicalOperandIndex < numPhysicalOperands);
504   }
505 
506   while (operandMapping[operandIndex] != operandIndex) {
507     Spec->operands[operandIndex].encoding = ENCODING_DUP;
508     Spec->operands[operandIndex].type =
509       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
510     ++operandIndex;
511   }
512 
513   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
514 
515   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
516                                                               HasOpSizePrefix);
517   Spec->operands[operandIndex].type = typeFromString(typeName,
518                                                      IsSSE,
519                                                      HasREX_WPrefix,
520                                                      HasOpSizePrefix);
521 
522   ++operandIndex;
523   ++physicalOperandIndex;
524 }
525 
526 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
527   Spec->name       = Name;
528 
529   if (!Rec->isSubClassOf("X86Inst"))
530     return;
531 
532   switch (filter()) {
533   case FILTER_WEAK:
534     Spec->filtered = true;
535     break;
536   case FILTER_STRONG:
537     ShouldBeEmitted = false;
538     return;
539   case FILTER_NORMAL:
540     break;
541   }
542 
543   Spec->insnContext = insnContext();
544 
545   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
546 
547   unsigned operandIndex;
548   unsigned numOperands = OperandList.size();
549   unsigned numPhysicalOperands = 0;
550 
551   // operandMapping maps from operands in OperandList to their originals.
552   // If operandMapping[i] != i, then the entry is a duplicate.
553   unsigned operandMapping[X86_MAX_OPERANDS];
554 
555   bool hasFROperands = false;
556 
557   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
558 
559   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
560     if (OperandList[operandIndex].Constraints.size()) {
561       const CGIOperandList::ConstraintInfo &Constraint =
562         OperandList[operandIndex].Constraints[0];
563       if (Constraint.isTied()) {
564         operandMapping[operandIndex] = Constraint.getTiedOperand();
565       } else {
566         ++numPhysicalOperands;
567         operandMapping[operandIndex] = operandIndex;
568       }
569     } else {
570       ++numPhysicalOperands;
571       operandMapping[operandIndex] = operandIndex;
572     }
573 
574     const std::string &recName = OperandList[operandIndex].Rec->getName();
575 
576     if (recName.find("FR") != recName.npos)
577       hasFROperands = true;
578   }
579 
580   if (hasFROperands && Name.find("MOV") != Name.npos &&
581      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
582       (Name.find("to") != Name.npos)))
583     ShouldBeEmitted = false;
584 
585   if (!ShouldBeEmitted)
586     return;
587 
588 #define HANDLE_OPERAND(class)               \
589   handleOperand(false,                      \
590                 operandIndex,               \
591                 physicalOperandIndex,       \
592                 numPhysicalOperands,        \
593                 operandMapping,             \
594                 class##EncodingFromString);
595 
596 #define HANDLE_OPTIONAL(class)              \
597   handleOperand(true,                       \
598                 operandIndex,               \
599                 physicalOperandIndex,       \
600                 numPhysicalOperands,        \
601                 operandMapping,             \
602                 class##EncodingFromString);
603 
604   // operandIndex should always be < numOperands
605   operandIndex = 0;
606   // physicalOperandIndex should always be < numPhysicalOperands
607   unsigned physicalOperandIndex = 0;
608 
609   switch (Form) {
610   case X86Local::RawFrm:
611     // Operand 1 (optional) is an address or immediate.
612     // Operand 2 (optional) is an immediate.
613     assert(numPhysicalOperands <= 2 &&
614            "Unexpected number of operands for RawFrm");
615     HANDLE_OPTIONAL(relocation)
616     HANDLE_OPTIONAL(immediate)
617     break;
618   case X86Local::AddRegFrm:
619     // Operand 1 is added to the opcode.
620     // Operand 2 (optional) is an address.
621     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
622            "Unexpected number of operands for AddRegFrm");
623     HANDLE_OPERAND(opcodeModifier)
624     HANDLE_OPTIONAL(relocation)
625     break;
626   case X86Local::MRMDestReg:
627     // Operand 1 is a register operand in the R/M field.
628     // Operand 2 is a register operand in the Reg/Opcode field.
629     // - In AVX, there is a register operand in the VEX.vvvv field here -
630     // Operand 3 (optional) is an immediate.
631     if (HasVEX_4VPrefix)
632       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
633              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
634     else
635       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
636              "Unexpected number of operands for MRMDestRegFrm");
637 
638     HANDLE_OPERAND(rmRegister)
639 
640     if (HasVEX_4VPrefix)
641       // FIXME: In AVX, the register below becomes the one encoded
642       // in ModRMVEX and the one above the one in the VEX.VVVV field
643       HANDLE_OPERAND(vvvvRegister)
644 
645     HANDLE_OPERAND(roRegister)
646     HANDLE_OPTIONAL(immediate)
647     break;
648   case X86Local::MRMDestMem:
649     // Operand 1 is a memory operand (possibly SIB-extended)
650     // Operand 2 is a register operand in the Reg/Opcode field.
651     // - In AVX, there is a register operand in the VEX.vvvv field here -
652     // Operand 3 (optional) is an immediate.
653     if (HasVEX_4VPrefix)
654       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
655              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
656     else
657       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
658              "Unexpected number of operands for MRMDestMemFrm");
659     HANDLE_OPERAND(memory)
660 
661     if (HasVEX_4VPrefix)
662       // FIXME: In AVX, the register below becomes the one encoded
663       // in ModRMVEX and the one above the one in the VEX.VVVV field
664       HANDLE_OPERAND(vvvvRegister)
665 
666     HANDLE_OPERAND(roRegister)
667     HANDLE_OPTIONAL(immediate)
668     break;
669   case X86Local::MRMSrcReg:
670     // Operand 1 is a register operand in the Reg/Opcode field.
671     // Operand 2 is a register operand in the R/M field.
672     // - In AVX, there is a register operand in the VEX.vvvv field here -
673     // Operand 3 (optional) is an immediate.
674 
675     if (HasVEX_4VPrefix)
676       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
677              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
678     else
679       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
680              "Unexpected number of operands for MRMSrcRegFrm");
681 
682     HANDLE_OPERAND(roRegister)
683 
684     if (HasVEX_4VPrefix)
685       // FIXME: In AVX, the register below becomes the one encoded
686       // in ModRMVEX and the one above the one in the VEX.VVVV field
687       HANDLE_OPERAND(vvvvRegister)
688 
689     HANDLE_OPERAND(rmRegister)
690     HANDLE_OPTIONAL(immediate)
691     break;
692   case X86Local::MRMSrcMem:
693     // Operand 1 is a register operand in the Reg/Opcode field.
694     // Operand 2 is a memory operand (possibly SIB-extended)
695     // - In AVX, there is a register operand in the VEX.vvvv field here -
696     // Operand 3 (optional) is an immediate.
697 
698     if (HasVEX_4VPrefix)
699       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
700              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
701     else
702       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
703              "Unexpected number of operands for MRMSrcMemFrm");
704 
705     HANDLE_OPERAND(roRegister)
706 
707     if (HasVEX_4VPrefix)
708       // FIXME: In AVX, the register below becomes the one encoded
709       // in ModRMVEX and the one above the one in the VEX.VVVV field
710       HANDLE_OPERAND(vvvvRegister)
711 
712     HANDLE_OPERAND(memory)
713     HANDLE_OPTIONAL(immediate)
714     break;
715   case X86Local::MRM0r:
716   case X86Local::MRM1r:
717   case X86Local::MRM2r:
718   case X86Local::MRM3r:
719   case X86Local::MRM4r:
720   case X86Local::MRM5r:
721   case X86Local::MRM6r:
722   case X86Local::MRM7r:
723     // Operand 1 is a register operand in the R/M field.
724     // Operand 2 (optional) is an immediate or relocation.
725     if (HasVEX_4VPrefix)
726       assert(numPhysicalOperands <= 3 &&
727              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
728     else
729       assert(numPhysicalOperands <= 2 &&
730              "Unexpected number of operands for MRMnRFrm");
731     if (HasVEX_4VPrefix)
732       HANDLE_OPERAND(vvvvRegister);
733     HANDLE_OPTIONAL(rmRegister)
734     HANDLE_OPTIONAL(relocation)
735     break;
736   case X86Local::MRM0m:
737   case X86Local::MRM1m:
738   case X86Local::MRM2m:
739   case X86Local::MRM3m:
740   case X86Local::MRM4m:
741   case X86Local::MRM5m:
742   case X86Local::MRM6m:
743   case X86Local::MRM7m:
744     // Operand 1 is a memory operand (possibly SIB-extended)
745     // Operand 2 (optional) is an immediate or relocation.
746     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
747            "Unexpected number of operands for MRMnMFrm");
748     HANDLE_OPERAND(memory)
749     HANDLE_OPTIONAL(relocation)
750     break;
751   case X86Local::RawFrmImm8:
752     // operand 1 is a 16-bit immediate
753     // operand 2 is an 8-bit immediate
754     assert(numPhysicalOperands == 2 &&
755            "Unexpected number of operands for X86Local::RawFrmImm8");
756     HANDLE_OPERAND(immediate)
757     HANDLE_OPERAND(immediate)
758     break;
759   case X86Local::RawFrmImm16:
760     // operand 1 is a 16-bit immediate
761     // operand 2 is a 16-bit immediate
762     HANDLE_OPERAND(immediate)
763     HANDLE_OPERAND(immediate)
764     break;
765   case X86Local::MRMInitReg:
766     // Ignored.
767     break;
768   }
769 
770   #undef HANDLE_OPERAND
771   #undef HANDLE_OPTIONAL
772 }
773 
774 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
775   // Special cases where the LLVM tables are not complete
776 
777 #define MAP(from, to)                     \
778   case X86Local::MRM_##from:              \
779     filter = new ExactFilter(0x##from);   \
780     break;
781 
782   OpcodeType    opcodeType  = (OpcodeType)-1;
783 
784   ModRMFilter*  filter      = NULL;
785   uint8_t       opcodeToSet = 0;
786 
787   switch (Prefix) {
788   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
789   case X86Local::XD:
790   case X86Local::XS:
791   case X86Local::TB:
792     opcodeType = TWOBYTE;
793 
794     switch (Opcode) {
795     default:
796       if (needsModRMForDecode(Form))
797         filter = new ModFilter(isRegFormat(Form));
798       else
799         filter = new DumbFilter();
800       break;
801 #define EXTENSION_TABLE(n) case 0x##n:
802     TWO_BYTE_EXTENSION_TABLES
803 #undef EXTENSION_TABLE
804       switch (Form) {
805       default:
806         llvm_unreachable("Unhandled two-byte extended opcode");
807       case X86Local::MRM0r:
808       case X86Local::MRM1r:
809       case X86Local::MRM2r:
810       case X86Local::MRM3r:
811       case X86Local::MRM4r:
812       case X86Local::MRM5r:
813       case X86Local::MRM6r:
814       case X86Local::MRM7r:
815         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
816         break;
817       case X86Local::MRM0m:
818       case X86Local::MRM1m:
819       case X86Local::MRM2m:
820       case X86Local::MRM3m:
821       case X86Local::MRM4m:
822       case X86Local::MRM5m:
823       case X86Local::MRM6m:
824       case X86Local::MRM7m:
825         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
826         break;
827       MRM_MAPPING
828       } // switch (Form)
829       break;
830     } // switch (Opcode)
831     opcodeToSet = Opcode;
832     break;
833   case X86Local::T8:
834   case X86Local::TF:
835     opcodeType = THREEBYTE_38;
836     if (needsModRMForDecode(Form))
837       filter = new ModFilter(isRegFormat(Form));
838     else
839       filter = new DumbFilter();
840     opcodeToSet = Opcode;
841     break;
842   case X86Local::P_TA:
843     opcodeType = THREEBYTE_3A;
844     if (needsModRMForDecode(Form))
845       filter = new ModFilter(isRegFormat(Form));
846     else
847       filter = new DumbFilter();
848     opcodeToSet = Opcode;
849     break;
850   case X86Local::A6:
851     opcodeType = THREEBYTE_A6;
852     if (needsModRMForDecode(Form))
853       filter = new ModFilter(isRegFormat(Form));
854     else
855       filter = new DumbFilter();
856     opcodeToSet = Opcode;
857     break;
858   case X86Local::A7:
859     opcodeType = THREEBYTE_A7;
860     if (needsModRMForDecode(Form))
861       filter = new ModFilter(isRegFormat(Form));
862     else
863       filter = new DumbFilter();
864     opcodeToSet = Opcode;
865     break;
866   case X86Local::D8:
867   case X86Local::D9:
868   case X86Local::DA:
869   case X86Local::DB:
870   case X86Local::DC:
871   case X86Local::DD:
872   case X86Local::DE:
873   case X86Local::DF:
874     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
875     opcodeType = ONEBYTE;
876     if (Form == X86Local::AddRegFrm) {
877       Spec->modifierType = MODIFIER_MODRM;
878       Spec->modifierBase = Opcode;
879       filter = new AddRegEscapeFilter(Opcode);
880     } else {
881       filter = new EscapeFilter(true, Opcode);
882     }
883     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
884     break;
885   case X86Local::REP:
886   default:
887     opcodeType = ONEBYTE;
888     switch (Opcode) {
889 #define EXTENSION_TABLE(n) case 0x##n:
890     ONE_BYTE_EXTENSION_TABLES
891 #undef EXTENSION_TABLE
892       switch (Form) {
893       default:
894         llvm_unreachable("Fell through the cracks of a single-byte "
895                          "extended opcode");
896       case X86Local::MRM0r:
897       case X86Local::MRM1r:
898       case X86Local::MRM2r:
899       case X86Local::MRM3r:
900       case X86Local::MRM4r:
901       case X86Local::MRM5r:
902       case X86Local::MRM6r:
903       case X86Local::MRM7r:
904         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
905         break;
906       case X86Local::MRM0m:
907       case X86Local::MRM1m:
908       case X86Local::MRM2m:
909       case X86Local::MRM3m:
910       case X86Local::MRM4m:
911       case X86Local::MRM5m:
912       case X86Local::MRM6m:
913       case X86Local::MRM7m:
914         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
915         break;
916       MRM_MAPPING
917       } // switch (Form)
918       break;
919     case 0xd8:
920     case 0xd9:
921     case 0xda:
922     case 0xdb:
923     case 0xdc:
924     case 0xdd:
925     case 0xde:
926     case 0xdf:
927       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
928       break;
929     default:
930       if (needsModRMForDecode(Form))
931         filter = new ModFilter(isRegFormat(Form));
932       else
933         filter = new DumbFilter();
934       break;
935     } // switch (Opcode)
936     opcodeToSet = Opcode;
937   } // switch (Prefix)
938 
939   assert(opcodeType != (OpcodeType)-1 &&
940          "Opcode type not set");
941   assert(filter && "Filter not set");
942 
943   if (Form == X86Local::AddRegFrm) {
944     if(Spec->modifierType != MODIFIER_MODRM) {
945       assert(opcodeToSet < 0xf9 &&
946              "Not enough room for all ADDREG_FRM operands");
947 
948       uint8_t currentOpcode;
949 
950       for (currentOpcode = opcodeToSet;
951            currentOpcode < opcodeToSet + 8;
952            ++currentOpcode)
953         tables.setTableFields(opcodeType,
954                               insnContext(),
955                               currentOpcode,
956                               *filter,
957                               UID);
958 
959       Spec->modifierType = MODIFIER_OPCODE;
960       Spec->modifierBase = opcodeToSet;
961     } else {
962       // modifierBase was set where MODIFIER_MODRM was set
963       tables.setTableFields(opcodeType,
964                             insnContext(),
965                             opcodeToSet,
966                             *filter,
967                             UID);
968     }
969   } else {
970     tables.setTableFields(opcodeType,
971                           insnContext(),
972                           opcodeToSet,
973                           *filter,
974                           UID);
975 
976     Spec->modifierType = MODIFIER_NONE;
977     Spec->modifierBase = opcodeToSet;
978   }
979 
980   delete filter;
981 
982 #undef MAP
983 }
984 
985 #define TYPE(str, type) if (s == str) return type;
986 OperandType RecognizableInstr::typeFromString(const std::string &s,
987                                               bool isSSE,
988                                               bool hasREX_WPrefix,
989                                               bool hasOpSizePrefix) {
990   if (isSSE) {
991     // For SSE instructions, we ignore the OpSize prefix and force operand
992     // sizes.
993     TYPE("GR16",              TYPE_R16)
994     TYPE("GR32",              TYPE_R32)
995     TYPE("GR64",              TYPE_R64)
996   }
997   if(hasREX_WPrefix) {
998     // For instructions with a REX_W prefix, a declared 32-bit register encoding
999     // is special.
1000     TYPE("GR32",              TYPE_R32)
1001   }
1002   if(!hasOpSizePrefix) {
1003     // For instructions without an OpSize prefix, a declared 16-bit register or
1004     // immediate encoding is special.
1005     TYPE("GR16",              TYPE_R16)
1006     TYPE("i16imm",            TYPE_IMM16)
1007   }
1008   TYPE("i16mem",              TYPE_Mv)
1009   TYPE("i16imm",              TYPE_IMMv)
1010   TYPE("i16i8imm",            TYPE_IMMv)
1011   TYPE("GR16",                TYPE_Rv)
1012   TYPE("i32mem",              TYPE_Mv)
1013   TYPE("i32imm",              TYPE_IMMv)
1014   TYPE("i32i8imm",            TYPE_IMM32)
1015   TYPE("u32u8imm",            TYPE_IMM32)
1016   TYPE("GR32",                TYPE_Rv)
1017   TYPE("i64mem",              TYPE_Mv)
1018   TYPE("i64i32imm",           TYPE_IMM64)
1019   TYPE("i64i8imm",            TYPE_IMM64)
1020   TYPE("GR64",                TYPE_R64)
1021   TYPE("i8mem",               TYPE_M8)
1022   TYPE("i8imm",               TYPE_IMM8)
1023   TYPE("GR8",                 TYPE_R8)
1024   TYPE("VR128",               TYPE_XMM128)
1025   TYPE("f128mem",             TYPE_M128)
1026   TYPE("f256mem",             TYPE_M256)
1027   TYPE("FR64",                TYPE_XMM64)
1028   TYPE("f64mem",              TYPE_M64FP)
1029   TYPE("sdmem",               TYPE_M64FP)
1030   TYPE("FR32",                TYPE_XMM32)
1031   TYPE("f32mem",              TYPE_M32FP)
1032   TYPE("ssmem",               TYPE_M32FP)
1033   TYPE("RST",                 TYPE_ST)
1034   TYPE("i128mem",             TYPE_M128)
1035   TYPE("i256mem",             TYPE_M256)
1036   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1037   TYPE("i16imm_pcrel",        TYPE_REL16)
1038   TYPE("i32imm_pcrel",        TYPE_REL32)
1039   TYPE("SSECC",               TYPE_IMM3)
1040   TYPE("brtarget",            TYPE_RELv)
1041   TYPE("uncondbrtarget",      TYPE_RELv)
1042   TYPE("brtarget8",           TYPE_REL8)
1043   TYPE("f80mem",              TYPE_M80FP)
1044   TYPE("lea32mem",            TYPE_LEA)
1045   TYPE("lea64_32mem",         TYPE_LEA)
1046   TYPE("lea64mem",            TYPE_LEA)
1047   TYPE("VR64",                TYPE_MM64)
1048   TYPE("i64imm",              TYPE_IMMv)
1049   TYPE("opaque32mem",         TYPE_M1616)
1050   TYPE("opaque48mem",         TYPE_M1632)
1051   TYPE("opaque80mem",         TYPE_M1664)
1052   TYPE("opaque512mem",        TYPE_M512)
1053   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1054   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1055   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1056   TYPE("offset8",             TYPE_MOFFS8)
1057   TYPE("offset16",            TYPE_MOFFS16)
1058   TYPE("offset32",            TYPE_MOFFS32)
1059   TYPE("offset64",            TYPE_MOFFS64)
1060   TYPE("VR256",               TYPE_XMM256)
1061   errs() << "Unhandled type string " << s << "\n";
1062   llvm_unreachable("Unhandled type string");
1063 }
1064 #undef TYPE
1065 
1066 #define ENCODING(str, encoding) if (s == str) return encoding;
1067 OperandEncoding RecognizableInstr::immediateEncodingFromString
1068   (const std::string &s,
1069    bool hasOpSizePrefix) {
1070   if(!hasOpSizePrefix) {
1071     // For instructions without an OpSize prefix, a declared 16-bit register or
1072     // immediate encoding is special.
1073     ENCODING("i16imm",        ENCODING_IW)
1074   }
1075   ENCODING("i32i8imm",        ENCODING_IB)
1076   ENCODING("u32u8imm",        ENCODING_IB)
1077   ENCODING("SSECC",           ENCODING_IB)
1078   ENCODING("i16imm",          ENCODING_Iv)
1079   ENCODING("i16i8imm",        ENCODING_IB)
1080   ENCODING("i32imm",          ENCODING_Iv)
1081   ENCODING("i64i32imm",       ENCODING_ID)
1082   ENCODING("i64i8imm",        ENCODING_IB)
1083   ENCODING("i8imm",           ENCODING_IB)
1084   // This is not a typo.  Instructions like BLENDVPD put
1085   // register IDs in 8-bit immediates nowadays.
1086   ENCODING("VR256",           ENCODING_IB)
1087   ENCODING("VR128",           ENCODING_IB)
1088   errs() << "Unhandled immediate encoding " << s << "\n";
1089   llvm_unreachable("Unhandled immediate encoding");
1090 }
1091 
1092 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1093   (const std::string &s,
1094    bool hasOpSizePrefix) {
1095   ENCODING("GR16",            ENCODING_RM)
1096   ENCODING("GR32",            ENCODING_RM)
1097   ENCODING("GR64",            ENCODING_RM)
1098   ENCODING("GR8",             ENCODING_RM)
1099   ENCODING("VR128",           ENCODING_RM)
1100   ENCODING("FR64",            ENCODING_RM)
1101   ENCODING("FR32",            ENCODING_RM)
1102   ENCODING("VR64",            ENCODING_RM)
1103   ENCODING("VR256",           ENCODING_RM)
1104   errs() << "Unhandled R/M register encoding " << s << "\n";
1105   llvm_unreachable("Unhandled R/M register encoding");
1106 }
1107 
1108 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1109   (const std::string &s,
1110    bool hasOpSizePrefix) {
1111   ENCODING("GR16",            ENCODING_REG)
1112   ENCODING("GR32",            ENCODING_REG)
1113   ENCODING("GR64",            ENCODING_REG)
1114   ENCODING("GR8",             ENCODING_REG)
1115   ENCODING("VR128",           ENCODING_REG)
1116   ENCODING("FR64",            ENCODING_REG)
1117   ENCODING("FR32",            ENCODING_REG)
1118   ENCODING("VR64",            ENCODING_REG)
1119   ENCODING("SEGMENT_REG",     ENCODING_REG)
1120   ENCODING("DEBUG_REG",       ENCODING_REG)
1121   ENCODING("CONTROL_REG",     ENCODING_REG)
1122   ENCODING("VR256",           ENCODING_REG)
1123   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1124   llvm_unreachable("Unhandled reg/opcode register encoding");
1125 }
1126 
1127 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1128   (const std::string &s,
1129    bool hasOpSizePrefix) {
1130   ENCODING("FR32",            ENCODING_VVVV)
1131   ENCODING("FR64",            ENCODING_VVVV)
1132   ENCODING("VR128",           ENCODING_VVVV)
1133   ENCODING("VR256",           ENCODING_VVVV)
1134   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1135   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1136 }
1137 
1138 OperandEncoding RecognizableInstr::memoryEncodingFromString
1139   (const std::string &s,
1140    bool hasOpSizePrefix) {
1141   ENCODING("i16mem",          ENCODING_RM)
1142   ENCODING("i32mem",          ENCODING_RM)
1143   ENCODING("i64mem",          ENCODING_RM)
1144   ENCODING("i8mem",           ENCODING_RM)
1145   ENCODING("ssmem",           ENCODING_RM)
1146   ENCODING("sdmem",           ENCODING_RM)
1147   ENCODING("f128mem",         ENCODING_RM)
1148   ENCODING("f256mem",         ENCODING_RM)
1149   ENCODING("f64mem",          ENCODING_RM)
1150   ENCODING("f32mem",          ENCODING_RM)
1151   ENCODING("i128mem",         ENCODING_RM)
1152   ENCODING("i256mem",         ENCODING_RM)
1153   ENCODING("f80mem",          ENCODING_RM)
1154   ENCODING("lea32mem",        ENCODING_RM)
1155   ENCODING("lea64_32mem",     ENCODING_RM)
1156   ENCODING("lea64mem",        ENCODING_RM)
1157   ENCODING("opaque32mem",     ENCODING_RM)
1158   ENCODING("opaque48mem",     ENCODING_RM)
1159   ENCODING("opaque80mem",     ENCODING_RM)
1160   ENCODING("opaque512mem",    ENCODING_RM)
1161   errs() << "Unhandled memory encoding " << s << "\n";
1162   llvm_unreachable("Unhandled memory encoding");
1163 }
1164 
1165 OperandEncoding RecognizableInstr::relocationEncodingFromString
1166   (const std::string &s,
1167    bool hasOpSizePrefix) {
1168   if(!hasOpSizePrefix) {
1169     // For instructions without an OpSize prefix, a declared 16-bit register or
1170     // immediate encoding is special.
1171     ENCODING("i16imm",        ENCODING_IW)
1172   }
1173   ENCODING("i16imm",          ENCODING_Iv)
1174   ENCODING("i16i8imm",        ENCODING_IB)
1175   ENCODING("i32imm",          ENCODING_Iv)
1176   ENCODING("i32i8imm",        ENCODING_IB)
1177   ENCODING("i64i32imm",       ENCODING_ID)
1178   ENCODING("i64i8imm",        ENCODING_IB)
1179   ENCODING("i8imm",           ENCODING_IB)
1180   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1181   ENCODING("i16imm_pcrel",    ENCODING_IW)
1182   ENCODING("i32imm_pcrel",    ENCODING_ID)
1183   ENCODING("brtarget",        ENCODING_Iv)
1184   ENCODING("brtarget8",       ENCODING_IB)
1185   ENCODING("i64imm",          ENCODING_IO)
1186   ENCODING("offset8",         ENCODING_Ia)
1187   ENCODING("offset16",        ENCODING_Ia)
1188   ENCODING("offset32",        ENCODING_Ia)
1189   ENCODING("offset64",        ENCODING_Ia)
1190   errs() << "Unhandled relocation encoding " << s << "\n";
1191   llvm_unreachable("Unhandled relocation encoding");
1192 }
1193 
1194 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1195   (const std::string &s,
1196    bool hasOpSizePrefix) {
1197   ENCODING("RST",             ENCODING_I)
1198   ENCODING("GR32",            ENCODING_Rv)
1199   ENCODING("GR64",            ENCODING_RO)
1200   ENCODING("GR16",            ENCODING_Rv)
1201   ENCODING("GR8",             ENCODING_RB)
1202   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1203   llvm_unreachable("Unhandled opcode modifier encoding");
1204 }
1205 #undef ENCODING
1206