1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, TF = 17
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 using namespace X86Disassembler;
123 
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
126 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 ///   0b11.
128 ///
129 /// @param form - The form of the instruction.
130 /// @return     - true if the form implies that a ModR/M byte is required, false
131 ///               otherwise.
132 static bool needsModRMForDecode(uint8_t form) {
133   if (form == X86Local::MRMDestReg    ||
134      form == X86Local::MRMDestMem    ||
135      form == X86Local::MRMSrcReg     ||
136      form == X86Local::MRMSrcMem     ||
137      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
139     return true;
140   else
141     return false;
142 }
143 
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 ///   the ModR/M byte to be 0b11.
146 ///
147 /// @param form - The form of the instruction.
148 /// @return     - true if the form implies that Mod must be 0b11, false
149 ///               otherwise.
150 static bool isRegFormat(uint8_t form) {
151   if (form == X86Local::MRMDestReg ||
152      form == X86Local::MRMSrcReg  ||
153      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
154     return true;
155   else
156     return false;
157 }
158 
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 ///   Useful for switch statements and the like.
161 ///
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return     - The field, with the first bit in the BitsInit as the lowest
164 ///               order bit.
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166   int width = init.getNumBits();
167 
168   assert(width <= 8 && "Field is too large for uint8_t!");
169 
170   int     index;
171   uint8_t mask = 0x01;
172 
173   uint8_t ret = 0;
174 
175   for (index = 0; index < width; index++) {
176     if (static_cast<BitInit*>(init.getBit(index))->getValue())
177       ret |= mask;
178 
179     mask <<= 1;
180   }
181 
182   return ret;
183 }
184 
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 ///   name of the field.
187 ///
188 /// @param rec  - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return     - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192   BitsInit* bits = rec->getValueAsBitsInit(name);
193   return byteFromBitsInit(*bits);
194 }
195 
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197                                      const CodeGenInstruction &insn,
198                                      InstrUID uid) {
199   UID = uid;
200 
201   Rec = insn.TheDef;
202   Name = Rec->getName();
203   Spec = &tables.specForUID(UID);
204 
205   if (!Rec->isSubClassOf("X86Inst")) {
206     ShouldBeEmitted = false;
207     return;
208   }
209 
210   Prefix   = byteFromRec(Rec, "Prefix");
211   Opcode   = byteFromRec(Rec, "Opcode");
212   Form     = byteFromRec(Rec, "FormBits");
213   SegOvr   = byteFromRec(Rec, "SegOvrBits");
214 
215   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
216   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
217   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
218   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
219   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
220   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
221   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
222 
223   Name      = Rec->getName();
224   AsmString = Rec->getValueAsString("AsmString");
225 
226   Operands = &insn.Operands.OperandList;
227 
228   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
229                      (Name.find("CRC32") != Name.npos);
230   HasFROperands    = hasFROperands();
231   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
232 
233   // Check for 64-bit inst which does not require REX
234   Is64Bit = false;
235   // FIXME: Is there some better way to check for In64BitMode?
236   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
237   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
238     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
239       Is64Bit = true;
240       break;
241     }
242   }
243   // FIXME: These instructions aren't marked as 64-bit in any way
244   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
245              Rec->getName() == "MASKMOVDQU64" ||
246              Rec->getName() == "POPFS64" ||
247              Rec->getName() == "POPGS64" ||
248              Rec->getName() == "PUSHFS64" ||
249              Rec->getName() == "PUSHGS64" ||
250              Rec->getName() == "REX64_PREFIX" ||
251              Rec->getName().find("VMREAD64") != Name.npos ||
252              Rec->getName().find("VMWRITE64") != Name.npos ||
253              Rec->getName().find("MOV64") != Name.npos ||
254              Rec->getName().find("PUSH64") != Name.npos ||
255              Rec->getName().find("POP64") != Name.npos;
256 
257   ShouldBeEmitted  = true;
258 }
259 
260 void RecognizableInstr::processInstr(DisassemblerTables &tables,
261 	const CodeGenInstruction &insn,
262                                    InstrUID uid)
263 {
264   // Ignore "asm parser only" instructions.
265   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
266     return;
267 
268   RecognizableInstr recogInstr(tables, insn, uid);
269 
270   recogInstr.emitInstructionSpecifier(tables);
271 
272   if (recogInstr.shouldBeEmitted())
273     recogInstr.emitDecodePath(tables);
274 }
275 
276 InstructionContext RecognizableInstr::insnContext() const {
277   InstructionContext insnContext;
278 
279   if (HasVEX_4VPrefix || HasVEXPrefix) {
280     if (HasOpSizePrefix && HasVEX_LPrefix)
281       insnContext = IC_VEX_L_OPSIZE;
282     else if (HasOpSizePrefix && HasVEX_WPrefix)
283       insnContext = IC_VEX_W_OPSIZE;
284     else if (HasOpSizePrefix)
285       insnContext = IC_VEX_OPSIZE;
286     else if (HasVEX_LPrefix && Prefix == X86Local::XS)
287       insnContext = IC_VEX_L_XS;
288     else if (HasVEX_LPrefix && Prefix == X86Local::XD)
289       insnContext = IC_VEX_L_XD;
290     else if (HasVEX_WPrefix && Prefix == X86Local::XS)
291       insnContext = IC_VEX_W_XS;
292     else if (HasVEX_WPrefix && Prefix == X86Local::XD)
293       insnContext = IC_VEX_W_XD;
294     else if (HasVEX_WPrefix)
295       insnContext = IC_VEX_W;
296     else if (HasVEX_LPrefix)
297       insnContext = IC_VEX_L;
298     else if (Prefix == X86Local::XD)
299       insnContext = IC_VEX_XD;
300     else if (Prefix == X86Local::XS)
301       insnContext = IC_VEX_XS;
302     else
303       insnContext = IC_VEX;
304   } else if (Is64Bit || HasREX_WPrefix) {
305     if (HasREX_WPrefix && HasOpSizePrefix)
306       insnContext = IC_64BIT_REXW_OPSIZE;
307     else if (HasOpSizePrefix)
308       insnContext = IC_64BIT_OPSIZE;
309     else if (HasREX_WPrefix && Prefix == X86Local::XS)
310       insnContext = IC_64BIT_REXW_XS;
311     else if (HasREX_WPrefix && Prefix == X86Local::XD)
312       insnContext = IC_64BIT_REXW_XD;
313     else if (Prefix == X86Local::XD)
314       insnContext = IC_64BIT_XD;
315     else if (Prefix == X86Local::XS)
316       insnContext = IC_64BIT_XS;
317     else if (HasREX_WPrefix)
318       insnContext = IC_64BIT_REXW;
319     else
320       insnContext = IC_64BIT;
321   } else {
322     if (HasOpSizePrefix && Prefix == X86Local::TF)
323       insnContext = IC_XD;
324     else if (HasOpSizePrefix)
325       insnContext = IC_OPSIZE;
326     else if (Prefix == X86Local::XD)
327       insnContext = IC_XD;
328     else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
329       insnContext = IC_XS;
330     else
331       insnContext = IC;
332   }
333 
334   return insnContext;
335 }
336 
337 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
338   ///////////////////
339   // FILTER_STRONG
340   //
341 
342   // Filter out intrinsics
343 
344   if (!Rec->isSubClassOf("X86Inst"))
345     return FILTER_STRONG;
346 
347   if (Form == X86Local::Pseudo ||
348       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
349     return FILTER_STRONG;
350 
351   if (Form == X86Local::MRMInitReg)
352     return FILTER_STRONG;
353 
354 
355   // Filter out artificial instructions
356 
357   if (Name.find("TAILJMP") != Name.npos    ||
358       Name.find("_Int") != Name.npos       ||
359       Name.find("_int") != Name.npos       ||
360       Name.find("Int_") != Name.npos       ||
361       Name.find("_NOREX") != Name.npos     ||
362       Name.find("_TC") != Name.npos        ||
363       Name.find("EH_RETURN") != Name.npos  ||
364       Name.find("V_SET") != Name.npos      ||
365       Name.find("LOCK_") != Name.npos      ||
366       Name.find("WIN") != Name.npos        ||
367       Name.find("_AVX") != Name.npos       ||
368       Name.find("2SDL") != Name.npos)
369     return FILTER_STRONG;
370 
371   // Filter out instructions with segment override prefixes.
372   // They're too messy to handle now and we'll special case them if needed.
373 
374   if (SegOvr)
375     return FILTER_STRONG;
376 
377   // Filter out instructions that can't be printed.
378 
379   if (AsmString.size() == 0)
380     return FILTER_STRONG;
381 
382   // Filter out instructions with subreg operands.
383 
384   if (AsmString.find("subreg") != AsmString.npos)
385     return FILTER_STRONG;
386 
387   /////////////////
388   // FILTER_WEAK
389   //
390 
391 
392   // Filter out instructions with a LOCK prefix;
393   //   prefer forms that do not have the prefix
394   if (HasLockPrefix)
395     return FILTER_WEAK;
396 
397   // Filter out alternate forms of AVX instructions
398   if (Name.find("_alt") != Name.npos ||
399       Name.find("XrYr") != Name.npos ||
400       Name.find("r64r") != Name.npos ||
401       Name.find("_64mr") != Name.npos ||
402       Name.find("Xrr") != Name.npos ||
403       Name.find("rr64") != Name.npos)
404     return FILTER_WEAK;
405 
406   if (Name == "VMASKMOVDQU64"  ||
407       Name == "VEXTRACTPSrr64" ||
408       Name == "VMOVQd64rr"     ||
409       Name == "VMOVQs64rr")
410     return FILTER_WEAK;
411 
412   // Special cases.
413 
414   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
415     return FILTER_WEAK;
416   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
417     return FILTER_WEAK;
418 
419   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
420     return FILTER_WEAK;
421   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
422     return FILTER_WEAK;
423   if (Name.find("Fs") != Name.npos)
424     return FILTER_WEAK;
425   if (Name == "MOVLPDrr"          ||
426       Name == "MOVLPSrr"          ||
427       Name == "PUSHFQ"            ||
428       Name == "BSF16rr"           ||
429       Name == "BSF16rm"           ||
430       Name == "BSR16rr"           ||
431       Name == "BSR16rm"           ||
432       Name == "MOVSX16rm8"        ||
433       Name == "MOVSX16rr8"        ||
434       Name == "MOVZX16rm8"        ||
435       Name == "MOVZX16rr8"        ||
436       Name == "PUSH32i16"         ||
437       Name == "PUSH64i16"         ||
438       Name == "MOVPQI2QImr"       ||
439       Name == "VMOVPQI2QImr"      ||
440       Name == "MOVSDmr"           ||
441       Name == "MOVSDrm"           ||
442       Name == "MOVSSmr"           ||
443       Name == "MOVSSrm"           ||
444       Name == "MMX_MOVD64rrv164"  ||
445       Name == "CRC32m16"          ||
446       Name == "MOV64ri64i32"      ||
447       Name == "CRC32r16")
448     return FILTER_WEAK;
449 
450   if (HasFROperands && Name.find("MOV") != Name.npos &&
451      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
452       (Name.find("to") != Name.npos)))
453     return FILTER_WEAK;
454 
455   return FILTER_NORMAL;
456 }
457 
458 bool RecognizableInstr::hasFROperands() const {
459   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
460   unsigned numOperands = OperandList.size();
461 
462   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
463     const std::string &recName = OperandList[operandIndex].Rec->getName();
464 
465     if (recName.find("FR") != recName.npos)
466       return true;
467   }
468   return false;
469 }
470 
471 bool RecognizableInstr::has256BitOperands() const {
472   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
473   unsigned numOperands = OperandList.size();
474 
475   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
476     const std::string &recName = OperandList[operandIndex].Rec->getName();
477 
478     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
479       return true;
480     }
481   }
482   return false;
483 }
484 
485 void RecognizableInstr::handleOperand(
486   bool optional,
487   unsigned &operandIndex,
488   unsigned &physicalOperandIndex,
489   unsigned &numPhysicalOperands,
490   unsigned *operandMapping,
491   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
492   if (optional) {
493     if (physicalOperandIndex >= numPhysicalOperands)
494       return;
495   } else {
496     assert(physicalOperandIndex < numPhysicalOperands);
497   }
498 
499   while (operandMapping[operandIndex] != operandIndex) {
500     Spec->operands[operandIndex].encoding = ENCODING_DUP;
501     Spec->operands[operandIndex].type =
502       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
503     ++operandIndex;
504   }
505 
506   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
507 
508   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
509                                                               HasOpSizePrefix);
510   Spec->operands[operandIndex].type = typeFromString(typeName,
511                                                      IsSSE,
512                                                      HasREX_WPrefix,
513                                                      HasOpSizePrefix);
514 
515   ++operandIndex;
516   ++physicalOperandIndex;
517 }
518 
519 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
520   Spec->name       = Name;
521 
522   if (!Rec->isSubClassOf("X86Inst"))
523     return;
524 
525   switch (filter()) {
526   case FILTER_WEAK:
527     Spec->filtered = true;
528     break;
529   case FILTER_STRONG:
530     ShouldBeEmitted = false;
531     return;
532   case FILTER_NORMAL:
533     break;
534   }
535 
536   Spec->insnContext = insnContext();
537 
538   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
539 
540   unsigned operandIndex;
541   unsigned numOperands = OperandList.size();
542   unsigned numPhysicalOperands = 0;
543 
544   // operandMapping maps from operands in OperandList to their originals.
545   // If operandMapping[i] != i, then the entry is a duplicate.
546   unsigned operandMapping[X86_MAX_OPERANDS];
547 
548   bool hasFROperands = false;
549 
550   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
551 
552   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
553     if (OperandList[operandIndex].Constraints.size()) {
554       const CGIOperandList::ConstraintInfo &Constraint =
555         OperandList[operandIndex].Constraints[0];
556       if (Constraint.isTied()) {
557         operandMapping[operandIndex] = Constraint.getTiedOperand();
558       } else {
559         ++numPhysicalOperands;
560         operandMapping[operandIndex] = operandIndex;
561       }
562     } else {
563       ++numPhysicalOperands;
564       operandMapping[operandIndex] = operandIndex;
565     }
566 
567     const std::string &recName = OperandList[operandIndex].Rec->getName();
568 
569     if (recName.find("FR") != recName.npos)
570       hasFROperands = true;
571   }
572 
573   if (hasFROperands && Name.find("MOV") != Name.npos &&
574      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
575       (Name.find("to") != Name.npos)))
576     ShouldBeEmitted = false;
577 
578   if (!ShouldBeEmitted)
579     return;
580 
581 #define HANDLE_OPERAND(class)               \
582   handleOperand(false,                      \
583                 operandIndex,               \
584                 physicalOperandIndex,       \
585                 numPhysicalOperands,        \
586                 operandMapping,             \
587                 class##EncodingFromString);
588 
589 #define HANDLE_OPTIONAL(class)              \
590   handleOperand(true,                       \
591                 operandIndex,               \
592                 physicalOperandIndex,       \
593                 numPhysicalOperands,        \
594                 operandMapping,             \
595                 class##EncodingFromString);
596 
597   // operandIndex should always be < numOperands
598   operandIndex = 0;
599   // physicalOperandIndex should always be < numPhysicalOperands
600   unsigned physicalOperandIndex = 0;
601 
602   switch (Form) {
603   case X86Local::RawFrm:
604     // Operand 1 (optional) is an address or immediate.
605     // Operand 2 (optional) is an immediate.
606     assert(numPhysicalOperands <= 2 &&
607            "Unexpected number of operands for RawFrm");
608     HANDLE_OPTIONAL(relocation)
609     HANDLE_OPTIONAL(immediate)
610     break;
611   case X86Local::AddRegFrm:
612     // Operand 1 is added to the opcode.
613     // Operand 2 (optional) is an address.
614     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
615            "Unexpected number of operands for AddRegFrm");
616     HANDLE_OPERAND(opcodeModifier)
617     HANDLE_OPTIONAL(relocation)
618     break;
619   case X86Local::MRMDestReg:
620     // Operand 1 is a register operand in the R/M field.
621     // Operand 2 is a register operand in the Reg/Opcode field.
622     // - In AVX, there is a register operand in the VEX.vvvv field here -
623     // Operand 3 (optional) is an immediate.
624     if (HasVEX_4VPrefix)
625       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
626              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
627     else
628       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
629              "Unexpected number of operands for MRMDestRegFrm");
630 
631     HANDLE_OPERAND(rmRegister)
632 
633     if (HasVEX_4VPrefix)
634       // FIXME: In AVX, the register below becomes the one encoded
635       // in ModRMVEX and the one above the one in the VEX.VVVV field
636       HANDLE_OPERAND(vvvvRegister)
637 
638     HANDLE_OPERAND(roRegister)
639     HANDLE_OPTIONAL(immediate)
640     break;
641   case X86Local::MRMDestMem:
642     // Operand 1 is a memory operand (possibly SIB-extended)
643     // Operand 2 is a register operand in the Reg/Opcode field.
644     // - In AVX, there is a register operand in the VEX.vvvv field here -
645     // Operand 3 (optional) is an immediate.
646     if (HasVEX_4VPrefix)
647       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
648              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
649     else
650       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
651              "Unexpected number of operands for MRMDestMemFrm");
652     HANDLE_OPERAND(memory)
653 
654     if (HasVEX_4VPrefix)
655       // FIXME: In AVX, the register below becomes the one encoded
656       // in ModRMVEX and the one above the one in the VEX.VVVV field
657       HANDLE_OPERAND(vvvvRegister)
658 
659     HANDLE_OPERAND(roRegister)
660     HANDLE_OPTIONAL(immediate)
661     break;
662   case X86Local::MRMSrcReg:
663     // Operand 1 is a register operand in the Reg/Opcode field.
664     // Operand 2 is a register operand in the R/M field.
665     // - In AVX, there is a register operand in the VEX.vvvv field here -
666     // Operand 3 (optional) is an immediate.
667 
668     if (HasVEX_4VPrefix)
669       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
670              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
671     else
672       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
673              "Unexpected number of operands for MRMSrcRegFrm");
674 
675     HANDLE_OPERAND(roRegister)
676 
677     if (HasVEX_4VPrefix)
678       // FIXME: In AVX, the register below becomes the one encoded
679       // in ModRMVEX and the one above the one in the VEX.VVVV field
680       HANDLE_OPERAND(vvvvRegister)
681 
682     HANDLE_OPERAND(rmRegister)
683     HANDLE_OPTIONAL(immediate)
684     break;
685   case X86Local::MRMSrcMem:
686     // Operand 1 is a register operand in the Reg/Opcode field.
687     // Operand 2 is a memory operand (possibly SIB-extended)
688     // - In AVX, there is a register operand in the VEX.vvvv field here -
689     // Operand 3 (optional) is an immediate.
690 
691     if (HasVEX_4VPrefix)
692       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
693              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
694     else
695       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
696              "Unexpected number of operands for MRMSrcMemFrm");
697 
698     HANDLE_OPERAND(roRegister)
699 
700     if (HasVEX_4VPrefix)
701       // FIXME: In AVX, the register below becomes the one encoded
702       // in ModRMVEX and the one above the one in the VEX.VVVV field
703       HANDLE_OPERAND(vvvvRegister)
704 
705     HANDLE_OPERAND(memory)
706     HANDLE_OPTIONAL(immediate)
707     break;
708   case X86Local::MRM0r:
709   case X86Local::MRM1r:
710   case X86Local::MRM2r:
711   case X86Local::MRM3r:
712   case X86Local::MRM4r:
713   case X86Local::MRM5r:
714   case X86Local::MRM6r:
715   case X86Local::MRM7r:
716     // Operand 1 is a register operand in the R/M field.
717     // Operand 2 (optional) is an immediate or relocation.
718     if (HasVEX_4VPrefix)
719       assert(numPhysicalOperands <= 3 &&
720              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
721     else
722       assert(numPhysicalOperands <= 2 &&
723              "Unexpected number of operands for MRMnRFrm");
724     if (HasVEX_4VPrefix)
725       HANDLE_OPERAND(vvvvRegister);
726     HANDLE_OPTIONAL(rmRegister)
727     HANDLE_OPTIONAL(relocation)
728     break;
729   case X86Local::MRM0m:
730   case X86Local::MRM1m:
731   case X86Local::MRM2m:
732   case X86Local::MRM3m:
733   case X86Local::MRM4m:
734   case X86Local::MRM5m:
735   case X86Local::MRM6m:
736   case X86Local::MRM7m:
737     // Operand 1 is a memory operand (possibly SIB-extended)
738     // Operand 2 (optional) is an immediate or relocation.
739     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
740            "Unexpected number of operands for MRMnMFrm");
741     HANDLE_OPERAND(memory)
742     HANDLE_OPTIONAL(relocation)
743     break;
744   case X86Local::RawFrmImm8:
745     // operand 1 is a 16-bit immediate
746     // operand 2 is an 8-bit immediate
747     assert(numPhysicalOperands == 2 &&
748            "Unexpected number of operands for X86Local::RawFrmImm8");
749     HANDLE_OPERAND(immediate)
750     HANDLE_OPERAND(immediate)
751     break;
752   case X86Local::RawFrmImm16:
753     // operand 1 is a 16-bit immediate
754     // operand 2 is a 16-bit immediate
755     HANDLE_OPERAND(immediate)
756     HANDLE_OPERAND(immediate)
757     break;
758   case X86Local::MRMInitReg:
759     // Ignored.
760     break;
761   }
762 
763   #undef HANDLE_OPERAND
764   #undef HANDLE_OPTIONAL
765 }
766 
767 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
768   // Special cases where the LLVM tables are not complete
769 
770 #define MAP(from, to)                     \
771   case X86Local::MRM_##from:              \
772     filter = new ExactFilter(0x##from);   \
773     break;
774 
775   OpcodeType    opcodeType  = (OpcodeType)-1;
776 
777   ModRMFilter*  filter      = NULL;
778   uint8_t       opcodeToSet = 0;
779 
780   switch (Prefix) {
781   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
782   case X86Local::XD:
783   case X86Local::XS:
784   case X86Local::TB:
785     opcodeType = TWOBYTE;
786 
787     switch (Opcode) {
788     default:
789       if (needsModRMForDecode(Form))
790         filter = new ModFilter(isRegFormat(Form));
791       else
792         filter = new DumbFilter();
793       break;
794 #define EXTENSION_TABLE(n) case 0x##n:
795     TWO_BYTE_EXTENSION_TABLES
796 #undef EXTENSION_TABLE
797       switch (Form) {
798       default:
799         llvm_unreachable("Unhandled two-byte extended opcode");
800       case X86Local::MRM0r:
801       case X86Local::MRM1r:
802       case X86Local::MRM2r:
803       case X86Local::MRM3r:
804       case X86Local::MRM4r:
805       case X86Local::MRM5r:
806       case X86Local::MRM6r:
807       case X86Local::MRM7r:
808         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
809         break;
810       case X86Local::MRM0m:
811       case X86Local::MRM1m:
812       case X86Local::MRM2m:
813       case X86Local::MRM3m:
814       case X86Local::MRM4m:
815       case X86Local::MRM5m:
816       case X86Local::MRM6m:
817       case X86Local::MRM7m:
818         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
819         break;
820       MRM_MAPPING
821       } // switch (Form)
822       break;
823     } // switch (Opcode)
824     opcodeToSet = Opcode;
825     break;
826   case X86Local::T8:
827   case X86Local::TF:
828     opcodeType = THREEBYTE_38;
829     if (needsModRMForDecode(Form))
830       filter = new ModFilter(isRegFormat(Form));
831     else
832       filter = new DumbFilter();
833     opcodeToSet = Opcode;
834     break;
835   case X86Local::P_TA:
836     opcodeType = THREEBYTE_3A;
837     if (needsModRMForDecode(Form))
838       filter = new ModFilter(isRegFormat(Form));
839     else
840       filter = new DumbFilter();
841     opcodeToSet = Opcode;
842     break;
843   case X86Local::A6:
844     opcodeType = THREEBYTE_A6;
845     if (needsModRMForDecode(Form))
846       filter = new ModFilter(isRegFormat(Form));
847     else
848       filter = new DumbFilter();
849     opcodeToSet = Opcode;
850     break;
851   case X86Local::A7:
852     opcodeType = THREEBYTE_A7;
853     if (needsModRMForDecode(Form))
854       filter = new ModFilter(isRegFormat(Form));
855     else
856       filter = new DumbFilter();
857     opcodeToSet = Opcode;
858     break;
859   case X86Local::D8:
860   case X86Local::D9:
861   case X86Local::DA:
862   case X86Local::DB:
863   case X86Local::DC:
864   case X86Local::DD:
865   case X86Local::DE:
866   case X86Local::DF:
867     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
868     opcodeType = ONEBYTE;
869     if (Form == X86Local::AddRegFrm) {
870       Spec->modifierType = MODIFIER_MODRM;
871       Spec->modifierBase = Opcode;
872       filter = new AddRegEscapeFilter(Opcode);
873     } else {
874       filter = new EscapeFilter(true, Opcode);
875     }
876     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
877     break;
878   case X86Local::REP:
879   default:
880     opcodeType = ONEBYTE;
881     switch (Opcode) {
882 #define EXTENSION_TABLE(n) case 0x##n:
883     ONE_BYTE_EXTENSION_TABLES
884 #undef EXTENSION_TABLE
885       switch (Form) {
886       default:
887         llvm_unreachable("Fell through the cracks of a single-byte "
888                          "extended opcode");
889       case X86Local::MRM0r:
890       case X86Local::MRM1r:
891       case X86Local::MRM2r:
892       case X86Local::MRM3r:
893       case X86Local::MRM4r:
894       case X86Local::MRM5r:
895       case X86Local::MRM6r:
896       case X86Local::MRM7r:
897         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
898         break;
899       case X86Local::MRM0m:
900       case X86Local::MRM1m:
901       case X86Local::MRM2m:
902       case X86Local::MRM3m:
903       case X86Local::MRM4m:
904       case X86Local::MRM5m:
905       case X86Local::MRM6m:
906       case X86Local::MRM7m:
907         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
908         break;
909       MRM_MAPPING
910       } // switch (Form)
911       break;
912     case 0xd8:
913     case 0xd9:
914     case 0xda:
915     case 0xdb:
916     case 0xdc:
917     case 0xdd:
918     case 0xde:
919     case 0xdf:
920       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
921       break;
922     default:
923       if (needsModRMForDecode(Form))
924         filter = new ModFilter(isRegFormat(Form));
925       else
926         filter = new DumbFilter();
927       break;
928     } // switch (Opcode)
929     opcodeToSet = Opcode;
930   } // switch (Prefix)
931 
932   assert(opcodeType != (OpcodeType)-1 &&
933          "Opcode type not set");
934   assert(filter && "Filter not set");
935 
936   if (Form == X86Local::AddRegFrm) {
937     if(Spec->modifierType != MODIFIER_MODRM) {
938       assert(opcodeToSet < 0xf9 &&
939              "Not enough room for all ADDREG_FRM operands");
940 
941       uint8_t currentOpcode;
942 
943       for (currentOpcode = opcodeToSet;
944            currentOpcode < opcodeToSet + 8;
945            ++currentOpcode)
946         tables.setTableFields(opcodeType,
947                               insnContext(),
948                               currentOpcode,
949                               *filter,
950                               UID);
951 
952       Spec->modifierType = MODIFIER_OPCODE;
953       Spec->modifierBase = opcodeToSet;
954     } else {
955       // modifierBase was set where MODIFIER_MODRM was set
956       tables.setTableFields(opcodeType,
957                             insnContext(),
958                             opcodeToSet,
959                             *filter,
960                             UID);
961     }
962   } else {
963     tables.setTableFields(opcodeType,
964                           insnContext(),
965                           opcodeToSet,
966                           *filter,
967                           UID);
968 
969     Spec->modifierType = MODIFIER_NONE;
970     Spec->modifierBase = opcodeToSet;
971   }
972 
973   delete filter;
974 
975 #undef MAP
976 }
977 
978 #define TYPE(str, type) if (s == str) return type;
979 OperandType RecognizableInstr::typeFromString(const std::string &s,
980                                               bool isSSE,
981                                               bool hasREX_WPrefix,
982                                               bool hasOpSizePrefix) {
983   if (isSSE) {
984     // For SSE instructions, we ignore the OpSize prefix and force operand
985     // sizes.
986     TYPE("GR16",              TYPE_R16)
987     TYPE("GR32",              TYPE_R32)
988     TYPE("GR64",              TYPE_R64)
989   }
990   if(hasREX_WPrefix) {
991     // For instructions with a REX_W prefix, a declared 32-bit register encoding
992     // is special.
993     TYPE("GR32",              TYPE_R32)
994   }
995   if(!hasOpSizePrefix) {
996     // For instructions without an OpSize prefix, a declared 16-bit register or
997     // immediate encoding is special.
998     TYPE("GR16",              TYPE_R16)
999     TYPE("i16imm",            TYPE_IMM16)
1000   }
1001   TYPE("i16mem",              TYPE_Mv)
1002   TYPE("i16imm",              TYPE_IMMv)
1003   TYPE("i16i8imm",            TYPE_IMMv)
1004   TYPE("GR16",                TYPE_Rv)
1005   TYPE("i32mem",              TYPE_Mv)
1006   TYPE("i32imm",              TYPE_IMMv)
1007   TYPE("i32i8imm",            TYPE_IMM32)
1008   TYPE("u32u8imm",            TYPE_IMM32)
1009   TYPE("GR32",                TYPE_Rv)
1010   TYPE("i64mem",              TYPE_Mv)
1011   TYPE("i64i32imm",           TYPE_IMM64)
1012   TYPE("i64i8imm",            TYPE_IMM64)
1013   TYPE("GR64",                TYPE_R64)
1014   TYPE("i8mem",               TYPE_M8)
1015   TYPE("i8imm",               TYPE_IMM8)
1016   TYPE("GR8",                 TYPE_R8)
1017   TYPE("VR128",               TYPE_XMM128)
1018   TYPE("f128mem",             TYPE_M128)
1019   TYPE("f256mem",             TYPE_M256)
1020   TYPE("FR64",                TYPE_XMM64)
1021   TYPE("f64mem",              TYPE_M64FP)
1022   TYPE("sdmem",               TYPE_M64FP)
1023   TYPE("FR32",                TYPE_XMM32)
1024   TYPE("f32mem",              TYPE_M32FP)
1025   TYPE("ssmem",               TYPE_M32FP)
1026   TYPE("RST",                 TYPE_ST)
1027   TYPE("i128mem",             TYPE_M128)
1028   TYPE("i256mem",             TYPE_M256)
1029   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1030   TYPE("i16imm_pcrel",        TYPE_REL16)
1031   TYPE("i32imm_pcrel",        TYPE_REL32)
1032   TYPE("SSECC",               TYPE_IMM3)
1033   TYPE("brtarget",            TYPE_RELv)
1034   TYPE("uncondbrtarget",      TYPE_RELv)
1035   TYPE("brtarget8",           TYPE_REL8)
1036   TYPE("f80mem",              TYPE_M80FP)
1037   TYPE("lea32mem",            TYPE_LEA)
1038   TYPE("lea64_32mem",         TYPE_LEA)
1039   TYPE("lea64mem",            TYPE_LEA)
1040   TYPE("VR64",                TYPE_MM64)
1041   TYPE("i64imm",              TYPE_IMMv)
1042   TYPE("opaque32mem",         TYPE_M1616)
1043   TYPE("opaque48mem",         TYPE_M1632)
1044   TYPE("opaque80mem",         TYPE_M1664)
1045   TYPE("opaque512mem",        TYPE_M512)
1046   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1047   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1048   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1049   TYPE("offset8",             TYPE_MOFFS8)
1050   TYPE("offset16",            TYPE_MOFFS16)
1051   TYPE("offset32",            TYPE_MOFFS32)
1052   TYPE("offset64",            TYPE_MOFFS64)
1053   TYPE("VR256",               TYPE_XMM256)
1054   errs() << "Unhandled type string " << s << "\n";
1055   llvm_unreachable("Unhandled type string");
1056 }
1057 #undef TYPE
1058 
1059 #define ENCODING(str, encoding) if (s == str) return encoding;
1060 OperandEncoding RecognizableInstr::immediateEncodingFromString
1061   (const std::string &s,
1062    bool hasOpSizePrefix) {
1063   if(!hasOpSizePrefix) {
1064     // For instructions without an OpSize prefix, a declared 16-bit register or
1065     // immediate encoding is special.
1066     ENCODING("i16imm",        ENCODING_IW)
1067   }
1068   ENCODING("i32i8imm",        ENCODING_IB)
1069   ENCODING("u32u8imm",        ENCODING_IB)
1070   ENCODING("SSECC",           ENCODING_IB)
1071   ENCODING("i16imm",          ENCODING_Iv)
1072   ENCODING("i16i8imm",        ENCODING_IB)
1073   ENCODING("i32imm",          ENCODING_Iv)
1074   ENCODING("i64i32imm",       ENCODING_ID)
1075   ENCODING("i64i8imm",        ENCODING_IB)
1076   ENCODING("i8imm",           ENCODING_IB)
1077   // This is not a typo.  Instructions like BLENDVPD put
1078   // register IDs in 8-bit immediates nowadays.
1079   ENCODING("VR256",           ENCODING_IB)
1080   ENCODING("VR128",           ENCODING_IB)
1081   errs() << "Unhandled immediate encoding " << s << "\n";
1082   llvm_unreachable("Unhandled immediate encoding");
1083 }
1084 
1085 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1086   (const std::string &s,
1087    bool hasOpSizePrefix) {
1088   ENCODING("GR16",            ENCODING_RM)
1089   ENCODING("GR32",            ENCODING_RM)
1090   ENCODING("GR64",            ENCODING_RM)
1091   ENCODING("GR8",             ENCODING_RM)
1092   ENCODING("VR128",           ENCODING_RM)
1093   ENCODING("FR64",            ENCODING_RM)
1094   ENCODING("FR32",            ENCODING_RM)
1095   ENCODING("VR64",            ENCODING_RM)
1096   ENCODING("VR256",           ENCODING_RM)
1097   errs() << "Unhandled R/M register encoding " << s << "\n";
1098   llvm_unreachable("Unhandled R/M register encoding");
1099 }
1100 
1101 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1102   (const std::string &s,
1103    bool hasOpSizePrefix) {
1104   ENCODING("GR16",            ENCODING_REG)
1105   ENCODING("GR32",            ENCODING_REG)
1106   ENCODING("GR64",            ENCODING_REG)
1107   ENCODING("GR8",             ENCODING_REG)
1108   ENCODING("VR128",           ENCODING_REG)
1109   ENCODING("FR64",            ENCODING_REG)
1110   ENCODING("FR32",            ENCODING_REG)
1111   ENCODING("VR64",            ENCODING_REG)
1112   ENCODING("SEGMENT_REG",     ENCODING_REG)
1113   ENCODING("DEBUG_REG",       ENCODING_REG)
1114   ENCODING("CONTROL_REG",     ENCODING_REG)
1115   ENCODING("VR256",           ENCODING_REG)
1116   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1117   llvm_unreachable("Unhandled reg/opcode register encoding");
1118 }
1119 
1120 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1121   (const std::string &s,
1122    bool hasOpSizePrefix) {
1123   ENCODING("FR32",            ENCODING_VVVV)
1124   ENCODING("FR64",            ENCODING_VVVV)
1125   ENCODING("VR128",           ENCODING_VVVV)
1126   ENCODING("VR256",           ENCODING_VVVV)
1127   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1128   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1129 }
1130 
1131 OperandEncoding RecognizableInstr::memoryEncodingFromString
1132   (const std::string &s,
1133    bool hasOpSizePrefix) {
1134   ENCODING("i16mem",          ENCODING_RM)
1135   ENCODING("i32mem",          ENCODING_RM)
1136   ENCODING("i64mem",          ENCODING_RM)
1137   ENCODING("i8mem",           ENCODING_RM)
1138   ENCODING("ssmem",           ENCODING_RM)
1139   ENCODING("sdmem",           ENCODING_RM)
1140   ENCODING("f128mem",         ENCODING_RM)
1141   ENCODING("f256mem",         ENCODING_RM)
1142   ENCODING("f64mem",          ENCODING_RM)
1143   ENCODING("f32mem",          ENCODING_RM)
1144   ENCODING("i128mem",         ENCODING_RM)
1145   ENCODING("i256mem",         ENCODING_RM)
1146   ENCODING("f80mem",          ENCODING_RM)
1147   ENCODING("lea32mem",        ENCODING_RM)
1148   ENCODING("lea64_32mem",     ENCODING_RM)
1149   ENCODING("lea64mem",        ENCODING_RM)
1150   ENCODING("opaque32mem",     ENCODING_RM)
1151   ENCODING("opaque48mem",     ENCODING_RM)
1152   ENCODING("opaque80mem",     ENCODING_RM)
1153   ENCODING("opaque512mem",    ENCODING_RM)
1154   errs() << "Unhandled memory encoding " << s << "\n";
1155   llvm_unreachable("Unhandled memory encoding");
1156 }
1157 
1158 OperandEncoding RecognizableInstr::relocationEncodingFromString
1159   (const std::string &s,
1160    bool hasOpSizePrefix) {
1161   if(!hasOpSizePrefix) {
1162     // For instructions without an OpSize prefix, a declared 16-bit register or
1163     // immediate encoding is special.
1164     ENCODING("i16imm",        ENCODING_IW)
1165   }
1166   ENCODING("i16imm",          ENCODING_Iv)
1167   ENCODING("i16i8imm",        ENCODING_IB)
1168   ENCODING("i32imm",          ENCODING_Iv)
1169   ENCODING("i32i8imm",        ENCODING_IB)
1170   ENCODING("i64i32imm",       ENCODING_ID)
1171   ENCODING("i64i8imm",        ENCODING_IB)
1172   ENCODING("i8imm",           ENCODING_IB)
1173   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1174   ENCODING("i16imm_pcrel",    ENCODING_IW)
1175   ENCODING("i32imm_pcrel",    ENCODING_ID)
1176   ENCODING("brtarget",        ENCODING_Iv)
1177   ENCODING("brtarget8",       ENCODING_IB)
1178   ENCODING("i64imm",          ENCODING_IO)
1179   ENCODING("offset8",         ENCODING_Ia)
1180   ENCODING("offset16",        ENCODING_Ia)
1181   ENCODING("offset32",        ENCODING_Ia)
1182   ENCODING("offset64",        ENCODING_Ia)
1183   errs() << "Unhandled relocation encoding " << s << "\n";
1184   llvm_unreachable("Unhandled relocation encoding");
1185 }
1186 
1187 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1188   (const std::string &s,
1189    bool hasOpSizePrefix) {
1190   ENCODING("RST",             ENCODING_I)
1191   ENCODING("GR32",            ENCODING_Rv)
1192   ENCODING("GR64",            ENCODING_RO)
1193   ENCODING("GR16",            ENCODING_Rv)
1194   ENCODING("GR8",             ENCODING_RB)
1195   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1196   llvm_unreachable("Unhandled opcode modifier encoding");
1197 }
1198 #undef ENCODING
1199