1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, TF = 17
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 using namespace X86Disassembler;
123 
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
126 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 ///   0b11.
128 ///
129 /// @param form - The form of the instruction.
130 /// @return     - true if the form implies that a ModR/M byte is required, false
131 ///               otherwise.
132 static bool needsModRMForDecode(uint8_t form) {
133   if (form == X86Local::MRMDestReg    ||
134      form == X86Local::MRMDestMem    ||
135      form == X86Local::MRMSrcReg     ||
136      form == X86Local::MRMSrcMem     ||
137      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
139     return true;
140   else
141     return false;
142 }
143 
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 ///   the ModR/M byte to be 0b11.
146 ///
147 /// @param form - The form of the instruction.
148 /// @return     - true if the form implies that Mod must be 0b11, false
149 ///               otherwise.
150 static bool isRegFormat(uint8_t form) {
151   if (form == X86Local::MRMDestReg ||
152      form == X86Local::MRMSrcReg  ||
153      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
154     return true;
155   else
156     return false;
157 }
158 
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 ///   Useful for switch statements and the like.
161 ///
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return     - The field, with the first bit in the BitsInit as the lowest
164 ///               order bit.
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166   int width = init.getNumBits();
167 
168   assert(width <= 8 && "Field is too large for uint8_t!");
169 
170   int     index;
171   uint8_t mask = 0x01;
172 
173   uint8_t ret = 0;
174 
175   for (index = 0; index < width; index++) {
176     if (static_cast<BitInit*>(init.getBit(index))->getValue())
177       ret |= mask;
178 
179     mask <<= 1;
180   }
181 
182   return ret;
183 }
184 
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 ///   name of the field.
187 ///
188 /// @param rec  - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return     - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192   BitsInit* bits = rec->getValueAsBitsInit(name);
193   return byteFromBitsInit(*bits);
194 }
195 
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197                                      const CodeGenInstruction &insn,
198                                      InstrUID uid) {
199   UID = uid;
200 
201   Rec = insn.TheDef;
202   Name = Rec->getName();
203   Spec = &tables.specForUID(UID);
204 
205   if (!Rec->isSubClassOf("X86Inst")) {
206     ShouldBeEmitted = false;
207     return;
208   }
209 
210   Prefix   = byteFromRec(Rec, "Prefix");
211   Opcode   = byteFromRec(Rec, "Opcode");
212   Form     = byteFromRec(Rec, "FormBits");
213   SegOvr   = byteFromRec(Rec, "SegOvrBits");
214 
215   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
216   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
217   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
218   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
219   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
220   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
221   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
222 
223   Name      = Rec->getName();
224   AsmString = Rec->getValueAsString("AsmString");
225 
226   Operands = &insn.Operands.OperandList;
227 
228   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
229                      (Name.find("CRC32") != Name.npos);
230   HasFROperands    = hasFROperands();
231   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
232 
233   // Check for 64-bit inst which does not require REX
234   Is64Bit = false;
235   // FIXME: Is there some better way to check for In64BitMode?
236   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
237   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
238     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
239       Is64Bit = true;
240       break;
241     }
242   }
243   // FIXME: These instructions aren't marked as 64-bit in any way
244   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
245              Rec->getName() == "MASKMOVDQU64" ||
246              Rec->getName() == "POPFS64" ||
247              Rec->getName() == "POPGS64" ||
248              Rec->getName() == "PUSHFS64" ||
249              Rec->getName() == "PUSHGS64" ||
250              Rec->getName() == "REX64_PREFIX" ||
251              Rec->getName().find("VMREAD64") != Name.npos ||
252              Rec->getName().find("VMWRITE64") != Name.npos ||
253              Rec->getName().find("MOV64") != Name.npos ||
254              Rec->getName().find("PUSH64") != Name.npos ||
255              Rec->getName().find("POP64") != Name.npos;
256 
257   ShouldBeEmitted  = true;
258 }
259 
260 void RecognizableInstr::processInstr(DisassemblerTables &tables,
261 	const CodeGenInstruction &insn,
262                                    InstrUID uid)
263 {
264   // Ignore "asm parser only" instructions.
265   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
266     return;
267 
268   RecognizableInstr recogInstr(tables, insn, uid);
269 
270   recogInstr.emitInstructionSpecifier(tables);
271 
272   if (recogInstr.shouldBeEmitted())
273     recogInstr.emitDecodePath(tables);
274 }
275 
276 InstructionContext RecognizableInstr::insnContext() const {
277   InstructionContext insnContext;
278 
279   if (HasVEX_4VPrefix || HasVEXPrefix) {
280     if (HasOpSizePrefix && HasVEX_LPrefix)
281       insnContext = IC_VEX_L_OPSIZE;
282     else if (HasOpSizePrefix && HasVEX_WPrefix)
283       insnContext = IC_VEX_W_OPSIZE;
284     else if (HasOpSizePrefix)
285       insnContext = IC_VEX_OPSIZE;
286     else if (HasVEX_LPrefix && Prefix == X86Local::XS)
287       insnContext = IC_VEX_L_XS;
288     else if (HasVEX_LPrefix && Prefix == X86Local::XD)
289       insnContext = IC_VEX_L_XD;
290     else if (HasVEX_WPrefix && Prefix == X86Local::XS)
291       insnContext = IC_VEX_W_XS;
292     else if (HasVEX_WPrefix && Prefix == X86Local::XD)
293       insnContext = IC_VEX_W_XD;
294     else if (HasVEX_WPrefix)
295       insnContext = IC_VEX_W;
296     else if (HasVEX_LPrefix)
297       insnContext = IC_VEX_L;
298     else if (Prefix == X86Local::XD)
299       insnContext = IC_VEX_XD;
300     else if (Prefix == X86Local::XS)
301       insnContext = IC_VEX_XS;
302     else
303       insnContext = IC_VEX;
304   } else if (Is64Bit || HasREX_WPrefix) {
305     if (HasREX_WPrefix && HasOpSizePrefix)
306       insnContext = IC_64BIT_REXW_OPSIZE;
307     else if (HasOpSizePrefix)
308       insnContext = IC_64BIT_OPSIZE;
309     else if (HasREX_WPrefix && Prefix == X86Local::XS)
310       insnContext = IC_64BIT_REXW_XS;
311     else if (HasREX_WPrefix && Prefix == X86Local::XD)
312       insnContext = IC_64BIT_REXW_XD;
313     else if (Prefix == X86Local::XD)
314       insnContext = IC_64BIT_XD;
315     else if (Prefix == X86Local::XS)
316       insnContext = IC_64BIT_XS;
317     else if (HasREX_WPrefix)
318       insnContext = IC_64BIT_REXW;
319     else
320       insnContext = IC_64BIT;
321   } else {
322     if (HasOpSizePrefix && Prefix == X86Local::TF)
323       insnContext = IC_XD;
324     else if (HasOpSizePrefix)
325       insnContext = IC_OPSIZE;
326     else if (Prefix == X86Local::XD)
327       insnContext = IC_XD;
328     else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
329       insnContext = IC_XS;
330     else
331       insnContext = IC;
332   }
333 
334   return insnContext;
335 }
336 
337 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
338   ///////////////////
339   // FILTER_STRONG
340   //
341 
342   // Filter out intrinsics
343 
344   if (!Rec->isSubClassOf("X86Inst"))
345     return FILTER_STRONG;
346 
347   if (Form == X86Local::Pseudo ||
348       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
349     return FILTER_STRONG;
350 
351   if (Form == X86Local::MRMInitReg)
352     return FILTER_STRONG;
353 
354 
355   // TEMPORARY pending bug fixes
356 
357   if (Name.find("VROUND") != Name.npos)
358     return FILTER_STRONG;
359 
360   // Filter out artificial instructions
361 
362   if (Name.find("TAILJMP") != Name.npos    ||
363       Name.find("_Int") != Name.npos       ||
364       Name.find("_int") != Name.npos       ||
365       Name.find("Int_") != Name.npos       ||
366       Name.find("_NOREX") != Name.npos     ||
367       Name.find("_TC") != Name.npos        ||
368       Name.find("EH_RETURN") != Name.npos  ||
369       Name.find("V_SET") != Name.npos      ||
370       Name.find("LOCK_") != Name.npos      ||
371       Name.find("WIN") != Name.npos        ||
372       Name.find("_AVX") != Name.npos       ||
373       Name.find("2SDL") != Name.npos)
374     return FILTER_STRONG;
375 
376   // Filter out instructions with segment override prefixes.
377   // They're too messy to handle now and we'll special case them if needed.
378 
379   if (SegOvr)
380     return FILTER_STRONG;
381 
382   // Filter out instructions that can't be printed.
383 
384   if (AsmString.size() == 0)
385     return FILTER_STRONG;
386 
387   // Filter out instructions with subreg operands.
388 
389   if (AsmString.find("subreg") != AsmString.npos)
390     return FILTER_STRONG;
391 
392   /////////////////
393   // FILTER_WEAK
394   //
395 
396 
397   // Filter out instructions with a LOCK prefix;
398   //   prefer forms that do not have the prefix
399   if (HasLockPrefix)
400     return FILTER_WEAK;
401 
402   // Filter out alternate forms of AVX instructions
403   if (Name.find("_alt") != Name.npos ||
404       Name.find("XrYr") != Name.npos ||
405       Name.find("r64r") != Name.npos ||
406       Name.find("_64mr") != Name.npos ||
407       Name.find("Xrr") != Name.npos ||
408       Name.find("rr64") != Name.npos)
409     return FILTER_WEAK;
410 
411   if (Name == "VMASKMOVDQU64"  ||
412       Name == "VEXTRACTPSrr64" ||
413       Name == "VMOVQd64rr"     ||
414       Name == "VMOVQs64rr")
415     return FILTER_WEAK;
416 
417   // Special cases.
418 
419   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
420     return FILTER_WEAK;
421   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
422     return FILTER_WEAK;
423 
424   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
425     return FILTER_WEAK;
426   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
427     return FILTER_WEAK;
428   if (Name.find("Fs") != Name.npos)
429     return FILTER_WEAK;
430   if (Name == "MOVLPDrr"          ||
431       Name == "MOVLPSrr"          ||
432       Name == "PUSHFQ"            ||
433       Name == "BSF16rr"           ||
434       Name == "BSF16rm"           ||
435       Name == "BSR16rr"           ||
436       Name == "BSR16rm"           ||
437       Name == "MOVSX16rm8"        ||
438       Name == "MOVSX16rr8"        ||
439       Name == "MOVZX16rm8"        ||
440       Name == "MOVZX16rr8"        ||
441       Name == "PUSH32i16"         ||
442       Name == "PUSH64i16"         ||
443       Name == "MOVPQI2QImr"       ||
444       Name == "VMOVPQI2QImr"      ||
445       Name == "MOVSDmr"           ||
446       Name == "MOVSDrm"           ||
447       Name == "MOVSSmr"           ||
448       Name == "MOVSSrm"           ||
449       Name == "MMX_MOVD64rrv164"  ||
450       Name == "CRC32m16"          ||
451       Name == "MOV64ri64i32"      ||
452       Name == "CRC32r16")
453     return FILTER_WEAK;
454 
455   if (HasFROperands && Name.find("MOV") != Name.npos &&
456      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
457       (Name.find("to") != Name.npos)))
458     return FILTER_WEAK;
459 
460   return FILTER_NORMAL;
461 }
462 
463 bool RecognizableInstr::hasFROperands() const {
464   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
465   unsigned numOperands = OperandList.size();
466 
467   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
468     const std::string &recName = OperandList[operandIndex].Rec->getName();
469 
470     if (recName.find("FR") != recName.npos)
471       return true;
472   }
473   return false;
474 }
475 
476 bool RecognizableInstr::has256BitOperands() const {
477   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
478   unsigned numOperands = OperandList.size();
479 
480   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
481     const std::string &recName = OperandList[operandIndex].Rec->getName();
482 
483     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
484       return true;
485     }
486   }
487   return false;
488 }
489 
490 void RecognizableInstr::handleOperand(
491   bool optional,
492   unsigned &operandIndex,
493   unsigned &physicalOperandIndex,
494   unsigned &numPhysicalOperands,
495   unsigned *operandMapping,
496   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
497   if (optional) {
498     if (physicalOperandIndex >= numPhysicalOperands)
499       return;
500   } else {
501     assert(physicalOperandIndex < numPhysicalOperands);
502   }
503 
504   while (operandMapping[operandIndex] != operandIndex) {
505     Spec->operands[operandIndex].encoding = ENCODING_DUP;
506     Spec->operands[operandIndex].type =
507       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
508     ++operandIndex;
509   }
510 
511   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
512 
513   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
514                                                               HasOpSizePrefix);
515   Spec->operands[operandIndex].type = typeFromString(typeName,
516                                                      IsSSE,
517                                                      HasREX_WPrefix,
518                                                      HasOpSizePrefix);
519 
520   ++operandIndex;
521   ++physicalOperandIndex;
522 }
523 
524 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
525   Spec->name       = Name;
526 
527   if (!Rec->isSubClassOf("X86Inst"))
528     return;
529 
530   switch (filter()) {
531   case FILTER_WEAK:
532     Spec->filtered = true;
533     break;
534   case FILTER_STRONG:
535     ShouldBeEmitted = false;
536     return;
537   case FILTER_NORMAL:
538     break;
539   }
540 
541   Spec->insnContext = insnContext();
542 
543   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
544 
545   unsigned operandIndex;
546   unsigned numOperands = OperandList.size();
547   unsigned numPhysicalOperands = 0;
548 
549   // operandMapping maps from operands in OperandList to their originals.
550   // If operandMapping[i] != i, then the entry is a duplicate.
551   unsigned operandMapping[X86_MAX_OPERANDS];
552 
553   bool hasFROperands = false;
554 
555   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
556 
557   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
558     if (OperandList[operandIndex].Constraints.size()) {
559       const CGIOperandList::ConstraintInfo &Constraint =
560         OperandList[operandIndex].Constraints[0];
561       if (Constraint.isTied()) {
562         operandMapping[operandIndex] = Constraint.getTiedOperand();
563       } else {
564         ++numPhysicalOperands;
565         operandMapping[operandIndex] = operandIndex;
566       }
567     } else {
568       ++numPhysicalOperands;
569       operandMapping[operandIndex] = operandIndex;
570     }
571 
572     const std::string &recName = OperandList[operandIndex].Rec->getName();
573 
574     if (recName.find("FR") != recName.npos)
575       hasFROperands = true;
576   }
577 
578   if (hasFROperands && Name.find("MOV") != Name.npos &&
579      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
580       (Name.find("to") != Name.npos)))
581     ShouldBeEmitted = false;
582 
583   if (!ShouldBeEmitted)
584     return;
585 
586 #define HANDLE_OPERAND(class)               \
587   handleOperand(false,                      \
588                 operandIndex,               \
589                 physicalOperandIndex,       \
590                 numPhysicalOperands,        \
591                 operandMapping,             \
592                 class##EncodingFromString);
593 
594 #define HANDLE_OPTIONAL(class)              \
595   handleOperand(true,                       \
596                 operandIndex,               \
597                 physicalOperandIndex,       \
598                 numPhysicalOperands,        \
599                 operandMapping,             \
600                 class##EncodingFromString);
601 
602   // operandIndex should always be < numOperands
603   operandIndex = 0;
604   // physicalOperandIndex should always be < numPhysicalOperands
605   unsigned physicalOperandIndex = 0;
606 
607   switch (Form) {
608   case X86Local::RawFrm:
609     // Operand 1 (optional) is an address or immediate.
610     // Operand 2 (optional) is an immediate.
611     assert(numPhysicalOperands <= 2 &&
612            "Unexpected number of operands for RawFrm");
613     HANDLE_OPTIONAL(relocation)
614     HANDLE_OPTIONAL(immediate)
615     break;
616   case X86Local::AddRegFrm:
617     // Operand 1 is added to the opcode.
618     // Operand 2 (optional) is an address.
619     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
620            "Unexpected number of operands for AddRegFrm");
621     HANDLE_OPERAND(opcodeModifier)
622     HANDLE_OPTIONAL(relocation)
623     break;
624   case X86Local::MRMDestReg:
625     // Operand 1 is a register operand in the R/M field.
626     // Operand 2 is a register operand in the Reg/Opcode field.
627     // - In AVX, there is a register operand in the VEX.vvvv field here -
628     // Operand 3 (optional) is an immediate.
629     if (HasVEX_4VPrefix)
630       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
631              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
632     else
633       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
634              "Unexpected number of operands for MRMDestRegFrm");
635 
636     HANDLE_OPERAND(rmRegister)
637 
638     if (HasVEX_4VPrefix)
639       // FIXME: In AVX, the register below becomes the one encoded
640       // in ModRMVEX and the one above the one in the VEX.VVVV field
641       HANDLE_OPERAND(vvvvRegister)
642 
643     HANDLE_OPERAND(roRegister)
644     HANDLE_OPTIONAL(immediate)
645     break;
646   case X86Local::MRMDestMem:
647     // Operand 1 is a memory operand (possibly SIB-extended)
648     // Operand 2 is a register operand in the Reg/Opcode field.
649     // - In AVX, there is a register operand in the VEX.vvvv field here -
650     // Operand 3 (optional) is an immediate.
651     if (HasVEX_4VPrefix)
652       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
653              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
654     else
655       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
656              "Unexpected number of operands for MRMDestMemFrm");
657     HANDLE_OPERAND(memory)
658 
659     if (HasVEX_4VPrefix)
660       // FIXME: In AVX, the register below becomes the one encoded
661       // in ModRMVEX and the one above the one in the VEX.VVVV field
662       HANDLE_OPERAND(vvvvRegister)
663 
664     HANDLE_OPERAND(roRegister)
665     HANDLE_OPTIONAL(immediate)
666     break;
667   case X86Local::MRMSrcReg:
668     // Operand 1 is a register operand in the Reg/Opcode field.
669     // Operand 2 is a register operand in the R/M field.
670     // - In AVX, there is a register operand in the VEX.vvvv field here -
671     // Operand 3 (optional) is an immediate.
672 
673     if (HasVEX_4VPrefix)
674       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
675              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
676     else
677       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
678              "Unexpected number of operands for MRMSrcRegFrm");
679 
680     HANDLE_OPERAND(roRegister)
681 
682     if (HasVEX_4VPrefix)
683       // FIXME: In AVX, the register below becomes the one encoded
684       // in ModRMVEX and the one above the one in the VEX.VVVV field
685       HANDLE_OPERAND(vvvvRegister)
686 
687     HANDLE_OPERAND(rmRegister)
688     HANDLE_OPTIONAL(immediate)
689     break;
690   case X86Local::MRMSrcMem:
691     // Operand 1 is a register operand in the Reg/Opcode field.
692     // Operand 2 is a memory operand (possibly SIB-extended)
693     // - In AVX, there is a register operand in the VEX.vvvv field here -
694     // Operand 3 (optional) is an immediate.
695 
696     if (HasVEX_4VPrefix)
697       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
698              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
699     else
700       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
701              "Unexpected number of operands for MRMSrcMemFrm");
702 
703     HANDLE_OPERAND(roRegister)
704 
705     if (HasVEX_4VPrefix)
706       // FIXME: In AVX, the register below becomes the one encoded
707       // in ModRMVEX and the one above the one in the VEX.VVVV field
708       HANDLE_OPERAND(vvvvRegister)
709 
710     HANDLE_OPERAND(memory)
711     HANDLE_OPTIONAL(immediate)
712     break;
713   case X86Local::MRM0r:
714   case X86Local::MRM1r:
715   case X86Local::MRM2r:
716   case X86Local::MRM3r:
717   case X86Local::MRM4r:
718   case X86Local::MRM5r:
719   case X86Local::MRM6r:
720   case X86Local::MRM7r:
721     // Operand 1 is a register operand in the R/M field.
722     // Operand 2 (optional) is an immediate or relocation.
723     if (HasVEX_4VPrefix)
724       assert(numPhysicalOperands <= 3 &&
725              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
726     else
727       assert(numPhysicalOperands <= 2 &&
728              "Unexpected number of operands for MRMnRFrm");
729     if (HasVEX_4VPrefix)
730       HANDLE_OPERAND(vvvvRegister);
731     HANDLE_OPTIONAL(rmRegister)
732     HANDLE_OPTIONAL(relocation)
733     break;
734   case X86Local::MRM0m:
735   case X86Local::MRM1m:
736   case X86Local::MRM2m:
737   case X86Local::MRM3m:
738   case X86Local::MRM4m:
739   case X86Local::MRM5m:
740   case X86Local::MRM6m:
741   case X86Local::MRM7m:
742     // Operand 1 is a memory operand (possibly SIB-extended)
743     // Operand 2 (optional) is an immediate or relocation.
744     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
745            "Unexpected number of operands for MRMnMFrm");
746     HANDLE_OPERAND(memory)
747     HANDLE_OPTIONAL(relocation)
748     break;
749   case X86Local::RawFrmImm8:
750     // operand 1 is a 16-bit immediate
751     // operand 2 is an 8-bit immediate
752     assert(numPhysicalOperands == 2 &&
753            "Unexpected number of operands for X86Local::RawFrmImm8");
754     HANDLE_OPERAND(immediate)
755     HANDLE_OPERAND(immediate)
756     break;
757   case X86Local::RawFrmImm16:
758     // operand 1 is a 16-bit immediate
759     // operand 2 is a 16-bit immediate
760     HANDLE_OPERAND(immediate)
761     HANDLE_OPERAND(immediate)
762     break;
763   case X86Local::MRMInitReg:
764     // Ignored.
765     break;
766   }
767 
768   #undef HANDLE_OPERAND
769   #undef HANDLE_OPTIONAL
770 }
771 
772 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
773   // Special cases where the LLVM tables are not complete
774 
775 #define MAP(from, to)                     \
776   case X86Local::MRM_##from:              \
777     filter = new ExactFilter(0x##from);   \
778     break;
779 
780   OpcodeType    opcodeType  = (OpcodeType)-1;
781 
782   ModRMFilter*  filter      = NULL;
783   uint8_t       opcodeToSet = 0;
784 
785   switch (Prefix) {
786   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
787   case X86Local::XD:
788   case X86Local::XS:
789   case X86Local::TB:
790     opcodeType = TWOBYTE;
791 
792     switch (Opcode) {
793     default:
794       if (needsModRMForDecode(Form))
795         filter = new ModFilter(isRegFormat(Form));
796       else
797         filter = new DumbFilter();
798       break;
799 #define EXTENSION_TABLE(n) case 0x##n:
800     TWO_BYTE_EXTENSION_TABLES
801 #undef EXTENSION_TABLE
802       switch (Form) {
803       default:
804         llvm_unreachable("Unhandled two-byte extended opcode");
805       case X86Local::MRM0r:
806       case X86Local::MRM1r:
807       case X86Local::MRM2r:
808       case X86Local::MRM3r:
809       case X86Local::MRM4r:
810       case X86Local::MRM5r:
811       case X86Local::MRM6r:
812       case X86Local::MRM7r:
813         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
814         break;
815       case X86Local::MRM0m:
816       case X86Local::MRM1m:
817       case X86Local::MRM2m:
818       case X86Local::MRM3m:
819       case X86Local::MRM4m:
820       case X86Local::MRM5m:
821       case X86Local::MRM6m:
822       case X86Local::MRM7m:
823         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
824         break;
825       MRM_MAPPING
826       } // switch (Form)
827       break;
828     } // switch (Opcode)
829     opcodeToSet = Opcode;
830     break;
831   case X86Local::T8:
832   case X86Local::TF:
833     opcodeType = THREEBYTE_38;
834     if (needsModRMForDecode(Form))
835       filter = new ModFilter(isRegFormat(Form));
836     else
837       filter = new DumbFilter();
838     opcodeToSet = Opcode;
839     break;
840   case X86Local::P_TA:
841     opcodeType = THREEBYTE_3A;
842     if (needsModRMForDecode(Form))
843       filter = new ModFilter(isRegFormat(Form));
844     else
845       filter = new DumbFilter();
846     opcodeToSet = Opcode;
847     break;
848   case X86Local::A6:
849     opcodeType = THREEBYTE_A6;
850     if (needsModRMForDecode(Form))
851       filter = new ModFilter(isRegFormat(Form));
852     else
853       filter = new DumbFilter();
854     opcodeToSet = Opcode;
855     break;
856   case X86Local::A7:
857     opcodeType = THREEBYTE_A7;
858     if (needsModRMForDecode(Form))
859       filter = new ModFilter(isRegFormat(Form));
860     else
861       filter = new DumbFilter();
862     opcodeToSet = Opcode;
863     break;
864   case X86Local::D8:
865   case X86Local::D9:
866   case X86Local::DA:
867   case X86Local::DB:
868   case X86Local::DC:
869   case X86Local::DD:
870   case X86Local::DE:
871   case X86Local::DF:
872     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
873     opcodeType = ONEBYTE;
874     if (Form == X86Local::AddRegFrm) {
875       Spec->modifierType = MODIFIER_MODRM;
876       Spec->modifierBase = Opcode;
877       filter = new AddRegEscapeFilter(Opcode);
878     } else {
879       filter = new EscapeFilter(true, Opcode);
880     }
881     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
882     break;
883   case X86Local::REP:
884   default:
885     opcodeType = ONEBYTE;
886     switch (Opcode) {
887 #define EXTENSION_TABLE(n) case 0x##n:
888     ONE_BYTE_EXTENSION_TABLES
889 #undef EXTENSION_TABLE
890       switch (Form) {
891       default:
892         llvm_unreachable("Fell through the cracks of a single-byte "
893                          "extended opcode");
894       case X86Local::MRM0r:
895       case X86Local::MRM1r:
896       case X86Local::MRM2r:
897       case X86Local::MRM3r:
898       case X86Local::MRM4r:
899       case X86Local::MRM5r:
900       case X86Local::MRM6r:
901       case X86Local::MRM7r:
902         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
903         break;
904       case X86Local::MRM0m:
905       case X86Local::MRM1m:
906       case X86Local::MRM2m:
907       case X86Local::MRM3m:
908       case X86Local::MRM4m:
909       case X86Local::MRM5m:
910       case X86Local::MRM6m:
911       case X86Local::MRM7m:
912         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
913         break;
914       MRM_MAPPING
915       } // switch (Form)
916       break;
917     case 0xd8:
918     case 0xd9:
919     case 0xda:
920     case 0xdb:
921     case 0xdc:
922     case 0xdd:
923     case 0xde:
924     case 0xdf:
925       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
926       break;
927     default:
928       if (needsModRMForDecode(Form))
929         filter = new ModFilter(isRegFormat(Form));
930       else
931         filter = new DumbFilter();
932       break;
933     } // switch (Opcode)
934     opcodeToSet = Opcode;
935   } // switch (Prefix)
936 
937   assert(opcodeType != (OpcodeType)-1 &&
938          "Opcode type not set");
939   assert(filter && "Filter not set");
940 
941   if (Form == X86Local::AddRegFrm) {
942     if(Spec->modifierType != MODIFIER_MODRM) {
943       assert(opcodeToSet < 0xf9 &&
944              "Not enough room for all ADDREG_FRM operands");
945 
946       uint8_t currentOpcode;
947 
948       for (currentOpcode = opcodeToSet;
949            currentOpcode < opcodeToSet + 8;
950            ++currentOpcode)
951         tables.setTableFields(opcodeType,
952                               insnContext(),
953                               currentOpcode,
954                               *filter,
955                               UID);
956 
957       Spec->modifierType = MODIFIER_OPCODE;
958       Spec->modifierBase = opcodeToSet;
959     } else {
960       // modifierBase was set where MODIFIER_MODRM was set
961       tables.setTableFields(opcodeType,
962                             insnContext(),
963                             opcodeToSet,
964                             *filter,
965                             UID);
966     }
967   } else {
968     tables.setTableFields(opcodeType,
969                           insnContext(),
970                           opcodeToSet,
971                           *filter,
972                           UID);
973 
974     Spec->modifierType = MODIFIER_NONE;
975     Spec->modifierBase = opcodeToSet;
976   }
977 
978   delete filter;
979 
980 #undef MAP
981 }
982 
983 #define TYPE(str, type) if (s == str) return type;
984 OperandType RecognizableInstr::typeFromString(const std::string &s,
985                                               bool isSSE,
986                                               bool hasREX_WPrefix,
987                                               bool hasOpSizePrefix) {
988   if (isSSE) {
989     // For SSE instructions, we ignore the OpSize prefix and force operand
990     // sizes.
991     TYPE("GR16",              TYPE_R16)
992     TYPE("GR32",              TYPE_R32)
993     TYPE("GR64",              TYPE_R64)
994   }
995   if(hasREX_WPrefix) {
996     // For instructions with a REX_W prefix, a declared 32-bit register encoding
997     // is special.
998     TYPE("GR32",              TYPE_R32)
999   }
1000   if(!hasOpSizePrefix) {
1001     // For instructions without an OpSize prefix, a declared 16-bit register or
1002     // immediate encoding is special.
1003     TYPE("GR16",              TYPE_R16)
1004     TYPE("i16imm",            TYPE_IMM16)
1005   }
1006   TYPE("i16mem",              TYPE_Mv)
1007   TYPE("i16imm",              TYPE_IMMv)
1008   TYPE("i16i8imm",            TYPE_IMMv)
1009   TYPE("GR16",                TYPE_Rv)
1010   TYPE("i32mem",              TYPE_Mv)
1011   TYPE("i32imm",              TYPE_IMMv)
1012   TYPE("i32i8imm",            TYPE_IMM32)
1013   TYPE("u32u8imm",            TYPE_IMM32)
1014   TYPE("GR32",                TYPE_Rv)
1015   TYPE("i64mem",              TYPE_Mv)
1016   TYPE("i64i32imm",           TYPE_IMM64)
1017   TYPE("i64i8imm",            TYPE_IMM64)
1018   TYPE("GR64",                TYPE_R64)
1019   TYPE("i8mem",               TYPE_M8)
1020   TYPE("i8imm",               TYPE_IMM8)
1021   TYPE("GR8",                 TYPE_R8)
1022   TYPE("VR128",               TYPE_XMM128)
1023   TYPE("f128mem",             TYPE_M128)
1024   TYPE("f256mem",             TYPE_M256)
1025   TYPE("FR64",                TYPE_XMM64)
1026   TYPE("f64mem",              TYPE_M64FP)
1027   TYPE("sdmem",               TYPE_M64FP)
1028   TYPE("FR32",                TYPE_XMM32)
1029   TYPE("f32mem",              TYPE_M32FP)
1030   TYPE("ssmem",               TYPE_M32FP)
1031   TYPE("RST",                 TYPE_ST)
1032   TYPE("i128mem",             TYPE_M128)
1033   TYPE("i256mem",             TYPE_M256)
1034   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1035   TYPE("i16imm_pcrel",        TYPE_REL16)
1036   TYPE("i32imm_pcrel",        TYPE_REL32)
1037   TYPE("SSECC",               TYPE_IMM3)
1038   TYPE("brtarget",            TYPE_RELv)
1039   TYPE("uncondbrtarget",      TYPE_RELv)
1040   TYPE("brtarget8",           TYPE_REL8)
1041   TYPE("f80mem",              TYPE_M80FP)
1042   TYPE("lea32mem",            TYPE_LEA)
1043   TYPE("lea64_32mem",         TYPE_LEA)
1044   TYPE("lea64mem",            TYPE_LEA)
1045   TYPE("VR64",                TYPE_MM64)
1046   TYPE("i64imm",              TYPE_IMMv)
1047   TYPE("opaque32mem",         TYPE_M1616)
1048   TYPE("opaque48mem",         TYPE_M1632)
1049   TYPE("opaque80mem",         TYPE_M1664)
1050   TYPE("opaque512mem",        TYPE_M512)
1051   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1052   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1053   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1054   TYPE("offset8",             TYPE_MOFFS8)
1055   TYPE("offset16",            TYPE_MOFFS16)
1056   TYPE("offset32",            TYPE_MOFFS32)
1057   TYPE("offset64",            TYPE_MOFFS64)
1058   TYPE("VR256",               TYPE_XMM256)
1059   errs() << "Unhandled type string " << s << "\n";
1060   llvm_unreachable("Unhandled type string");
1061 }
1062 #undef TYPE
1063 
1064 #define ENCODING(str, encoding) if (s == str) return encoding;
1065 OperandEncoding RecognizableInstr::immediateEncodingFromString
1066   (const std::string &s,
1067    bool hasOpSizePrefix) {
1068   if(!hasOpSizePrefix) {
1069     // For instructions without an OpSize prefix, a declared 16-bit register or
1070     // immediate encoding is special.
1071     ENCODING("i16imm",        ENCODING_IW)
1072   }
1073   ENCODING("i32i8imm",        ENCODING_IB)
1074   ENCODING("u32u8imm",        ENCODING_IB)
1075   ENCODING("SSECC",           ENCODING_IB)
1076   ENCODING("i16imm",          ENCODING_Iv)
1077   ENCODING("i16i8imm",        ENCODING_IB)
1078   ENCODING("i32imm",          ENCODING_Iv)
1079   ENCODING("i64i32imm",       ENCODING_ID)
1080   ENCODING("i64i8imm",        ENCODING_IB)
1081   ENCODING("i8imm",           ENCODING_IB)
1082   // This is not a typo.  Instructions like BLENDVPD put
1083   // register IDs in 8-bit immediates nowadays.
1084   ENCODING("VR256",           ENCODING_IB)
1085   ENCODING("VR128",           ENCODING_IB)
1086   errs() << "Unhandled immediate encoding " << s << "\n";
1087   llvm_unreachable("Unhandled immediate encoding");
1088 }
1089 
1090 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1091   (const std::string &s,
1092    bool hasOpSizePrefix) {
1093   ENCODING("GR16",            ENCODING_RM)
1094   ENCODING("GR32",            ENCODING_RM)
1095   ENCODING("GR64",            ENCODING_RM)
1096   ENCODING("GR8",             ENCODING_RM)
1097   ENCODING("VR128",           ENCODING_RM)
1098   ENCODING("FR64",            ENCODING_RM)
1099   ENCODING("FR32",            ENCODING_RM)
1100   ENCODING("VR64",            ENCODING_RM)
1101   ENCODING("VR256",           ENCODING_RM)
1102   errs() << "Unhandled R/M register encoding " << s << "\n";
1103   llvm_unreachable("Unhandled R/M register encoding");
1104 }
1105 
1106 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1107   (const std::string &s,
1108    bool hasOpSizePrefix) {
1109   ENCODING("GR16",            ENCODING_REG)
1110   ENCODING("GR32",            ENCODING_REG)
1111   ENCODING("GR64",            ENCODING_REG)
1112   ENCODING("GR8",             ENCODING_REG)
1113   ENCODING("VR128",           ENCODING_REG)
1114   ENCODING("FR64",            ENCODING_REG)
1115   ENCODING("FR32",            ENCODING_REG)
1116   ENCODING("VR64",            ENCODING_REG)
1117   ENCODING("SEGMENT_REG",     ENCODING_REG)
1118   ENCODING("DEBUG_REG",       ENCODING_REG)
1119   ENCODING("CONTROL_REG",     ENCODING_REG)
1120   ENCODING("VR256",           ENCODING_REG)
1121   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1122   llvm_unreachable("Unhandled reg/opcode register encoding");
1123 }
1124 
1125 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1126   (const std::string &s,
1127    bool hasOpSizePrefix) {
1128   ENCODING("FR32",            ENCODING_VVVV)
1129   ENCODING("FR64",            ENCODING_VVVV)
1130   ENCODING("VR128",           ENCODING_VVVV)
1131   ENCODING("VR256",           ENCODING_VVVV)
1132   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1133   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1134 }
1135 
1136 OperandEncoding RecognizableInstr::memoryEncodingFromString
1137   (const std::string &s,
1138    bool hasOpSizePrefix) {
1139   ENCODING("i16mem",          ENCODING_RM)
1140   ENCODING("i32mem",          ENCODING_RM)
1141   ENCODING("i64mem",          ENCODING_RM)
1142   ENCODING("i8mem",           ENCODING_RM)
1143   ENCODING("ssmem",           ENCODING_RM)
1144   ENCODING("sdmem",           ENCODING_RM)
1145   ENCODING("f128mem",         ENCODING_RM)
1146   ENCODING("f256mem",         ENCODING_RM)
1147   ENCODING("f64mem",          ENCODING_RM)
1148   ENCODING("f32mem",          ENCODING_RM)
1149   ENCODING("i128mem",         ENCODING_RM)
1150   ENCODING("i256mem",         ENCODING_RM)
1151   ENCODING("f80mem",          ENCODING_RM)
1152   ENCODING("lea32mem",        ENCODING_RM)
1153   ENCODING("lea64_32mem",     ENCODING_RM)
1154   ENCODING("lea64mem",        ENCODING_RM)
1155   ENCODING("opaque32mem",     ENCODING_RM)
1156   ENCODING("opaque48mem",     ENCODING_RM)
1157   ENCODING("opaque80mem",     ENCODING_RM)
1158   ENCODING("opaque512mem",    ENCODING_RM)
1159   errs() << "Unhandled memory encoding " << s << "\n";
1160   llvm_unreachable("Unhandled memory encoding");
1161 }
1162 
1163 OperandEncoding RecognizableInstr::relocationEncodingFromString
1164   (const std::string &s,
1165    bool hasOpSizePrefix) {
1166   if(!hasOpSizePrefix) {
1167     // For instructions without an OpSize prefix, a declared 16-bit register or
1168     // immediate encoding is special.
1169     ENCODING("i16imm",        ENCODING_IW)
1170   }
1171   ENCODING("i16imm",          ENCODING_Iv)
1172   ENCODING("i16i8imm",        ENCODING_IB)
1173   ENCODING("i32imm",          ENCODING_Iv)
1174   ENCODING("i32i8imm",        ENCODING_IB)
1175   ENCODING("i64i32imm",       ENCODING_ID)
1176   ENCODING("i64i8imm",        ENCODING_IB)
1177   ENCODING("i8imm",           ENCODING_IB)
1178   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1179   ENCODING("i16imm_pcrel",    ENCODING_IW)
1180   ENCODING("i32imm_pcrel",    ENCODING_ID)
1181   ENCODING("brtarget",        ENCODING_Iv)
1182   ENCODING("brtarget8",       ENCODING_IB)
1183   ENCODING("i64imm",          ENCODING_IO)
1184   ENCODING("offset8",         ENCODING_Ia)
1185   ENCODING("offset16",        ENCODING_Ia)
1186   ENCODING("offset32",        ENCODING_Ia)
1187   ENCODING("offset64",        ENCODING_Ia)
1188   errs() << "Unhandled relocation encoding " << s << "\n";
1189   llvm_unreachable("Unhandled relocation encoding");
1190 }
1191 
1192 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1193   (const std::string &s,
1194    bool hasOpSizePrefix) {
1195   ENCODING("RST",             ENCODING_I)
1196   ENCODING("GR32",            ENCODING_Rv)
1197   ENCODING("GR64",            ENCODING_RO)
1198   ENCODING("GR16",            ENCODING_Rv)
1199   ENCODING("GR8",             ENCODING_RB)
1200   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1201   llvm_unreachable("Unhandled opcode modifier encoding");
1202 }
1203 #undef ENCODING
1204