1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisassemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 using namespace X86Disassembler; 25 26 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 27 /// Useful for switch statements and the like. 28 /// 29 /// @param init - A reference to the BitsInit to be decoded. 30 /// @return - The field, with the first bit in the BitsInit as the lowest 31 /// order bit. 32 static uint8_t byteFromBitsInit(BitsInit &init) { 33 int width = init.getNumBits(); 34 35 assert(width <= 8 && "Field is too large for uint8_t!"); 36 37 int index; 38 uint8_t mask = 0x01; 39 40 uint8_t ret = 0; 41 42 for (index = 0; index < width; index++) { 43 if (cast<BitInit>(init.getBit(index))->getValue()) 44 ret |= mask; 45 46 mask <<= 1; 47 } 48 49 return ret; 50 } 51 52 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 53 /// name of the field. 54 /// 55 /// @param rec - The record from which to extract the value. 56 /// @param name - The name of the field in the record. 57 /// @return - The field, as translated by byteFromBitsInit(). 58 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 59 BitsInit* bits = rec->getValueAsBitsInit(name); 60 return byteFromBitsInit(*bits); 61 } 62 63 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 64 const CodeGenInstruction &insn, 65 InstrUID uid) { 66 UID = uid; 67 68 Rec = insn.TheDef; 69 Name = Rec->getName(); 70 Spec = &tables.specForUID(UID); 71 72 if (!Rec->isSubClassOf("X86Inst")) { 73 ShouldBeEmitted = false; 74 return; 75 } 76 77 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 78 OpMap = byteFromRec(Rec, "OpMapBits"); 79 Opcode = byteFromRec(Rec, "Opcode"); 80 Form = byteFromRec(Rec, "FormBits"); 81 Encoding = byteFromRec(Rec, "OpEncBits"); 82 83 OpSize = byteFromRec(Rec, "OpSizeBits"); 84 AdSize = byteFromRec(Rec, "AdSizeBits"); 85 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 86 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 87 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 95 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 96 97 Name = Rec->getName(); 98 99 Operands = &insn.Operands.OperandList; 100 101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 102 103 EncodeRC = HasEVEX_B && 104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 105 106 // Check for 64-bit inst which does not require REX 107 Is32Bit = false; 108 Is64Bit = false; 109 // FIXME: Is there some better way to check for In64BitMode? 110 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 111 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 112 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 113 Predicates[i]->getName().find("In32Bit") != Name.npos) { 114 Is32Bit = true; 115 break; 116 } 117 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 118 Is64Bit = true; 119 break; 120 } 121 } 122 123 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 124 ShouldBeEmitted = false; 125 return; 126 } 127 128 // Special case since there is no attribute class for 64-bit and VEX 129 if (Name == "VMASKMOVDQU64") { 130 ShouldBeEmitted = false; 131 return; 132 } 133 134 ShouldBeEmitted = true; 135 } 136 137 void RecognizableInstr::processInstr(DisassemblerTables &tables, 138 const CodeGenInstruction &insn, 139 InstrUID uid) 140 { 141 // Ignore "asm parser only" instructions. 142 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 143 return; 144 145 RecognizableInstr recogInstr(tables, insn, uid); 146 147 if (recogInstr.shouldBeEmitted()) { 148 recogInstr.emitInstructionSpecifier(); 149 recogInstr.emitDecodePath(tables); 150 } 151 } 152 153 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 154 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 155 (HasEVEX_KZ ? n##_KZ : \ 156 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 157 158 InstructionContext RecognizableInstr::insnContext() const { 159 InstructionContext insnContext; 160 161 if (Encoding == X86Local::EVEX) { 162 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 165 } 166 // VEX_L & VEX_W 167 if (!EncodeRC && HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 168 if (OpPrefix == X86Local::PD) 169 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 170 else if (OpPrefix == X86Local::XS) 171 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 172 else if (OpPrefix == X86Local::XD) 173 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 174 else if (OpPrefix == X86Local::PS) 175 insnContext = EVEX_KB(IC_EVEX_L_W); 176 else { 177 errs() << "Instruction does not use a prefix: " << Name << "\n"; 178 llvm_unreachable("Invalid prefix"); 179 } 180 } else if (!EncodeRC && HasVEX_LPrefix) { 181 // VEX_L 182 if (OpPrefix == X86Local::PD) 183 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 184 else if (OpPrefix == X86Local::XS) 185 insnContext = EVEX_KB(IC_EVEX_L_XS); 186 else if (OpPrefix == X86Local::XD) 187 insnContext = EVEX_KB(IC_EVEX_L_XD); 188 else if (OpPrefix == X86Local::PS) 189 insnContext = EVEX_KB(IC_EVEX_L); 190 else { 191 errs() << "Instruction does not use a prefix: " << Name << "\n"; 192 llvm_unreachable("Invalid prefix"); 193 } 194 } else if (!EncodeRC && HasEVEX_L2Prefix && 195 VEX_WPrefix == X86Local::VEX_W1) { 196 // EVEX_L2 & VEX_W 197 if (OpPrefix == X86Local::PD) 198 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 199 else if (OpPrefix == X86Local::XS) 200 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 201 else if (OpPrefix == X86Local::XD) 202 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 203 else if (OpPrefix == X86Local::PS) 204 insnContext = EVEX_KB(IC_EVEX_L2_W); 205 else { 206 errs() << "Instruction does not use a prefix: " << Name << "\n"; 207 llvm_unreachable("Invalid prefix"); 208 } 209 } else if (!EncodeRC && HasEVEX_L2Prefix) { 210 // EVEX_L2 211 if (OpPrefix == X86Local::PD) 212 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 213 else if (OpPrefix == X86Local::XD) 214 insnContext = EVEX_KB(IC_EVEX_L2_XD); 215 else if (OpPrefix == X86Local::XS) 216 insnContext = EVEX_KB(IC_EVEX_L2_XS); 217 else if (OpPrefix == X86Local::PS) 218 insnContext = EVEX_KB(IC_EVEX_L2); 219 else { 220 errs() << "Instruction does not use a prefix: " << Name << "\n"; 221 llvm_unreachable("Invalid prefix"); 222 } 223 } 224 else if (VEX_WPrefix == X86Local::VEX_W1) { 225 // VEX_W 226 if (OpPrefix == X86Local::PD) 227 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 228 else if (OpPrefix == X86Local::XS) 229 insnContext = EVEX_KB(IC_EVEX_W_XS); 230 else if (OpPrefix == X86Local::XD) 231 insnContext = EVEX_KB(IC_EVEX_W_XD); 232 else if (OpPrefix == X86Local::PS) 233 insnContext = EVEX_KB(IC_EVEX_W); 234 else { 235 errs() << "Instruction does not use a prefix: " << Name << "\n"; 236 llvm_unreachable("Invalid prefix"); 237 } 238 } 239 // No L, no W 240 else if (OpPrefix == X86Local::PD) 241 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 242 else if (OpPrefix == X86Local::XD) 243 insnContext = EVEX_KB(IC_EVEX_XD); 244 else if (OpPrefix == X86Local::XS) 245 insnContext = EVEX_KB(IC_EVEX_XS); 246 else if (OpPrefix == X86Local::PS) 247 insnContext = EVEX_KB(IC_EVEX); 248 else { 249 errs() << "Instruction does not use a prefix: " << Name << "\n"; 250 llvm_unreachable("Invalid prefix"); 251 } 252 /// eof EVEX 253 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 254 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 255 if (OpPrefix == X86Local::PD) 256 insnContext = IC_VEX_L_W_OPSIZE; 257 else if (OpPrefix == X86Local::XS) 258 insnContext = IC_VEX_L_W_XS; 259 else if (OpPrefix == X86Local::XD) 260 insnContext = IC_VEX_L_W_XD; 261 else if (OpPrefix == X86Local::PS) 262 insnContext = IC_VEX_L_W; 263 else { 264 errs() << "Instruction does not use a prefix: " << Name << "\n"; 265 llvm_unreachable("Invalid prefix"); 266 } 267 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 268 insnContext = IC_VEX_L_OPSIZE; 269 else if (OpPrefix == X86Local::PD && VEX_WPrefix == X86Local::VEX_W1) 270 insnContext = IC_VEX_W_OPSIZE; 271 else if (OpPrefix == X86Local::PD) 272 insnContext = IC_VEX_OPSIZE; 273 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 274 insnContext = IC_VEX_L_XS; 275 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 276 insnContext = IC_VEX_L_XD; 277 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XS) 278 insnContext = IC_VEX_W_XS; 279 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XD) 280 insnContext = IC_VEX_W_XD; 281 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::PS) 282 insnContext = IC_VEX_W; 283 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 284 insnContext = IC_VEX_L; 285 else if (OpPrefix == X86Local::XD) 286 insnContext = IC_VEX_XD; 287 else if (OpPrefix == X86Local::XS) 288 insnContext = IC_VEX_XS; 289 else if (OpPrefix == X86Local::PS) 290 insnContext = IC_VEX; 291 else { 292 errs() << "Instruction does not use a prefix: " << Name << "\n"; 293 llvm_unreachable("Invalid prefix"); 294 } 295 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 296 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 297 insnContext = IC_64BIT_REXW_OPSIZE; 298 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 299 insnContext = IC_64BIT_REXW_ADSIZE; 300 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 301 insnContext = IC_64BIT_XD_OPSIZE; 302 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 303 insnContext = IC_64BIT_XS_OPSIZE; 304 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 305 insnContext = IC_64BIT_OPSIZE_ADSIZE; 306 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 307 insnContext = IC_64BIT_OPSIZE; 308 else if (AdSize == X86Local::AdSize32) 309 insnContext = IC_64BIT_ADSIZE; 310 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 311 insnContext = IC_64BIT_REXW_XS; 312 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 313 insnContext = IC_64BIT_REXW_XD; 314 else if (OpPrefix == X86Local::XD) 315 insnContext = IC_64BIT_XD; 316 else if (OpPrefix == X86Local::XS) 317 insnContext = IC_64BIT_XS; 318 else if (HasREX_WPrefix) 319 insnContext = IC_64BIT_REXW; 320 else 321 insnContext = IC_64BIT; 322 } else { 323 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 324 insnContext = IC_XD_OPSIZE; 325 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 326 insnContext = IC_XS_OPSIZE; 327 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 328 insnContext = IC_OPSIZE_ADSIZE; 329 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 330 insnContext = IC_OPSIZE; 331 else if (AdSize == X86Local::AdSize16) 332 insnContext = IC_ADSIZE; 333 else if (OpPrefix == X86Local::XD) 334 insnContext = IC_XD; 335 else if (OpPrefix == X86Local::XS) 336 insnContext = IC_XS; 337 else 338 insnContext = IC; 339 } 340 341 return insnContext; 342 } 343 344 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 345 // The scaling factor for AVX512 compressed displacement encoding is an 346 // instruction attribute. Adjust the ModRM encoding type to include the 347 // scale for compressed displacement. 348 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 349 return; 350 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 351 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 352 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 353 "Invalid CDisp scaling"); 354 } 355 356 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 357 unsigned &physicalOperandIndex, 358 unsigned numPhysicalOperands, 359 const unsigned *operandMapping, 360 OperandEncoding (*encodingFromString) 361 (const std::string&, 362 uint8_t OpSize)) { 363 if (optional) { 364 if (physicalOperandIndex >= numPhysicalOperands) 365 return; 366 } else { 367 assert(physicalOperandIndex < numPhysicalOperands); 368 } 369 370 while (operandMapping[operandIndex] != operandIndex) { 371 Spec->operands[operandIndex].encoding = ENCODING_DUP; 372 Spec->operands[operandIndex].type = 373 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 374 ++operandIndex; 375 } 376 377 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 378 379 OperandEncoding encoding = encodingFromString(typeName, OpSize); 380 // Adjust the encoding type for an operand based on the instruction. 381 adjustOperandEncoding(encoding); 382 Spec->operands[operandIndex].encoding = encoding; 383 Spec->operands[operandIndex].type = typeFromString(typeName, 384 HasREX_WPrefix, OpSize); 385 386 ++operandIndex; 387 ++physicalOperandIndex; 388 } 389 390 void RecognizableInstr::emitInstructionSpecifier() { 391 Spec->name = Name; 392 393 Spec->insnContext = insnContext(); 394 395 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 396 397 unsigned numOperands = OperandList.size(); 398 unsigned numPhysicalOperands = 0; 399 400 // operandMapping maps from operands in OperandList to their originals. 401 // If operandMapping[i] != i, then the entry is a duplicate. 402 unsigned operandMapping[X86_MAX_OPERANDS]; 403 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 404 405 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 406 if (!OperandList[operandIndex].Constraints.empty()) { 407 const CGIOperandList::ConstraintInfo &Constraint = 408 OperandList[operandIndex].Constraints[0]; 409 if (Constraint.isTied()) { 410 operandMapping[operandIndex] = operandIndex; 411 operandMapping[Constraint.getTiedOperand()] = operandIndex; 412 } else { 413 ++numPhysicalOperands; 414 operandMapping[operandIndex] = operandIndex; 415 } 416 } else { 417 ++numPhysicalOperands; 418 operandMapping[operandIndex] = operandIndex; 419 } 420 } 421 422 #define HANDLE_OPERAND(class) \ 423 handleOperand(false, \ 424 operandIndex, \ 425 physicalOperandIndex, \ 426 numPhysicalOperands, \ 427 operandMapping, \ 428 class##EncodingFromString); 429 430 #define HANDLE_OPTIONAL(class) \ 431 handleOperand(true, \ 432 operandIndex, \ 433 physicalOperandIndex, \ 434 numPhysicalOperands, \ 435 operandMapping, \ 436 class##EncodingFromString); 437 438 // operandIndex should always be < numOperands 439 unsigned operandIndex = 0; 440 // physicalOperandIndex should always be < numPhysicalOperands 441 unsigned physicalOperandIndex = 0; 442 443 #ifndef NDEBUG 444 // Given the set of prefix bits, how many additional operands does the 445 // instruction have? 446 unsigned additionalOperands = 0; 447 if (HasVEX_4V) 448 ++additionalOperands; 449 if (HasEVEX_K) 450 ++additionalOperands; 451 #endif 452 453 switch (Form) { 454 default: llvm_unreachable("Unhandled form"); 455 case X86Local::RawFrmSrc: 456 HANDLE_OPERAND(relocation); 457 return; 458 case X86Local::RawFrmDst: 459 HANDLE_OPERAND(relocation); 460 return; 461 case X86Local::RawFrmDstSrc: 462 HANDLE_OPERAND(relocation); 463 HANDLE_OPERAND(relocation); 464 return; 465 case X86Local::RawFrm: 466 // Operand 1 (optional) is an address or immediate. 467 assert(numPhysicalOperands <= 1 && 468 "Unexpected number of operands for RawFrm"); 469 HANDLE_OPTIONAL(relocation) 470 break; 471 case X86Local::RawFrmMemOffs: 472 // Operand 1 is an address. 473 HANDLE_OPERAND(relocation); 474 break; 475 case X86Local::AddRegFrm: 476 // Operand 1 is added to the opcode. 477 // Operand 2 (optional) is an address. 478 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 479 "Unexpected number of operands for AddRegFrm"); 480 HANDLE_OPERAND(opcodeModifier) 481 HANDLE_OPTIONAL(relocation) 482 break; 483 case X86Local::MRMDestReg: 484 // Operand 1 is a register operand in the R/M field. 485 // - In AVX512 there may be a mask operand here - 486 // Operand 2 is a register operand in the Reg/Opcode field. 487 // - In AVX, there is a register operand in the VEX.vvvv field here - 488 // Operand 3 (optional) is an immediate. 489 assert(numPhysicalOperands >= 2 + additionalOperands && 490 numPhysicalOperands <= 3 + additionalOperands && 491 "Unexpected number of operands for MRMDestRegFrm"); 492 493 HANDLE_OPERAND(rmRegister) 494 if (HasEVEX_K) 495 HANDLE_OPERAND(writemaskRegister) 496 497 if (HasVEX_4V) 498 // FIXME: In AVX, the register below becomes the one encoded 499 // in ModRMVEX and the one above the one in the VEX.VVVV field 500 HANDLE_OPERAND(vvvvRegister) 501 502 HANDLE_OPERAND(roRegister) 503 HANDLE_OPTIONAL(immediate) 504 break; 505 case X86Local::MRMDestMem: 506 // Operand 1 is a memory operand (possibly SIB-extended) 507 // Operand 2 is a register operand in the Reg/Opcode field. 508 // - In AVX, there is a register operand in the VEX.vvvv field here - 509 // Operand 3 (optional) is an immediate. 510 assert(numPhysicalOperands >= 2 + additionalOperands && 511 numPhysicalOperands <= 3 + additionalOperands && 512 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 513 514 HANDLE_OPERAND(memory) 515 516 if (HasEVEX_K) 517 HANDLE_OPERAND(writemaskRegister) 518 519 if (HasVEX_4V) 520 // FIXME: In AVX, the register below becomes the one encoded 521 // in ModRMVEX and the one above the one in the VEX.VVVV field 522 HANDLE_OPERAND(vvvvRegister) 523 524 HANDLE_OPERAND(roRegister) 525 HANDLE_OPTIONAL(immediate) 526 break; 527 case X86Local::MRMSrcReg: 528 // Operand 1 is a register operand in the Reg/Opcode field. 529 // Operand 2 is a register operand in the R/M field. 530 // - In AVX, there is a register operand in the VEX.vvvv field here - 531 // Operand 3 (optional) is an immediate. 532 // Operand 4 (optional) is an immediate. 533 534 assert(numPhysicalOperands >= 2 + additionalOperands && 535 numPhysicalOperands <= 4 + additionalOperands && 536 "Unexpected number of operands for MRMSrcRegFrm"); 537 538 HANDLE_OPERAND(roRegister) 539 540 if (HasEVEX_K) 541 HANDLE_OPERAND(writemaskRegister) 542 543 if (HasVEX_4V) 544 // FIXME: In AVX, the register below becomes the one encoded 545 // in ModRMVEX and the one above the one in the VEX.VVVV field 546 HANDLE_OPERAND(vvvvRegister) 547 548 HANDLE_OPERAND(rmRegister) 549 HANDLE_OPTIONAL(immediate) 550 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 551 HANDLE_OPTIONAL(immediate) 552 break; 553 case X86Local::MRMSrcReg4VOp3: 554 assert(numPhysicalOperands == 3 && 555 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 556 HANDLE_OPERAND(roRegister) 557 HANDLE_OPERAND(rmRegister) 558 HANDLE_OPERAND(vvvvRegister) 559 break; 560 case X86Local::MRMSrcRegOp4: 561 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 562 "Unexpected number of operands for MRMSrcRegOp4Frm"); 563 HANDLE_OPERAND(roRegister) 564 HANDLE_OPERAND(vvvvRegister) 565 HANDLE_OPERAND(immediate) // Register in imm[7:4] 566 HANDLE_OPERAND(rmRegister) 567 HANDLE_OPTIONAL(immediate) 568 break; 569 case X86Local::MRMSrcMem: 570 // Operand 1 is a register operand in the Reg/Opcode field. 571 // Operand 2 is a memory operand (possibly SIB-extended) 572 // - In AVX, there is a register operand in the VEX.vvvv field here - 573 // Operand 3 (optional) is an immediate. 574 575 assert(numPhysicalOperands >= 2 + additionalOperands && 576 numPhysicalOperands <= 4 + additionalOperands && 577 "Unexpected number of operands for MRMSrcMemFrm"); 578 579 HANDLE_OPERAND(roRegister) 580 581 if (HasEVEX_K) 582 HANDLE_OPERAND(writemaskRegister) 583 584 if (HasVEX_4V) 585 // FIXME: In AVX, the register below becomes the one encoded 586 // in ModRMVEX and the one above the one in the VEX.VVVV field 587 HANDLE_OPERAND(vvvvRegister) 588 589 HANDLE_OPERAND(memory) 590 HANDLE_OPTIONAL(immediate) 591 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 592 break; 593 case X86Local::MRMSrcMem4VOp3: 594 assert(numPhysicalOperands == 3 && 595 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 596 HANDLE_OPERAND(roRegister) 597 HANDLE_OPERAND(memory) 598 HANDLE_OPERAND(vvvvRegister) 599 break; 600 case X86Local::MRMSrcMemOp4: 601 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 602 "Unexpected number of operands for MRMSrcMemOp4Frm"); 603 HANDLE_OPERAND(roRegister) 604 HANDLE_OPERAND(vvvvRegister) 605 HANDLE_OPERAND(immediate) // Register in imm[7:4] 606 HANDLE_OPERAND(memory) 607 HANDLE_OPTIONAL(immediate) 608 break; 609 case X86Local::MRMXr: 610 case X86Local::MRM0r: 611 case X86Local::MRM1r: 612 case X86Local::MRM2r: 613 case X86Local::MRM3r: 614 case X86Local::MRM4r: 615 case X86Local::MRM5r: 616 case X86Local::MRM6r: 617 case X86Local::MRM7r: 618 // Operand 1 is a register operand in the R/M field. 619 // Operand 2 (optional) is an immediate or relocation. 620 // Operand 3 (optional) is an immediate. 621 assert(numPhysicalOperands >= 0 + additionalOperands && 622 numPhysicalOperands <= 3 + additionalOperands && 623 "Unexpected number of operands for MRMnr"); 624 625 if (HasVEX_4V) 626 HANDLE_OPERAND(vvvvRegister) 627 628 if (HasEVEX_K) 629 HANDLE_OPERAND(writemaskRegister) 630 HANDLE_OPTIONAL(rmRegister) 631 HANDLE_OPTIONAL(relocation) 632 HANDLE_OPTIONAL(immediate) 633 break; 634 case X86Local::MRMXm: 635 case X86Local::MRM0m: 636 case X86Local::MRM1m: 637 case X86Local::MRM2m: 638 case X86Local::MRM3m: 639 case X86Local::MRM4m: 640 case X86Local::MRM5m: 641 case X86Local::MRM6m: 642 case X86Local::MRM7m: 643 // Operand 1 is a memory operand (possibly SIB-extended) 644 // Operand 2 (optional) is an immediate or relocation. 645 assert(numPhysicalOperands >= 1 + additionalOperands && 646 numPhysicalOperands <= 2 + additionalOperands && 647 "Unexpected number of operands for MRMnm"); 648 649 if (HasVEX_4V) 650 HANDLE_OPERAND(vvvvRegister) 651 if (HasEVEX_K) 652 HANDLE_OPERAND(writemaskRegister) 653 HANDLE_OPERAND(memory) 654 HANDLE_OPTIONAL(relocation) 655 break; 656 case X86Local::RawFrmImm8: 657 // operand 1 is a 16-bit immediate 658 // operand 2 is an 8-bit immediate 659 assert(numPhysicalOperands == 2 && 660 "Unexpected number of operands for X86Local::RawFrmImm8"); 661 HANDLE_OPERAND(immediate) 662 HANDLE_OPERAND(immediate) 663 break; 664 case X86Local::RawFrmImm16: 665 // operand 1 is a 16-bit immediate 666 // operand 2 is a 16-bit immediate 667 HANDLE_OPERAND(immediate) 668 HANDLE_OPERAND(immediate) 669 break; 670 #define MAP(from, to) case X86Local::MRM_##from: 671 X86_INSTR_MRM_MAPPING 672 #undef MAP 673 HANDLE_OPTIONAL(relocation) 674 break; 675 } 676 677 #undef HANDLE_OPERAND 678 #undef HANDLE_OPTIONAL 679 } 680 681 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 682 // Special cases where the LLVM tables are not complete 683 684 #define MAP(from, to) \ 685 case X86Local::MRM_##from: 686 687 llvm::Optional<OpcodeType> opcodeType; 688 switch (OpMap) { 689 default: llvm_unreachable("Invalid map!"); 690 case X86Local::OB: opcodeType = ONEBYTE; break; 691 case X86Local::TB: opcodeType = TWOBYTE; break; 692 case X86Local::T8: opcodeType = THREEBYTE_38; break; 693 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 694 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 695 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 696 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 697 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 698 } 699 700 std::unique_ptr<ModRMFilter> filter; 701 switch (Form) { 702 default: llvm_unreachable("Invalid form!"); 703 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 704 case X86Local::RawFrm: 705 case X86Local::AddRegFrm: 706 case X86Local::RawFrmMemOffs: 707 case X86Local::RawFrmSrc: 708 case X86Local::RawFrmDst: 709 case X86Local::RawFrmDstSrc: 710 case X86Local::RawFrmImm8: 711 case X86Local::RawFrmImm16: 712 filter = llvm::make_unique<DumbFilter>(); 713 break; 714 case X86Local::MRMDestReg: 715 case X86Local::MRMSrcReg: 716 case X86Local::MRMSrcReg4VOp3: 717 case X86Local::MRMSrcRegOp4: 718 case X86Local::MRMXr: 719 filter = llvm::make_unique<ModFilter>(true); 720 break; 721 case X86Local::MRMDestMem: 722 case X86Local::MRMSrcMem: 723 case X86Local::MRMSrcMem4VOp3: 724 case X86Local::MRMSrcMemOp4: 725 case X86Local::MRMXm: 726 filter = llvm::make_unique<ModFilter>(false); 727 break; 728 case X86Local::MRM0r: case X86Local::MRM1r: 729 case X86Local::MRM2r: case X86Local::MRM3r: 730 case X86Local::MRM4r: case X86Local::MRM5r: 731 case X86Local::MRM6r: case X86Local::MRM7r: 732 filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 733 break; 734 case X86Local::MRM0m: case X86Local::MRM1m: 735 case X86Local::MRM2m: case X86Local::MRM3m: 736 case X86Local::MRM4m: case X86Local::MRM5m: 737 case X86Local::MRM6m: case X86Local::MRM7m: 738 filter = llvm::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 739 break; 740 X86_INSTR_MRM_MAPPING 741 filter = llvm::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 742 break; 743 } // switch (Form) 744 745 uint8_t opcodeToSet = Opcode; 746 747 unsigned AddressSize = 0; 748 switch (AdSize) { 749 case X86Local::AdSize16: AddressSize = 16; break; 750 case X86Local::AdSize32: AddressSize = 32; break; 751 case X86Local::AdSize64: AddressSize = 64; break; 752 } 753 754 assert(opcodeType && "Opcode type not set"); 755 assert(filter && "Filter not set"); 756 757 if (Form == X86Local::AddRegFrm) { 758 assert(((opcodeToSet & 7) == 0) && 759 "ADDREG_FRM opcode not aligned"); 760 761 uint8_t currentOpcode; 762 763 for (currentOpcode = opcodeToSet; 764 currentOpcode < opcodeToSet + 8; 765 ++currentOpcode) 766 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 767 UID, Is32Bit, OpPrefix == 0, 768 IgnoresVEX_L || EncodeRC, 769 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 770 } else { 771 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 772 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 773 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 774 } 775 776 #undef MAP 777 } 778 779 #define TYPE(str, type) if (s == str) return type; 780 OperandType RecognizableInstr::typeFromString(const std::string &s, 781 bool hasREX_WPrefix, 782 uint8_t OpSize) { 783 if(hasREX_WPrefix) { 784 // For instructions with a REX_W prefix, a declared 32-bit register encoding 785 // is special. 786 TYPE("GR32", TYPE_R32) 787 } 788 if(OpSize == X86Local::OpSize16) { 789 // For OpSize16 instructions, a declared 16-bit register or 790 // immediate encoding is special. 791 TYPE("GR16", TYPE_Rv) 792 } else if(OpSize == X86Local::OpSize32) { 793 // For OpSize32 instructions, a declared 32-bit register or 794 // immediate encoding is special. 795 TYPE("GR32", TYPE_Rv) 796 } 797 TYPE("i16mem", TYPE_M) 798 TYPE("i16imm", TYPE_IMM) 799 TYPE("i16i8imm", TYPE_IMM) 800 TYPE("GR16", TYPE_R16) 801 TYPE("i32mem", TYPE_M) 802 TYPE("i32imm", TYPE_IMM) 803 TYPE("i32i8imm", TYPE_IMM) 804 TYPE("GR32", TYPE_R32) 805 TYPE("GR32orGR64", TYPE_R32) 806 TYPE("i64mem", TYPE_M) 807 TYPE("i64i32imm", TYPE_IMM) 808 TYPE("i64i8imm", TYPE_IMM) 809 TYPE("GR64", TYPE_R64) 810 TYPE("i8mem", TYPE_M) 811 TYPE("i8imm", TYPE_IMM) 812 TYPE("u8imm", TYPE_UIMM8) 813 TYPE("i32u8imm", TYPE_UIMM8) 814 TYPE("GR8", TYPE_R8) 815 TYPE("VR128", TYPE_XMM) 816 TYPE("VR128X", TYPE_XMM) 817 TYPE("f128mem", TYPE_M) 818 TYPE("f256mem", TYPE_M) 819 TYPE("f512mem", TYPE_M) 820 TYPE("FR128", TYPE_XMM) 821 TYPE("FR64", TYPE_XMM) 822 TYPE("FR64X", TYPE_XMM) 823 TYPE("f64mem", TYPE_M) 824 TYPE("sdmem", TYPE_M) 825 TYPE("FR32", TYPE_XMM) 826 TYPE("FR32X", TYPE_XMM) 827 TYPE("f32mem", TYPE_M) 828 TYPE("ssmem", TYPE_M) 829 TYPE("RST", TYPE_ST) 830 TYPE("i128mem", TYPE_M) 831 TYPE("i256mem", TYPE_M) 832 TYPE("i512mem", TYPE_M) 833 TYPE("i64i32imm_pcrel", TYPE_REL) 834 TYPE("i16imm_pcrel", TYPE_REL) 835 TYPE("i32imm_pcrel", TYPE_REL) 836 TYPE("SSECC", TYPE_IMM3) 837 TYPE("XOPCC", TYPE_IMM3) 838 TYPE("AVXCC", TYPE_IMM5) 839 TYPE("AVX512ICC", TYPE_AVX512ICC) 840 TYPE("AVX512RC", TYPE_IMM) 841 TYPE("brtarget32", TYPE_REL) 842 TYPE("brtarget16", TYPE_REL) 843 TYPE("brtarget8", TYPE_REL) 844 TYPE("f80mem", TYPE_M) 845 TYPE("lea64_32mem", TYPE_M) 846 TYPE("lea64mem", TYPE_M) 847 TYPE("VR64", TYPE_MM64) 848 TYPE("i64imm", TYPE_IMM) 849 TYPE("anymem", TYPE_M) 850 TYPE("opaque32mem", TYPE_M) 851 TYPE("opaque48mem", TYPE_M) 852 TYPE("opaque80mem", TYPE_M) 853 TYPE("opaque512mem", TYPE_M) 854 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 855 TYPE("DEBUG_REG", TYPE_DEBUGREG) 856 TYPE("CONTROL_REG", TYPE_CONTROLREG) 857 TYPE("srcidx8", TYPE_SRCIDX) 858 TYPE("srcidx16", TYPE_SRCIDX) 859 TYPE("srcidx32", TYPE_SRCIDX) 860 TYPE("srcidx64", TYPE_SRCIDX) 861 TYPE("dstidx8", TYPE_DSTIDX) 862 TYPE("dstidx16", TYPE_DSTIDX) 863 TYPE("dstidx32", TYPE_DSTIDX) 864 TYPE("dstidx64", TYPE_DSTIDX) 865 TYPE("offset16_8", TYPE_MOFFS) 866 TYPE("offset16_16", TYPE_MOFFS) 867 TYPE("offset16_32", TYPE_MOFFS) 868 TYPE("offset32_8", TYPE_MOFFS) 869 TYPE("offset32_16", TYPE_MOFFS) 870 TYPE("offset32_32", TYPE_MOFFS) 871 TYPE("offset32_64", TYPE_MOFFS) 872 TYPE("offset64_8", TYPE_MOFFS) 873 TYPE("offset64_16", TYPE_MOFFS) 874 TYPE("offset64_32", TYPE_MOFFS) 875 TYPE("offset64_64", TYPE_MOFFS) 876 TYPE("VR256", TYPE_YMM) 877 TYPE("VR256X", TYPE_YMM) 878 TYPE("VR512", TYPE_ZMM) 879 TYPE("VK1", TYPE_VK) 880 TYPE("VK1WM", TYPE_VK) 881 TYPE("VK2", TYPE_VK) 882 TYPE("VK2WM", TYPE_VK) 883 TYPE("VK4", TYPE_VK) 884 TYPE("VK4WM", TYPE_VK) 885 TYPE("VK8", TYPE_VK) 886 TYPE("VK8WM", TYPE_VK) 887 TYPE("VK16", TYPE_VK) 888 TYPE("VK16WM", TYPE_VK) 889 TYPE("VK32", TYPE_VK) 890 TYPE("VK32WM", TYPE_VK) 891 TYPE("VK64", TYPE_VK) 892 TYPE("VK64WM", TYPE_VK) 893 TYPE("vx64mem", TYPE_MVSIBX) 894 TYPE("vx128mem", TYPE_MVSIBX) 895 TYPE("vx256mem", TYPE_MVSIBX) 896 TYPE("vy128mem", TYPE_MVSIBY) 897 TYPE("vy256mem", TYPE_MVSIBY) 898 TYPE("vx64xmem", TYPE_MVSIBX) 899 TYPE("vx128xmem", TYPE_MVSIBX) 900 TYPE("vx256xmem", TYPE_MVSIBX) 901 TYPE("vy128xmem", TYPE_MVSIBY) 902 TYPE("vy256xmem", TYPE_MVSIBY) 903 TYPE("vy512mem", TYPE_MVSIBY) 904 TYPE("vz256xmem", TYPE_MVSIBZ) 905 TYPE("vz512mem", TYPE_MVSIBZ) 906 TYPE("BNDR", TYPE_BNDR) 907 errs() << "Unhandled type string " << s << "\n"; 908 llvm_unreachable("Unhandled type string"); 909 } 910 #undef TYPE 911 912 #define ENCODING(str, encoding) if (s == str) return encoding; 913 OperandEncoding 914 RecognizableInstr::immediateEncodingFromString(const std::string &s, 915 uint8_t OpSize) { 916 if(OpSize != X86Local::OpSize16) { 917 // For instructions without an OpSize prefix, a declared 16-bit register or 918 // immediate encoding is special. 919 ENCODING("i16imm", ENCODING_IW) 920 } 921 ENCODING("i32i8imm", ENCODING_IB) 922 ENCODING("SSECC", ENCODING_IB) 923 ENCODING("XOPCC", ENCODING_IB) 924 ENCODING("AVXCC", ENCODING_IB) 925 ENCODING("AVX512ICC", ENCODING_IB) 926 ENCODING("AVX512RC", ENCODING_IRC) 927 ENCODING("i16imm", ENCODING_Iv) 928 ENCODING("i16i8imm", ENCODING_IB) 929 ENCODING("i32imm", ENCODING_Iv) 930 ENCODING("i64i32imm", ENCODING_ID) 931 ENCODING("i64i8imm", ENCODING_IB) 932 ENCODING("i8imm", ENCODING_IB) 933 ENCODING("u8imm", ENCODING_IB) 934 ENCODING("i32u8imm", ENCODING_IB) 935 // This is not a typo. Instructions like BLENDVPD put 936 // register IDs in 8-bit immediates nowadays. 937 ENCODING("FR32", ENCODING_IB) 938 ENCODING("FR64", ENCODING_IB) 939 ENCODING("FR128", ENCODING_IB) 940 ENCODING("VR128", ENCODING_IB) 941 ENCODING("VR256", ENCODING_IB) 942 ENCODING("FR32X", ENCODING_IB) 943 ENCODING("FR64X", ENCODING_IB) 944 ENCODING("VR128X", ENCODING_IB) 945 ENCODING("VR256X", ENCODING_IB) 946 ENCODING("VR512", ENCODING_IB) 947 errs() << "Unhandled immediate encoding " << s << "\n"; 948 llvm_unreachable("Unhandled immediate encoding"); 949 } 950 951 OperandEncoding 952 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 953 uint8_t OpSize) { 954 ENCODING("RST", ENCODING_FP) 955 ENCODING("GR16", ENCODING_RM) 956 ENCODING("GR32", ENCODING_RM) 957 ENCODING("GR32orGR64", ENCODING_RM) 958 ENCODING("GR64", ENCODING_RM) 959 ENCODING("GR8", ENCODING_RM) 960 ENCODING("VR128", ENCODING_RM) 961 ENCODING("VR128X", ENCODING_RM) 962 ENCODING("FR128", ENCODING_RM) 963 ENCODING("FR64", ENCODING_RM) 964 ENCODING("FR32", ENCODING_RM) 965 ENCODING("FR64X", ENCODING_RM) 966 ENCODING("FR32X", ENCODING_RM) 967 ENCODING("VR64", ENCODING_RM) 968 ENCODING("VR256", ENCODING_RM) 969 ENCODING("VR256X", ENCODING_RM) 970 ENCODING("VR512", ENCODING_RM) 971 ENCODING("VK1", ENCODING_RM) 972 ENCODING("VK2", ENCODING_RM) 973 ENCODING("VK4", ENCODING_RM) 974 ENCODING("VK8", ENCODING_RM) 975 ENCODING("VK16", ENCODING_RM) 976 ENCODING("VK32", ENCODING_RM) 977 ENCODING("VK64", ENCODING_RM) 978 ENCODING("BNDR", ENCODING_RM) 979 errs() << "Unhandled R/M register encoding " << s << "\n"; 980 llvm_unreachable("Unhandled R/M register encoding"); 981 } 982 983 OperandEncoding 984 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 985 uint8_t OpSize) { 986 ENCODING("GR16", ENCODING_REG) 987 ENCODING("GR32", ENCODING_REG) 988 ENCODING("GR32orGR64", ENCODING_REG) 989 ENCODING("GR64", ENCODING_REG) 990 ENCODING("GR8", ENCODING_REG) 991 ENCODING("VR128", ENCODING_REG) 992 ENCODING("FR128", ENCODING_REG) 993 ENCODING("FR64", ENCODING_REG) 994 ENCODING("FR32", ENCODING_REG) 995 ENCODING("VR64", ENCODING_REG) 996 ENCODING("SEGMENT_REG", ENCODING_REG) 997 ENCODING("DEBUG_REG", ENCODING_REG) 998 ENCODING("CONTROL_REG", ENCODING_REG) 999 ENCODING("VR256", ENCODING_REG) 1000 ENCODING("VR256X", ENCODING_REG) 1001 ENCODING("VR128X", ENCODING_REG) 1002 ENCODING("FR64X", ENCODING_REG) 1003 ENCODING("FR32X", ENCODING_REG) 1004 ENCODING("VR512", ENCODING_REG) 1005 ENCODING("VK1", ENCODING_REG) 1006 ENCODING("VK2", ENCODING_REG) 1007 ENCODING("VK4", ENCODING_REG) 1008 ENCODING("VK8", ENCODING_REG) 1009 ENCODING("VK16", ENCODING_REG) 1010 ENCODING("VK32", ENCODING_REG) 1011 ENCODING("VK64", ENCODING_REG) 1012 ENCODING("VK1WM", ENCODING_REG) 1013 ENCODING("VK2WM", ENCODING_REG) 1014 ENCODING("VK4WM", ENCODING_REG) 1015 ENCODING("VK8WM", ENCODING_REG) 1016 ENCODING("VK16WM", ENCODING_REG) 1017 ENCODING("VK32WM", ENCODING_REG) 1018 ENCODING("VK64WM", ENCODING_REG) 1019 ENCODING("BNDR", ENCODING_REG) 1020 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1021 llvm_unreachable("Unhandled reg/opcode register encoding"); 1022 } 1023 1024 OperandEncoding 1025 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1026 uint8_t OpSize) { 1027 ENCODING("GR32", ENCODING_VVVV) 1028 ENCODING("GR64", ENCODING_VVVV) 1029 ENCODING("FR32", ENCODING_VVVV) 1030 ENCODING("FR128", ENCODING_VVVV) 1031 ENCODING("FR64", ENCODING_VVVV) 1032 ENCODING("VR128", ENCODING_VVVV) 1033 ENCODING("VR256", ENCODING_VVVV) 1034 ENCODING("FR32X", ENCODING_VVVV) 1035 ENCODING("FR64X", ENCODING_VVVV) 1036 ENCODING("VR128X", ENCODING_VVVV) 1037 ENCODING("VR256X", ENCODING_VVVV) 1038 ENCODING("VR512", ENCODING_VVVV) 1039 ENCODING("VK1", ENCODING_VVVV) 1040 ENCODING("VK2", ENCODING_VVVV) 1041 ENCODING("VK4", ENCODING_VVVV) 1042 ENCODING("VK8", ENCODING_VVVV) 1043 ENCODING("VK16", ENCODING_VVVV) 1044 ENCODING("VK32", ENCODING_VVVV) 1045 ENCODING("VK64", ENCODING_VVVV) 1046 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1047 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1048 } 1049 1050 OperandEncoding 1051 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1052 uint8_t OpSize) { 1053 ENCODING("VK1WM", ENCODING_WRITEMASK) 1054 ENCODING("VK2WM", ENCODING_WRITEMASK) 1055 ENCODING("VK4WM", ENCODING_WRITEMASK) 1056 ENCODING("VK8WM", ENCODING_WRITEMASK) 1057 ENCODING("VK16WM", ENCODING_WRITEMASK) 1058 ENCODING("VK32WM", ENCODING_WRITEMASK) 1059 ENCODING("VK64WM", ENCODING_WRITEMASK) 1060 errs() << "Unhandled mask register encoding " << s << "\n"; 1061 llvm_unreachable("Unhandled mask register encoding"); 1062 } 1063 1064 OperandEncoding 1065 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1066 uint8_t OpSize) { 1067 ENCODING("i16mem", ENCODING_RM) 1068 ENCODING("i32mem", ENCODING_RM) 1069 ENCODING("i64mem", ENCODING_RM) 1070 ENCODING("i8mem", ENCODING_RM) 1071 ENCODING("ssmem", ENCODING_RM) 1072 ENCODING("sdmem", ENCODING_RM) 1073 ENCODING("f128mem", ENCODING_RM) 1074 ENCODING("f256mem", ENCODING_RM) 1075 ENCODING("f512mem", ENCODING_RM) 1076 ENCODING("f64mem", ENCODING_RM) 1077 ENCODING("f32mem", ENCODING_RM) 1078 ENCODING("i128mem", ENCODING_RM) 1079 ENCODING("i256mem", ENCODING_RM) 1080 ENCODING("i512mem", ENCODING_RM) 1081 ENCODING("f80mem", ENCODING_RM) 1082 ENCODING("lea64_32mem", ENCODING_RM) 1083 ENCODING("lea64mem", ENCODING_RM) 1084 ENCODING("anymem", ENCODING_RM) 1085 ENCODING("opaque32mem", ENCODING_RM) 1086 ENCODING("opaque48mem", ENCODING_RM) 1087 ENCODING("opaque80mem", ENCODING_RM) 1088 ENCODING("opaque512mem", ENCODING_RM) 1089 ENCODING("vx64mem", ENCODING_VSIB) 1090 ENCODING("vx128mem", ENCODING_VSIB) 1091 ENCODING("vx256mem", ENCODING_VSIB) 1092 ENCODING("vy128mem", ENCODING_VSIB) 1093 ENCODING("vy256mem", ENCODING_VSIB) 1094 ENCODING("vx64xmem", ENCODING_VSIB) 1095 ENCODING("vx128xmem", ENCODING_VSIB) 1096 ENCODING("vx256xmem", ENCODING_VSIB) 1097 ENCODING("vy128xmem", ENCODING_VSIB) 1098 ENCODING("vy256xmem", ENCODING_VSIB) 1099 ENCODING("vy512mem", ENCODING_VSIB) 1100 ENCODING("vz256xmem", ENCODING_VSIB) 1101 ENCODING("vz512mem", ENCODING_VSIB) 1102 errs() << "Unhandled memory encoding " << s << "\n"; 1103 llvm_unreachable("Unhandled memory encoding"); 1104 } 1105 1106 OperandEncoding 1107 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1108 uint8_t OpSize) { 1109 if(OpSize != X86Local::OpSize16) { 1110 // For instructions without an OpSize prefix, a declared 16-bit register or 1111 // immediate encoding is special. 1112 ENCODING("i16imm", ENCODING_IW) 1113 } 1114 ENCODING("i16imm", ENCODING_Iv) 1115 ENCODING("i16i8imm", ENCODING_IB) 1116 ENCODING("i32imm", ENCODING_Iv) 1117 ENCODING("i32i8imm", ENCODING_IB) 1118 ENCODING("i64i32imm", ENCODING_ID) 1119 ENCODING("i64i8imm", ENCODING_IB) 1120 ENCODING("i8imm", ENCODING_IB) 1121 ENCODING("u8imm", ENCODING_IB) 1122 ENCODING("i32u8imm", ENCODING_IB) 1123 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1124 ENCODING("i16imm_pcrel", ENCODING_IW) 1125 ENCODING("i32imm_pcrel", ENCODING_ID) 1126 ENCODING("brtarget32", ENCODING_Iv) 1127 ENCODING("brtarget16", ENCODING_Iv) 1128 ENCODING("brtarget8", ENCODING_IB) 1129 ENCODING("i64imm", ENCODING_IO) 1130 ENCODING("offset16_8", ENCODING_Ia) 1131 ENCODING("offset16_16", ENCODING_Ia) 1132 ENCODING("offset16_32", ENCODING_Ia) 1133 ENCODING("offset32_8", ENCODING_Ia) 1134 ENCODING("offset32_16", ENCODING_Ia) 1135 ENCODING("offset32_32", ENCODING_Ia) 1136 ENCODING("offset32_64", ENCODING_Ia) 1137 ENCODING("offset64_8", ENCODING_Ia) 1138 ENCODING("offset64_16", ENCODING_Ia) 1139 ENCODING("offset64_32", ENCODING_Ia) 1140 ENCODING("offset64_64", ENCODING_Ia) 1141 ENCODING("srcidx8", ENCODING_SI) 1142 ENCODING("srcidx16", ENCODING_SI) 1143 ENCODING("srcidx32", ENCODING_SI) 1144 ENCODING("srcidx64", ENCODING_SI) 1145 ENCODING("dstidx8", ENCODING_DI) 1146 ENCODING("dstidx16", ENCODING_DI) 1147 ENCODING("dstidx32", ENCODING_DI) 1148 ENCODING("dstidx64", ENCODING_DI) 1149 errs() << "Unhandled relocation encoding " << s << "\n"; 1150 llvm_unreachable("Unhandled relocation encoding"); 1151 } 1152 1153 OperandEncoding 1154 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1155 uint8_t OpSize) { 1156 ENCODING("GR32", ENCODING_Rv) 1157 ENCODING("GR64", ENCODING_RO) 1158 ENCODING("GR16", ENCODING_Rv) 1159 ENCODING("GR8", ENCODING_RB) 1160 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1161 llvm_unreachable("Unhandled opcode modifier encoding"); 1162 } 1163 #undef ENCODING 1164