1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) { 28 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 29 StringRef Mnemonic(AsmString); 30 // Extract a mnemonic assuming it's separated by \t 31 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 32 33 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 34 // Replace it with "CC" in-place. 35 size_t CondPos = Mnemonic.find("${cond}"); 36 if (CondPos != StringRef::npos) 37 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 38 return Mnemonic.upper(); 39 } 40 41 bool X86Disassembler::isRegisterOperand(const Record *Rec) { 42 return Rec->isSubClassOf("RegisterClass") || 43 Rec->isSubClassOf("RegisterOperand"); 44 } 45 46 bool X86Disassembler::isMemoryOperand(const Record *Rec) { 47 return Rec->isSubClassOf("Operand") && 48 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY"; 49 } 50 51 bool X86Disassembler::isImmediateOperand(const Record *Rec) { 52 return Rec->isSubClassOf("Operand") && 53 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE"; 54 } 55 56 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) { 57 if (RegRec->isSubClassOf("RegisterClass")) 58 return RegRec->getValueAsInt("Alignment"); 59 if (RegRec->isSubClassOf("RegisterOperand")) 60 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment"); 61 62 llvm_unreachable("Register operand's size not known!"); 63 } 64 65 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) { 66 if (MemRec->isSubClassOf("Operand")) { 67 StringRef Name = 68 MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name"); 69 if (Name == "Mem8") 70 return 8; 71 if (Name == "Mem16") 72 return 16; 73 if (Name == "Mem32") 74 return 32; 75 if (Name == "Mem64") 76 return 64; 77 if (Name == "Mem80") 78 return 80; 79 if (Name == "Mem128") 80 return 128; 81 if (Name == "Mem256") 82 return 256; 83 if (Name == "Mem512") 84 return 512; 85 } 86 87 llvm_unreachable("Memory operand's size not known!"); 88 } 89 90 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 91 /// Useful for switch statements and the like. 92 /// 93 /// @param init - A reference to the BitsInit to be decoded. 94 /// @return - The field, with the first bit in the BitsInit as the lowest 95 /// order bit. 96 static uint8_t byteFromBitsInit(BitsInit &init) { 97 int width = init.getNumBits(); 98 99 assert(width <= 8 && "Field is too large for uint8_t!"); 100 101 int index; 102 uint8_t mask = 0x01; 103 104 uint8_t ret = 0; 105 106 for (index = 0; index < width; index++) { 107 if (cast<BitInit>(init.getBit(index))->getValue()) 108 ret |= mask; 109 110 mask <<= 1; 111 } 112 113 return ret; 114 } 115 116 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 117 /// name of the field. 118 /// 119 /// @param rec - The record from which to extract the value. 120 /// @param name - The name of the field in the record. 121 /// @return - The field, as translated by byteFromBitsInit(). 122 static uint8_t byteFromRec(const Record* rec, StringRef name) { 123 BitsInit* bits = rec->getValueAsBitsInit(name); 124 return byteFromBitsInit(*bits); 125 } 126 127 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) { 128 const Record *Rec = insn.TheDef; 129 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction"); 130 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 131 OpMap = byteFromRec(Rec, "OpMapBits"); 132 Opcode = byteFromRec(Rec, "Opcode"); 133 Form = byteFromRec(Rec, "FormBits"); 134 Encoding = byteFromRec(Rec, "OpEncBits"); 135 OpSize = byteFromRec(Rec, "OpSizeBits"); 136 AdSize = byteFromRec(Rec, "AdSizeBits"); 137 HasREX_W = Rec->getValueAsBit("hasREX_W"); 138 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 139 HasVEX_W = Rec->getValueAsBit("HasVEX_W"); 140 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); 141 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 142 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); 143 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 144 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 145 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 146 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 147 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly"); 148 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 149 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 150 HasVEX_L = Rec->getValueAsBit("hasVEX_L"); 151 152 EncodeRC = HasEVEX_B && 153 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 154 } 155 156 bool RecognizableInstrBase::shouldBeEmitted() const { 157 return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) && 158 !IsAsmParserOnly; 159 } 160 161 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 162 const CodeGenInstruction &insn, 163 InstrUID uid) 164 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()), 165 Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList), 166 UID(uid), Spec(&tables.specForUID(uid)) { 167 // Check for 64-bit inst which does not require REX 168 // FIXME: Is there some better way to check for In64BitMode? 169 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates"); 170 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 171 if (Predicates[i]->getName().contains("Not64Bit") || 172 Predicates[i]->getName().contains("In32Bit")) { 173 Is32Bit = true; 174 break; 175 } 176 if (Predicates[i]->getName().contains("In64Bit")) { 177 Is64Bit = true; 178 break; 179 } 180 } 181 } 182 183 void RecognizableInstr::processInstr(DisassemblerTables &tables, 184 const CodeGenInstruction &insn, 185 InstrUID uid) { 186 if (!insn.TheDef->isSubClassOf("X86Inst")) 187 return; 188 RecognizableInstr recogInstr(tables, insn, uid); 189 190 if (!recogInstr.shouldBeEmitted()) 191 return; 192 recogInstr.emitInstructionSpecifier(); 193 recogInstr.emitDecodePath(tables); 194 } 195 196 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 197 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 198 (HasEVEX_KZ ? n##_KZ : \ 199 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 200 201 InstructionContext RecognizableInstr::insnContext() const { 202 InstructionContext insnContext; 203 204 if (Encoding == X86Local::EVEX) { 205 if (HasVEX_L && HasEVEX_L2) { 206 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 207 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 208 } 209 // VEX_L & VEX_W 210 if (!EncodeRC && HasVEX_L && HasVEX_W) { 211 if (OpPrefix == X86Local::PD) 212 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 213 else if (OpPrefix == X86Local::XS) 214 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 215 else if (OpPrefix == X86Local::XD) 216 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 217 else if (OpPrefix == X86Local::PS) 218 insnContext = EVEX_KB(IC_EVEX_L_W); 219 else { 220 errs() << "Instruction does not use a prefix: " << Name << "\n"; 221 llvm_unreachable("Invalid prefix"); 222 } 223 } else if (!EncodeRC && HasVEX_L) { 224 // VEX_L 225 if (OpPrefix == X86Local::PD) 226 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 227 else if (OpPrefix == X86Local::XS) 228 insnContext = EVEX_KB(IC_EVEX_L_XS); 229 else if (OpPrefix == X86Local::XD) 230 insnContext = EVEX_KB(IC_EVEX_L_XD); 231 else if (OpPrefix == X86Local::PS) 232 insnContext = EVEX_KB(IC_EVEX_L); 233 else { 234 errs() << "Instruction does not use a prefix: " << Name << "\n"; 235 llvm_unreachable("Invalid prefix"); 236 } 237 } else if (!EncodeRC && HasEVEX_L2 && HasVEX_W) { 238 // EVEX_L2 & VEX_W 239 if (OpPrefix == X86Local::PD) 240 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 241 else if (OpPrefix == X86Local::XS) 242 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 243 else if (OpPrefix == X86Local::XD) 244 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 245 else if (OpPrefix == X86Local::PS) 246 insnContext = EVEX_KB(IC_EVEX_L2_W); 247 else { 248 errs() << "Instruction does not use a prefix: " << Name << "\n"; 249 llvm_unreachable("Invalid prefix"); 250 } 251 } else if (!EncodeRC && HasEVEX_L2) { 252 // EVEX_L2 253 if (OpPrefix == X86Local::PD) 254 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 255 else if (OpPrefix == X86Local::XD) 256 insnContext = EVEX_KB(IC_EVEX_L2_XD); 257 else if (OpPrefix == X86Local::XS) 258 insnContext = EVEX_KB(IC_EVEX_L2_XS); 259 else if (OpPrefix == X86Local::PS) 260 insnContext = EVEX_KB(IC_EVEX_L2); 261 else { 262 errs() << "Instruction does not use a prefix: " << Name << "\n"; 263 llvm_unreachable("Invalid prefix"); 264 } 265 } 266 else if (HasVEX_W) { 267 // VEX_W 268 if (OpPrefix == X86Local::PD) 269 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 270 else if (OpPrefix == X86Local::XS) 271 insnContext = EVEX_KB(IC_EVEX_W_XS); 272 else if (OpPrefix == X86Local::XD) 273 insnContext = EVEX_KB(IC_EVEX_W_XD); 274 else if (OpPrefix == X86Local::PS) 275 insnContext = EVEX_KB(IC_EVEX_W); 276 else { 277 errs() << "Instruction does not use a prefix: " << Name << "\n"; 278 llvm_unreachable("Invalid prefix"); 279 } 280 } 281 // No L, no W 282 else if (OpPrefix == X86Local::PD) 283 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 284 else if (OpPrefix == X86Local::XD) 285 insnContext = EVEX_KB(IC_EVEX_XD); 286 else if (OpPrefix == X86Local::XS) 287 insnContext = EVEX_KB(IC_EVEX_XS); 288 else if (OpPrefix == X86Local::PS) 289 insnContext = EVEX_KB(IC_EVEX); 290 else { 291 errs() << "Instruction does not use a prefix: " << Name << "\n"; 292 llvm_unreachable("Invalid prefix"); 293 } 294 /// eof EVEX 295 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 296 if (HasVEX_L && HasVEX_W) { 297 if (OpPrefix == X86Local::PD) 298 insnContext = IC_VEX_L_W_OPSIZE; 299 else if (OpPrefix == X86Local::XS) 300 insnContext = IC_VEX_L_W_XS; 301 else if (OpPrefix == X86Local::XD) 302 insnContext = IC_VEX_L_W_XD; 303 else if (OpPrefix == X86Local::PS) 304 insnContext = IC_VEX_L_W; 305 else { 306 errs() << "Instruction does not use a prefix: " << Name << "\n"; 307 llvm_unreachable("Invalid prefix"); 308 } 309 } else if (OpPrefix == X86Local::PD && HasVEX_L) 310 insnContext = IC_VEX_L_OPSIZE; 311 else if (OpPrefix == X86Local::PD && HasVEX_W) 312 insnContext = IC_VEX_W_OPSIZE; 313 else if (OpPrefix == X86Local::PD && Is64Bit && 314 AdSize == X86Local::AdSize32) 315 insnContext = IC_64BIT_VEX_OPSIZE_ADSIZE; 316 else if (OpPrefix == X86Local::PD && Is64Bit) 317 insnContext = IC_64BIT_VEX_OPSIZE; 318 else if (OpPrefix == X86Local::PD) 319 insnContext = IC_VEX_OPSIZE; 320 else if (HasVEX_L && OpPrefix == X86Local::XS) 321 insnContext = IC_VEX_L_XS; 322 else if (HasVEX_L && OpPrefix == X86Local::XD) 323 insnContext = IC_VEX_L_XD; 324 else if (HasVEX_W && OpPrefix == X86Local::XS) 325 insnContext = IC_VEX_W_XS; 326 else if (HasVEX_W && OpPrefix == X86Local::XD) 327 insnContext = IC_VEX_W_XD; 328 else if (HasVEX_W && OpPrefix == X86Local::PS) 329 insnContext = IC_VEX_W; 330 else if (HasVEX_L && OpPrefix == X86Local::PS) 331 insnContext = IC_VEX_L; 332 else if (OpPrefix == X86Local::XD) 333 insnContext = IC_VEX_XD; 334 else if (OpPrefix == X86Local::XS) 335 insnContext = IC_VEX_XS; 336 else if (OpPrefix == X86Local::PS) 337 insnContext = IC_VEX; 338 else { 339 errs() << "Instruction does not use a prefix: " << Name << "\n"; 340 llvm_unreachable("Invalid prefix"); 341 } 342 } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) { 343 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 344 insnContext = IC_64BIT_REXW_OPSIZE; 345 else if (HasREX_W && AdSize == X86Local::AdSize32) 346 insnContext = IC_64BIT_REXW_ADSIZE; 347 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 348 insnContext = IC_64BIT_XD_OPSIZE; 349 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 350 insnContext = IC_64BIT_XS_OPSIZE; 351 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 352 insnContext = IC_64BIT_OPSIZE_ADSIZE; 353 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 354 insnContext = IC_64BIT_OPSIZE_ADSIZE; 355 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 356 insnContext = IC_64BIT_OPSIZE; 357 else if (AdSize == X86Local::AdSize32) 358 insnContext = IC_64BIT_ADSIZE; 359 else if (HasREX_W && OpPrefix == X86Local::XS) 360 insnContext = IC_64BIT_REXW_XS; 361 else if (HasREX_W && OpPrefix == X86Local::XD) 362 insnContext = IC_64BIT_REXW_XD; 363 else if (OpPrefix == X86Local::XD) 364 insnContext = IC_64BIT_XD; 365 else if (OpPrefix == X86Local::XS) 366 insnContext = IC_64BIT_XS; 367 else if (HasREX_W) 368 insnContext = IC_64BIT_REXW; 369 else 370 insnContext = IC_64BIT; 371 } else { 372 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 373 insnContext = IC_XD_OPSIZE; 374 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 375 insnContext = IC_XS_OPSIZE; 376 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 377 insnContext = IC_XD_ADSIZE; 378 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 379 insnContext = IC_XS_ADSIZE; 380 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 381 insnContext = IC_OPSIZE_ADSIZE; 382 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 383 insnContext = IC_OPSIZE_ADSIZE; 384 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 385 insnContext = IC_OPSIZE; 386 else if (AdSize == X86Local::AdSize16) 387 insnContext = IC_ADSIZE; 388 else if (OpPrefix == X86Local::XD) 389 insnContext = IC_XD; 390 else if (OpPrefix == X86Local::XS) 391 insnContext = IC_XS; 392 else 393 insnContext = IC; 394 } 395 396 return insnContext; 397 } 398 399 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 400 // The scaling factor for AVX512 compressed displacement encoding is an 401 // instruction attribute. Adjust the ModRM encoding type to include the 402 // scale for compressed displacement. 403 if ((encoding != ENCODING_RM && 404 encoding != ENCODING_VSIB && 405 encoding != ENCODING_SIB) ||CD8_Scale == 0) 406 return; 407 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 408 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 409 (encoding == ENCODING_SIB) || 410 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 411 "Invalid CDisp scaling"); 412 } 413 414 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 415 unsigned &physicalOperandIndex, 416 unsigned numPhysicalOperands, 417 const unsigned *operandMapping, 418 OperandEncoding (*encodingFromString) 419 (const std::string&, 420 uint8_t OpSize)) { 421 if (optional) { 422 if (physicalOperandIndex >= numPhysicalOperands) 423 return; 424 } else { 425 assert(physicalOperandIndex < numPhysicalOperands); 426 } 427 428 while (operandMapping[operandIndex] != operandIndex) { 429 Spec->operands[operandIndex].encoding = ENCODING_DUP; 430 Spec->operands[operandIndex].type = 431 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 432 ++operandIndex; 433 } 434 435 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 436 437 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 438 // Adjust the encoding type for an operand based on the instruction. 439 adjustOperandEncoding(encoding); 440 Spec->operands[operandIndex].encoding = encoding; 441 Spec->operands[operandIndex].type = 442 typeFromString(std::string(typeName), HasREX_W, OpSize); 443 444 ++operandIndex; 445 ++physicalOperandIndex; 446 } 447 448 void RecognizableInstr::emitInstructionSpecifier() { 449 Spec->name = Name; 450 451 Spec->insnContext = insnContext(); 452 453 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 454 455 unsigned numOperands = OperandList.size(); 456 unsigned numPhysicalOperands = 0; 457 458 // operandMapping maps from operands in OperandList to their originals. 459 // If operandMapping[i] != i, then the entry is a duplicate. 460 unsigned operandMapping[X86_MAX_OPERANDS]; 461 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 462 463 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 464 if (!OperandList[operandIndex].Constraints.empty()) { 465 const CGIOperandList::ConstraintInfo &Constraint = 466 OperandList[operandIndex].Constraints[0]; 467 if (Constraint.isTied()) { 468 operandMapping[operandIndex] = operandIndex; 469 operandMapping[Constraint.getTiedOperand()] = operandIndex; 470 } else { 471 ++numPhysicalOperands; 472 operandMapping[operandIndex] = operandIndex; 473 } 474 } else { 475 ++numPhysicalOperands; 476 operandMapping[operandIndex] = operandIndex; 477 } 478 } 479 480 #define HANDLE_OPERAND(class) \ 481 handleOperand(false, \ 482 operandIndex, \ 483 physicalOperandIndex, \ 484 numPhysicalOperands, \ 485 operandMapping, \ 486 class##EncodingFromString); 487 488 #define HANDLE_OPTIONAL(class) \ 489 handleOperand(true, \ 490 operandIndex, \ 491 physicalOperandIndex, \ 492 numPhysicalOperands, \ 493 operandMapping, \ 494 class##EncodingFromString); 495 496 // operandIndex should always be < numOperands 497 unsigned operandIndex = 0; 498 // physicalOperandIndex should always be < numPhysicalOperands 499 unsigned physicalOperandIndex = 0; 500 501 #ifndef NDEBUG 502 // Given the set of prefix bits, how many additional operands does the 503 // instruction have? 504 unsigned additionalOperands = 0; 505 if (HasVEX_4V) 506 ++additionalOperands; 507 if (HasEVEX_K) 508 ++additionalOperands; 509 #endif 510 511 switch (Form) { 512 default: llvm_unreachable("Unhandled form"); 513 case X86Local::PrefixByte: 514 return; 515 case X86Local::RawFrmSrc: 516 HANDLE_OPERAND(relocation); 517 return; 518 case X86Local::RawFrmDst: 519 HANDLE_OPERAND(relocation); 520 return; 521 case X86Local::RawFrmDstSrc: 522 HANDLE_OPERAND(relocation); 523 HANDLE_OPERAND(relocation); 524 return; 525 case X86Local::RawFrm: 526 // Operand 1 (optional) is an address or immediate. 527 assert(numPhysicalOperands <= 1 && 528 "Unexpected number of operands for RawFrm"); 529 HANDLE_OPTIONAL(relocation) 530 break; 531 case X86Local::RawFrmMemOffs: 532 // Operand 1 is an address. 533 HANDLE_OPERAND(relocation); 534 break; 535 case X86Local::AddRegFrm: 536 // Operand 1 is added to the opcode. 537 // Operand 2 (optional) is an address. 538 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 539 "Unexpected number of operands for AddRegFrm"); 540 HANDLE_OPERAND(opcodeModifier) 541 HANDLE_OPTIONAL(relocation) 542 break; 543 case X86Local::AddCCFrm: 544 // Operand 1 (optional) is an address or immediate. 545 assert(numPhysicalOperands == 2 && 546 "Unexpected number of operands for AddCCFrm"); 547 HANDLE_OPERAND(relocation) 548 HANDLE_OPERAND(opcodeModifier) 549 break; 550 case X86Local::MRMDestReg: 551 // Operand 1 is a register operand in the R/M field. 552 // - In AVX512 there may be a mask operand here - 553 // Operand 2 is a register operand in the Reg/Opcode field. 554 // - In AVX, there is a register operand in the VEX.vvvv field here - 555 // Operand 3 (optional) is an immediate. 556 assert(numPhysicalOperands >= 2 + additionalOperands && 557 numPhysicalOperands <= 3 + additionalOperands && 558 "Unexpected number of operands for MRMDestRegFrm"); 559 560 HANDLE_OPERAND(rmRegister) 561 if (HasEVEX_K) 562 HANDLE_OPERAND(writemaskRegister) 563 564 if (HasVEX_4V) 565 // FIXME: In AVX, the register below becomes the one encoded 566 // in ModRMVEX and the one above the one in the VEX.VVVV field 567 HANDLE_OPERAND(vvvvRegister) 568 569 HANDLE_OPERAND(roRegister) 570 HANDLE_OPTIONAL(immediate) 571 break; 572 case X86Local::MRMDestMem: 573 case X86Local::MRMDestMemFSIB: 574 // Operand 1 is a memory operand (possibly SIB-extended) 575 // Operand 2 is a register operand in the Reg/Opcode field. 576 // - In AVX, there is a register operand in the VEX.vvvv field here - 577 // Operand 3 (optional) is an immediate. 578 assert(numPhysicalOperands >= 2 + additionalOperands && 579 numPhysicalOperands <= 3 + additionalOperands && 580 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 581 582 HANDLE_OPERAND(memory) 583 584 if (HasEVEX_K) 585 HANDLE_OPERAND(writemaskRegister) 586 587 if (HasVEX_4V) 588 // FIXME: In AVX, the register below becomes the one encoded 589 // in ModRMVEX and the one above the one in the VEX.VVVV field 590 HANDLE_OPERAND(vvvvRegister) 591 592 HANDLE_OPERAND(roRegister) 593 HANDLE_OPTIONAL(immediate) 594 break; 595 case X86Local::MRMSrcReg: 596 // Operand 1 is a register operand in the Reg/Opcode field. 597 // Operand 2 is a register operand in the R/M field. 598 // - In AVX, there is a register operand in the VEX.vvvv field here - 599 // Operand 3 (optional) is an immediate. 600 // Operand 4 (optional) is an immediate. 601 602 assert(numPhysicalOperands >= 2 + additionalOperands && 603 numPhysicalOperands <= 4 + additionalOperands && 604 "Unexpected number of operands for MRMSrcRegFrm"); 605 606 HANDLE_OPERAND(roRegister) 607 608 if (HasEVEX_K) 609 HANDLE_OPERAND(writemaskRegister) 610 611 if (HasVEX_4V) 612 // FIXME: In AVX, the register below becomes the one encoded 613 // in ModRMVEX and the one above the one in the VEX.VVVV field 614 HANDLE_OPERAND(vvvvRegister) 615 616 HANDLE_OPERAND(rmRegister) 617 HANDLE_OPTIONAL(immediate) 618 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 619 break; 620 case X86Local::MRMSrcReg4VOp3: 621 assert(numPhysicalOperands == 3 && 622 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 623 HANDLE_OPERAND(roRegister) 624 HANDLE_OPERAND(rmRegister) 625 HANDLE_OPERAND(vvvvRegister) 626 break; 627 case X86Local::MRMSrcRegOp4: 628 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 629 "Unexpected number of operands for MRMSrcRegOp4Frm"); 630 HANDLE_OPERAND(roRegister) 631 HANDLE_OPERAND(vvvvRegister) 632 HANDLE_OPERAND(immediate) // Register in imm[7:4] 633 HANDLE_OPERAND(rmRegister) 634 HANDLE_OPTIONAL(immediate) 635 break; 636 case X86Local::MRMSrcRegCC: 637 assert(numPhysicalOperands == 3 && 638 "Unexpected number of operands for MRMSrcRegCC"); 639 HANDLE_OPERAND(roRegister) 640 HANDLE_OPERAND(rmRegister) 641 HANDLE_OPERAND(opcodeModifier) 642 break; 643 case X86Local::MRMSrcMem: 644 case X86Local::MRMSrcMemFSIB: 645 // Operand 1 is a register operand in the Reg/Opcode field. 646 // Operand 2 is a memory operand (possibly SIB-extended) 647 // - In AVX, there is a register operand in the VEX.vvvv field here - 648 // Operand 3 (optional) is an immediate. 649 650 assert(numPhysicalOperands >= 2 + additionalOperands && 651 numPhysicalOperands <= 4 + additionalOperands && 652 "Unexpected number of operands for MRMSrcMemFrm"); 653 654 HANDLE_OPERAND(roRegister) 655 656 if (HasEVEX_K) 657 HANDLE_OPERAND(writemaskRegister) 658 659 if (HasVEX_4V) 660 // FIXME: In AVX, the register below becomes the one encoded 661 // in ModRMVEX and the one above the one in the VEX.VVVV field 662 HANDLE_OPERAND(vvvvRegister) 663 664 HANDLE_OPERAND(memory) 665 HANDLE_OPTIONAL(immediate) 666 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 667 break; 668 case X86Local::MRMSrcMem4VOp3: 669 assert(numPhysicalOperands == 3 && 670 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 671 HANDLE_OPERAND(roRegister) 672 HANDLE_OPERAND(memory) 673 HANDLE_OPERAND(vvvvRegister) 674 break; 675 case X86Local::MRMSrcMemOp4: 676 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 677 "Unexpected number of operands for MRMSrcMemOp4Frm"); 678 HANDLE_OPERAND(roRegister) 679 HANDLE_OPERAND(vvvvRegister) 680 HANDLE_OPERAND(immediate) // Register in imm[7:4] 681 HANDLE_OPERAND(memory) 682 HANDLE_OPTIONAL(immediate) 683 break; 684 case X86Local::MRMSrcMemCC: 685 assert(numPhysicalOperands == 3 && 686 "Unexpected number of operands for MRMSrcMemCC"); 687 HANDLE_OPERAND(roRegister) 688 HANDLE_OPERAND(memory) 689 HANDLE_OPERAND(opcodeModifier) 690 break; 691 case X86Local::MRMXrCC: 692 assert(numPhysicalOperands == 2 && 693 "Unexpected number of operands for MRMXrCC"); 694 HANDLE_OPERAND(rmRegister) 695 HANDLE_OPERAND(opcodeModifier) 696 break; 697 case X86Local::MRMr0: 698 // Operand 1 is a register operand in the R/M field. 699 HANDLE_OPERAND(roRegister) 700 break; 701 case X86Local::MRMXr: 702 case X86Local::MRM0r: 703 case X86Local::MRM1r: 704 case X86Local::MRM2r: 705 case X86Local::MRM3r: 706 case X86Local::MRM4r: 707 case X86Local::MRM5r: 708 case X86Local::MRM6r: 709 case X86Local::MRM7r: 710 // Operand 1 is a register operand in the R/M field. 711 // Operand 2 (optional) is an immediate or relocation. 712 // Operand 3 (optional) is an immediate. 713 assert(numPhysicalOperands >= 0 + additionalOperands && 714 numPhysicalOperands <= 3 + additionalOperands && 715 "Unexpected number of operands for MRMnr"); 716 717 if (HasVEX_4V) 718 HANDLE_OPERAND(vvvvRegister) 719 720 if (HasEVEX_K) 721 HANDLE_OPERAND(writemaskRegister) 722 HANDLE_OPTIONAL(rmRegister) 723 HANDLE_OPTIONAL(relocation) 724 HANDLE_OPTIONAL(immediate) 725 break; 726 case X86Local::MRMXmCC: 727 assert(numPhysicalOperands == 2 && 728 "Unexpected number of operands for MRMXm"); 729 HANDLE_OPERAND(memory) 730 HANDLE_OPERAND(opcodeModifier) 731 break; 732 case X86Local::MRMXm: 733 case X86Local::MRM0m: 734 case X86Local::MRM1m: 735 case X86Local::MRM2m: 736 case X86Local::MRM3m: 737 case X86Local::MRM4m: 738 case X86Local::MRM5m: 739 case X86Local::MRM6m: 740 case X86Local::MRM7m: 741 // Operand 1 is a memory operand (possibly SIB-extended) 742 // Operand 2 (optional) is an immediate or relocation. 743 assert(numPhysicalOperands >= 1 + additionalOperands && 744 numPhysicalOperands <= 2 + additionalOperands && 745 "Unexpected number of operands for MRMnm"); 746 747 if (HasVEX_4V) 748 HANDLE_OPERAND(vvvvRegister) 749 if (HasEVEX_K) 750 HANDLE_OPERAND(writemaskRegister) 751 HANDLE_OPERAND(memory) 752 HANDLE_OPTIONAL(relocation) 753 break; 754 case X86Local::RawFrmImm8: 755 // operand 1 is a 16-bit immediate 756 // operand 2 is an 8-bit immediate 757 assert(numPhysicalOperands == 2 && 758 "Unexpected number of operands for X86Local::RawFrmImm8"); 759 HANDLE_OPERAND(immediate) 760 HANDLE_OPERAND(immediate) 761 break; 762 case X86Local::RawFrmImm16: 763 // operand 1 is a 16-bit immediate 764 // operand 2 is a 16-bit immediate 765 HANDLE_OPERAND(immediate) 766 HANDLE_OPERAND(immediate) 767 break; 768 case X86Local::MRM0X: 769 case X86Local::MRM1X: 770 case X86Local::MRM2X: 771 case X86Local::MRM3X: 772 case X86Local::MRM4X: 773 case X86Local::MRM5X: 774 case X86Local::MRM6X: 775 case X86Local::MRM7X: 776 #define MAP(from, to) case X86Local::MRM_##from: 777 X86_INSTR_MRM_MAPPING 778 #undef MAP 779 HANDLE_OPTIONAL(relocation) 780 break; 781 } 782 783 #undef HANDLE_OPERAND 784 #undef HANDLE_OPTIONAL 785 } 786 787 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 788 // Special cases where the LLVM tables are not complete 789 790 #define MAP(from, to) \ 791 case X86Local::MRM_##from: 792 793 llvm::Optional<OpcodeType> opcodeType; 794 switch (OpMap) { 795 default: llvm_unreachable("Invalid map!"); 796 case X86Local::OB: opcodeType = ONEBYTE; break; 797 case X86Local::TB: opcodeType = TWOBYTE; break; 798 case X86Local::T8: opcodeType = THREEBYTE_38; break; 799 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 800 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 801 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 802 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 803 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 804 case X86Local::T_MAP5: opcodeType = MAP5; break; 805 case X86Local::T_MAP6: opcodeType = MAP6; break; 806 } 807 808 std::unique_ptr<ModRMFilter> filter; 809 switch (Form) { 810 default: llvm_unreachable("Invalid form!"); 811 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 812 case X86Local::RawFrm: 813 case X86Local::AddRegFrm: 814 case X86Local::RawFrmMemOffs: 815 case X86Local::RawFrmSrc: 816 case X86Local::RawFrmDst: 817 case X86Local::RawFrmDstSrc: 818 case X86Local::RawFrmImm8: 819 case X86Local::RawFrmImm16: 820 case X86Local::AddCCFrm: 821 case X86Local::PrefixByte: 822 filter = std::make_unique<DumbFilter>(); 823 break; 824 case X86Local::MRMDestReg: 825 case X86Local::MRMSrcReg: 826 case X86Local::MRMSrcReg4VOp3: 827 case X86Local::MRMSrcRegOp4: 828 case X86Local::MRMSrcRegCC: 829 case X86Local::MRMXrCC: 830 case X86Local::MRMXr: 831 filter = std::make_unique<ModFilter>(true); 832 break; 833 case X86Local::MRMDestMem: 834 case X86Local::MRMDestMemFSIB: 835 case X86Local::MRMSrcMem: 836 case X86Local::MRMSrcMemFSIB: 837 case X86Local::MRMSrcMem4VOp3: 838 case X86Local::MRMSrcMemOp4: 839 case X86Local::MRMSrcMemCC: 840 case X86Local::MRMXmCC: 841 case X86Local::MRMXm: 842 filter = std::make_unique<ModFilter>(false); 843 break; 844 case X86Local::MRM0r: case X86Local::MRM1r: 845 case X86Local::MRM2r: case X86Local::MRM3r: 846 case X86Local::MRM4r: case X86Local::MRM5r: 847 case X86Local::MRM6r: case X86Local::MRM7r: 848 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 849 break; 850 case X86Local::MRM0X: case X86Local::MRM1X: 851 case X86Local::MRM2X: case X86Local::MRM3X: 852 case X86Local::MRM4X: case X86Local::MRM5X: 853 case X86Local::MRM6X: case X86Local::MRM7X: 854 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 855 break; 856 case X86Local::MRMr0: 857 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 858 break; 859 case X86Local::MRM0m: case X86Local::MRM1m: 860 case X86Local::MRM2m: case X86Local::MRM3m: 861 case X86Local::MRM4m: case X86Local::MRM5m: 862 case X86Local::MRM6m: case X86Local::MRM7m: 863 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 864 break; 865 X86_INSTR_MRM_MAPPING 866 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 867 break; 868 } // switch (Form) 869 870 uint8_t opcodeToSet = Opcode; 871 872 unsigned AddressSize = 0; 873 switch (AdSize) { 874 case X86Local::AdSize16: AddressSize = 16; break; 875 case X86Local::AdSize32: AddressSize = 32; break; 876 case X86Local::AdSize64: AddressSize = 64; break; 877 } 878 879 assert(opcodeType && "Opcode type not set"); 880 assert(filter && "Filter not set"); 881 882 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 883 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 884 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { 885 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 886 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 887 888 uint8_t currentOpcode; 889 890 for (currentOpcode = opcodeToSet; 891 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 892 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 893 UID, Is32Bit, OpPrefix == 0, 894 IgnoresVEX_L || EncodeRC, 895 IgnoresVEX_W, AddressSize); 896 } else { 897 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 898 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 899 IgnoresVEX_W, AddressSize); 900 } 901 902 #undef MAP 903 } 904 905 #define TYPE(str, type) if (s == str) return type; 906 OperandType RecognizableInstr::typeFromString(const std::string &s, 907 bool hasREX_W, 908 uint8_t OpSize) { 909 if(hasREX_W) { 910 // For instructions with a REX_W prefix, a declared 32-bit register encoding 911 // is special. 912 TYPE("GR32", TYPE_R32) 913 } 914 if(OpSize == X86Local::OpSize16) { 915 // For OpSize16 instructions, a declared 16-bit register or 916 // immediate encoding is special. 917 TYPE("GR16", TYPE_Rv) 918 } else if(OpSize == X86Local::OpSize32) { 919 // For OpSize32 instructions, a declared 32-bit register or 920 // immediate encoding is special. 921 TYPE("GR32", TYPE_Rv) 922 } 923 TYPE("i16mem", TYPE_M) 924 TYPE("i16imm", TYPE_IMM) 925 TYPE("i16i8imm", TYPE_IMM) 926 TYPE("GR16", TYPE_R16) 927 TYPE("GR16orGR32orGR64", TYPE_R16) 928 TYPE("i32mem", TYPE_M) 929 TYPE("i32imm", TYPE_IMM) 930 TYPE("i32i8imm", TYPE_IMM) 931 TYPE("GR32", TYPE_R32) 932 TYPE("GR32orGR64", TYPE_R32) 933 TYPE("i64mem", TYPE_M) 934 TYPE("i64i32imm", TYPE_IMM) 935 TYPE("i64i8imm", TYPE_IMM) 936 TYPE("GR64", TYPE_R64) 937 TYPE("i8mem", TYPE_M) 938 TYPE("i8imm", TYPE_IMM) 939 TYPE("u4imm", TYPE_UIMM8) 940 TYPE("u8imm", TYPE_UIMM8) 941 TYPE("i16u8imm", TYPE_UIMM8) 942 TYPE("i32u8imm", TYPE_UIMM8) 943 TYPE("i64u8imm", TYPE_UIMM8) 944 TYPE("GR8", TYPE_R8) 945 TYPE("VR128", TYPE_XMM) 946 TYPE("VR128X", TYPE_XMM) 947 TYPE("f128mem", TYPE_M) 948 TYPE("f256mem", TYPE_M) 949 TYPE("f512mem", TYPE_M) 950 TYPE("FR128", TYPE_XMM) 951 TYPE("FR64", TYPE_XMM) 952 TYPE("FR64X", TYPE_XMM) 953 TYPE("f64mem", TYPE_M) 954 TYPE("sdmem", TYPE_M) 955 TYPE("FR16X", TYPE_XMM) 956 TYPE("FR32", TYPE_XMM) 957 TYPE("FR32X", TYPE_XMM) 958 TYPE("f32mem", TYPE_M) 959 TYPE("f16mem", TYPE_M) 960 TYPE("ssmem", TYPE_M) 961 TYPE("shmem", TYPE_M) 962 TYPE("RST", TYPE_ST) 963 TYPE("RSTi", TYPE_ST) 964 TYPE("i128mem", TYPE_M) 965 TYPE("i256mem", TYPE_M) 966 TYPE("i512mem", TYPE_M) 967 TYPE("i64i32imm_brtarget", TYPE_REL) 968 TYPE("i16imm_brtarget", TYPE_REL) 969 TYPE("i32imm_brtarget", TYPE_REL) 970 TYPE("ccode", TYPE_IMM) 971 TYPE("AVX512RC", TYPE_IMM) 972 TYPE("brtarget32", TYPE_REL) 973 TYPE("brtarget16", TYPE_REL) 974 TYPE("brtarget8", TYPE_REL) 975 TYPE("f80mem", TYPE_M) 976 TYPE("lea64_32mem", TYPE_M) 977 TYPE("lea64mem", TYPE_M) 978 TYPE("VR64", TYPE_MM64) 979 TYPE("i64imm", TYPE_IMM) 980 TYPE("anymem", TYPE_M) 981 TYPE("opaquemem", TYPE_M) 982 TYPE("sibmem", TYPE_MSIB) 983 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 984 TYPE("DEBUG_REG", TYPE_DEBUGREG) 985 TYPE("CONTROL_REG", TYPE_CONTROLREG) 986 TYPE("srcidx8", TYPE_SRCIDX) 987 TYPE("srcidx16", TYPE_SRCIDX) 988 TYPE("srcidx32", TYPE_SRCIDX) 989 TYPE("srcidx64", TYPE_SRCIDX) 990 TYPE("dstidx8", TYPE_DSTIDX) 991 TYPE("dstidx16", TYPE_DSTIDX) 992 TYPE("dstidx32", TYPE_DSTIDX) 993 TYPE("dstidx64", TYPE_DSTIDX) 994 TYPE("offset16_8", TYPE_MOFFS) 995 TYPE("offset16_16", TYPE_MOFFS) 996 TYPE("offset16_32", TYPE_MOFFS) 997 TYPE("offset32_8", TYPE_MOFFS) 998 TYPE("offset32_16", TYPE_MOFFS) 999 TYPE("offset32_32", TYPE_MOFFS) 1000 TYPE("offset32_64", TYPE_MOFFS) 1001 TYPE("offset64_8", TYPE_MOFFS) 1002 TYPE("offset64_16", TYPE_MOFFS) 1003 TYPE("offset64_32", TYPE_MOFFS) 1004 TYPE("offset64_64", TYPE_MOFFS) 1005 TYPE("VR256", TYPE_YMM) 1006 TYPE("VR256X", TYPE_YMM) 1007 TYPE("VR512", TYPE_ZMM) 1008 TYPE("VK1", TYPE_VK) 1009 TYPE("VK1WM", TYPE_VK) 1010 TYPE("VK2", TYPE_VK) 1011 TYPE("VK2WM", TYPE_VK) 1012 TYPE("VK4", TYPE_VK) 1013 TYPE("VK4WM", TYPE_VK) 1014 TYPE("VK8", TYPE_VK) 1015 TYPE("VK8WM", TYPE_VK) 1016 TYPE("VK16", TYPE_VK) 1017 TYPE("VK16WM", TYPE_VK) 1018 TYPE("VK32", TYPE_VK) 1019 TYPE("VK32WM", TYPE_VK) 1020 TYPE("VK64", TYPE_VK) 1021 TYPE("VK64WM", TYPE_VK) 1022 TYPE("VK1Pair", TYPE_VK_PAIR) 1023 TYPE("VK2Pair", TYPE_VK_PAIR) 1024 TYPE("VK4Pair", TYPE_VK_PAIR) 1025 TYPE("VK8Pair", TYPE_VK_PAIR) 1026 TYPE("VK16Pair", TYPE_VK_PAIR) 1027 TYPE("vx64mem", TYPE_MVSIBX) 1028 TYPE("vx128mem", TYPE_MVSIBX) 1029 TYPE("vx256mem", TYPE_MVSIBX) 1030 TYPE("vy128mem", TYPE_MVSIBY) 1031 TYPE("vy256mem", TYPE_MVSIBY) 1032 TYPE("vx64xmem", TYPE_MVSIBX) 1033 TYPE("vx128xmem", TYPE_MVSIBX) 1034 TYPE("vx256xmem", TYPE_MVSIBX) 1035 TYPE("vy128xmem", TYPE_MVSIBY) 1036 TYPE("vy256xmem", TYPE_MVSIBY) 1037 TYPE("vy512xmem", TYPE_MVSIBY) 1038 TYPE("vz256mem", TYPE_MVSIBZ) 1039 TYPE("vz512mem", TYPE_MVSIBZ) 1040 TYPE("BNDR", TYPE_BNDR) 1041 TYPE("TILE", TYPE_TMM) 1042 errs() << "Unhandled type string " << s << "\n"; 1043 llvm_unreachable("Unhandled type string"); 1044 } 1045 #undef TYPE 1046 1047 #define ENCODING(str, encoding) if (s == str) return encoding; 1048 OperandEncoding 1049 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1050 uint8_t OpSize) { 1051 if(OpSize != X86Local::OpSize16) { 1052 // For instructions without an OpSize prefix, a declared 16-bit register or 1053 // immediate encoding is special. 1054 ENCODING("i16imm", ENCODING_IW) 1055 } 1056 ENCODING("i32i8imm", ENCODING_IB) 1057 ENCODING("AVX512RC", ENCODING_IRC) 1058 ENCODING("i16imm", ENCODING_Iv) 1059 ENCODING("i16i8imm", ENCODING_IB) 1060 ENCODING("i32imm", ENCODING_Iv) 1061 ENCODING("i64i32imm", ENCODING_ID) 1062 ENCODING("i64i8imm", ENCODING_IB) 1063 ENCODING("i8imm", ENCODING_IB) 1064 ENCODING("u4imm", ENCODING_IB) 1065 ENCODING("u8imm", ENCODING_IB) 1066 ENCODING("i16u8imm", ENCODING_IB) 1067 ENCODING("i32u8imm", ENCODING_IB) 1068 ENCODING("i64u8imm", ENCODING_IB) 1069 // This is not a typo. Instructions like BLENDVPD put 1070 // register IDs in 8-bit immediates nowadays. 1071 ENCODING("FR32", ENCODING_IB) 1072 ENCODING("FR64", ENCODING_IB) 1073 ENCODING("FR128", ENCODING_IB) 1074 ENCODING("VR128", ENCODING_IB) 1075 ENCODING("VR256", ENCODING_IB) 1076 ENCODING("FR16X", ENCODING_IB) 1077 ENCODING("FR32X", ENCODING_IB) 1078 ENCODING("FR64X", ENCODING_IB) 1079 ENCODING("VR128X", ENCODING_IB) 1080 ENCODING("VR256X", ENCODING_IB) 1081 ENCODING("VR512", ENCODING_IB) 1082 ENCODING("TILE", ENCODING_IB) 1083 errs() << "Unhandled immediate encoding " << s << "\n"; 1084 llvm_unreachable("Unhandled immediate encoding"); 1085 } 1086 1087 OperandEncoding 1088 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1089 uint8_t OpSize) { 1090 ENCODING("RST", ENCODING_FP) 1091 ENCODING("RSTi", ENCODING_FP) 1092 ENCODING("GR16", ENCODING_RM) 1093 ENCODING("GR16orGR32orGR64",ENCODING_RM) 1094 ENCODING("GR32", ENCODING_RM) 1095 ENCODING("GR32orGR64", ENCODING_RM) 1096 ENCODING("GR64", ENCODING_RM) 1097 ENCODING("GR8", ENCODING_RM) 1098 ENCODING("VR128", ENCODING_RM) 1099 ENCODING("VR128X", ENCODING_RM) 1100 ENCODING("FR128", ENCODING_RM) 1101 ENCODING("FR64", ENCODING_RM) 1102 ENCODING("FR32", ENCODING_RM) 1103 ENCODING("FR64X", ENCODING_RM) 1104 ENCODING("FR32X", ENCODING_RM) 1105 ENCODING("FR16X", ENCODING_RM) 1106 ENCODING("VR64", ENCODING_RM) 1107 ENCODING("VR256", ENCODING_RM) 1108 ENCODING("VR256X", ENCODING_RM) 1109 ENCODING("VR512", ENCODING_RM) 1110 ENCODING("VK1", ENCODING_RM) 1111 ENCODING("VK2", ENCODING_RM) 1112 ENCODING("VK4", ENCODING_RM) 1113 ENCODING("VK8", ENCODING_RM) 1114 ENCODING("VK16", ENCODING_RM) 1115 ENCODING("VK32", ENCODING_RM) 1116 ENCODING("VK64", ENCODING_RM) 1117 ENCODING("BNDR", ENCODING_RM) 1118 ENCODING("TILE", ENCODING_RM) 1119 errs() << "Unhandled R/M register encoding " << s << "\n"; 1120 llvm_unreachable("Unhandled R/M register encoding"); 1121 } 1122 1123 OperandEncoding 1124 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1125 uint8_t OpSize) { 1126 ENCODING("GR16", ENCODING_REG) 1127 ENCODING("GR16orGR32orGR64",ENCODING_REG) 1128 ENCODING("GR32", ENCODING_REG) 1129 ENCODING("GR32orGR64", ENCODING_REG) 1130 ENCODING("GR64", ENCODING_REG) 1131 ENCODING("GR8", ENCODING_REG) 1132 ENCODING("VR128", ENCODING_REG) 1133 ENCODING("FR128", ENCODING_REG) 1134 ENCODING("FR64", ENCODING_REG) 1135 ENCODING("FR32", ENCODING_REG) 1136 ENCODING("VR64", ENCODING_REG) 1137 ENCODING("SEGMENT_REG", ENCODING_REG) 1138 ENCODING("DEBUG_REG", ENCODING_REG) 1139 ENCODING("CONTROL_REG", ENCODING_REG) 1140 ENCODING("VR256", ENCODING_REG) 1141 ENCODING("VR256X", ENCODING_REG) 1142 ENCODING("VR128X", ENCODING_REG) 1143 ENCODING("FR64X", ENCODING_REG) 1144 ENCODING("FR32X", ENCODING_REG) 1145 ENCODING("FR16X", ENCODING_REG) 1146 ENCODING("VR512", ENCODING_REG) 1147 ENCODING("VK1", ENCODING_REG) 1148 ENCODING("VK2", ENCODING_REG) 1149 ENCODING("VK4", ENCODING_REG) 1150 ENCODING("VK8", ENCODING_REG) 1151 ENCODING("VK16", ENCODING_REG) 1152 ENCODING("VK32", ENCODING_REG) 1153 ENCODING("VK64", ENCODING_REG) 1154 ENCODING("VK1Pair", ENCODING_REG) 1155 ENCODING("VK2Pair", ENCODING_REG) 1156 ENCODING("VK4Pair", ENCODING_REG) 1157 ENCODING("VK8Pair", ENCODING_REG) 1158 ENCODING("VK16Pair", ENCODING_REG) 1159 ENCODING("VK1WM", ENCODING_REG) 1160 ENCODING("VK2WM", ENCODING_REG) 1161 ENCODING("VK4WM", ENCODING_REG) 1162 ENCODING("VK8WM", ENCODING_REG) 1163 ENCODING("VK16WM", ENCODING_REG) 1164 ENCODING("VK32WM", ENCODING_REG) 1165 ENCODING("VK64WM", ENCODING_REG) 1166 ENCODING("BNDR", ENCODING_REG) 1167 ENCODING("TILE", ENCODING_REG) 1168 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1169 llvm_unreachable("Unhandled reg/opcode register encoding"); 1170 } 1171 1172 OperandEncoding 1173 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1174 uint8_t OpSize) { 1175 ENCODING("GR32", ENCODING_VVVV) 1176 ENCODING("GR64", ENCODING_VVVV) 1177 ENCODING("FR32", ENCODING_VVVV) 1178 ENCODING("FR128", ENCODING_VVVV) 1179 ENCODING("FR64", ENCODING_VVVV) 1180 ENCODING("VR128", ENCODING_VVVV) 1181 ENCODING("VR256", ENCODING_VVVV) 1182 ENCODING("FR16X", ENCODING_VVVV) 1183 ENCODING("FR32X", ENCODING_VVVV) 1184 ENCODING("FR64X", ENCODING_VVVV) 1185 ENCODING("VR128X", ENCODING_VVVV) 1186 ENCODING("VR256X", ENCODING_VVVV) 1187 ENCODING("VR512", ENCODING_VVVV) 1188 ENCODING("VK1", ENCODING_VVVV) 1189 ENCODING("VK2", ENCODING_VVVV) 1190 ENCODING("VK4", ENCODING_VVVV) 1191 ENCODING("VK8", ENCODING_VVVV) 1192 ENCODING("VK16", ENCODING_VVVV) 1193 ENCODING("VK32", ENCODING_VVVV) 1194 ENCODING("VK64", ENCODING_VVVV) 1195 ENCODING("TILE", ENCODING_VVVV) 1196 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1197 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1198 } 1199 1200 OperandEncoding 1201 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1202 uint8_t OpSize) { 1203 ENCODING("VK1WM", ENCODING_WRITEMASK) 1204 ENCODING("VK2WM", ENCODING_WRITEMASK) 1205 ENCODING("VK4WM", ENCODING_WRITEMASK) 1206 ENCODING("VK8WM", ENCODING_WRITEMASK) 1207 ENCODING("VK16WM", ENCODING_WRITEMASK) 1208 ENCODING("VK32WM", ENCODING_WRITEMASK) 1209 ENCODING("VK64WM", ENCODING_WRITEMASK) 1210 errs() << "Unhandled mask register encoding " << s << "\n"; 1211 llvm_unreachable("Unhandled mask register encoding"); 1212 } 1213 1214 OperandEncoding 1215 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1216 uint8_t OpSize) { 1217 ENCODING("i16mem", ENCODING_RM) 1218 ENCODING("i32mem", ENCODING_RM) 1219 ENCODING("i64mem", ENCODING_RM) 1220 ENCODING("i8mem", ENCODING_RM) 1221 ENCODING("shmem", ENCODING_RM) 1222 ENCODING("ssmem", ENCODING_RM) 1223 ENCODING("sdmem", ENCODING_RM) 1224 ENCODING("f128mem", ENCODING_RM) 1225 ENCODING("f256mem", ENCODING_RM) 1226 ENCODING("f512mem", ENCODING_RM) 1227 ENCODING("f64mem", ENCODING_RM) 1228 ENCODING("f32mem", ENCODING_RM) 1229 ENCODING("f16mem", ENCODING_RM) 1230 ENCODING("i128mem", ENCODING_RM) 1231 ENCODING("i256mem", ENCODING_RM) 1232 ENCODING("i512mem", ENCODING_RM) 1233 ENCODING("f80mem", ENCODING_RM) 1234 ENCODING("lea64_32mem", ENCODING_RM) 1235 ENCODING("lea64mem", ENCODING_RM) 1236 ENCODING("anymem", ENCODING_RM) 1237 ENCODING("opaquemem", ENCODING_RM) 1238 ENCODING("sibmem", ENCODING_SIB) 1239 ENCODING("vx64mem", ENCODING_VSIB) 1240 ENCODING("vx128mem", ENCODING_VSIB) 1241 ENCODING("vx256mem", ENCODING_VSIB) 1242 ENCODING("vy128mem", ENCODING_VSIB) 1243 ENCODING("vy256mem", ENCODING_VSIB) 1244 ENCODING("vx64xmem", ENCODING_VSIB) 1245 ENCODING("vx128xmem", ENCODING_VSIB) 1246 ENCODING("vx256xmem", ENCODING_VSIB) 1247 ENCODING("vy128xmem", ENCODING_VSIB) 1248 ENCODING("vy256xmem", ENCODING_VSIB) 1249 ENCODING("vy512xmem", ENCODING_VSIB) 1250 ENCODING("vz256mem", ENCODING_VSIB) 1251 ENCODING("vz512mem", ENCODING_VSIB) 1252 errs() << "Unhandled memory encoding " << s << "\n"; 1253 llvm_unreachable("Unhandled memory encoding"); 1254 } 1255 1256 OperandEncoding 1257 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1258 uint8_t OpSize) { 1259 if(OpSize != X86Local::OpSize16) { 1260 // For instructions without an OpSize prefix, a declared 16-bit register or 1261 // immediate encoding is special. 1262 ENCODING("i16imm", ENCODING_IW) 1263 } 1264 ENCODING("i16imm", ENCODING_Iv) 1265 ENCODING("i16i8imm", ENCODING_IB) 1266 ENCODING("i32imm", ENCODING_Iv) 1267 ENCODING("i32i8imm", ENCODING_IB) 1268 ENCODING("i64i32imm", ENCODING_ID) 1269 ENCODING("i64i8imm", ENCODING_IB) 1270 ENCODING("i8imm", ENCODING_IB) 1271 ENCODING("u8imm", ENCODING_IB) 1272 ENCODING("i16u8imm", ENCODING_IB) 1273 ENCODING("i32u8imm", ENCODING_IB) 1274 ENCODING("i64u8imm", ENCODING_IB) 1275 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1276 ENCODING("i16imm_brtarget", ENCODING_IW) 1277 ENCODING("i32imm_brtarget", ENCODING_ID) 1278 ENCODING("brtarget32", ENCODING_ID) 1279 ENCODING("brtarget16", ENCODING_IW) 1280 ENCODING("brtarget8", ENCODING_IB) 1281 ENCODING("i64imm", ENCODING_IO) 1282 ENCODING("offset16_8", ENCODING_Ia) 1283 ENCODING("offset16_16", ENCODING_Ia) 1284 ENCODING("offset16_32", ENCODING_Ia) 1285 ENCODING("offset32_8", ENCODING_Ia) 1286 ENCODING("offset32_16", ENCODING_Ia) 1287 ENCODING("offset32_32", ENCODING_Ia) 1288 ENCODING("offset32_64", ENCODING_Ia) 1289 ENCODING("offset64_8", ENCODING_Ia) 1290 ENCODING("offset64_16", ENCODING_Ia) 1291 ENCODING("offset64_32", ENCODING_Ia) 1292 ENCODING("offset64_64", ENCODING_Ia) 1293 ENCODING("srcidx8", ENCODING_SI) 1294 ENCODING("srcidx16", ENCODING_SI) 1295 ENCODING("srcidx32", ENCODING_SI) 1296 ENCODING("srcidx64", ENCODING_SI) 1297 ENCODING("dstidx8", ENCODING_DI) 1298 ENCODING("dstidx16", ENCODING_DI) 1299 ENCODING("dstidx32", ENCODING_DI) 1300 ENCODING("dstidx64", ENCODING_DI) 1301 errs() << "Unhandled relocation encoding " << s << "\n"; 1302 llvm_unreachable("Unhandled relocation encoding"); 1303 } 1304 1305 OperandEncoding 1306 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1307 uint8_t OpSize) { 1308 ENCODING("GR32", ENCODING_Rv) 1309 ENCODING("GR64", ENCODING_RO) 1310 ENCODING("GR16", ENCODING_Rv) 1311 ENCODING("GR8", ENCODING_RB) 1312 ENCODING("ccode", ENCODING_CC) 1313 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1314 llvm_unreachable("Unhandled opcode modifier encoding"); 1315 } 1316 #undef ENCODING 1317