1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 using namespace X86Disassembler;
123 
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
126 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 ///   0b11.
128 ///
129 /// @param form - The form of the instruction.
130 /// @return     - true if the form implies that a ModR/M byte is required, false
131 ///               otherwise.
132 static bool needsModRMForDecode(uint8_t form) {
133   if (form == X86Local::MRMDestReg    ||
134      form == X86Local::MRMDestMem    ||
135      form == X86Local::MRMSrcReg     ||
136      form == X86Local::MRMSrcMem     ||
137      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
139     return true;
140   else
141     return false;
142 }
143 
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 ///   the ModR/M byte to be 0b11.
146 ///
147 /// @param form - The form of the instruction.
148 /// @return     - true if the form implies that Mod must be 0b11, false
149 ///               otherwise.
150 static bool isRegFormat(uint8_t form) {
151   if (form == X86Local::MRMDestReg ||
152      form == X86Local::MRMSrcReg  ||
153      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
154     return true;
155   else
156     return false;
157 }
158 
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 ///   Useful for switch statements and the like.
161 ///
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return     - The field, with the first bit in the BitsInit as the lowest
164 ///               order bit.
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166   int width = init.getNumBits();
167 
168   assert(width <= 8 && "Field is too large for uint8_t!");
169 
170   int     index;
171   uint8_t mask = 0x01;
172 
173   uint8_t ret = 0;
174 
175   for (index = 0; index < width; index++) {
176     if (static_cast<BitInit*>(init.getBit(index))->getValue())
177       ret |= mask;
178 
179     mask <<= 1;
180   }
181 
182   return ret;
183 }
184 
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 ///   name of the field.
187 ///
188 /// @param rec  - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return     - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192   BitsInit* bits = rec->getValueAsBitsInit(name);
193   return byteFromBitsInit(*bits);
194 }
195 
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197                                      const CodeGenInstruction &insn,
198                                      InstrUID uid) {
199   UID = uid;
200 
201   Rec = insn.TheDef;
202   Name = Rec->getName();
203   Spec = &tables.specForUID(UID);
204 
205   if (!Rec->isSubClassOf("X86Inst")) {
206     ShouldBeEmitted = false;
207     return;
208   }
209 
210   Prefix   = byteFromRec(Rec, "Prefix");
211   Opcode   = byteFromRec(Rec, "Opcode");
212   Form     = byteFromRec(Rec, "FormBits");
213   SegOvr   = byteFromRec(Rec, "SegOvrBits");
214 
215   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
216   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
217   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
218   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
219   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
220   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
221   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
222 
223   Name      = Rec->getName();
224   AsmString = Rec->getValueAsString("AsmString");
225 
226   Operands = &insn.Operands.OperandList;
227 
228   IsSSE            = HasOpSizePrefix && (Name.find("16") == Name.npos);
229   HasFROperands    = hasFROperands();
230   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
231 
232   // Check for 64-bit inst which does not require REX
233   Is64Bit = false;
234   // FIXME: Is there some better way to check for In64BitMode?
235   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
236   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
237     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
238       Is64Bit = true;
239       break;
240     }
241   }
242   // FIXME: These instructions aren't marked as 64-bit in any way
243   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
244              Rec->getName() == "MASKMOVDQU64" ||
245              Rec->getName() == "POPFS64" ||
246              Rec->getName() == "POPGS64" ||
247              Rec->getName() == "PUSHFS64" ||
248              Rec->getName() == "PUSHGS64" ||
249              Rec->getName() == "REX64_PREFIX" ||
250              Rec->getName().find("VMREAD64") != Name.npos ||
251              Rec->getName().find("VMWRITE64") != Name.npos ||
252              Rec->getName().find("MOV64") != Name.npos ||
253              Rec->getName().find("PUSH64") != Name.npos ||
254              Rec->getName().find("POP64") != Name.npos;
255 
256   ShouldBeEmitted  = true;
257 }
258 
259 void RecognizableInstr::processInstr(DisassemblerTables &tables,
260                                    const CodeGenInstruction &insn,
261                                    InstrUID uid)
262 {
263   // Ignore "asm parser only" instructions.
264   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
265     return;
266 
267   RecognizableInstr recogInstr(tables, insn, uid);
268 
269   recogInstr.emitInstructionSpecifier(tables);
270 
271   if (recogInstr.shouldBeEmitted())
272     recogInstr.emitDecodePath(tables);
273 }
274 
275 InstructionContext RecognizableInstr::insnContext() const {
276   InstructionContext insnContext;
277 
278   if (HasVEX_4VPrefix || HasVEXPrefix) {
279     if (HasOpSizePrefix && HasVEX_LPrefix)
280       insnContext = IC_VEX_L_OPSIZE;
281     else if (HasOpSizePrefix && HasVEX_WPrefix)
282       insnContext = IC_VEX_W_OPSIZE;
283     else if (HasOpSizePrefix)
284       insnContext = IC_VEX_OPSIZE;
285     else if (HasVEX_LPrefix && Prefix == X86Local::XS)
286       insnContext = IC_VEX_L_XS;
287     else if (HasVEX_LPrefix && Prefix == X86Local::XD)
288       insnContext = IC_VEX_L_XD;
289     else if (HasVEX_WPrefix && Prefix == X86Local::XS)
290       insnContext = IC_VEX_W_XS;
291     else if (HasVEX_WPrefix && Prefix == X86Local::XD)
292       insnContext = IC_VEX_W_XD;
293     else if (HasVEX_WPrefix)
294       insnContext = IC_VEX_W;
295     else if (HasVEX_LPrefix)
296       insnContext = IC_VEX_L;
297     else if (Prefix == X86Local::XD)
298       insnContext = IC_VEX_XD;
299     else if (Prefix == X86Local::XS)
300       insnContext = IC_VEX_XS;
301     else
302       insnContext = IC_VEX;
303   } else if (Is64Bit || HasREX_WPrefix) {
304     if (HasREX_WPrefix && HasOpSizePrefix)
305       insnContext = IC_64BIT_REXW_OPSIZE;
306     else if (HasOpSizePrefix)
307       insnContext = IC_64BIT_OPSIZE;
308     else if (HasREX_WPrefix && Prefix == X86Local::XS)
309       insnContext = IC_64BIT_REXW_XS;
310     else if (HasREX_WPrefix && Prefix == X86Local::XD)
311       insnContext = IC_64BIT_REXW_XD;
312     else if (Prefix == X86Local::XD)
313       insnContext = IC_64BIT_XD;
314     else if (Prefix == X86Local::XS)
315       insnContext = IC_64BIT_XS;
316     else if (HasREX_WPrefix)
317       insnContext = IC_64BIT_REXW;
318     else
319       insnContext = IC_64BIT;
320   } else {
321     if (HasOpSizePrefix)
322       insnContext = IC_OPSIZE;
323     else if (Prefix == X86Local::XD)
324       insnContext = IC_XD;
325     else if (Prefix == X86Local::XS)
326       insnContext = IC_XS;
327     else
328       insnContext = IC;
329   }
330 
331   return insnContext;
332 }
333 
334 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
335   ///////////////////
336   // FILTER_STRONG
337   //
338 
339   // Filter out intrinsics
340 
341   if (!Rec->isSubClassOf("X86Inst"))
342     return FILTER_STRONG;
343 
344   if (Form == X86Local::Pseudo ||
345       IsCodeGenOnly)
346     return FILTER_STRONG;
347 
348   if (Form == X86Local::MRMInitReg)
349     return FILTER_STRONG;
350 
351 
352   // TEMPORARY pending bug fixes
353 
354   if (Name.find("VMOVDQU") != Name.npos ||
355       Name.find("VMOVDQA") != Name.npos ||
356       Name.find("VROUND") != Name.npos)
357     return FILTER_STRONG;
358 
359   // Filter out artificial instructions
360 
361   if (Name.find("TAILJMP") != Name.npos    ||
362       Name.find("_Int") != Name.npos       ||
363       Name.find("_int") != Name.npos       ||
364       Name.find("Int_") != Name.npos       ||
365       Name.find("_NOREX") != Name.npos     ||
366       Name.find("_TC") != Name.npos        ||
367       Name.find("EH_RETURN") != Name.npos  ||
368       Name.find("V_SET") != Name.npos      ||
369       Name.find("LOCK_") != Name.npos      ||
370       Name.find("WIN") != Name.npos        ||
371       Name.find("_AVX") != Name.npos       ||
372       Name.find("2SDL") != Name.npos)
373     return FILTER_STRONG;
374 
375   // Filter out instructions with segment override prefixes.
376   // They're too messy to handle now and we'll special case them if needed.
377 
378   if (SegOvr)
379     return FILTER_STRONG;
380 
381   // Filter out instructions that can't be printed.
382 
383   if (AsmString.size() == 0)
384     return FILTER_STRONG;
385 
386   // Filter out instructions with subreg operands.
387 
388   if (AsmString.find("subreg") != AsmString.npos)
389     return FILTER_STRONG;
390 
391   /////////////////
392   // FILTER_WEAK
393   //
394 
395 
396   // Filter out instructions with a LOCK prefix;
397   //   prefer forms that do not have the prefix
398   if (HasLockPrefix)
399     return FILTER_WEAK;
400 
401   // Filter out alternate forms of AVX instructions
402   if (Name.find("_alt") != Name.npos ||
403       Name.find("XrYr") != Name.npos ||
404       Name.find("r64r") != Name.npos ||
405       Name.find("_64mr") != Name.npos ||
406       Name.find("Xrr") != Name.npos ||
407       Name.find("rr64") != Name.npos)
408     return FILTER_WEAK;
409 
410   if (Name == "VMASKMOVDQU64"  ||
411       Name == "VEXTRACTPSrr64" ||
412       Name == "VMOVQd64rr"     ||
413       Name == "VMOVQs64rr")
414     return FILTER_WEAK;
415 
416   // Special cases.
417 
418   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
419     return FILTER_WEAK;
420   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
421     return FILTER_WEAK;
422 
423   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
424     return FILTER_WEAK;
425   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
426     return FILTER_WEAK;
427   if (Name.find("Fs") != Name.npos)
428     return FILTER_WEAK;
429   if (Name == "MOVLPDrr"          ||
430       Name == "MOVLPSrr"          ||
431       Name == "PUSHFQ"            ||
432       Name == "BSF16rr"           ||
433       Name == "BSF16rm"           ||
434       Name == "BSR16rr"           ||
435       Name == "BSR16rm"           ||
436       Name == "MOVSX16rm8"        ||
437       Name == "MOVSX16rr8"        ||
438       Name == "MOVZX16rm8"        ||
439       Name == "MOVZX16rr8"        ||
440       Name == "PUSH32i16"         ||
441       Name == "PUSH64i16"         ||
442       Name == "MOVPQI2QImr"       ||
443       Name == "VMOVPQI2QImr"      ||
444       Name == "MOVSDmr"           ||
445       Name == "MOVSDrm"           ||
446       Name == "MOVSSmr"           ||
447       Name == "MOVSSrm"           ||
448       Name == "MMX_MOVD64rrv164"  ||
449       Name == "CRC32m16"          ||
450       Name == "MOV64ri64i32"      ||
451       Name == "CRC32r16")
452     return FILTER_WEAK;
453 
454   if (HasFROperands && Name.find("MOV") != Name.npos &&
455      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
456       (Name.find("to") != Name.npos)))
457     return FILTER_WEAK;
458 
459   return FILTER_NORMAL;
460 }
461 
462 bool RecognizableInstr::hasFROperands() const {
463   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
464   unsigned numOperands = OperandList.size();
465 
466   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
467     const std::string &recName = OperandList[operandIndex].Rec->getName();
468 
469     if (recName.find("FR") != recName.npos)
470       return true;
471   }
472   return false;
473 }
474 
475 bool RecognizableInstr::has256BitOperands() const {
476   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
477   unsigned numOperands = OperandList.size();
478 
479   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
480     const std::string &recName = OperandList[operandIndex].Rec->getName();
481 
482     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
483       return true;
484     }
485   }
486   return false;
487 }
488 
489 void RecognizableInstr::handleOperand(
490   bool optional,
491   unsigned &operandIndex,
492   unsigned &physicalOperandIndex,
493   unsigned &numPhysicalOperands,
494   unsigned *operandMapping,
495   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
496   if (optional) {
497     if (physicalOperandIndex >= numPhysicalOperands)
498       return;
499   } else {
500     assert(physicalOperandIndex < numPhysicalOperands);
501   }
502 
503   while (operandMapping[operandIndex] != operandIndex) {
504     Spec->operands[operandIndex].encoding = ENCODING_DUP;
505     Spec->operands[operandIndex].type =
506       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
507     ++operandIndex;
508   }
509 
510   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
511 
512   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
513                                                               HasOpSizePrefix);
514   Spec->operands[operandIndex].type = typeFromString(typeName,
515                                                      IsSSE,
516                                                      HasREX_WPrefix,
517                                                      HasOpSizePrefix);
518 
519   ++operandIndex;
520   ++physicalOperandIndex;
521 }
522 
523 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
524   Spec->name       = Name;
525 
526   if (!Rec->isSubClassOf("X86Inst"))
527     return;
528 
529   switch (filter()) {
530   case FILTER_WEAK:
531     Spec->filtered = true;
532     break;
533   case FILTER_STRONG:
534     ShouldBeEmitted = false;
535     return;
536   case FILTER_NORMAL:
537     break;
538   }
539 
540   Spec->insnContext = insnContext();
541 
542   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
543 
544   unsigned operandIndex;
545   unsigned numOperands = OperandList.size();
546   unsigned numPhysicalOperands = 0;
547 
548   // operandMapping maps from operands in OperandList to their originals.
549   // If operandMapping[i] != i, then the entry is a duplicate.
550   unsigned operandMapping[X86_MAX_OPERANDS];
551 
552   bool hasFROperands = false;
553 
554   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
555 
556   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
557     if (OperandList[operandIndex].Constraints.size()) {
558       const CGIOperandList::ConstraintInfo &Constraint =
559         OperandList[operandIndex].Constraints[0];
560       if (Constraint.isTied()) {
561         operandMapping[operandIndex] = Constraint.getTiedOperand();
562       } else {
563         ++numPhysicalOperands;
564         operandMapping[operandIndex] = operandIndex;
565       }
566     } else {
567       ++numPhysicalOperands;
568       operandMapping[operandIndex] = operandIndex;
569     }
570 
571     const std::string &recName = OperandList[operandIndex].Rec->getName();
572 
573     if (recName.find("FR") != recName.npos)
574       hasFROperands = true;
575   }
576 
577   if (hasFROperands && Name.find("MOV") != Name.npos &&
578      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
579       (Name.find("to") != Name.npos)))
580     ShouldBeEmitted = false;
581 
582   if (!ShouldBeEmitted)
583     return;
584 
585 #define HANDLE_OPERAND(class)               \
586   handleOperand(false,                      \
587                 operandIndex,               \
588                 physicalOperandIndex,       \
589                 numPhysicalOperands,        \
590                 operandMapping,             \
591                 class##EncodingFromString);
592 
593 #define HANDLE_OPTIONAL(class)              \
594   handleOperand(true,                       \
595                 operandIndex,               \
596                 physicalOperandIndex,       \
597                 numPhysicalOperands,        \
598                 operandMapping,             \
599                 class##EncodingFromString);
600 
601   // operandIndex should always be < numOperands
602   operandIndex = 0;
603   // physicalOperandIndex should always be < numPhysicalOperands
604   unsigned physicalOperandIndex = 0;
605 
606   switch (Form) {
607   case X86Local::RawFrm:
608     // Operand 1 (optional) is an address or immediate.
609     // Operand 2 (optional) is an immediate.
610     assert(numPhysicalOperands <= 2 &&
611            "Unexpected number of operands for RawFrm");
612     HANDLE_OPTIONAL(relocation)
613     HANDLE_OPTIONAL(immediate)
614     break;
615   case X86Local::AddRegFrm:
616     // Operand 1 is added to the opcode.
617     // Operand 2 (optional) is an address.
618     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
619            "Unexpected number of operands for AddRegFrm");
620     HANDLE_OPERAND(opcodeModifier)
621     HANDLE_OPTIONAL(relocation)
622     break;
623   case X86Local::MRMDestReg:
624     // Operand 1 is a register operand in the R/M field.
625     // Operand 2 is a register operand in the Reg/Opcode field.
626     // Operand 3 (optional) is an immediate.
627     assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
628            "Unexpected number of operands for MRMDestRegFrm");
629     HANDLE_OPERAND(rmRegister)
630     HANDLE_OPERAND(roRegister)
631     HANDLE_OPTIONAL(immediate)
632     break;
633   case X86Local::MRMDestMem:
634     // Operand 1 is a memory operand (possibly SIB-extended)
635     // Operand 2 is a register operand in the Reg/Opcode field.
636     // Operand 3 (optional) is an immediate.
637     assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
638            "Unexpected number of operands for MRMDestMemFrm");
639     HANDLE_OPERAND(memory)
640     HANDLE_OPERAND(roRegister)
641     HANDLE_OPTIONAL(immediate)
642     break;
643   case X86Local::MRMSrcReg:
644     // Operand 1 is a register operand in the Reg/Opcode field.
645     // Operand 2 is a register operand in the R/M field.
646     // - In AVX, there is a register operand in the VEX.vvvv field here -
647     // Operand 3 (optional) is an immediate.
648 
649     if (HasVEX_4VPrefix)
650       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
651              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
652     else
653       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
654              "Unexpected number of operands for MRMSrcRegFrm");
655 
656     HANDLE_OPERAND(roRegister)
657 
658     if (HasVEX_4VPrefix)
659       // FIXME: In AVX, the register below becomes the one encoded
660       // in ModRMVEX and the one above the one in the VEX.VVVV field
661       HANDLE_OPERAND(vvvvRegister)
662 
663     HANDLE_OPERAND(rmRegister)
664     HANDLE_OPTIONAL(immediate)
665     break;
666   case X86Local::MRMSrcMem:
667     // Operand 1 is a register operand in the Reg/Opcode field.
668     // Operand 2 is a memory operand (possibly SIB-extended)
669     // - In AVX, there is a register operand in the VEX.vvvv field here -
670     // Operand 3 (optional) is an immediate.
671 
672     if (HasVEX_4VPrefix)
673       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
674              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
675     else
676       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
677              "Unexpected number of operands for MRMSrcMemFrm");
678 
679     HANDLE_OPERAND(roRegister)
680 
681     if (HasVEX_4VPrefix)
682       // FIXME: In AVX, the register below becomes the one encoded
683       // in ModRMVEX and the one above the one in the VEX.VVVV field
684       HANDLE_OPERAND(vvvvRegister)
685 
686     HANDLE_OPERAND(memory)
687     HANDLE_OPTIONAL(immediate)
688     break;
689   case X86Local::MRM0r:
690   case X86Local::MRM1r:
691   case X86Local::MRM2r:
692   case X86Local::MRM3r:
693   case X86Local::MRM4r:
694   case X86Local::MRM5r:
695   case X86Local::MRM6r:
696   case X86Local::MRM7r:
697     // Operand 1 is a register operand in the R/M field.
698     // Operand 2 (optional) is an immediate or relocation.
699     if (HasVEX_4VPrefix)
700       assert(numPhysicalOperands <= 3 &&
701              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
702     else
703       assert(numPhysicalOperands <= 2 &&
704              "Unexpected number of operands for MRMnRFrm");
705     if (HasVEX_4VPrefix)
706       HANDLE_OPERAND(vvvvRegister);
707     HANDLE_OPTIONAL(rmRegister)
708     HANDLE_OPTIONAL(relocation)
709     break;
710   case X86Local::MRM0m:
711   case X86Local::MRM1m:
712   case X86Local::MRM2m:
713   case X86Local::MRM3m:
714   case X86Local::MRM4m:
715   case X86Local::MRM5m:
716   case X86Local::MRM6m:
717   case X86Local::MRM7m:
718     // Operand 1 is a memory operand (possibly SIB-extended)
719     // Operand 2 (optional) is an immediate or relocation.
720     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
721            "Unexpected number of operands for MRMnMFrm");
722     HANDLE_OPERAND(memory)
723     HANDLE_OPTIONAL(relocation)
724     break;
725   case X86Local::RawFrmImm8:
726     // operand 1 is a 16-bit immediate
727     // operand 2 is an 8-bit immediate
728     assert(numPhysicalOperands == 2 &&
729            "Unexpected number of operands for X86Local::RawFrmImm8");
730     HANDLE_OPERAND(immediate)
731     HANDLE_OPERAND(immediate)
732     break;
733   case X86Local::RawFrmImm16:
734     // operand 1 is a 16-bit immediate
735     // operand 2 is a 16-bit immediate
736     HANDLE_OPERAND(immediate)
737     HANDLE_OPERAND(immediate)
738     break;
739   case X86Local::MRMInitReg:
740     // Ignored.
741     break;
742   }
743 
744   #undef HANDLE_OPERAND
745   #undef HANDLE_OPTIONAL
746 }
747 
748 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
749   // Special cases where the LLVM tables are not complete
750 
751 #define MAP(from, to)                     \
752   case X86Local::MRM_##from:              \
753     filter = new ExactFilter(0x##from);   \
754     break;
755 
756   OpcodeType    opcodeType  = (OpcodeType)-1;
757 
758   ModRMFilter*  filter      = NULL;
759   uint8_t       opcodeToSet = 0;
760 
761   switch (Prefix) {
762   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
763   case X86Local::XD:
764   case X86Local::XS:
765   case X86Local::TB:
766     opcodeType = TWOBYTE;
767 
768     switch (Opcode) {
769     default:
770       if (needsModRMForDecode(Form))
771         filter = new ModFilter(isRegFormat(Form));
772       else
773         filter = new DumbFilter();
774       break;
775 #define EXTENSION_TABLE(n) case 0x##n:
776     TWO_BYTE_EXTENSION_TABLES
777 #undef EXTENSION_TABLE
778       switch (Form) {
779       default:
780         llvm_unreachable("Unhandled two-byte extended opcode");
781       case X86Local::MRM0r:
782       case X86Local::MRM1r:
783       case X86Local::MRM2r:
784       case X86Local::MRM3r:
785       case X86Local::MRM4r:
786       case X86Local::MRM5r:
787       case X86Local::MRM6r:
788       case X86Local::MRM7r:
789         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
790         break;
791       case X86Local::MRM0m:
792       case X86Local::MRM1m:
793       case X86Local::MRM2m:
794       case X86Local::MRM3m:
795       case X86Local::MRM4m:
796       case X86Local::MRM5m:
797       case X86Local::MRM6m:
798       case X86Local::MRM7m:
799         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
800         break;
801       MRM_MAPPING
802       } // switch (Form)
803       break;
804     } // switch (Opcode)
805     opcodeToSet = Opcode;
806     break;
807   case X86Local::T8:
808     opcodeType = THREEBYTE_38;
809     if (needsModRMForDecode(Form))
810       filter = new ModFilter(isRegFormat(Form));
811     else
812       filter = new DumbFilter();
813     opcodeToSet = Opcode;
814     break;
815   case X86Local::P_TA:
816     opcodeType = THREEBYTE_3A;
817     if (needsModRMForDecode(Form))
818       filter = new ModFilter(isRegFormat(Form));
819     else
820       filter = new DumbFilter();
821     opcodeToSet = Opcode;
822     break;
823   case X86Local::A6:
824     opcodeType = THREEBYTE_A6;
825     if (needsModRMForDecode(Form))
826       filter = new ModFilter(isRegFormat(Form));
827     else
828       filter = new DumbFilter();
829     opcodeToSet = Opcode;
830     break;
831   case X86Local::A7:
832     opcodeType = THREEBYTE_A7;
833     if (needsModRMForDecode(Form))
834       filter = new ModFilter(isRegFormat(Form));
835     else
836       filter = new DumbFilter();
837     opcodeToSet = Opcode;
838     break;
839   case X86Local::D8:
840   case X86Local::D9:
841   case X86Local::DA:
842   case X86Local::DB:
843   case X86Local::DC:
844   case X86Local::DD:
845   case X86Local::DE:
846   case X86Local::DF:
847     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
848     opcodeType = ONEBYTE;
849     if (Form == X86Local::AddRegFrm) {
850       Spec->modifierType = MODIFIER_MODRM;
851       Spec->modifierBase = Opcode;
852       filter = new AddRegEscapeFilter(Opcode);
853     } else {
854       filter = new EscapeFilter(true, Opcode);
855     }
856     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
857     break;
858   default:
859     opcodeType = ONEBYTE;
860     switch (Opcode) {
861 #define EXTENSION_TABLE(n) case 0x##n:
862     ONE_BYTE_EXTENSION_TABLES
863 #undef EXTENSION_TABLE
864       switch (Form) {
865       default:
866         llvm_unreachable("Fell through the cracks of a single-byte "
867                          "extended opcode");
868       case X86Local::MRM0r:
869       case X86Local::MRM1r:
870       case X86Local::MRM2r:
871       case X86Local::MRM3r:
872       case X86Local::MRM4r:
873       case X86Local::MRM5r:
874       case X86Local::MRM6r:
875       case X86Local::MRM7r:
876         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
877         break;
878       case X86Local::MRM0m:
879       case X86Local::MRM1m:
880       case X86Local::MRM2m:
881       case X86Local::MRM3m:
882       case X86Local::MRM4m:
883       case X86Local::MRM5m:
884       case X86Local::MRM6m:
885       case X86Local::MRM7m:
886         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
887         break;
888       MRM_MAPPING
889       } // switch (Form)
890       break;
891     case 0xd8:
892     case 0xd9:
893     case 0xda:
894     case 0xdb:
895     case 0xdc:
896     case 0xdd:
897     case 0xde:
898     case 0xdf:
899       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
900       break;
901     default:
902       if (needsModRMForDecode(Form))
903         filter = new ModFilter(isRegFormat(Form));
904       else
905         filter = new DumbFilter();
906       break;
907     } // switch (Opcode)
908     opcodeToSet = Opcode;
909   } // switch (Prefix)
910 
911   assert(opcodeType != (OpcodeType)-1 &&
912          "Opcode type not set");
913   assert(filter && "Filter not set");
914 
915   if (Form == X86Local::AddRegFrm) {
916     if(Spec->modifierType != MODIFIER_MODRM) {
917       assert(opcodeToSet < 0xf9 &&
918              "Not enough room for all ADDREG_FRM operands");
919 
920       uint8_t currentOpcode;
921 
922       for (currentOpcode = opcodeToSet;
923            currentOpcode < opcodeToSet + 8;
924            ++currentOpcode)
925         tables.setTableFields(opcodeType,
926                               insnContext(),
927                               currentOpcode,
928                               *filter,
929                               UID);
930 
931       Spec->modifierType = MODIFIER_OPCODE;
932       Spec->modifierBase = opcodeToSet;
933     } else {
934       // modifierBase was set where MODIFIER_MODRM was set
935       tables.setTableFields(opcodeType,
936                             insnContext(),
937                             opcodeToSet,
938                             *filter,
939                             UID);
940     }
941   } else {
942     tables.setTableFields(opcodeType,
943                           insnContext(),
944                           opcodeToSet,
945                           *filter,
946                           UID);
947 
948     Spec->modifierType = MODIFIER_NONE;
949     Spec->modifierBase = opcodeToSet;
950   }
951 
952   delete filter;
953 
954 #undef MAP
955 }
956 
957 #define TYPE(str, type) if (s == str) return type;
958 OperandType RecognizableInstr::typeFromString(const std::string &s,
959                                               bool isSSE,
960                                               bool hasREX_WPrefix,
961                                               bool hasOpSizePrefix) {
962   if (isSSE) {
963     // For SSE instructions, we ignore the OpSize prefix and force operand
964     // sizes.
965     TYPE("GR16",              TYPE_R16)
966     TYPE("GR32",              TYPE_R32)
967     TYPE("GR64",              TYPE_R64)
968   }
969   if(hasREX_WPrefix) {
970     // For instructions with a REX_W prefix, a declared 32-bit register encoding
971     // is special.
972     TYPE("GR32",              TYPE_R32)
973   }
974   if(!hasOpSizePrefix) {
975     // For instructions without an OpSize prefix, a declared 16-bit register or
976     // immediate encoding is special.
977     TYPE("GR16",              TYPE_R16)
978     TYPE("i16imm",            TYPE_IMM16)
979   }
980   TYPE("i16mem",              TYPE_Mv)
981   TYPE("i16imm",              TYPE_IMMv)
982   TYPE("i16i8imm",            TYPE_IMMv)
983   TYPE("GR16",                TYPE_Rv)
984   TYPE("i32mem",              TYPE_Mv)
985   TYPE("i32imm",              TYPE_IMMv)
986   TYPE("i32i8imm",            TYPE_IMM32)
987   TYPE("u32u8imm",            TYPE_IMM32)
988   TYPE("GR32",                TYPE_Rv)
989   TYPE("i64mem",              TYPE_Mv)
990   TYPE("i64i32imm",           TYPE_IMM64)
991   TYPE("i64i8imm",            TYPE_IMM64)
992   TYPE("GR64",                TYPE_R64)
993   TYPE("i8mem",               TYPE_M8)
994   TYPE("i8imm",               TYPE_IMM8)
995   TYPE("GR8",                 TYPE_R8)
996   TYPE("VR128",               TYPE_XMM128)
997   TYPE("f128mem",             TYPE_M128)
998   TYPE("f256mem",             TYPE_M256)
999   TYPE("FR64",                TYPE_XMM64)
1000   TYPE("f64mem",              TYPE_M64FP)
1001   TYPE("sdmem",               TYPE_M64FP)
1002   TYPE("FR32",                TYPE_XMM32)
1003   TYPE("f32mem",              TYPE_M32FP)
1004   TYPE("ssmem",               TYPE_M32FP)
1005   TYPE("RST",                 TYPE_ST)
1006   TYPE("i128mem",             TYPE_M128)
1007   TYPE("i256mem",             TYPE_M256)
1008   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1009   TYPE("i16imm_pcrel",        TYPE_REL16)
1010   TYPE("i32imm_pcrel",        TYPE_REL32)
1011   TYPE("SSECC",               TYPE_IMM3)
1012   TYPE("brtarget",            TYPE_RELv)
1013   TYPE("uncondbrtarget",      TYPE_RELv)
1014   TYPE("brtarget8",           TYPE_REL8)
1015   TYPE("f80mem",              TYPE_M80FP)
1016   TYPE("lea32mem",            TYPE_LEA)
1017   TYPE("lea64_32mem",         TYPE_LEA)
1018   TYPE("lea64mem",            TYPE_LEA)
1019   TYPE("VR64",                TYPE_MM64)
1020   TYPE("i64imm",              TYPE_IMMv)
1021   TYPE("opaque32mem",         TYPE_M1616)
1022   TYPE("opaque48mem",         TYPE_M1632)
1023   TYPE("opaque80mem",         TYPE_M1664)
1024   TYPE("opaque512mem",        TYPE_M512)
1025   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1026   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1027   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1028   TYPE("offset8",             TYPE_MOFFS8)
1029   TYPE("offset16",            TYPE_MOFFS16)
1030   TYPE("offset32",            TYPE_MOFFS32)
1031   TYPE("offset64",            TYPE_MOFFS64)
1032   TYPE("VR256",               TYPE_XMM256)
1033   errs() << "Unhandled type string " << s << "\n";
1034   llvm_unreachable("Unhandled type string");
1035 }
1036 #undef TYPE
1037 
1038 #define ENCODING(str, encoding) if (s == str) return encoding;
1039 OperandEncoding RecognizableInstr::immediateEncodingFromString
1040   (const std::string &s,
1041    bool hasOpSizePrefix) {
1042   if(!hasOpSizePrefix) {
1043     // For instructions without an OpSize prefix, a declared 16-bit register or
1044     // immediate encoding is special.
1045     ENCODING("i16imm",        ENCODING_IW)
1046   }
1047   ENCODING("i32i8imm",        ENCODING_IB)
1048   ENCODING("u32u8imm",        ENCODING_IB)
1049   ENCODING("SSECC",           ENCODING_IB)
1050   ENCODING("i16imm",          ENCODING_Iv)
1051   ENCODING("i16i8imm",        ENCODING_IB)
1052   ENCODING("i32imm",          ENCODING_Iv)
1053   ENCODING("i64i32imm",       ENCODING_ID)
1054   ENCODING("i64i8imm",        ENCODING_IB)
1055   ENCODING("i8imm",           ENCODING_IB)
1056   // This is not a typo.  Instructions like BLENDVPD put
1057   // register IDs in 8-bit immediates nowadays.
1058   ENCODING("VR256",           ENCODING_IB)
1059   ENCODING("VR128",           ENCODING_IB)
1060   errs() << "Unhandled immediate encoding " << s << "\n";
1061   llvm_unreachable("Unhandled immediate encoding");
1062 }
1063 
1064 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1065   (const std::string &s,
1066    bool hasOpSizePrefix) {
1067   ENCODING("GR16",            ENCODING_RM)
1068   ENCODING("GR32",            ENCODING_RM)
1069   ENCODING("GR64",            ENCODING_RM)
1070   ENCODING("GR8",             ENCODING_RM)
1071   ENCODING("VR128",           ENCODING_RM)
1072   ENCODING("FR64",            ENCODING_RM)
1073   ENCODING("FR32",            ENCODING_RM)
1074   ENCODING("VR64",            ENCODING_RM)
1075   ENCODING("VR256",           ENCODING_RM)
1076   errs() << "Unhandled R/M register encoding " << s << "\n";
1077   llvm_unreachable("Unhandled R/M register encoding");
1078 }
1079 
1080 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1081   (const std::string &s,
1082    bool hasOpSizePrefix) {
1083   ENCODING("GR16",            ENCODING_REG)
1084   ENCODING("GR32",            ENCODING_REG)
1085   ENCODING("GR64",            ENCODING_REG)
1086   ENCODING("GR8",             ENCODING_REG)
1087   ENCODING("VR128",           ENCODING_REG)
1088   ENCODING("FR64",            ENCODING_REG)
1089   ENCODING("FR32",            ENCODING_REG)
1090   ENCODING("VR64",            ENCODING_REG)
1091   ENCODING("SEGMENT_REG",     ENCODING_REG)
1092   ENCODING("DEBUG_REG",       ENCODING_REG)
1093   ENCODING("CONTROL_REG",     ENCODING_REG)
1094   ENCODING("VR256",           ENCODING_REG)
1095   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1096   llvm_unreachable("Unhandled reg/opcode register encoding");
1097 }
1098 
1099 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1100   (const std::string &s,
1101    bool hasOpSizePrefix) {
1102   ENCODING("FR32",            ENCODING_VVVV)
1103   ENCODING("FR64",            ENCODING_VVVV)
1104   ENCODING("VR128",           ENCODING_VVVV)
1105   ENCODING("VR256",           ENCODING_VVVV)
1106   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1107   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1108 }
1109 
1110 OperandEncoding RecognizableInstr::memoryEncodingFromString
1111   (const std::string &s,
1112    bool hasOpSizePrefix) {
1113   ENCODING("i16mem",          ENCODING_RM)
1114   ENCODING("i32mem",          ENCODING_RM)
1115   ENCODING("i64mem",          ENCODING_RM)
1116   ENCODING("i8mem",           ENCODING_RM)
1117   ENCODING("ssmem",           ENCODING_RM)
1118   ENCODING("sdmem",           ENCODING_RM)
1119   ENCODING("f128mem",         ENCODING_RM)
1120   ENCODING("f256mem",         ENCODING_RM)
1121   ENCODING("f64mem",          ENCODING_RM)
1122   ENCODING("f32mem",          ENCODING_RM)
1123   ENCODING("i128mem",         ENCODING_RM)
1124   ENCODING("i256mem",         ENCODING_RM)
1125   ENCODING("f80mem",          ENCODING_RM)
1126   ENCODING("lea32mem",        ENCODING_RM)
1127   ENCODING("lea64_32mem",     ENCODING_RM)
1128   ENCODING("lea64mem",        ENCODING_RM)
1129   ENCODING("opaque32mem",     ENCODING_RM)
1130   ENCODING("opaque48mem",     ENCODING_RM)
1131   ENCODING("opaque80mem",     ENCODING_RM)
1132   ENCODING("opaque512mem",    ENCODING_RM)
1133   errs() << "Unhandled memory encoding " << s << "\n";
1134   llvm_unreachable("Unhandled memory encoding");
1135 }
1136 
1137 OperandEncoding RecognizableInstr::relocationEncodingFromString
1138   (const std::string &s,
1139    bool hasOpSizePrefix) {
1140   if(!hasOpSizePrefix) {
1141     // For instructions without an OpSize prefix, a declared 16-bit register or
1142     // immediate encoding is special.
1143     ENCODING("i16imm",        ENCODING_IW)
1144   }
1145   ENCODING("i16imm",          ENCODING_Iv)
1146   ENCODING("i16i8imm",        ENCODING_IB)
1147   ENCODING("i32imm",          ENCODING_Iv)
1148   ENCODING("i32i8imm",        ENCODING_IB)
1149   ENCODING("i64i32imm",       ENCODING_ID)
1150   ENCODING("i64i8imm",        ENCODING_IB)
1151   ENCODING("i8imm",           ENCODING_IB)
1152   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1153   ENCODING("i16imm_pcrel",    ENCODING_IW)
1154   ENCODING("i32imm_pcrel",    ENCODING_ID)
1155   ENCODING("brtarget",        ENCODING_Iv)
1156   ENCODING("brtarget8",       ENCODING_IB)
1157   ENCODING("i64imm",          ENCODING_IO)
1158   ENCODING("offset8",         ENCODING_Ia)
1159   ENCODING("offset16",        ENCODING_Ia)
1160   ENCODING("offset32",        ENCODING_Ia)
1161   ENCODING("offset64",        ENCODING_Ia)
1162   errs() << "Unhandled relocation encoding " << s << "\n";
1163   llvm_unreachable("Unhandled relocation encoding");
1164 }
1165 
1166 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1167   (const std::string &s,
1168    bool hasOpSizePrefix) {
1169   ENCODING("RST",             ENCODING_I)
1170   ENCODING("GR32",            ENCODING_Rv)
1171   ENCODING("GR64",            ENCODING_RO)
1172   ENCODING("GR16",            ENCODING_Rv)
1173   ENCODING("GR8",             ENCODING_RB)
1174   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1175   llvm_unreachable("Unhandled opcode modifier encoding");
1176 }
1177 #undef ENCODING
1178