1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 25 #define MRM_MAPPING \ 26 MAP(C0, 64) \ 27 MAP(C1, 65) \ 28 MAP(C2, 66) \ 29 MAP(C3, 67) \ 30 MAP(C4, 68) \ 31 MAP(C5, 69) \ 32 MAP(C6, 70) \ 33 MAP(C7, 71) \ 34 MAP(C8, 72) \ 35 MAP(C9, 73) \ 36 MAP(CA, 74) \ 37 MAP(CB, 75) \ 38 MAP(CC, 76) \ 39 MAP(CD, 77) \ 40 MAP(CE, 78) \ 41 MAP(CF, 79) \ 42 MAP(D0, 80) \ 43 MAP(D1, 81) \ 44 MAP(D2, 82) \ 45 MAP(D3, 83) \ 46 MAP(D4, 84) \ 47 MAP(D5, 85) \ 48 MAP(D6, 86) \ 49 MAP(D7, 87) \ 50 MAP(D8, 88) \ 51 MAP(D9, 89) \ 52 MAP(DA, 90) \ 53 MAP(DB, 91) \ 54 MAP(DC, 92) \ 55 MAP(DD, 93) \ 56 MAP(DE, 94) \ 57 MAP(DF, 95) \ 58 MAP(E0, 96) \ 59 MAP(E1, 97) \ 60 MAP(E2, 98) \ 61 MAP(E3, 99) \ 62 MAP(E4, 100) \ 63 MAP(E5, 101) \ 64 MAP(E6, 102) \ 65 MAP(E7, 103) \ 66 MAP(E8, 104) \ 67 MAP(E9, 105) \ 68 MAP(EA, 106) \ 69 MAP(EB, 107) \ 70 MAP(EC, 108) \ 71 MAP(ED, 109) \ 72 MAP(EE, 110) \ 73 MAP(EF, 111) \ 74 MAP(F0, 112) \ 75 MAP(F1, 113) \ 76 MAP(F2, 114) \ 77 MAP(F3, 115) \ 78 MAP(F4, 116) \ 79 MAP(F5, 117) \ 80 MAP(F6, 118) \ 81 MAP(F7, 119) \ 82 MAP(F8, 120) \ 83 MAP(F9, 121) \ 84 MAP(FA, 122) \ 85 MAP(FB, 123) \ 86 MAP(FC, 124) \ 87 MAP(FD, 125) \ 88 MAP(FE, 126) \ 89 MAP(FF, 127) 90 91 // A clone of X86 since we can't depend on something that is generated. 92 namespace X86Local { 93 enum { 94 Pseudo = 0, 95 RawFrm = 1, 96 AddRegFrm = 2, 97 RawFrmMemOffs = 3, 98 RawFrmSrc = 4, 99 RawFrmDst = 5, 100 RawFrmDstSrc = 6, 101 RawFrmImm8 = 7, 102 RawFrmImm16 = 8, 103 MRMDestMem = 32, 104 MRMSrcMem = 33, 105 MRMSrcMem4VOp3 = 34, 106 MRMSrcMemOp4 = 35, 107 MRMXm = 39, 108 MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, 109 MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, 110 MRMDestReg = 48, 111 MRMSrcReg = 49, 112 MRMSrcReg4VOp3 = 50, 113 MRMSrcRegOp4 = 51, 114 MRMXr = 55, 115 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, 116 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, 117 #define MAP(from, to) MRM_##from = to, 118 MRM_MAPPING 119 #undef MAP 120 }; 121 122 enum { 123 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 124 }; 125 126 enum { 127 PS = 1, PD = 2, XS = 3, XD = 4 128 }; 129 130 enum { 131 VEX = 1, XOP = 2, EVEX = 3 132 }; 133 134 enum { 135 OpSize16 = 1, OpSize32 = 2 136 }; 137 138 enum { 139 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 140 }; 141 142 enum { 143 VEX_W0 = 0, VEX_W1 = 1, VEX_WIG = 2 144 }; 145 } 146 147 using namespace X86Disassembler; 148 149 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 150 /// Useful for switch statements and the like. 151 /// 152 /// @param init - A reference to the BitsInit to be decoded. 153 /// @return - The field, with the first bit in the BitsInit as the lowest 154 /// order bit. 155 static uint8_t byteFromBitsInit(BitsInit &init) { 156 int width = init.getNumBits(); 157 158 assert(width <= 8 && "Field is too large for uint8_t!"); 159 160 int index; 161 uint8_t mask = 0x01; 162 163 uint8_t ret = 0; 164 165 for (index = 0; index < width; index++) { 166 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 167 ret |= mask; 168 169 mask <<= 1; 170 } 171 172 return ret; 173 } 174 175 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 176 /// name of the field. 177 /// 178 /// @param rec - The record from which to extract the value. 179 /// @param name - The name of the field in the record. 180 /// @return - The field, as translated by byteFromBitsInit(). 181 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 182 BitsInit* bits = rec->getValueAsBitsInit(name); 183 return byteFromBitsInit(*bits); 184 } 185 186 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 187 const CodeGenInstruction &insn, 188 InstrUID uid) { 189 UID = uid; 190 191 Rec = insn.TheDef; 192 Name = Rec->getName(); 193 Spec = &tables.specForUID(UID); 194 195 if (!Rec->isSubClassOf("X86Inst")) { 196 ShouldBeEmitted = false; 197 return; 198 } 199 200 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 201 OpMap = byteFromRec(Rec, "OpMapBits"); 202 Opcode = byteFromRec(Rec, "Opcode"); 203 Form = byteFromRec(Rec, "FormBits"); 204 Encoding = byteFromRec(Rec, "OpEncBits"); 205 206 OpSize = byteFromRec(Rec, "OpSizeBits"); 207 AdSize = byteFromRec(Rec, "AdSizeBits"); 208 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 209 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 210 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 211 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 212 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 213 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 214 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 215 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 216 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 217 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 218 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 219 220 Name = Rec->getName(); 221 222 Operands = &insn.Operands.OperandList; 223 224 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 225 226 // Check for 64-bit inst which does not require REX 227 Is32Bit = false; 228 Is64Bit = false; 229 // FIXME: Is there some better way to check for In64BitMode? 230 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 231 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 232 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 233 Predicates[i]->getName().find("In32Bit") != Name.npos) { 234 Is32Bit = true; 235 break; 236 } 237 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 238 Is64Bit = true; 239 break; 240 } 241 } 242 243 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 244 ShouldBeEmitted = false; 245 return; 246 } 247 248 // Special case since there is no attribute class for 64-bit and VEX 249 if (Name == "VMASKMOVDQU64") { 250 ShouldBeEmitted = false; 251 return; 252 } 253 254 ShouldBeEmitted = true; 255 } 256 257 void RecognizableInstr::processInstr(DisassemblerTables &tables, 258 const CodeGenInstruction &insn, 259 InstrUID uid) 260 { 261 // Ignore "asm parser only" instructions. 262 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 263 return; 264 265 RecognizableInstr recogInstr(tables, insn, uid); 266 267 if (recogInstr.shouldBeEmitted()) { 268 recogInstr.emitInstructionSpecifier(); 269 recogInstr.emitDecodePath(tables); 270 } 271 } 272 273 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 274 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 275 (HasEVEX_KZ ? n##_KZ : \ 276 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 277 278 InstructionContext RecognizableInstr::insnContext() const { 279 InstructionContext insnContext; 280 281 if (Encoding == X86Local::EVEX) { 282 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 283 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 284 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 285 } 286 // VEX_L & VEX_W 287 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 288 if (OpPrefix == X86Local::PD) 289 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 290 else if (OpPrefix == X86Local::XS) 291 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 292 else if (OpPrefix == X86Local::XD) 293 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 294 else if (OpPrefix == X86Local::PS) 295 insnContext = EVEX_KB(IC_EVEX_L_W); 296 else { 297 errs() << "Instruction does not use a prefix: " << Name << "\n"; 298 llvm_unreachable("Invalid prefix"); 299 } 300 } else if (HasVEX_LPrefix) { 301 // VEX_L 302 if (OpPrefix == X86Local::PD) 303 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 304 else if (OpPrefix == X86Local::XS) 305 insnContext = EVEX_KB(IC_EVEX_L_XS); 306 else if (OpPrefix == X86Local::XD) 307 insnContext = EVEX_KB(IC_EVEX_L_XD); 308 else if (OpPrefix == X86Local::PS) 309 insnContext = EVEX_KB(IC_EVEX_L); 310 else { 311 errs() << "Instruction does not use a prefix: " << Name << "\n"; 312 llvm_unreachable("Invalid prefix"); 313 } 314 } 315 else if (HasEVEX_L2Prefix && VEX_WPrefix == X86Local::VEX_W1) { 316 // EVEX_L2 & VEX_W 317 if (OpPrefix == X86Local::PD) 318 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 319 else if (OpPrefix == X86Local::XS) 320 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 321 else if (OpPrefix == X86Local::XD) 322 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 323 else if (OpPrefix == X86Local::PS) 324 insnContext = EVEX_KB(IC_EVEX_L2_W); 325 else { 326 errs() << "Instruction does not use a prefix: " << Name << "\n"; 327 llvm_unreachable("Invalid prefix"); 328 } 329 } else if (HasEVEX_L2Prefix) { 330 // EVEX_L2 331 if (OpPrefix == X86Local::PD) 332 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 333 else if (OpPrefix == X86Local::XD) 334 insnContext = EVEX_KB(IC_EVEX_L2_XD); 335 else if (OpPrefix == X86Local::XS) 336 insnContext = EVEX_KB(IC_EVEX_L2_XS); 337 else if (OpPrefix == X86Local::PS) 338 insnContext = EVEX_KB(IC_EVEX_L2); 339 else { 340 errs() << "Instruction does not use a prefix: " << Name << "\n"; 341 llvm_unreachable("Invalid prefix"); 342 } 343 } 344 else if (VEX_WPrefix == X86Local::VEX_W1) { 345 // VEX_W 346 if (OpPrefix == X86Local::PD) 347 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 348 else if (OpPrefix == X86Local::XS) 349 insnContext = EVEX_KB(IC_EVEX_W_XS); 350 else if (OpPrefix == X86Local::XD) 351 insnContext = EVEX_KB(IC_EVEX_W_XD); 352 else if (OpPrefix == X86Local::PS) 353 insnContext = EVEX_KB(IC_EVEX_W); 354 else { 355 errs() << "Instruction does not use a prefix: " << Name << "\n"; 356 llvm_unreachable("Invalid prefix"); 357 } 358 } 359 // No L, no W 360 else if (OpPrefix == X86Local::PD) 361 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 362 else if (OpPrefix == X86Local::XD) 363 insnContext = EVEX_KB(IC_EVEX_XD); 364 else if (OpPrefix == X86Local::XS) 365 insnContext = EVEX_KB(IC_EVEX_XS); 366 else 367 insnContext = EVEX_KB(IC_EVEX); 368 /// eof EVEX 369 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 370 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 371 if (OpPrefix == X86Local::PD) 372 insnContext = IC_VEX_L_W_OPSIZE; 373 else if (OpPrefix == X86Local::XS) 374 insnContext = IC_VEX_L_W_XS; 375 else if (OpPrefix == X86Local::XD) 376 insnContext = IC_VEX_L_W_XD; 377 else if (OpPrefix == X86Local::PS) 378 insnContext = IC_VEX_L_W; 379 else { 380 errs() << "Instruction does not use a prefix: " << Name << "\n"; 381 llvm_unreachable("Invalid prefix"); 382 } 383 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 384 insnContext = IC_VEX_L_OPSIZE; 385 else if (OpPrefix == X86Local::PD && VEX_WPrefix == X86Local::VEX_W1) 386 insnContext = IC_VEX_W_OPSIZE; 387 else if (OpPrefix == X86Local::PD) 388 insnContext = IC_VEX_OPSIZE; 389 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 390 insnContext = IC_VEX_L_XS; 391 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 392 insnContext = IC_VEX_L_XD; 393 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XS) 394 insnContext = IC_VEX_W_XS; 395 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XD) 396 insnContext = IC_VEX_W_XD; 397 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::PS) 398 insnContext = IC_VEX_W; 399 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 400 insnContext = IC_VEX_L; 401 else if (OpPrefix == X86Local::XD) 402 insnContext = IC_VEX_XD; 403 else if (OpPrefix == X86Local::XS) 404 insnContext = IC_VEX_XS; 405 else if (OpPrefix == X86Local::PS) 406 insnContext = IC_VEX; 407 else { 408 errs() << "Instruction does not use a prefix: " << Name << "\n"; 409 llvm_unreachable("Invalid prefix"); 410 } 411 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 412 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 413 insnContext = IC_64BIT_REXW_OPSIZE; 414 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 415 insnContext = IC_64BIT_REXW_ADSIZE; 416 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 417 insnContext = IC_64BIT_XD_OPSIZE; 418 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 419 insnContext = IC_64BIT_XS_OPSIZE; 420 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 421 insnContext = IC_64BIT_OPSIZE_ADSIZE; 422 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 423 insnContext = IC_64BIT_OPSIZE; 424 else if (AdSize == X86Local::AdSize32) 425 insnContext = IC_64BIT_ADSIZE; 426 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 427 insnContext = IC_64BIT_REXW_XS; 428 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 429 insnContext = IC_64BIT_REXW_XD; 430 else if (OpPrefix == X86Local::XD) 431 insnContext = IC_64BIT_XD; 432 else if (OpPrefix == X86Local::XS) 433 insnContext = IC_64BIT_XS; 434 else if (HasREX_WPrefix) 435 insnContext = IC_64BIT_REXW; 436 else 437 insnContext = IC_64BIT; 438 } else { 439 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 440 insnContext = IC_XD_OPSIZE; 441 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 442 insnContext = IC_XS_OPSIZE; 443 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 444 insnContext = IC_OPSIZE_ADSIZE; 445 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 446 insnContext = IC_OPSIZE; 447 else if (AdSize == X86Local::AdSize16) 448 insnContext = IC_ADSIZE; 449 else if (OpPrefix == X86Local::XD) 450 insnContext = IC_XD; 451 else if (OpPrefix == X86Local::XS) 452 insnContext = IC_XS; 453 else 454 insnContext = IC; 455 } 456 457 return insnContext; 458 } 459 460 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 461 // The scaling factor for AVX512 compressed displacement encoding is an 462 // instruction attribute. Adjust the ModRM encoding type to include the 463 // scale for compressed displacement. 464 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 465 return; 466 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 467 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 468 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 469 "Invalid CDisp scaling"); 470 } 471 472 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 473 unsigned &physicalOperandIndex, 474 unsigned numPhysicalOperands, 475 const unsigned *operandMapping, 476 OperandEncoding (*encodingFromString) 477 (const std::string&, 478 uint8_t OpSize)) { 479 if (optional) { 480 if (physicalOperandIndex >= numPhysicalOperands) 481 return; 482 } else { 483 assert(physicalOperandIndex < numPhysicalOperands); 484 } 485 486 while (operandMapping[operandIndex] != operandIndex) { 487 Spec->operands[operandIndex].encoding = ENCODING_DUP; 488 Spec->operands[operandIndex].type = 489 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 490 ++operandIndex; 491 } 492 493 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 494 495 OperandEncoding encoding = encodingFromString(typeName, OpSize); 496 // Adjust the encoding type for an operand based on the instruction. 497 adjustOperandEncoding(encoding); 498 Spec->operands[operandIndex].encoding = encoding; 499 Spec->operands[operandIndex].type = typeFromString(typeName, 500 HasREX_WPrefix, OpSize); 501 502 ++operandIndex; 503 ++physicalOperandIndex; 504 } 505 506 void RecognizableInstr::emitInstructionSpecifier() { 507 Spec->name = Name; 508 509 Spec->insnContext = insnContext(); 510 511 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 512 513 unsigned numOperands = OperandList.size(); 514 unsigned numPhysicalOperands = 0; 515 516 // operandMapping maps from operands in OperandList to their originals. 517 // If operandMapping[i] != i, then the entry is a duplicate. 518 unsigned operandMapping[X86_MAX_OPERANDS]; 519 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 520 521 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 522 if (!OperandList[operandIndex].Constraints.empty()) { 523 const CGIOperandList::ConstraintInfo &Constraint = 524 OperandList[operandIndex].Constraints[0]; 525 if (Constraint.isTied()) { 526 operandMapping[operandIndex] = operandIndex; 527 operandMapping[Constraint.getTiedOperand()] = operandIndex; 528 } else { 529 ++numPhysicalOperands; 530 operandMapping[operandIndex] = operandIndex; 531 } 532 } else { 533 ++numPhysicalOperands; 534 operandMapping[operandIndex] = operandIndex; 535 } 536 } 537 538 #define HANDLE_OPERAND(class) \ 539 handleOperand(false, \ 540 operandIndex, \ 541 physicalOperandIndex, \ 542 numPhysicalOperands, \ 543 operandMapping, \ 544 class##EncodingFromString); 545 546 #define HANDLE_OPTIONAL(class) \ 547 handleOperand(true, \ 548 operandIndex, \ 549 physicalOperandIndex, \ 550 numPhysicalOperands, \ 551 operandMapping, \ 552 class##EncodingFromString); 553 554 // operandIndex should always be < numOperands 555 unsigned operandIndex = 0; 556 // physicalOperandIndex should always be < numPhysicalOperands 557 unsigned physicalOperandIndex = 0; 558 559 #ifndef NDEBUG 560 // Given the set of prefix bits, how many additional operands does the 561 // instruction have? 562 unsigned additionalOperands = 0; 563 if (HasVEX_4V) 564 ++additionalOperands; 565 if (HasEVEX_K) 566 ++additionalOperands; 567 #endif 568 569 switch (Form) { 570 default: llvm_unreachable("Unhandled form"); 571 case X86Local::RawFrmSrc: 572 HANDLE_OPERAND(relocation); 573 return; 574 case X86Local::RawFrmDst: 575 HANDLE_OPERAND(relocation); 576 return; 577 case X86Local::RawFrmDstSrc: 578 HANDLE_OPERAND(relocation); 579 HANDLE_OPERAND(relocation); 580 return; 581 case X86Local::RawFrm: 582 // Operand 1 (optional) is an address or immediate. 583 assert(numPhysicalOperands <= 1 && 584 "Unexpected number of operands for RawFrm"); 585 HANDLE_OPTIONAL(relocation) 586 break; 587 case X86Local::RawFrmMemOffs: 588 // Operand 1 is an address. 589 HANDLE_OPERAND(relocation); 590 break; 591 case X86Local::AddRegFrm: 592 // Operand 1 is added to the opcode. 593 // Operand 2 (optional) is an address. 594 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 595 "Unexpected number of operands for AddRegFrm"); 596 HANDLE_OPERAND(opcodeModifier) 597 HANDLE_OPTIONAL(relocation) 598 break; 599 case X86Local::MRMDestReg: 600 // Operand 1 is a register operand in the R/M field. 601 // - In AVX512 there may be a mask operand here - 602 // Operand 2 is a register operand in the Reg/Opcode field. 603 // - In AVX, there is a register operand in the VEX.vvvv field here - 604 // Operand 3 (optional) is an immediate. 605 assert(numPhysicalOperands >= 2 + additionalOperands && 606 numPhysicalOperands <= 3 + additionalOperands && 607 "Unexpected number of operands for MRMDestRegFrm"); 608 609 HANDLE_OPERAND(rmRegister) 610 if (HasEVEX_K) 611 HANDLE_OPERAND(writemaskRegister) 612 613 if (HasVEX_4V) 614 // FIXME: In AVX, the register below becomes the one encoded 615 // in ModRMVEX and the one above the one in the VEX.VVVV field 616 HANDLE_OPERAND(vvvvRegister) 617 618 HANDLE_OPERAND(roRegister) 619 HANDLE_OPTIONAL(immediate) 620 break; 621 case X86Local::MRMDestMem: 622 // Operand 1 is a memory operand (possibly SIB-extended) 623 // Operand 2 is a register operand in the Reg/Opcode field. 624 // - In AVX, there is a register operand in the VEX.vvvv field here - 625 // Operand 3 (optional) is an immediate. 626 assert(numPhysicalOperands >= 2 + additionalOperands && 627 numPhysicalOperands <= 3 + additionalOperands && 628 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 629 630 HANDLE_OPERAND(memory) 631 632 if (HasEVEX_K) 633 HANDLE_OPERAND(writemaskRegister) 634 635 if (HasVEX_4V) 636 // FIXME: In AVX, the register below becomes the one encoded 637 // in ModRMVEX and the one above the one in the VEX.VVVV field 638 HANDLE_OPERAND(vvvvRegister) 639 640 HANDLE_OPERAND(roRegister) 641 HANDLE_OPTIONAL(immediate) 642 break; 643 case X86Local::MRMSrcReg: 644 // Operand 1 is a register operand in the Reg/Opcode field. 645 // Operand 2 is a register operand in the R/M field. 646 // - In AVX, there is a register operand in the VEX.vvvv field here - 647 // Operand 3 (optional) is an immediate. 648 // Operand 4 (optional) is an immediate. 649 650 assert(numPhysicalOperands >= 2 + additionalOperands && 651 numPhysicalOperands <= 4 + additionalOperands && 652 "Unexpected number of operands for MRMSrcRegFrm"); 653 654 HANDLE_OPERAND(roRegister) 655 656 if (HasEVEX_K) 657 HANDLE_OPERAND(writemaskRegister) 658 659 if (HasVEX_4V) 660 // FIXME: In AVX, the register below becomes the one encoded 661 // in ModRMVEX and the one above the one in the VEX.VVVV field 662 HANDLE_OPERAND(vvvvRegister) 663 664 HANDLE_OPERAND(rmRegister) 665 HANDLE_OPTIONAL(immediate) 666 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 667 HANDLE_OPTIONAL(immediate) 668 break; 669 case X86Local::MRMSrcReg4VOp3: 670 assert(numPhysicalOperands == 3 && 671 "Unexpected number of operands for MRMSrcRegFrm"); 672 HANDLE_OPERAND(roRegister) 673 HANDLE_OPERAND(rmRegister) 674 HANDLE_OPERAND(vvvvRegister) 675 break; 676 case X86Local::MRMSrcRegOp4: 677 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 678 "Unexpected number of operands for MRMSrcRegOp4Frm"); 679 HANDLE_OPERAND(roRegister) 680 HANDLE_OPERAND(vvvvRegister) 681 HANDLE_OPERAND(immediate) // Register in imm[7:4] 682 HANDLE_OPERAND(rmRegister) 683 HANDLE_OPTIONAL(immediate) 684 break; 685 case X86Local::MRMSrcMem: 686 // Operand 1 is a register operand in the Reg/Opcode field. 687 // Operand 2 is a memory operand (possibly SIB-extended) 688 // - In AVX, there is a register operand in the VEX.vvvv field here - 689 // Operand 3 (optional) is an immediate. 690 691 assert(numPhysicalOperands >= 2 + additionalOperands && 692 numPhysicalOperands <= 4 + additionalOperands && 693 "Unexpected number of operands for MRMSrcMemFrm"); 694 695 HANDLE_OPERAND(roRegister) 696 697 if (HasEVEX_K) 698 HANDLE_OPERAND(writemaskRegister) 699 700 if (HasVEX_4V) 701 // FIXME: In AVX, the register below becomes the one encoded 702 // in ModRMVEX and the one above the one in the VEX.VVVV field 703 HANDLE_OPERAND(vvvvRegister) 704 705 HANDLE_OPERAND(memory) 706 HANDLE_OPTIONAL(immediate) 707 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 708 break; 709 case X86Local::MRMSrcMem4VOp3: 710 assert(numPhysicalOperands == 3 && 711 "Unexpected number of operands for MRMSrcMemFrm"); 712 HANDLE_OPERAND(roRegister) 713 HANDLE_OPERAND(memory) 714 HANDLE_OPERAND(vvvvRegister) 715 break; 716 case X86Local::MRMSrcMemOp4: 717 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 718 "Unexpected number of operands for MRMSrcMemOp4Frm"); 719 HANDLE_OPERAND(roRegister) 720 HANDLE_OPERAND(vvvvRegister) 721 HANDLE_OPERAND(immediate) // Register in imm[7:4] 722 HANDLE_OPERAND(memory) 723 HANDLE_OPTIONAL(immediate) 724 break; 725 case X86Local::MRMXr: 726 case X86Local::MRM0r: 727 case X86Local::MRM1r: 728 case X86Local::MRM2r: 729 case X86Local::MRM3r: 730 case X86Local::MRM4r: 731 case X86Local::MRM5r: 732 case X86Local::MRM6r: 733 case X86Local::MRM7r: 734 // Operand 1 is a register operand in the R/M field. 735 // Operand 2 (optional) is an immediate or relocation. 736 // Operand 3 (optional) is an immediate. 737 assert(numPhysicalOperands >= 0 + additionalOperands && 738 numPhysicalOperands <= 3 + additionalOperands && 739 "Unexpected number of operands for MRMnr"); 740 741 if (HasVEX_4V) 742 HANDLE_OPERAND(vvvvRegister) 743 744 if (HasEVEX_K) 745 HANDLE_OPERAND(writemaskRegister) 746 HANDLE_OPTIONAL(rmRegister) 747 HANDLE_OPTIONAL(relocation) 748 HANDLE_OPTIONAL(immediate) 749 break; 750 case X86Local::MRMXm: 751 case X86Local::MRM0m: 752 case X86Local::MRM1m: 753 case X86Local::MRM2m: 754 case X86Local::MRM3m: 755 case X86Local::MRM4m: 756 case X86Local::MRM5m: 757 case X86Local::MRM6m: 758 case X86Local::MRM7m: 759 // Operand 1 is a memory operand (possibly SIB-extended) 760 // Operand 2 (optional) is an immediate or relocation. 761 assert(numPhysicalOperands >= 1 + additionalOperands && 762 numPhysicalOperands <= 2 + additionalOperands && 763 "Unexpected number of operands for MRMnm"); 764 765 if (HasVEX_4V) 766 HANDLE_OPERAND(vvvvRegister) 767 if (HasEVEX_K) 768 HANDLE_OPERAND(writemaskRegister) 769 HANDLE_OPERAND(memory) 770 HANDLE_OPTIONAL(relocation) 771 break; 772 case X86Local::RawFrmImm8: 773 // operand 1 is a 16-bit immediate 774 // operand 2 is an 8-bit immediate 775 assert(numPhysicalOperands == 2 && 776 "Unexpected number of operands for X86Local::RawFrmImm8"); 777 HANDLE_OPERAND(immediate) 778 HANDLE_OPERAND(immediate) 779 break; 780 case X86Local::RawFrmImm16: 781 // operand 1 is a 16-bit immediate 782 // operand 2 is a 16-bit immediate 783 HANDLE_OPERAND(immediate) 784 HANDLE_OPERAND(immediate) 785 break; 786 case X86Local::MRM_F8: 787 if (Opcode == 0xc6) { 788 assert(numPhysicalOperands == 1 && 789 "Unexpected number of operands for X86Local::MRM_F8"); 790 HANDLE_OPERAND(immediate) 791 } else if (Opcode == 0xc7) { 792 assert(numPhysicalOperands == 1 && 793 "Unexpected number of operands for X86Local::MRM_F8"); 794 HANDLE_OPERAND(relocation) 795 } 796 break; 797 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 798 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 799 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 800 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1: 801 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6: 802 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9: 803 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC: 804 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF: 805 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2: 806 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5: 807 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA: 808 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED: 809 case X86Local::MRM_EE: case X86Local::MRM_EF: case X86Local::MRM_F0: 810 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: 811 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: 812 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: 813 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: 814 case X86Local::MRM_FE: case X86Local::MRM_FF: 815 // Ignored. 816 break; 817 } 818 819 #undef HANDLE_OPERAND 820 #undef HANDLE_OPTIONAL 821 } 822 823 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 824 // Special cases where the LLVM tables are not complete 825 826 #define MAP(from, to) \ 827 case X86Local::MRM_##from: 828 829 OpcodeType opcodeType = (OpcodeType)-1; 830 831 ModRMFilter* filter = nullptr; 832 uint8_t opcodeToSet = 0; 833 834 switch (OpMap) { 835 default: llvm_unreachable("Invalid map!"); 836 case X86Local::OB: 837 case X86Local::TB: 838 case X86Local::T8: 839 case X86Local::TA: 840 case X86Local::XOP8: 841 case X86Local::XOP9: 842 case X86Local::XOPA: 843 switch (OpMap) { 844 default: llvm_unreachable("Unexpected map!"); 845 case X86Local::OB: opcodeType = ONEBYTE; break; 846 case X86Local::TB: opcodeType = TWOBYTE; break; 847 case X86Local::T8: opcodeType = THREEBYTE_38; break; 848 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 849 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 850 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 851 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 852 } 853 854 switch (Form) { 855 default: llvm_unreachable("Invalid form!"); 856 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 857 case X86Local::RawFrm: 858 case X86Local::AddRegFrm: 859 case X86Local::RawFrmMemOffs: 860 case X86Local::RawFrmSrc: 861 case X86Local::RawFrmDst: 862 case X86Local::RawFrmDstSrc: 863 case X86Local::RawFrmImm8: 864 case X86Local::RawFrmImm16: 865 filter = new DumbFilter(); 866 break; 867 case X86Local::MRMDestReg: 868 case X86Local::MRMSrcReg: 869 case X86Local::MRMSrcReg4VOp3: 870 case X86Local::MRMSrcRegOp4: 871 case X86Local::MRMXr: 872 filter = new ModFilter(true); 873 break; 874 case X86Local::MRMDestMem: 875 case X86Local::MRMSrcMem: 876 case X86Local::MRMSrcMem4VOp3: 877 case X86Local::MRMSrcMemOp4: 878 case X86Local::MRMXm: 879 filter = new ModFilter(false); 880 break; 881 case X86Local::MRM0r: case X86Local::MRM1r: 882 case X86Local::MRM2r: case X86Local::MRM3r: 883 case X86Local::MRM4r: case X86Local::MRM5r: 884 case X86Local::MRM6r: case X86Local::MRM7r: 885 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 886 break; 887 case X86Local::MRM0m: case X86Local::MRM1m: 888 case X86Local::MRM2m: case X86Local::MRM3m: 889 case X86Local::MRM4m: case X86Local::MRM5m: 890 case X86Local::MRM6m: case X86Local::MRM7m: 891 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 892 break; 893 MRM_MAPPING 894 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \ 895 break; 896 } // switch (Form) 897 898 opcodeToSet = Opcode; 899 break; 900 } // switch (OpMap) 901 902 unsigned AddressSize = 0; 903 switch (AdSize) { 904 case X86Local::AdSize16: AddressSize = 16; break; 905 case X86Local::AdSize32: AddressSize = 32; break; 906 case X86Local::AdSize64: AddressSize = 64; break; 907 } 908 909 assert(opcodeType != (OpcodeType)-1 && 910 "Opcode type not set"); 911 assert(filter && "Filter not set"); 912 913 if (Form == X86Local::AddRegFrm) { 914 assert(((opcodeToSet & 7) == 0) && 915 "ADDREG_FRM opcode not aligned"); 916 917 uint8_t currentOpcode; 918 919 for (currentOpcode = opcodeToSet; 920 currentOpcode < opcodeToSet + 8; 921 ++currentOpcode) 922 tables.setTableFields(opcodeType, 923 insnContext(), 924 currentOpcode, 925 *filter, 926 UID, Is32Bit, IgnoresVEX_L, AddressSize); 927 } else { 928 tables.setTableFields(opcodeType, 929 insnContext(), 930 opcodeToSet, 931 *filter, 932 UID, Is32Bit, IgnoresVEX_L, AddressSize); 933 } 934 935 delete filter; 936 937 #undef MAP 938 } 939 940 #define TYPE(str, type) if (s == str) return type; 941 OperandType RecognizableInstr::typeFromString(const std::string &s, 942 bool hasREX_WPrefix, 943 uint8_t OpSize) { 944 if(hasREX_WPrefix) { 945 // For instructions with a REX_W prefix, a declared 32-bit register encoding 946 // is special. 947 TYPE("GR32", TYPE_R32) 948 } 949 if(OpSize == X86Local::OpSize16) { 950 // For OpSize16 instructions, a declared 16-bit register or 951 // immediate encoding is special. 952 TYPE("GR16", TYPE_Rv) 953 } else if(OpSize == X86Local::OpSize32) { 954 // For OpSize32 instructions, a declared 32-bit register or 955 // immediate encoding is special. 956 TYPE("GR32", TYPE_Rv) 957 } 958 TYPE("i16mem", TYPE_M) 959 TYPE("i16imm", TYPE_IMM) 960 TYPE("i16i8imm", TYPE_IMM) 961 TYPE("GR16", TYPE_R16) 962 TYPE("i32mem", TYPE_M) 963 TYPE("i32imm", TYPE_IMM) 964 TYPE("i32i8imm", TYPE_IMM) 965 TYPE("GR32", TYPE_R32) 966 TYPE("GR32orGR64", TYPE_R32) 967 TYPE("i64mem", TYPE_M) 968 TYPE("i64i32imm", TYPE_IMM) 969 TYPE("i64i8imm", TYPE_IMM) 970 TYPE("GR64", TYPE_R64) 971 TYPE("i8mem", TYPE_M) 972 TYPE("i8imm", TYPE_IMM) 973 TYPE("u8imm", TYPE_UIMM8) 974 TYPE("i32u8imm", TYPE_UIMM8) 975 TYPE("GR8", TYPE_R8) 976 TYPE("VR128", TYPE_XMM) 977 TYPE("VR128X", TYPE_XMM) 978 TYPE("f128mem", TYPE_M) 979 TYPE("f256mem", TYPE_M) 980 TYPE("f512mem", TYPE_M) 981 TYPE("FR128", TYPE_XMM) 982 TYPE("FR64", TYPE_XMM) 983 TYPE("FR64X", TYPE_XMM) 984 TYPE("f64mem", TYPE_M) 985 TYPE("sdmem", TYPE_M) 986 TYPE("FR32", TYPE_XMM) 987 TYPE("FR32X", TYPE_XMM) 988 TYPE("f32mem", TYPE_M) 989 TYPE("ssmem", TYPE_M) 990 TYPE("RST", TYPE_ST) 991 TYPE("i128mem", TYPE_M) 992 TYPE("i256mem", TYPE_M) 993 TYPE("i512mem", TYPE_M) 994 TYPE("i64i32imm_pcrel", TYPE_REL) 995 TYPE("i16imm_pcrel", TYPE_REL) 996 TYPE("i32imm_pcrel", TYPE_REL) 997 TYPE("SSECC", TYPE_IMM3) 998 TYPE("XOPCC", TYPE_IMM3) 999 TYPE("AVXCC", TYPE_IMM5) 1000 TYPE("AVX512ICC", TYPE_AVX512ICC) 1001 TYPE("AVX512RC", TYPE_IMM) 1002 TYPE("brtarget32", TYPE_REL) 1003 TYPE("brtarget16", TYPE_REL) 1004 TYPE("brtarget8", TYPE_REL) 1005 TYPE("f80mem", TYPE_M) 1006 TYPE("lea64_32mem", TYPE_M) 1007 TYPE("lea64mem", TYPE_M) 1008 TYPE("VR64", TYPE_MM64) 1009 TYPE("i64imm", TYPE_IMM) 1010 TYPE("anymem", TYPE_M) 1011 TYPE("opaque32mem", TYPE_M) 1012 TYPE("opaque48mem", TYPE_M) 1013 TYPE("opaque80mem", TYPE_M) 1014 TYPE("opaque512mem", TYPE_M) 1015 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1016 TYPE("DEBUG_REG", TYPE_DEBUGREG) 1017 TYPE("CONTROL_REG", TYPE_CONTROLREG) 1018 TYPE("srcidx8", TYPE_SRCIDX) 1019 TYPE("srcidx16", TYPE_SRCIDX) 1020 TYPE("srcidx32", TYPE_SRCIDX) 1021 TYPE("srcidx64", TYPE_SRCIDX) 1022 TYPE("dstidx8", TYPE_DSTIDX) 1023 TYPE("dstidx16", TYPE_DSTIDX) 1024 TYPE("dstidx32", TYPE_DSTIDX) 1025 TYPE("dstidx64", TYPE_DSTIDX) 1026 TYPE("offset16_8", TYPE_MOFFS) 1027 TYPE("offset16_16", TYPE_MOFFS) 1028 TYPE("offset16_32", TYPE_MOFFS) 1029 TYPE("offset32_8", TYPE_MOFFS) 1030 TYPE("offset32_16", TYPE_MOFFS) 1031 TYPE("offset32_32", TYPE_MOFFS) 1032 TYPE("offset32_64", TYPE_MOFFS) 1033 TYPE("offset64_8", TYPE_MOFFS) 1034 TYPE("offset64_16", TYPE_MOFFS) 1035 TYPE("offset64_32", TYPE_MOFFS) 1036 TYPE("offset64_64", TYPE_MOFFS) 1037 TYPE("VR256", TYPE_YMM) 1038 TYPE("VR256X", TYPE_YMM) 1039 TYPE("VR512", TYPE_ZMM) 1040 TYPE("VK1", TYPE_VK) 1041 TYPE("VK1WM", TYPE_VK) 1042 TYPE("VK2", TYPE_VK) 1043 TYPE("VK2WM", TYPE_VK) 1044 TYPE("VK4", TYPE_VK) 1045 TYPE("VK4WM", TYPE_VK) 1046 TYPE("VK8", TYPE_VK) 1047 TYPE("VK8WM", TYPE_VK) 1048 TYPE("VK16", TYPE_VK) 1049 TYPE("VK16WM", TYPE_VK) 1050 TYPE("VK32", TYPE_VK) 1051 TYPE("VK32WM", TYPE_VK) 1052 TYPE("VK64", TYPE_VK) 1053 TYPE("VK64WM", TYPE_VK) 1054 TYPE("GR32_NOAX", TYPE_Rv) 1055 TYPE("vx64mem", TYPE_M) 1056 TYPE("vx128mem", TYPE_M) 1057 TYPE("vx256mem", TYPE_M) 1058 TYPE("vy128mem", TYPE_M) 1059 TYPE("vy256mem", TYPE_M) 1060 TYPE("vx64xmem", TYPE_M) 1061 TYPE("vx128xmem", TYPE_M) 1062 TYPE("vx256xmem", TYPE_M) 1063 TYPE("vy128xmem", TYPE_M) 1064 TYPE("vy256xmem", TYPE_M) 1065 TYPE("vy512mem", TYPE_M) 1066 TYPE("vz256xmem", TYPE_M) 1067 TYPE("vz512mem", TYPE_M) 1068 TYPE("BNDR", TYPE_BNDR) 1069 errs() << "Unhandled type string " << s << "\n"; 1070 llvm_unreachable("Unhandled type string"); 1071 } 1072 #undef TYPE 1073 1074 #define ENCODING(str, encoding) if (s == str) return encoding; 1075 OperandEncoding 1076 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1077 uint8_t OpSize) { 1078 if(OpSize != X86Local::OpSize16) { 1079 // For instructions without an OpSize prefix, a declared 16-bit register or 1080 // immediate encoding is special. 1081 ENCODING("i16imm", ENCODING_IW) 1082 } 1083 ENCODING("i32i8imm", ENCODING_IB) 1084 ENCODING("SSECC", ENCODING_IB) 1085 ENCODING("XOPCC", ENCODING_IB) 1086 ENCODING("AVXCC", ENCODING_IB) 1087 ENCODING("AVX512ICC", ENCODING_IB) 1088 ENCODING("AVX512RC", ENCODING_IB) 1089 ENCODING("i16imm", ENCODING_Iv) 1090 ENCODING("i16i8imm", ENCODING_IB) 1091 ENCODING("i32imm", ENCODING_Iv) 1092 ENCODING("i64i32imm", ENCODING_ID) 1093 ENCODING("i64i8imm", ENCODING_IB) 1094 ENCODING("i8imm", ENCODING_IB) 1095 ENCODING("u8imm", ENCODING_IB) 1096 ENCODING("i32u8imm", ENCODING_IB) 1097 // This is not a typo. Instructions like BLENDVPD put 1098 // register IDs in 8-bit immediates nowadays. 1099 ENCODING("FR32", ENCODING_IB) 1100 ENCODING("FR64", ENCODING_IB) 1101 ENCODING("FR128", ENCODING_IB) 1102 ENCODING("VR128", ENCODING_IB) 1103 ENCODING("VR256", ENCODING_IB) 1104 ENCODING("FR32X", ENCODING_IB) 1105 ENCODING("FR64X", ENCODING_IB) 1106 ENCODING("VR128X", ENCODING_IB) 1107 ENCODING("VR256X", ENCODING_IB) 1108 ENCODING("VR512", ENCODING_IB) 1109 errs() << "Unhandled immediate encoding " << s << "\n"; 1110 llvm_unreachable("Unhandled immediate encoding"); 1111 } 1112 1113 OperandEncoding 1114 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1115 uint8_t OpSize) { 1116 ENCODING("RST", ENCODING_FP) 1117 ENCODING("GR16", ENCODING_RM) 1118 ENCODING("GR32", ENCODING_RM) 1119 ENCODING("GR32orGR64", ENCODING_RM) 1120 ENCODING("GR64", ENCODING_RM) 1121 ENCODING("GR8", ENCODING_RM) 1122 ENCODING("VR128", ENCODING_RM) 1123 ENCODING("VR128X", ENCODING_RM) 1124 ENCODING("FR128", ENCODING_RM) 1125 ENCODING("FR64", ENCODING_RM) 1126 ENCODING("FR32", ENCODING_RM) 1127 ENCODING("FR64X", ENCODING_RM) 1128 ENCODING("FR32X", ENCODING_RM) 1129 ENCODING("VR64", ENCODING_RM) 1130 ENCODING("VR256", ENCODING_RM) 1131 ENCODING("VR256X", ENCODING_RM) 1132 ENCODING("VR512", ENCODING_RM) 1133 ENCODING("VK1", ENCODING_RM) 1134 ENCODING("VK2", ENCODING_RM) 1135 ENCODING("VK4", ENCODING_RM) 1136 ENCODING("VK8", ENCODING_RM) 1137 ENCODING("VK16", ENCODING_RM) 1138 ENCODING("VK32", ENCODING_RM) 1139 ENCODING("VK64", ENCODING_RM) 1140 ENCODING("BNDR", ENCODING_RM) 1141 errs() << "Unhandled R/M register encoding " << s << "\n"; 1142 llvm_unreachable("Unhandled R/M register encoding"); 1143 } 1144 1145 OperandEncoding 1146 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1147 uint8_t OpSize) { 1148 ENCODING("GR16", ENCODING_REG) 1149 ENCODING("GR32", ENCODING_REG) 1150 ENCODING("GR32orGR64", ENCODING_REG) 1151 ENCODING("GR64", ENCODING_REG) 1152 ENCODING("GR8", ENCODING_REG) 1153 ENCODING("VR128", ENCODING_REG) 1154 ENCODING("FR128", ENCODING_REG) 1155 ENCODING("FR64", ENCODING_REG) 1156 ENCODING("FR32", ENCODING_REG) 1157 ENCODING("VR64", ENCODING_REG) 1158 ENCODING("SEGMENT_REG", ENCODING_REG) 1159 ENCODING("DEBUG_REG", ENCODING_REG) 1160 ENCODING("CONTROL_REG", ENCODING_REG) 1161 ENCODING("VR256", ENCODING_REG) 1162 ENCODING("VR256X", ENCODING_REG) 1163 ENCODING("VR128X", ENCODING_REG) 1164 ENCODING("FR64X", ENCODING_REG) 1165 ENCODING("FR32X", ENCODING_REG) 1166 ENCODING("VR512", ENCODING_REG) 1167 ENCODING("VK1", ENCODING_REG) 1168 ENCODING("VK2", ENCODING_REG) 1169 ENCODING("VK4", ENCODING_REG) 1170 ENCODING("VK8", ENCODING_REG) 1171 ENCODING("VK16", ENCODING_REG) 1172 ENCODING("VK32", ENCODING_REG) 1173 ENCODING("VK64", ENCODING_REG) 1174 ENCODING("VK1WM", ENCODING_REG) 1175 ENCODING("VK2WM", ENCODING_REG) 1176 ENCODING("VK4WM", ENCODING_REG) 1177 ENCODING("VK8WM", ENCODING_REG) 1178 ENCODING("VK16WM", ENCODING_REG) 1179 ENCODING("VK32WM", ENCODING_REG) 1180 ENCODING("VK64WM", ENCODING_REG) 1181 ENCODING("BNDR", ENCODING_REG) 1182 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1183 llvm_unreachable("Unhandled reg/opcode register encoding"); 1184 } 1185 1186 OperandEncoding 1187 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1188 uint8_t OpSize) { 1189 ENCODING("GR32", ENCODING_VVVV) 1190 ENCODING("GR64", ENCODING_VVVV) 1191 ENCODING("FR32", ENCODING_VVVV) 1192 ENCODING("FR128", ENCODING_VVVV) 1193 ENCODING("FR64", ENCODING_VVVV) 1194 ENCODING("VR128", ENCODING_VVVV) 1195 ENCODING("VR256", ENCODING_VVVV) 1196 ENCODING("FR32X", ENCODING_VVVV) 1197 ENCODING("FR64X", ENCODING_VVVV) 1198 ENCODING("VR128X", ENCODING_VVVV) 1199 ENCODING("VR256X", ENCODING_VVVV) 1200 ENCODING("VR512", ENCODING_VVVV) 1201 ENCODING("VK1", ENCODING_VVVV) 1202 ENCODING("VK2", ENCODING_VVVV) 1203 ENCODING("VK4", ENCODING_VVVV) 1204 ENCODING("VK8", ENCODING_VVVV) 1205 ENCODING("VK16", ENCODING_VVVV) 1206 ENCODING("VK32", ENCODING_VVVV) 1207 ENCODING("VK64", ENCODING_VVVV) 1208 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1209 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1210 } 1211 1212 OperandEncoding 1213 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1214 uint8_t OpSize) { 1215 ENCODING("VK1WM", ENCODING_WRITEMASK) 1216 ENCODING("VK2WM", ENCODING_WRITEMASK) 1217 ENCODING("VK4WM", ENCODING_WRITEMASK) 1218 ENCODING("VK8WM", ENCODING_WRITEMASK) 1219 ENCODING("VK16WM", ENCODING_WRITEMASK) 1220 ENCODING("VK32WM", ENCODING_WRITEMASK) 1221 ENCODING("VK64WM", ENCODING_WRITEMASK) 1222 errs() << "Unhandled mask register encoding " << s << "\n"; 1223 llvm_unreachable("Unhandled mask register encoding"); 1224 } 1225 1226 OperandEncoding 1227 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1228 uint8_t OpSize) { 1229 ENCODING("i16mem", ENCODING_RM) 1230 ENCODING("i32mem", ENCODING_RM) 1231 ENCODING("i64mem", ENCODING_RM) 1232 ENCODING("i8mem", ENCODING_RM) 1233 ENCODING("ssmem", ENCODING_RM) 1234 ENCODING("sdmem", ENCODING_RM) 1235 ENCODING("f128mem", ENCODING_RM) 1236 ENCODING("f256mem", ENCODING_RM) 1237 ENCODING("f512mem", ENCODING_RM) 1238 ENCODING("f64mem", ENCODING_RM) 1239 ENCODING("f32mem", ENCODING_RM) 1240 ENCODING("i128mem", ENCODING_RM) 1241 ENCODING("i256mem", ENCODING_RM) 1242 ENCODING("i512mem", ENCODING_RM) 1243 ENCODING("f80mem", ENCODING_RM) 1244 ENCODING("lea64_32mem", ENCODING_RM) 1245 ENCODING("lea64mem", ENCODING_RM) 1246 ENCODING("anymem", ENCODING_RM) 1247 ENCODING("opaque32mem", ENCODING_RM) 1248 ENCODING("opaque48mem", ENCODING_RM) 1249 ENCODING("opaque80mem", ENCODING_RM) 1250 ENCODING("opaque512mem", ENCODING_RM) 1251 ENCODING("vx64mem", ENCODING_VSIB) 1252 ENCODING("vx128mem", ENCODING_VSIB) 1253 ENCODING("vx256mem", ENCODING_VSIB) 1254 ENCODING("vy128mem", ENCODING_VSIB) 1255 ENCODING("vy256mem", ENCODING_VSIB) 1256 ENCODING("vx64xmem", ENCODING_VSIB) 1257 ENCODING("vx128xmem", ENCODING_VSIB) 1258 ENCODING("vx256xmem", ENCODING_VSIB) 1259 ENCODING("vy128xmem", ENCODING_VSIB) 1260 ENCODING("vy256xmem", ENCODING_VSIB) 1261 ENCODING("vy512mem", ENCODING_VSIB) 1262 ENCODING("vz256xmem", ENCODING_VSIB) 1263 ENCODING("vz512mem", ENCODING_VSIB) 1264 errs() << "Unhandled memory encoding " << s << "\n"; 1265 llvm_unreachable("Unhandled memory encoding"); 1266 } 1267 1268 OperandEncoding 1269 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1270 uint8_t OpSize) { 1271 if(OpSize != X86Local::OpSize16) { 1272 // For instructions without an OpSize prefix, a declared 16-bit register or 1273 // immediate encoding is special. 1274 ENCODING("i16imm", ENCODING_IW) 1275 } 1276 ENCODING("i16imm", ENCODING_Iv) 1277 ENCODING("i16i8imm", ENCODING_IB) 1278 ENCODING("i32imm", ENCODING_Iv) 1279 ENCODING("i32i8imm", ENCODING_IB) 1280 ENCODING("i64i32imm", ENCODING_ID) 1281 ENCODING("i64i8imm", ENCODING_IB) 1282 ENCODING("i8imm", ENCODING_IB) 1283 ENCODING("u8imm", ENCODING_IB) 1284 ENCODING("i32u8imm", ENCODING_IB) 1285 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1286 ENCODING("i16imm_pcrel", ENCODING_IW) 1287 ENCODING("i32imm_pcrel", ENCODING_ID) 1288 ENCODING("brtarget32", ENCODING_Iv) 1289 ENCODING("brtarget16", ENCODING_Iv) 1290 ENCODING("brtarget8", ENCODING_IB) 1291 ENCODING("i64imm", ENCODING_IO) 1292 ENCODING("offset16_8", ENCODING_Ia) 1293 ENCODING("offset16_16", ENCODING_Ia) 1294 ENCODING("offset16_32", ENCODING_Ia) 1295 ENCODING("offset32_8", ENCODING_Ia) 1296 ENCODING("offset32_16", ENCODING_Ia) 1297 ENCODING("offset32_32", ENCODING_Ia) 1298 ENCODING("offset32_64", ENCODING_Ia) 1299 ENCODING("offset64_8", ENCODING_Ia) 1300 ENCODING("offset64_16", ENCODING_Ia) 1301 ENCODING("offset64_32", ENCODING_Ia) 1302 ENCODING("offset64_64", ENCODING_Ia) 1303 ENCODING("srcidx8", ENCODING_SI) 1304 ENCODING("srcidx16", ENCODING_SI) 1305 ENCODING("srcidx32", ENCODING_SI) 1306 ENCODING("srcidx64", ENCODING_SI) 1307 ENCODING("dstidx8", ENCODING_DI) 1308 ENCODING("dstidx16", ENCODING_DI) 1309 ENCODING("dstidx32", ENCODING_DI) 1310 ENCODING("dstidx64", ENCODING_DI) 1311 errs() << "Unhandled relocation encoding " << s << "\n"; 1312 llvm_unreachable("Unhandled relocation encoding"); 1313 } 1314 1315 OperandEncoding 1316 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1317 uint8_t OpSize) { 1318 ENCODING("GR32", ENCODING_Rv) 1319 ENCODING("GR64", ENCODING_RO) 1320 ENCODING("GR16", ENCODING_Rv) 1321 ENCODING("GR8", ENCODING_RB) 1322 ENCODING("GR32_NOAX", ENCODING_Rv) 1323 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1324 llvm_unreachable("Unhandled opcode modifier encoding"); 1325 } 1326 #undef ENCODING 1327