1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 #define THREE_BYTE_38_EXTENSION_TABLES \
123   EXTENSION_TABLE(F3)
124 
125 using namespace X86Disassembler;
126 
127 /// needsModRMForDecode - Indicates whether a particular instruction requires a
128 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
129 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
130 ///   0b11.
131 ///
132 /// @param form - The form of the instruction.
133 /// @return     - true if the form implies that a ModR/M byte is required, false
134 ///               otherwise.
135 static bool needsModRMForDecode(uint8_t form) {
136   if (form == X86Local::MRMDestReg    ||
137      form == X86Local::MRMDestMem    ||
138      form == X86Local::MRMSrcReg     ||
139      form == X86Local::MRMSrcMem     ||
140      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
141      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142     return true;
143   else
144     return false;
145 }
146 
147 /// isRegFormat - Indicates whether a particular form requires the Mod field of
148 ///   the ModR/M byte to be 0b11.
149 ///
150 /// @param form - The form of the instruction.
151 /// @return     - true if the form implies that Mod must be 0b11, false
152 ///               otherwise.
153 static bool isRegFormat(uint8_t form) {
154   if (form == X86Local::MRMDestReg ||
155      form == X86Local::MRMSrcReg  ||
156      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157     return true;
158   else
159     return false;
160 }
161 
162 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
163 ///   Useful for switch statements and the like.
164 ///
165 /// @param init - A reference to the BitsInit to be decoded.
166 /// @return     - The field, with the first bit in the BitsInit as the lowest
167 ///               order bit.
168 static uint8_t byteFromBitsInit(BitsInit &init) {
169   int width = init.getNumBits();
170 
171   assert(width <= 8 && "Field is too large for uint8_t!");
172 
173   int     index;
174   uint8_t mask = 0x01;
175 
176   uint8_t ret = 0;
177 
178   for (index = 0; index < width; index++) {
179     if (static_cast<BitInit*>(init.getBit(index))->getValue())
180       ret |= mask;
181 
182     mask <<= 1;
183   }
184 
185   return ret;
186 }
187 
188 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
189 ///   name of the field.
190 ///
191 /// @param rec  - The record from which to extract the value.
192 /// @param name - The name of the field in the record.
193 /// @return     - The field, as translated by byteFromBitsInit().
194 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
195   BitsInit* bits = rec->getValueAsBitsInit(name);
196   return byteFromBitsInit(*bits);
197 }
198 
199 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
200                                      const CodeGenInstruction &insn,
201                                      InstrUID uid) {
202   UID = uid;
203 
204   Rec = insn.TheDef;
205   Name = Rec->getName();
206   Spec = &tables.specForUID(UID);
207 
208   if (!Rec->isSubClassOf("X86Inst")) {
209     ShouldBeEmitted = false;
210     return;
211   }
212 
213   Prefix   = byteFromRec(Rec, "Prefix");
214   Opcode   = byteFromRec(Rec, "Opcode");
215   Form     = byteFromRec(Rec, "FormBits");
216   SegOvr   = byteFromRec(Rec, "SegOvrBits");
217 
218   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
219   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
220   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
221   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
222   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
223   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
224   HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
225   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
226   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
227   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
228 
229   Name      = Rec->getName();
230   AsmString = Rec->getValueAsString("AsmString");
231 
232   Operands = &insn.Operands.OperandList;
233 
234   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
235                      (Name.find("CRC32") != Name.npos);
236   HasFROperands    = hasFROperands();
237   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
238 
239   // Check for 64-bit inst which does not require REX
240   Is32Bit = false;
241   Is64Bit = false;
242   // FIXME: Is there some better way to check for In64BitMode?
243   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
244   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
245     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
246       Is32Bit = true;
247       break;
248     }
249     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
250       Is64Bit = true;
251       break;
252     }
253   }
254   // FIXME: These instructions aren't marked as 64-bit in any way
255   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
256              Rec->getName() == "MASKMOVDQU64" ||
257              Rec->getName() == "POPFS64" ||
258              Rec->getName() == "POPGS64" ||
259              Rec->getName() == "PUSHFS64" ||
260              Rec->getName() == "PUSHGS64" ||
261              Rec->getName() == "REX64_PREFIX" ||
262              Rec->getName().find("MOV64") != Name.npos ||
263              Rec->getName().find("PUSH64") != Name.npos ||
264              Rec->getName().find("POP64") != Name.npos;
265 
266   ShouldBeEmitted  = true;
267 }
268 
269 void RecognizableInstr::processInstr(DisassemblerTables &tables,
270 	const CodeGenInstruction &insn,
271                                    InstrUID uid)
272 {
273   // Ignore "asm parser only" instructions.
274   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
275     return;
276 
277   RecognizableInstr recogInstr(tables, insn, uid);
278 
279   recogInstr.emitInstructionSpecifier(tables);
280 
281   if (recogInstr.shouldBeEmitted())
282     recogInstr.emitDecodePath(tables);
283 }
284 
285 InstructionContext RecognizableInstr::insnContext() const {
286   InstructionContext insnContext;
287 
288   if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
289     if (HasVEX_LPrefix && HasVEX_WPrefix) {
290       if (HasOpSizePrefix)
291         insnContext = IC_VEX_L_W_OPSIZE;
292       else
293         llvm_unreachable("Don't support VEX.L and VEX.W together");
294     } else if (HasOpSizePrefix && HasVEX_LPrefix)
295       insnContext = IC_VEX_L_OPSIZE;
296     else if (HasOpSizePrefix && HasVEX_WPrefix)
297       insnContext = IC_VEX_W_OPSIZE;
298     else if (HasOpSizePrefix)
299       insnContext = IC_VEX_OPSIZE;
300     else if (HasVEX_LPrefix &&
301              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
302       insnContext = IC_VEX_L_XS;
303     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
304                                 Prefix == X86Local::T8XD ||
305                                 Prefix == X86Local::TAXD))
306       insnContext = IC_VEX_L_XD;
307     else if (HasVEX_WPrefix &&
308              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
309       insnContext = IC_VEX_W_XS;
310     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
311                                 Prefix == X86Local::T8XD ||
312                                 Prefix == X86Local::TAXD))
313       insnContext = IC_VEX_W_XD;
314     else if (HasVEX_WPrefix)
315       insnContext = IC_VEX_W;
316     else if (HasVEX_LPrefix)
317       insnContext = IC_VEX_L;
318     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
319              Prefix == X86Local::TAXD)
320       insnContext = IC_VEX_XD;
321     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
322       insnContext = IC_VEX_XS;
323     else
324       insnContext = IC_VEX;
325   } else if (Is64Bit || HasREX_WPrefix) {
326     if (HasREX_WPrefix && HasOpSizePrefix)
327       insnContext = IC_64BIT_REXW_OPSIZE;
328     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
329                                  Prefix == X86Local::T8XD ||
330                                  Prefix == X86Local::TAXD))
331       insnContext = IC_64BIT_XD_OPSIZE;
332     else if (HasOpSizePrefix &&
333              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
334       insnContext = IC_64BIT_XS_OPSIZE;
335     else if (HasOpSizePrefix)
336       insnContext = IC_64BIT_OPSIZE;
337     else if (HasREX_WPrefix &&
338              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
339       insnContext = IC_64BIT_REXW_XS;
340     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
341                                 Prefix == X86Local::T8XD ||
342                                 Prefix == X86Local::TAXD))
343       insnContext = IC_64BIT_REXW_XD;
344     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
345              Prefix == X86Local::TAXD)
346       insnContext = IC_64BIT_XD;
347     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
348       insnContext = IC_64BIT_XS;
349     else if (HasREX_WPrefix)
350       insnContext = IC_64BIT_REXW;
351     else
352       insnContext = IC_64BIT;
353   } else {
354     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
355                             Prefix == X86Local::T8XD ||
356                             Prefix == X86Local::TAXD))
357       insnContext = IC_XD_OPSIZE;
358     else if (HasOpSizePrefix &&
359              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
360       insnContext = IC_XS_OPSIZE;
361     else if (HasOpSizePrefix)
362       insnContext = IC_OPSIZE;
363     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
364              Prefix == X86Local::TAXD)
365       insnContext = IC_XD;
366     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
367              Prefix == X86Local::REP)
368       insnContext = IC_XS;
369     else
370       insnContext = IC;
371   }
372 
373   return insnContext;
374 }
375 
376 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
377   ///////////////////
378   // FILTER_STRONG
379   //
380 
381   // Filter out intrinsics
382 
383   if (!Rec->isSubClassOf("X86Inst"))
384     return FILTER_STRONG;
385 
386   if (Form == X86Local::Pseudo ||
387       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
388     return FILTER_STRONG;
389 
390   if (Form == X86Local::MRMInitReg)
391     return FILTER_STRONG;
392 
393 
394   // Filter out artificial instructions
395 
396   if (Name.find("_Int") != Name.npos       ||
397       Name.find("Int_") != Name.npos       ||
398       Name.find("_NOREX") != Name.npos     ||
399       Name.find("2SDL") != Name.npos       ||
400       Name == "LOCK_PREFIX")
401     return FILTER_STRONG;
402 
403   // Filter out instructions with segment override prefixes.
404   // They're too messy to handle now and we'll special case them if needed.
405 
406   if (SegOvr)
407     return FILTER_STRONG;
408 
409   // Filter out instructions that can't be printed.
410 
411   if (AsmString.size() == 0)
412     return FILTER_STRONG;
413 
414   // Filter out instructions with subreg operands.
415 
416   if (AsmString.find("subreg") != AsmString.npos)
417     return FILTER_STRONG;
418 
419   /////////////////
420   // FILTER_WEAK
421   //
422 
423 
424   // Filter out instructions with a LOCK prefix;
425   //   prefer forms that do not have the prefix
426   if (HasLockPrefix)
427     return FILTER_WEAK;
428 
429   // Filter out alternate forms of AVX instructions
430   if (Name.find("_alt") != Name.npos ||
431       Name.find("XrYr") != Name.npos ||
432       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
433       Name.find("_64mr") != Name.npos ||
434       Name.find("Xrr") != Name.npos ||
435       Name.find("rr64") != Name.npos)
436     return FILTER_WEAK;
437 
438   // Special cases.
439 
440   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
441     return FILTER_WEAK;
442   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
443     return FILTER_WEAK;
444 
445   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
446     return FILTER_WEAK;
447   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
448     return FILTER_WEAK;
449   if (Name.find("Fs") != Name.npos)
450     return FILTER_WEAK;
451   if (Name == "PUSH64i16"         ||
452       Name == "MOVPQI2QImr"       ||
453       Name == "VMOVPQI2QImr"      ||
454       Name == "MMX_MOVD64rrv164"  ||
455       Name == "MOV64ri64i32"      ||
456       Name == "VMASKMOVDQU64"     ||
457       Name == "VEXTRACTPSrr64"    ||
458       Name == "VMOVQd64rr"        ||
459       Name == "VMOVQs64rr")
460     return FILTER_WEAK;
461 
462   if (HasFROperands && Name.find("MOV") != Name.npos &&
463      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
464       (Name.find("to") != Name.npos)))
465     return FILTER_WEAK;
466 
467   return FILTER_NORMAL;
468 }
469 
470 bool RecognizableInstr::hasFROperands() const {
471   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
472   unsigned numOperands = OperandList.size();
473 
474   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
475     const std::string &recName = OperandList[operandIndex].Rec->getName();
476 
477     if (recName.find("FR") != recName.npos)
478       return true;
479   }
480   return false;
481 }
482 
483 bool RecognizableInstr::has256BitOperands() const {
484   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
485   unsigned numOperands = OperandList.size();
486 
487   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
488     const std::string &recName = OperandList[operandIndex].Rec->getName();
489 
490     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
491       return true;
492     }
493   }
494   return false;
495 }
496 
497 void RecognizableInstr::handleOperand(
498   bool optional,
499   unsigned &operandIndex,
500   unsigned &physicalOperandIndex,
501   unsigned &numPhysicalOperands,
502   unsigned *operandMapping,
503   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
504   if (optional) {
505     if (physicalOperandIndex >= numPhysicalOperands)
506       return;
507   } else {
508     assert(physicalOperandIndex < numPhysicalOperands);
509   }
510 
511   while (operandMapping[operandIndex] != operandIndex) {
512     Spec->operands[operandIndex].encoding = ENCODING_DUP;
513     Spec->operands[operandIndex].type =
514       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
515     ++operandIndex;
516   }
517 
518   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
519 
520   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
521                                                               HasOpSizePrefix);
522   Spec->operands[operandIndex].type = typeFromString(typeName,
523                                                      IsSSE,
524                                                      HasREX_WPrefix,
525                                                      HasOpSizePrefix);
526 
527   ++operandIndex;
528   ++physicalOperandIndex;
529 }
530 
531 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
532   Spec->name       = Name;
533 
534   if (!Rec->isSubClassOf("X86Inst"))
535     return;
536 
537   switch (filter()) {
538   case FILTER_WEAK:
539     Spec->filtered = true;
540     break;
541   case FILTER_STRONG:
542     ShouldBeEmitted = false;
543     return;
544   case FILTER_NORMAL:
545     break;
546   }
547 
548   Spec->insnContext = insnContext();
549 
550   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
551 
552   unsigned operandIndex;
553   unsigned numOperands = OperandList.size();
554   unsigned numPhysicalOperands = 0;
555 
556   // operandMapping maps from operands in OperandList to their originals.
557   // If operandMapping[i] != i, then the entry is a duplicate.
558   unsigned operandMapping[X86_MAX_OPERANDS];
559 
560   bool hasFROperands = false;
561 
562   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
563 
564   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
565     if (OperandList[operandIndex].Constraints.size()) {
566       const CGIOperandList::ConstraintInfo &Constraint =
567         OperandList[operandIndex].Constraints[0];
568       if (Constraint.isTied()) {
569         operandMapping[operandIndex] = Constraint.getTiedOperand();
570       } else {
571         ++numPhysicalOperands;
572         operandMapping[operandIndex] = operandIndex;
573       }
574     } else {
575       ++numPhysicalOperands;
576       operandMapping[operandIndex] = operandIndex;
577     }
578 
579     const std::string &recName = OperandList[operandIndex].Rec->getName();
580 
581     if (recName.find("FR") != recName.npos)
582       hasFROperands = true;
583   }
584 
585   if (hasFROperands && Name.find("MOV") != Name.npos &&
586      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
587       (Name.find("to") != Name.npos)))
588     ShouldBeEmitted = false;
589 
590   if (!ShouldBeEmitted)
591     return;
592 
593 #define HANDLE_OPERAND(class)               \
594   handleOperand(false,                      \
595                 operandIndex,               \
596                 physicalOperandIndex,       \
597                 numPhysicalOperands,        \
598                 operandMapping,             \
599                 class##EncodingFromString);
600 
601 #define HANDLE_OPTIONAL(class)              \
602   handleOperand(true,                       \
603                 operandIndex,               \
604                 physicalOperandIndex,       \
605                 numPhysicalOperands,        \
606                 operandMapping,             \
607                 class##EncodingFromString);
608 
609   // operandIndex should always be < numOperands
610   operandIndex = 0;
611   // physicalOperandIndex should always be < numPhysicalOperands
612   unsigned physicalOperandIndex = 0;
613 
614   switch (Form) {
615   case X86Local::RawFrm:
616     // Operand 1 (optional) is an address or immediate.
617     // Operand 2 (optional) is an immediate.
618     assert(numPhysicalOperands <= 2 &&
619            "Unexpected number of operands for RawFrm");
620     HANDLE_OPTIONAL(relocation)
621     HANDLE_OPTIONAL(immediate)
622     break;
623   case X86Local::AddRegFrm:
624     // Operand 1 is added to the opcode.
625     // Operand 2 (optional) is an address.
626     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
627            "Unexpected number of operands for AddRegFrm");
628     HANDLE_OPERAND(opcodeModifier)
629     HANDLE_OPTIONAL(relocation)
630     break;
631   case X86Local::MRMDestReg:
632     // Operand 1 is a register operand in the R/M field.
633     // Operand 2 is a register operand in the Reg/Opcode field.
634     // - In AVX, there is a register operand in the VEX.vvvv field here -
635     // Operand 3 (optional) is an immediate.
636     if (HasVEX_4VPrefix)
637       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
638              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
639     else
640       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
641              "Unexpected number of operands for MRMDestRegFrm");
642 
643     HANDLE_OPERAND(rmRegister)
644 
645     if (HasVEX_4VPrefix)
646       // FIXME: In AVX, the register below becomes the one encoded
647       // in ModRMVEX and the one above the one in the VEX.VVVV field
648       HANDLE_OPERAND(vvvvRegister)
649 
650     HANDLE_OPERAND(roRegister)
651     HANDLE_OPTIONAL(immediate)
652     break;
653   case X86Local::MRMDestMem:
654     // Operand 1 is a memory operand (possibly SIB-extended)
655     // Operand 2 is a register operand in the Reg/Opcode field.
656     // - In AVX, there is a register operand in the VEX.vvvv field here -
657     // Operand 3 (optional) is an immediate.
658     if (HasVEX_4VPrefix)
659       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
660              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
661     else
662       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
663              "Unexpected number of operands for MRMDestMemFrm");
664     HANDLE_OPERAND(memory)
665 
666     if (HasVEX_4VPrefix)
667       // FIXME: In AVX, the register below becomes the one encoded
668       // in ModRMVEX and the one above the one in the VEX.VVVV field
669       HANDLE_OPERAND(vvvvRegister)
670 
671     HANDLE_OPERAND(roRegister)
672     HANDLE_OPTIONAL(immediate)
673     break;
674   case X86Local::MRMSrcReg:
675     // Operand 1 is a register operand in the Reg/Opcode field.
676     // Operand 2 is a register operand in the R/M field.
677     // - In AVX, there is a register operand in the VEX.vvvv field here -
678     // Operand 3 (optional) is an immediate.
679 
680     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
681       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
682              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
683     else
684       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
685              "Unexpected number of operands for MRMSrcRegFrm");
686 
687     HANDLE_OPERAND(roRegister)
688 
689     if (HasVEX_4VPrefix)
690       // FIXME: In AVX, the register below becomes the one encoded
691       // in ModRMVEX and the one above the one in the VEX.VVVV field
692       HANDLE_OPERAND(vvvvRegister)
693 
694     if (HasMemOp4Prefix)
695       HANDLE_OPERAND(immediate)
696 
697     HANDLE_OPERAND(rmRegister)
698 
699     if (HasVEX_4VOp3Prefix)
700       HANDLE_OPERAND(vvvvRegister)
701 
702     if (!HasMemOp4Prefix)
703       HANDLE_OPTIONAL(immediate)
704     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
705     break;
706   case X86Local::MRMSrcMem:
707     // Operand 1 is a register operand in the Reg/Opcode field.
708     // Operand 2 is a memory operand (possibly SIB-extended)
709     // - In AVX, there is a register operand in the VEX.vvvv field here -
710     // Operand 3 (optional) is an immediate.
711 
712     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
713       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
714              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
715     else
716       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
717              "Unexpected number of operands for MRMSrcMemFrm");
718 
719     HANDLE_OPERAND(roRegister)
720 
721     if (HasVEX_4VPrefix)
722       // FIXME: In AVX, the register below becomes the one encoded
723       // in ModRMVEX and the one above the one in the VEX.VVVV field
724       HANDLE_OPERAND(vvvvRegister)
725 
726     if (HasMemOp4Prefix)
727       HANDLE_OPERAND(immediate)
728 
729     HANDLE_OPERAND(memory)
730 
731     if (HasVEX_4VOp3Prefix)
732       HANDLE_OPERAND(vvvvRegister)
733 
734     if (!HasMemOp4Prefix)
735       HANDLE_OPTIONAL(immediate)
736     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
737     break;
738   case X86Local::MRM0r:
739   case X86Local::MRM1r:
740   case X86Local::MRM2r:
741   case X86Local::MRM3r:
742   case X86Local::MRM4r:
743   case X86Local::MRM5r:
744   case X86Local::MRM6r:
745   case X86Local::MRM7r:
746     // Operand 1 is a register operand in the R/M field.
747     // Operand 2 (optional) is an immediate or relocation.
748     if (HasVEX_4VPrefix)
749       assert(numPhysicalOperands <= 3 &&
750              "Unexpected number of operands for MRMnRFrm with VEX_4V");
751     else
752       assert(numPhysicalOperands <= 2 &&
753              "Unexpected number of operands for MRMnRFrm");
754     if (HasVEX_4VPrefix)
755       HANDLE_OPERAND(vvvvRegister)
756     HANDLE_OPTIONAL(rmRegister)
757     HANDLE_OPTIONAL(relocation)
758     break;
759   case X86Local::MRM0m:
760   case X86Local::MRM1m:
761   case X86Local::MRM2m:
762   case X86Local::MRM3m:
763   case X86Local::MRM4m:
764   case X86Local::MRM5m:
765   case X86Local::MRM6m:
766   case X86Local::MRM7m:
767     // Operand 1 is a memory operand (possibly SIB-extended)
768     // Operand 2 (optional) is an immediate or relocation.
769     if (HasVEX_4VPrefix)
770       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
771              "Unexpected number of operands for MRMnMFrm");
772     else
773       assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
774              "Unexpected number of operands for MRMnMFrm");
775     if (HasVEX_4VPrefix)
776       HANDLE_OPERAND(vvvvRegister)
777     HANDLE_OPERAND(memory)
778     HANDLE_OPTIONAL(relocation)
779     break;
780   case X86Local::RawFrmImm8:
781     // operand 1 is a 16-bit immediate
782     // operand 2 is an 8-bit immediate
783     assert(numPhysicalOperands == 2 &&
784            "Unexpected number of operands for X86Local::RawFrmImm8");
785     HANDLE_OPERAND(immediate)
786     HANDLE_OPERAND(immediate)
787     break;
788   case X86Local::RawFrmImm16:
789     // operand 1 is a 16-bit immediate
790     // operand 2 is a 16-bit immediate
791     HANDLE_OPERAND(immediate)
792     HANDLE_OPERAND(immediate)
793     break;
794   case X86Local::MRMInitReg:
795     // Ignored.
796     break;
797   }
798 
799   #undef HANDLE_OPERAND
800   #undef HANDLE_OPTIONAL
801 }
802 
803 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
804   // Special cases where the LLVM tables are not complete
805 
806 #define MAP(from, to)                     \
807   case X86Local::MRM_##from:              \
808     filter = new ExactFilter(0x##from);   \
809     break;
810 
811   OpcodeType    opcodeType  = (OpcodeType)-1;
812 
813   ModRMFilter*  filter      = NULL;
814   uint8_t       opcodeToSet = 0;
815 
816   switch (Prefix) {
817   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
818   case X86Local::XD:
819   case X86Local::XS:
820   case X86Local::TB:
821     opcodeType = TWOBYTE;
822 
823     switch (Opcode) {
824     default:
825       if (needsModRMForDecode(Form))
826         filter = new ModFilter(isRegFormat(Form));
827       else
828         filter = new DumbFilter();
829       break;
830 #define EXTENSION_TABLE(n) case 0x##n:
831     TWO_BYTE_EXTENSION_TABLES
832 #undef EXTENSION_TABLE
833       switch (Form) {
834       default:
835         llvm_unreachable("Unhandled two-byte extended opcode");
836       case X86Local::MRM0r:
837       case X86Local::MRM1r:
838       case X86Local::MRM2r:
839       case X86Local::MRM3r:
840       case X86Local::MRM4r:
841       case X86Local::MRM5r:
842       case X86Local::MRM6r:
843       case X86Local::MRM7r:
844         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
845         break;
846       case X86Local::MRM0m:
847       case X86Local::MRM1m:
848       case X86Local::MRM2m:
849       case X86Local::MRM3m:
850       case X86Local::MRM4m:
851       case X86Local::MRM5m:
852       case X86Local::MRM6m:
853       case X86Local::MRM7m:
854         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
855         break;
856       MRM_MAPPING
857       } // switch (Form)
858       break;
859     } // switch (Opcode)
860     opcodeToSet = Opcode;
861     break;
862   case X86Local::T8:
863   case X86Local::T8XD:
864   case X86Local::T8XS:
865     opcodeType = THREEBYTE_38;
866     switch (Opcode) {
867     default:
868       if (needsModRMForDecode(Form))
869         filter = new ModFilter(isRegFormat(Form));
870       else
871         filter = new DumbFilter();
872       break;
873 #define EXTENSION_TABLE(n) case 0x##n:
874     THREE_BYTE_38_EXTENSION_TABLES
875 #undef EXTENSION_TABLE
876       switch (Form) {
877       default:
878         llvm_unreachable("Unhandled two-byte extended opcode");
879       case X86Local::MRM0r:
880       case X86Local::MRM1r:
881       case X86Local::MRM2r:
882       case X86Local::MRM3r:
883       case X86Local::MRM4r:
884       case X86Local::MRM5r:
885       case X86Local::MRM6r:
886       case X86Local::MRM7r:
887         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
888         break;
889       case X86Local::MRM0m:
890       case X86Local::MRM1m:
891       case X86Local::MRM2m:
892       case X86Local::MRM3m:
893       case X86Local::MRM4m:
894       case X86Local::MRM5m:
895       case X86Local::MRM6m:
896       case X86Local::MRM7m:
897         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
898         break;
899       MRM_MAPPING
900       } // switch (Form)
901       break;
902     } // switch (Opcode)
903     opcodeToSet = Opcode;
904     break;
905   case X86Local::P_TA:
906   case X86Local::TAXD:
907     opcodeType = THREEBYTE_3A;
908     if (needsModRMForDecode(Form))
909       filter = new ModFilter(isRegFormat(Form));
910     else
911       filter = new DumbFilter();
912     opcodeToSet = Opcode;
913     break;
914   case X86Local::A6:
915     opcodeType = THREEBYTE_A6;
916     if (needsModRMForDecode(Form))
917       filter = new ModFilter(isRegFormat(Form));
918     else
919       filter = new DumbFilter();
920     opcodeToSet = Opcode;
921     break;
922   case X86Local::A7:
923     opcodeType = THREEBYTE_A7;
924     if (needsModRMForDecode(Form))
925       filter = new ModFilter(isRegFormat(Form));
926     else
927       filter = new DumbFilter();
928     opcodeToSet = Opcode;
929     break;
930   case X86Local::D8:
931   case X86Local::D9:
932   case X86Local::DA:
933   case X86Local::DB:
934   case X86Local::DC:
935   case X86Local::DD:
936   case X86Local::DE:
937   case X86Local::DF:
938     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
939     opcodeType = ONEBYTE;
940     if (Form == X86Local::AddRegFrm) {
941       Spec->modifierType = MODIFIER_MODRM;
942       Spec->modifierBase = Opcode;
943       filter = new AddRegEscapeFilter(Opcode);
944     } else {
945       filter = new EscapeFilter(true, Opcode);
946     }
947     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
948     break;
949   case X86Local::REP:
950   default:
951     opcodeType = ONEBYTE;
952     switch (Opcode) {
953 #define EXTENSION_TABLE(n) case 0x##n:
954     ONE_BYTE_EXTENSION_TABLES
955 #undef EXTENSION_TABLE
956       switch (Form) {
957       default:
958         llvm_unreachable("Fell through the cracks of a single-byte "
959                          "extended opcode");
960       case X86Local::MRM0r:
961       case X86Local::MRM1r:
962       case X86Local::MRM2r:
963       case X86Local::MRM3r:
964       case X86Local::MRM4r:
965       case X86Local::MRM5r:
966       case X86Local::MRM6r:
967       case X86Local::MRM7r:
968         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
969         break;
970       case X86Local::MRM0m:
971       case X86Local::MRM1m:
972       case X86Local::MRM2m:
973       case X86Local::MRM3m:
974       case X86Local::MRM4m:
975       case X86Local::MRM5m:
976       case X86Local::MRM6m:
977       case X86Local::MRM7m:
978         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
979         break;
980       MRM_MAPPING
981       } // switch (Form)
982       break;
983     case 0xd8:
984     case 0xd9:
985     case 0xda:
986     case 0xdb:
987     case 0xdc:
988     case 0xdd:
989     case 0xde:
990     case 0xdf:
991       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
992       break;
993     default:
994       if (needsModRMForDecode(Form))
995         filter = new ModFilter(isRegFormat(Form));
996       else
997         filter = new DumbFilter();
998       break;
999     } // switch (Opcode)
1000     opcodeToSet = Opcode;
1001   } // switch (Prefix)
1002 
1003   assert(opcodeType != (OpcodeType)-1 &&
1004          "Opcode type not set");
1005   assert(filter && "Filter not set");
1006 
1007   if (Form == X86Local::AddRegFrm) {
1008     if(Spec->modifierType != MODIFIER_MODRM) {
1009       assert(opcodeToSet < 0xf9 &&
1010              "Not enough room for all ADDREG_FRM operands");
1011 
1012       uint8_t currentOpcode;
1013 
1014       for (currentOpcode = opcodeToSet;
1015            currentOpcode < opcodeToSet + 8;
1016            ++currentOpcode)
1017         tables.setTableFields(opcodeType,
1018                               insnContext(),
1019                               currentOpcode,
1020                               *filter,
1021                               UID, Is32Bit, IgnoresVEX_L);
1022 
1023       Spec->modifierType = MODIFIER_OPCODE;
1024       Spec->modifierBase = opcodeToSet;
1025     } else {
1026       // modifierBase was set where MODIFIER_MODRM was set
1027       tables.setTableFields(opcodeType,
1028                             insnContext(),
1029                             opcodeToSet,
1030                             *filter,
1031                             UID, Is32Bit, IgnoresVEX_L);
1032     }
1033   } else {
1034     tables.setTableFields(opcodeType,
1035                           insnContext(),
1036                           opcodeToSet,
1037                           *filter,
1038                           UID, Is32Bit, IgnoresVEX_L);
1039 
1040     Spec->modifierType = MODIFIER_NONE;
1041     Spec->modifierBase = opcodeToSet;
1042   }
1043 
1044   delete filter;
1045 
1046 #undef MAP
1047 }
1048 
1049 #define TYPE(str, type) if (s == str) return type;
1050 OperandType RecognizableInstr::typeFromString(const std::string &s,
1051                                               bool isSSE,
1052                                               bool hasREX_WPrefix,
1053                                               bool hasOpSizePrefix) {
1054   if (isSSE) {
1055     // For SSE instructions, we ignore the OpSize prefix and force operand
1056     // sizes.
1057     TYPE("GR16",              TYPE_R16)
1058     TYPE("GR32",              TYPE_R32)
1059     TYPE("GR64",              TYPE_R64)
1060   }
1061   if(hasREX_WPrefix) {
1062     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1063     // is special.
1064     TYPE("GR32",              TYPE_R32)
1065   }
1066   if(!hasOpSizePrefix) {
1067     // For instructions without an OpSize prefix, a declared 16-bit register or
1068     // immediate encoding is special.
1069     TYPE("GR16",              TYPE_R16)
1070     TYPE("i16imm",            TYPE_IMM16)
1071   }
1072   TYPE("i16mem",              TYPE_Mv)
1073   TYPE("i16imm",              TYPE_IMMv)
1074   TYPE("i16i8imm",            TYPE_IMMv)
1075   TYPE("GR16",                TYPE_Rv)
1076   TYPE("i32mem",              TYPE_Mv)
1077   TYPE("i32imm",              TYPE_IMMv)
1078   TYPE("i32i8imm",            TYPE_IMM32)
1079   TYPE("u32u8imm",            TYPE_IMM32)
1080   TYPE("GR32",                TYPE_Rv)
1081   TYPE("i64mem",              TYPE_Mv)
1082   TYPE("i64i32imm",           TYPE_IMM64)
1083   TYPE("i64i8imm",            TYPE_IMM64)
1084   TYPE("GR64",                TYPE_R64)
1085   TYPE("i8mem",               TYPE_M8)
1086   TYPE("i8imm",               TYPE_IMM8)
1087   TYPE("GR8",                 TYPE_R8)
1088   TYPE("VR128",               TYPE_XMM128)
1089   TYPE("f128mem",             TYPE_M128)
1090   TYPE("f256mem",             TYPE_M256)
1091   TYPE("FR64",                TYPE_XMM64)
1092   TYPE("f64mem",              TYPE_M64FP)
1093   TYPE("sdmem",               TYPE_M64FP)
1094   TYPE("FR32",                TYPE_XMM32)
1095   TYPE("f32mem",              TYPE_M32FP)
1096   TYPE("ssmem",               TYPE_M32FP)
1097   TYPE("RST",                 TYPE_ST)
1098   TYPE("i128mem",             TYPE_M128)
1099   TYPE("i256mem",             TYPE_M256)
1100   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1101   TYPE("i16imm_pcrel",        TYPE_REL16)
1102   TYPE("i32imm_pcrel",        TYPE_REL32)
1103   TYPE("SSECC",               TYPE_IMM3)
1104   TYPE("brtarget",            TYPE_RELv)
1105   TYPE("uncondbrtarget",      TYPE_RELv)
1106   TYPE("brtarget8",           TYPE_REL8)
1107   TYPE("f80mem",              TYPE_M80FP)
1108   TYPE("lea32mem",            TYPE_LEA)
1109   TYPE("lea64_32mem",         TYPE_LEA)
1110   TYPE("lea64mem",            TYPE_LEA)
1111   TYPE("VR64",                TYPE_MM64)
1112   TYPE("i64imm",              TYPE_IMMv)
1113   TYPE("opaque32mem",         TYPE_M1616)
1114   TYPE("opaque48mem",         TYPE_M1632)
1115   TYPE("opaque80mem",         TYPE_M1664)
1116   TYPE("opaque512mem",        TYPE_M512)
1117   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1118   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1119   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1120   TYPE("offset8",             TYPE_MOFFS8)
1121   TYPE("offset16",            TYPE_MOFFS16)
1122   TYPE("offset32",            TYPE_MOFFS32)
1123   TYPE("offset64",            TYPE_MOFFS64)
1124   TYPE("VR256",               TYPE_XMM256)
1125   TYPE("GR16_NOAX",           TYPE_Rv)
1126   TYPE("GR32_NOAX",           TYPE_Rv)
1127   TYPE("GR64_NOAX",           TYPE_R64)
1128   errs() << "Unhandled type string " << s << "\n";
1129   llvm_unreachable("Unhandled type string");
1130 }
1131 #undef TYPE
1132 
1133 #define ENCODING(str, encoding) if (s == str) return encoding;
1134 OperandEncoding RecognizableInstr::immediateEncodingFromString
1135   (const std::string &s,
1136    bool hasOpSizePrefix) {
1137   if(!hasOpSizePrefix) {
1138     // For instructions without an OpSize prefix, a declared 16-bit register or
1139     // immediate encoding is special.
1140     ENCODING("i16imm",        ENCODING_IW)
1141   }
1142   ENCODING("i32i8imm",        ENCODING_IB)
1143   ENCODING("u32u8imm",        ENCODING_IB)
1144   ENCODING("SSECC",           ENCODING_IB)
1145   ENCODING("i16imm",          ENCODING_Iv)
1146   ENCODING("i16i8imm",        ENCODING_IB)
1147   ENCODING("i32imm",          ENCODING_Iv)
1148   ENCODING("i64i32imm",       ENCODING_ID)
1149   ENCODING("i64i8imm",        ENCODING_IB)
1150   ENCODING("i8imm",           ENCODING_IB)
1151   // This is not a typo.  Instructions like BLENDVPD put
1152   // register IDs in 8-bit immediates nowadays.
1153   ENCODING("VR256",           ENCODING_IB)
1154   ENCODING("VR128",           ENCODING_IB)
1155   errs() << "Unhandled immediate encoding " << s << "\n";
1156   llvm_unreachable("Unhandled immediate encoding");
1157 }
1158 
1159 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1160   (const std::string &s,
1161    bool hasOpSizePrefix) {
1162   ENCODING("GR16",            ENCODING_RM)
1163   ENCODING("GR32",            ENCODING_RM)
1164   ENCODING("GR64",            ENCODING_RM)
1165   ENCODING("GR8",             ENCODING_RM)
1166   ENCODING("VR128",           ENCODING_RM)
1167   ENCODING("FR64",            ENCODING_RM)
1168   ENCODING("FR32",            ENCODING_RM)
1169   ENCODING("VR64",            ENCODING_RM)
1170   ENCODING("VR256",           ENCODING_RM)
1171   errs() << "Unhandled R/M register encoding " << s << "\n";
1172   llvm_unreachable("Unhandled R/M register encoding");
1173 }
1174 
1175 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1176   (const std::string &s,
1177    bool hasOpSizePrefix) {
1178   ENCODING("GR16",            ENCODING_REG)
1179   ENCODING("GR32",            ENCODING_REG)
1180   ENCODING("GR64",            ENCODING_REG)
1181   ENCODING("GR8",             ENCODING_REG)
1182   ENCODING("VR128",           ENCODING_REG)
1183   ENCODING("FR64",            ENCODING_REG)
1184   ENCODING("FR32",            ENCODING_REG)
1185   ENCODING("VR64",            ENCODING_REG)
1186   ENCODING("SEGMENT_REG",     ENCODING_REG)
1187   ENCODING("DEBUG_REG",       ENCODING_REG)
1188   ENCODING("CONTROL_REG",     ENCODING_REG)
1189   ENCODING("VR256",           ENCODING_REG)
1190   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1191   llvm_unreachable("Unhandled reg/opcode register encoding");
1192 }
1193 
1194 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1195   (const std::string &s,
1196    bool hasOpSizePrefix) {
1197   ENCODING("GR32",            ENCODING_VVVV)
1198   ENCODING("GR64",            ENCODING_VVVV)
1199   ENCODING("FR32",            ENCODING_VVVV)
1200   ENCODING("FR64",            ENCODING_VVVV)
1201   ENCODING("VR128",           ENCODING_VVVV)
1202   ENCODING("VR256",           ENCODING_VVVV)
1203   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1204   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1205 }
1206 
1207 OperandEncoding RecognizableInstr::memoryEncodingFromString
1208   (const std::string &s,
1209    bool hasOpSizePrefix) {
1210   ENCODING("i16mem",          ENCODING_RM)
1211   ENCODING("i32mem",          ENCODING_RM)
1212   ENCODING("i64mem",          ENCODING_RM)
1213   ENCODING("i8mem",           ENCODING_RM)
1214   ENCODING("ssmem",           ENCODING_RM)
1215   ENCODING("sdmem",           ENCODING_RM)
1216   ENCODING("f128mem",         ENCODING_RM)
1217   ENCODING("f256mem",         ENCODING_RM)
1218   ENCODING("f64mem",          ENCODING_RM)
1219   ENCODING("f32mem",          ENCODING_RM)
1220   ENCODING("i128mem",         ENCODING_RM)
1221   ENCODING("i256mem",         ENCODING_RM)
1222   ENCODING("f80mem",          ENCODING_RM)
1223   ENCODING("lea32mem",        ENCODING_RM)
1224   ENCODING("lea64_32mem",     ENCODING_RM)
1225   ENCODING("lea64mem",        ENCODING_RM)
1226   ENCODING("opaque32mem",     ENCODING_RM)
1227   ENCODING("opaque48mem",     ENCODING_RM)
1228   ENCODING("opaque80mem",     ENCODING_RM)
1229   ENCODING("opaque512mem",    ENCODING_RM)
1230   errs() << "Unhandled memory encoding " << s << "\n";
1231   llvm_unreachable("Unhandled memory encoding");
1232 }
1233 
1234 OperandEncoding RecognizableInstr::relocationEncodingFromString
1235   (const std::string &s,
1236    bool hasOpSizePrefix) {
1237   if(!hasOpSizePrefix) {
1238     // For instructions without an OpSize prefix, a declared 16-bit register or
1239     // immediate encoding is special.
1240     ENCODING("i16imm",        ENCODING_IW)
1241   }
1242   ENCODING("i16imm",          ENCODING_Iv)
1243   ENCODING("i16i8imm",        ENCODING_IB)
1244   ENCODING("i32imm",          ENCODING_Iv)
1245   ENCODING("i32i8imm",        ENCODING_IB)
1246   ENCODING("i64i32imm",       ENCODING_ID)
1247   ENCODING("i64i8imm",        ENCODING_IB)
1248   ENCODING("i8imm",           ENCODING_IB)
1249   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1250   ENCODING("i16imm_pcrel",    ENCODING_IW)
1251   ENCODING("i32imm_pcrel",    ENCODING_ID)
1252   ENCODING("brtarget",        ENCODING_Iv)
1253   ENCODING("brtarget8",       ENCODING_IB)
1254   ENCODING("i64imm",          ENCODING_IO)
1255   ENCODING("offset8",         ENCODING_Ia)
1256   ENCODING("offset16",        ENCODING_Ia)
1257   ENCODING("offset32",        ENCODING_Ia)
1258   ENCODING("offset64",        ENCODING_Ia)
1259   errs() << "Unhandled relocation encoding " << s << "\n";
1260   llvm_unreachable("Unhandled relocation encoding");
1261 }
1262 
1263 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1264   (const std::string &s,
1265    bool hasOpSizePrefix) {
1266   ENCODING("RST",             ENCODING_I)
1267   ENCODING("GR32",            ENCODING_Rv)
1268   ENCODING("GR64",            ENCODING_RO)
1269   ENCODING("GR16",            ENCODING_Rv)
1270   ENCODING("GR8",             ENCODING_RB)
1271   ENCODING("GR16_NOAX",       ENCODING_Rv)
1272   ENCODING("GR32_NOAX",       ENCODING_Rv)
1273   ENCODING("GR64_NOAX",       ENCODING_RO)
1274   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1275   llvm_unreachable("Unhandled opcode modifier encoding");
1276 }
1277 #undef ENCODING
1278