1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisassemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 using namespace X86Disassembler; 25 26 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 27 /// Useful for switch statements and the like. 28 /// 29 /// @param init - A reference to the BitsInit to be decoded. 30 /// @return - The field, with the first bit in the BitsInit as the lowest 31 /// order bit. 32 static uint8_t byteFromBitsInit(BitsInit &init) { 33 int width = init.getNumBits(); 34 35 assert(width <= 8 && "Field is too large for uint8_t!"); 36 37 int index; 38 uint8_t mask = 0x01; 39 40 uint8_t ret = 0; 41 42 for (index = 0; index < width; index++) { 43 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 44 ret |= mask; 45 46 mask <<= 1; 47 } 48 49 return ret; 50 } 51 52 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 53 /// name of the field. 54 /// 55 /// @param rec - The record from which to extract the value. 56 /// @param name - The name of the field in the record. 57 /// @return - The field, as translated by byteFromBitsInit(). 58 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 59 BitsInit* bits = rec->getValueAsBitsInit(name); 60 return byteFromBitsInit(*bits); 61 } 62 63 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 64 const CodeGenInstruction &insn, 65 InstrUID uid) { 66 UID = uid; 67 68 Rec = insn.TheDef; 69 Name = Rec->getName(); 70 Spec = &tables.specForUID(UID); 71 72 if (!Rec->isSubClassOf("X86Inst")) { 73 ShouldBeEmitted = false; 74 return; 75 } 76 77 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 78 OpMap = byteFromRec(Rec, "OpMapBits"); 79 Opcode = byteFromRec(Rec, "Opcode"); 80 Form = byteFromRec(Rec, "FormBits"); 81 Encoding = byteFromRec(Rec, "OpEncBits"); 82 83 OpSize = byteFromRec(Rec, "OpSizeBits"); 84 AdSize = byteFromRec(Rec, "AdSizeBits"); 85 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 86 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 87 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 95 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 96 97 Name = Rec->getName(); 98 99 Operands = &insn.Operands.OperandList; 100 101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 102 103 EncodeRC = HasEVEX_B && 104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 105 106 // Check for 64-bit inst which does not require REX 107 Is32Bit = false; 108 Is64Bit = false; 109 // FIXME: Is there some better way to check for In64BitMode? 110 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 111 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 112 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 113 Predicates[i]->getName().find("In32Bit") != Name.npos) { 114 Is32Bit = true; 115 break; 116 } 117 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 118 Is64Bit = true; 119 break; 120 } 121 } 122 123 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 124 ShouldBeEmitted = false; 125 return; 126 } 127 128 // Special case since there is no attribute class for 64-bit and VEX 129 if (Name == "VMASKMOVDQU64") { 130 ShouldBeEmitted = false; 131 return; 132 } 133 134 ShouldBeEmitted = true; 135 } 136 137 void RecognizableInstr::processInstr(DisassemblerTables &tables, 138 const CodeGenInstruction &insn, 139 InstrUID uid) 140 { 141 // Ignore "asm parser only" instructions. 142 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 143 return; 144 145 RecognizableInstr recogInstr(tables, insn, uid); 146 147 if (recogInstr.shouldBeEmitted()) { 148 recogInstr.emitInstructionSpecifier(); 149 recogInstr.emitDecodePath(tables); 150 } 151 } 152 153 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 154 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 155 (HasEVEX_KZ ? n##_KZ : \ 156 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 157 158 InstructionContext RecognizableInstr::insnContext() const { 159 InstructionContext insnContext; 160 161 if (Encoding == X86Local::EVEX) { 162 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 165 } 166 // VEX_L & VEX_W 167 if (!EncodeRC && HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 168 if (OpPrefix == X86Local::PD) 169 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 170 else if (OpPrefix == X86Local::XS) 171 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 172 else if (OpPrefix == X86Local::XD) 173 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 174 else if (OpPrefix == X86Local::PS) 175 insnContext = EVEX_KB(IC_EVEX_L_W); 176 else { 177 errs() << "Instruction does not use a prefix: " << Name << "\n"; 178 llvm_unreachable("Invalid prefix"); 179 } 180 } else if (!EncodeRC && HasVEX_LPrefix) { 181 // VEX_L 182 if (OpPrefix == X86Local::PD) 183 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 184 else if (OpPrefix == X86Local::XS) 185 insnContext = EVEX_KB(IC_EVEX_L_XS); 186 else if (OpPrefix == X86Local::XD) 187 insnContext = EVEX_KB(IC_EVEX_L_XD); 188 else if (OpPrefix == X86Local::PS) 189 insnContext = EVEX_KB(IC_EVEX_L); 190 else { 191 errs() << "Instruction does not use a prefix: " << Name << "\n"; 192 llvm_unreachable("Invalid prefix"); 193 } 194 } else if (!EncodeRC && HasEVEX_L2Prefix && 195 VEX_WPrefix == X86Local::VEX_W1) { 196 // EVEX_L2 & VEX_W 197 if (OpPrefix == X86Local::PD) 198 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 199 else if (OpPrefix == X86Local::XS) 200 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 201 else if (OpPrefix == X86Local::XD) 202 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 203 else if (OpPrefix == X86Local::PS) 204 insnContext = EVEX_KB(IC_EVEX_L2_W); 205 else { 206 errs() << "Instruction does not use a prefix: " << Name << "\n"; 207 llvm_unreachable("Invalid prefix"); 208 } 209 } else if (!EncodeRC && HasEVEX_L2Prefix) { 210 // EVEX_L2 211 if (OpPrefix == X86Local::PD) 212 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 213 else if (OpPrefix == X86Local::XD) 214 insnContext = EVEX_KB(IC_EVEX_L2_XD); 215 else if (OpPrefix == X86Local::XS) 216 insnContext = EVEX_KB(IC_EVEX_L2_XS); 217 else if (OpPrefix == X86Local::PS) 218 insnContext = EVEX_KB(IC_EVEX_L2); 219 else { 220 errs() << "Instruction does not use a prefix: " << Name << "\n"; 221 llvm_unreachable("Invalid prefix"); 222 } 223 } 224 else if (VEX_WPrefix == X86Local::VEX_W1) { 225 // VEX_W 226 if (OpPrefix == X86Local::PD) 227 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 228 else if (OpPrefix == X86Local::XS) 229 insnContext = EVEX_KB(IC_EVEX_W_XS); 230 else if (OpPrefix == X86Local::XD) 231 insnContext = EVEX_KB(IC_EVEX_W_XD); 232 else if (OpPrefix == X86Local::PS) 233 insnContext = EVEX_KB(IC_EVEX_W); 234 else { 235 errs() << "Instruction does not use a prefix: " << Name << "\n"; 236 llvm_unreachable("Invalid prefix"); 237 } 238 } 239 // No L, no W 240 else if (OpPrefix == X86Local::PD) 241 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 242 else if (OpPrefix == X86Local::XD) 243 insnContext = EVEX_KB(IC_EVEX_XD); 244 else if (OpPrefix == X86Local::XS) 245 insnContext = EVEX_KB(IC_EVEX_XS); 246 else 247 insnContext = EVEX_KB(IC_EVEX); 248 /// eof EVEX 249 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 250 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 251 if (OpPrefix == X86Local::PD) 252 insnContext = IC_VEX_L_W_OPSIZE; 253 else if (OpPrefix == X86Local::XS) 254 insnContext = IC_VEX_L_W_XS; 255 else if (OpPrefix == X86Local::XD) 256 insnContext = IC_VEX_L_W_XD; 257 else if (OpPrefix == X86Local::PS) 258 insnContext = IC_VEX_L_W; 259 else { 260 errs() << "Instruction does not use a prefix: " << Name << "\n"; 261 llvm_unreachable("Invalid prefix"); 262 } 263 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 264 insnContext = IC_VEX_L_OPSIZE; 265 else if (OpPrefix == X86Local::PD && VEX_WPrefix == X86Local::VEX_W1) 266 insnContext = IC_VEX_W_OPSIZE; 267 else if (OpPrefix == X86Local::PD) 268 insnContext = IC_VEX_OPSIZE; 269 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 270 insnContext = IC_VEX_L_XS; 271 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 272 insnContext = IC_VEX_L_XD; 273 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XS) 274 insnContext = IC_VEX_W_XS; 275 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XD) 276 insnContext = IC_VEX_W_XD; 277 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::PS) 278 insnContext = IC_VEX_W; 279 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 280 insnContext = IC_VEX_L; 281 else if (OpPrefix == X86Local::XD) 282 insnContext = IC_VEX_XD; 283 else if (OpPrefix == X86Local::XS) 284 insnContext = IC_VEX_XS; 285 else if (OpPrefix == X86Local::PS) 286 insnContext = IC_VEX; 287 else { 288 errs() << "Instruction does not use a prefix: " << Name << "\n"; 289 llvm_unreachable("Invalid prefix"); 290 } 291 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 292 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 293 insnContext = IC_64BIT_REXW_OPSIZE; 294 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 295 insnContext = IC_64BIT_REXW_ADSIZE; 296 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 297 insnContext = IC_64BIT_XD_OPSIZE; 298 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 299 insnContext = IC_64BIT_XS_OPSIZE; 300 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 301 insnContext = IC_64BIT_OPSIZE_ADSIZE; 302 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 303 insnContext = IC_64BIT_OPSIZE; 304 else if (AdSize == X86Local::AdSize32) 305 insnContext = IC_64BIT_ADSIZE; 306 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 307 insnContext = IC_64BIT_REXW_XS; 308 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 309 insnContext = IC_64BIT_REXW_XD; 310 else if (OpPrefix == X86Local::XD) 311 insnContext = IC_64BIT_XD; 312 else if (OpPrefix == X86Local::XS) 313 insnContext = IC_64BIT_XS; 314 else if (HasREX_WPrefix) 315 insnContext = IC_64BIT_REXW; 316 else 317 insnContext = IC_64BIT; 318 } else { 319 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 320 insnContext = IC_XD_OPSIZE; 321 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 322 insnContext = IC_XS_OPSIZE; 323 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 324 insnContext = IC_OPSIZE_ADSIZE; 325 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 326 insnContext = IC_OPSIZE; 327 else if (AdSize == X86Local::AdSize16) 328 insnContext = IC_ADSIZE; 329 else if (OpPrefix == X86Local::XD) 330 insnContext = IC_XD; 331 else if (OpPrefix == X86Local::XS) 332 insnContext = IC_XS; 333 else 334 insnContext = IC; 335 } 336 337 return insnContext; 338 } 339 340 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 341 // The scaling factor for AVX512 compressed displacement encoding is an 342 // instruction attribute. Adjust the ModRM encoding type to include the 343 // scale for compressed displacement. 344 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 345 return; 346 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 347 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 348 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 349 "Invalid CDisp scaling"); 350 } 351 352 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 353 unsigned &physicalOperandIndex, 354 unsigned numPhysicalOperands, 355 const unsigned *operandMapping, 356 OperandEncoding (*encodingFromString) 357 (const std::string&, 358 uint8_t OpSize)) { 359 if (optional) { 360 if (physicalOperandIndex >= numPhysicalOperands) 361 return; 362 } else { 363 assert(physicalOperandIndex < numPhysicalOperands); 364 } 365 366 while (operandMapping[operandIndex] != operandIndex) { 367 Spec->operands[operandIndex].encoding = ENCODING_DUP; 368 Spec->operands[operandIndex].type = 369 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 370 ++operandIndex; 371 } 372 373 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 374 375 OperandEncoding encoding = encodingFromString(typeName, OpSize); 376 // Adjust the encoding type for an operand based on the instruction. 377 adjustOperandEncoding(encoding); 378 Spec->operands[operandIndex].encoding = encoding; 379 Spec->operands[operandIndex].type = typeFromString(typeName, 380 HasREX_WPrefix, OpSize); 381 382 ++operandIndex; 383 ++physicalOperandIndex; 384 } 385 386 void RecognizableInstr::emitInstructionSpecifier() { 387 Spec->name = Name; 388 389 Spec->insnContext = insnContext(); 390 391 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 392 393 unsigned numOperands = OperandList.size(); 394 unsigned numPhysicalOperands = 0; 395 396 // operandMapping maps from operands in OperandList to their originals. 397 // If operandMapping[i] != i, then the entry is a duplicate. 398 unsigned operandMapping[X86_MAX_OPERANDS]; 399 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 400 401 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 402 if (!OperandList[operandIndex].Constraints.empty()) { 403 const CGIOperandList::ConstraintInfo &Constraint = 404 OperandList[operandIndex].Constraints[0]; 405 if (Constraint.isTied()) { 406 operandMapping[operandIndex] = operandIndex; 407 operandMapping[Constraint.getTiedOperand()] = operandIndex; 408 } else { 409 ++numPhysicalOperands; 410 operandMapping[operandIndex] = operandIndex; 411 } 412 } else { 413 ++numPhysicalOperands; 414 operandMapping[operandIndex] = operandIndex; 415 } 416 } 417 418 #define HANDLE_OPERAND(class) \ 419 handleOperand(false, \ 420 operandIndex, \ 421 physicalOperandIndex, \ 422 numPhysicalOperands, \ 423 operandMapping, \ 424 class##EncodingFromString); 425 426 #define HANDLE_OPTIONAL(class) \ 427 handleOperand(true, \ 428 operandIndex, \ 429 physicalOperandIndex, \ 430 numPhysicalOperands, \ 431 operandMapping, \ 432 class##EncodingFromString); 433 434 // operandIndex should always be < numOperands 435 unsigned operandIndex = 0; 436 // physicalOperandIndex should always be < numPhysicalOperands 437 unsigned physicalOperandIndex = 0; 438 439 #ifndef NDEBUG 440 // Given the set of prefix bits, how many additional operands does the 441 // instruction have? 442 unsigned additionalOperands = 0; 443 if (HasVEX_4V) 444 ++additionalOperands; 445 if (HasEVEX_K) 446 ++additionalOperands; 447 #endif 448 449 switch (Form) { 450 default: llvm_unreachable("Unhandled form"); 451 case X86Local::RawFrmSrc: 452 HANDLE_OPERAND(relocation); 453 return; 454 case X86Local::RawFrmDst: 455 HANDLE_OPERAND(relocation); 456 return; 457 case X86Local::RawFrmDstSrc: 458 HANDLE_OPERAND(relocation); 459 HANDLE_OPERAND(relocation); 460 return; 461 case X86Local::RawFrm: 462 // Operand 1 (optional) is an address or immediate. 463 assert(numPhysicalOperands <= 1 && 464 "Unexpected number of operands for RawFrm"); 465 HANDLE_OPTIONAL(relocation) 466 break; 467 case X86Local::RawFrmMemOffs: 468 // Operand 1 is an address. 469 HANDLE_OPERAND(relocation); 470 break; 471 case X86Local::AddRegFrm: 472 // Operand 1 is added to the opcode. 473 // Operand 2 (optional) is an address. 474 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 475 "Unexpected number of operands for AddRegFrm"); 476 HANDLE_OPERAND(opcodeModifier) 477 HANDLE_OPTIONAL(relocation) 478 break; 479 case X86Local::MRMDestReg: 480 // Operand 1 is a register operand in the R/M field. 481 // - In AVX512 there may be a mask operand here - 482 // Operand 2 is a register operand in the Reg/Opcode field. 483 // - In AVX, there is a register operand in the VEX.vvvv field here - 484 // Operand 3 (optional) is an immediate. 485 assert(numPhysicalOperands >= 2 + additionalOperands && 486 numPhysicalOperands <= 3 + additionalOperands && 487 "Unexpected number of operands for MRMDestRegFrm"); 488 489 HANDLE_OPERAND(rmRegister) 490 if (HasEVEX_K) 491 HANDLE_OPERAND(writemaskRegister) 492 493 if (HasVEX_4V) 494 // FIXME: In AVX, the register below becomes the one encoded 495 // in ModRMVEX and the one above the one in the VEX.VVVV field 496 HANDLE_OPERAND(vvvvRegister) 497 498 HANDLE_OPERAND(roRegister) 499 HANDLE_OPTIONAL(immediate) 500 break; 501 case X86Local::MRMDestMem: 502 // Operand 1 is a memory operand (possibly SIB-extended) 503 // Operand 2 is a register operand in the Reg/Opcode field. 504 // - In AVX, there is a register operand in the VEX.vvvv field here - 505 // Operand 3 (optional) is an immediate. 506 assert(numPhysicalOperands >= 2 + additionalOperands && 507 numPhysicalOperands <= 3 + additionalOperands && 508 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 509 510 HANDLE_OPERAND(memory) 511 512 if (HasEVEX_K) 513 HANDLE_OPERAND(writemaskRegister) 514 515 if (HasVEX_4V) 516 // FIXME: In AVX, the register below becomes the one encoded 517 // in ModRMVEX and the one above the one in the VEX.VVVV field 518 HANDLE_OPERAND(vvvvRegister) 519 520 HANDLE_OPERAND(roRegister) 521 HANDLE_OPTIONAL(immediate) 522 break; 523 case X86Local::MRMSrcReg: 524 // Operand 1 is a register operand in the Reg/Opcode field. 525 // Operand 2 is a register operand in the R/M field. 526 // - In AVX, there is a register operand in the VEX.vvvv field here - 527 // Operand 3 (optional) is an immediate. 528 // Operand 4 (optional) is an immediate. 529 530 assert(numPhysicalOperands >= 2 + additionalOperands && 531 numPhysicalOperands <= 4 + additionalOperands && 532 "Unexpected number of operands for MRMSrcRegFrm"); 533 534 HANDLE_OPERAND(roRegister) 535 536 if (HasEVEX_K) 537 HANDLE_OPERAND(writemaskRegister) 538 539 if (HasVEX_4V) 540 // FIXME: In AVX, the register below becomes the one encoded 541 // in ModRMVEX and the one above the one in the VEX.VVVV field 542 HANDLE_OPERAND(vvvvRegister) 543 544 HANDLE_OPERAND(rmRegister) 545 HANDLE_OPTIONAL(immediate) 546 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 547 HANDLE_OPTIONAL(immediate) 548 break; 549 case X86Local::MRMSrcReg4VOp3: 550 assert(numPhysicalOperands == 3 && 551 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 552 HANDLE_OPERAND(roRegister) 553 HANDLE_OPERAND(rmRegister) 554 HANDLE_OPERAND(vvvvRegister) 555 break; 556 case X86Local::MRMSrcRegOp4: 557 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 558 "Unexpected number of operands for MRMSrcRegOp4Frm"); 559 HANDLE_OPERAND(roRegister) 560 HANDLE_OPERAND(vvvvRegister) 561 HANDLE_OPERAND(immediate) // Register in imm[7:4] 562 HANDLE_OPERAND(rmRegister) 563 HANDLE_OPTIONAL(immediate) 564 break; 565 case X86Local::MRMSrcMem: 566 // Operand 1 is a register operand in the Reg/Opcode field. 567 // Operand 2 is a memory operand (possibly SIB-extended) 568 // - In AVX, there is a register operand in the VEX.vvvv field here - 569 // Operand 3 (optional) is an immediate. 570 571 assert(numPhysicalOperands >= 2 + additionalOperands && 572 numPhysicalOperands <= 4 + additionalOperands && 573 "Unexpected number of operands for MRMSrcMemFrm"); 574 575 HANDLE_OPERAND(roRegister) 576 577 if (HasEVEX_K) 578 HANDLE_OPERAND(writemaskRegister) 579 580 if (HasVEX_4V) 581 // FIXME: In AVX, the register below becomes the one encoded 582 // in ModRMVEX and the one above the one in the VEX.VVVV field 583 HANDLE_OPERAND(vvvvRegister) 584 585 HANDLE_OPERAND(memory) 586 HANDLE_OPTIONAL(immediate) 587 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 588 break; 589 case X86Local::MRMSrcMem4VOp3: 590 assert(numPhysicalOperands == 3 && 591 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 592 HANDLE_OPERAND(roRegister) 593 HANDLE_OPERAND(memory) 594 HANDLE_OPERAND(vvvvRegister) 595 break; 596 case X86Local::MRMSrcMemOp4: 597 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 598 "Unexpected number of operands for MRMSrcMemOp4Frm"); 599 HANDLE_OPERAND(roRegister) 600 HANDLE_OPERAND(vvvvRegister) 601 HANDLE_OPERAND(immediate) // Register in imm[7:4] 602 HANDLE_OPERAND(memory) 603 HANDLE_OPTIONAL(immediate) 604 break; 605 case X86Local::MRMXr: 606 case X86Local::MRM0r: 607 case X86Local::MRM1r: 608 case X86Local::MRM2r: 609 case X86Local::MRM3r: 610 case X86Local::MRM4r: 611 case X86Local::MRM5r: 612 case X86Local::MRM6r: 613 case X86Local::MRM7r: 614 // Operand 1 is a register operand in the R/M field. 615 // Operand 2 (optional) is an immediate or relocation. 616 // Operand 3 (optional) is an immediate. 617 assert(numPhysicalOperands >= 0 + additionalOperands && 618 numPhysicalOperands <= 3 + additionalOperands && 619 "Unexpected number of operands for MRMnr"); 620 621 if (HasVEX_4V) 622 HANDLE_OPERAND(vvvvRegister) 623 624 if (HasEVEX_K) 625 HANDLE_OPERAND(writemaskRegister) 626 HANDLE_OPTIONAL(rmRegister) 627 HANDLE_OPTIONAL(relocation) 628 HANDLE_OPTIONAL(immediate) 629 break; 630 case X86Local::MRMXm: 631 case X86Local::MRM0m: 632 case X86Local::MRM1m: 633 case X86Local::MRM2m: 634 case X86Local::MRM3m: 635 case X86Local::MRM4m: 636 case X86Local::MRM5m: 637 case X86Local::MRM6m: 638 case X86Local::MRM7m: 639 // Operand 1 is a memory operand (possibly SIB-extended) 640 // Operand 2 (optional) is an immediate or relocation. 641 assert(numPhysicalOperands >= 1 + additionalOperands && 642 numPhysicalOperands <= 2 + additionalOperands && 643 "Unexpected number of operands for MRMnm"); 644 645 if (HasVEX_4V) 646 HANDLE_OPERAND(vvvvRegister) 647 if (HasEVEX_K) 648 HANDLE_OPERAND(writemaskRegister) 649 HANDLE_OPERAND(memory) 650 HANDLE_OPTIONAL(relocation) 651 break; 652 case X86Local::RawFrmImm8: 653 // operand 1 is a 16-bit immediate 654 // operand 2 is an 8-bit immediate 655 assert(numPhysicalOperands == 2 && 656 "Unexpected number of operands for X86Local::RawFrmImm8"); 657 HANDLE_OPERAND(immediate) 658 HANDLE_OPERAND(immediate) 659 break; 660 case X86Local::RawFrmImm16: 661 // operand 1 is a 16-bit immediate 662 // operand 2 is a 16-bit immediate 663 HANDLE_OPERAND(immediate) 664 HANDLE_OPERAND(immediate) 665 break; 666 #define MAP(from, to) case X86Local::MRM_##from: 667 X86_INSTR_MRM_MAPPING 668 #undef MAP 669 HANDLE_OPTIONAL(relocation) 670 break; 671 } 672 673 #undef HANDLE_OPERAND 674 #undef HANDLE_OPTIONAL 675 } 676 677 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 678 // Special cases where the LLVM tables are not complete 679 680 #define MAP(from, to) \ 681 case X86Local::MRM_##from: 682 683 llvm::Optional<OpcodeType> opcodeType; 684 switch (OpMap) { 685 default: llvm_unreachable("Invalid map!"); 686 case X86Local::OB: opcodeType = ONEBYTE; break; 687 case X86Local::TB: opcodeType = TWOBYTE; break; 688 case X86Local::T8: opcodeType = THREEBYTE_38; break; 689 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 690 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 691 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 692 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 693 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 694 } 695 696 std::unique_ptr<ModRMFilter> filter; 697 switch (Form) { 698 default: llvm_unreachable("Invalid form!"); 699 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 700 case X86Local::RawFrm: 701 case X86Local::AddRegFrm: 702 case X86Local::RawFrmMemOffs: 703 case X86Local::RawFrmSrc: 704 case X86Local::RawFrmDst: 705 case X86Local::RawFrmDstSrc: 706 case X86Local::RawFrmImm8: 707 case X86Local::RawFrmImm16: 708 filter = llvm::make_unique<DumbFilter>(); 709 break; 710 case X86Local::MRMDestReg: 711 case X86Local::MRMSrcReg: 712 case X86Local::MRMSrcReg4VOp3: 713 case X86Local::MRMSrcRegOp4: 714 case X86Local::MRMXr: 715 filter = llvm::make_unique<ModFilter>(true); 716 break; 717 case X86Local::MRMDestMem: 718 case X86Local::MRMSrcMem: 719 case X86Local::MRMSrcMem4VOp3: 720 case X86Local::MRMSrcMemOp4: 721 case X86Local::MRMXm: 722 filter = llvm::make_unique<ModFilter>(false); 723 break; 724 case X86Local::MRM0r: case X86Local::MRM1r: 725 case X86Local::MRM2r: case X86Local::MRM3r: 726 case X86Local::MRM4r: case X86Local::MRM5r: 727 case X86Local::MRM6r: case X86Local::MRM7r: 728 filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 729 break; 730 case X86Local::MRM0m: case X86Local::MRM1m: 731 case X86Local::MRM2m: case X86Local::MRM3m: 732 case X86Local::MRM4m: case X86Local::MRM5m: 733 case X86Local::MRM6m: case X86Local::MRM7m: 734 filter = llvm::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 735 break; 736 X86_INSTR_MRM_MAPPING 737 filter = llvm::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 738 break; 739 } // switch (Form) 740 741 uint8_t opcodeToSet = Opcode; 742 743 unsigned AddressSize = 0; 744 switch (AdSize) { 745 case X86Local::AdSize16: AddressSize = 16; break; 746 case X86Local::AdSize32: AddressSize = 32; break; 747 case X86Local::AdSize64: AddressSize = 64; break; 748 } 749 750 assert(opcodeType && "Opcode type not set"); 751 assert(filter && "Filter not set"); 752 753 if (Form == X86Local::AddRegFrm) { 754 assert(((opcodeToSet & 7) == 0) && 755 "ADDREG_FRM opcode not aligned"); 756 757 uint8_t currentOpcode; 758 759 for (currentOpcode = opcodeToSet; 760 currentOpcode < opcodeToSet + 8; 761 ++currentOpcode) 762 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 763 UID, Is32Bit, OpPrefix == 0, 764 IgnoresVEX_L || EncodeRC, 765 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 766 } else { 767 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 768 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 769 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 770 } 771 772 #undef MAP 773 } 774 775 #define TYPE(str, type) if (s == str) return type; 776 OperandType RecognizableInstr::typeFromString(const std::string &s, 777 bool hasREX_WPrefix, 778 uint8_t OpSize) { 779 if(hasREX_WPrefix) { 780 // For instructions with a REX_W prefix, a declared 32-bit register encoding 781 // is special. 782 TYPE("GR32", TYPE_R32) 783 } 784 if(OpSize == X86Local::OpSize16) { 785 // For OpSize16 instructions, a declared 16-bit register or 786 // immediate encoding is special. 787 TYPE("GR16", TYPE_Rv) 788 } else if(OpSize == X86Local::OpSize32) { 789 // For OpSize32 instructions, a declared 32-bit register or 790 // immediate encoding is special. 791 TYPE("GR32", TYPE_Rv) 792 } 793 TYPE("i16mem", TYPE_M) 794 TYPE("i16imm", TYPE_IMM) 795 TYPE("i16i8imm", TYPE_IMM) 796 TYPE("GR16", TYPE_R16) 797 TYPE("i32mem", TYPE_M) 798 TYPE("i32imm", TYPE_IMM) 799 TYPE("i32i8imm", TYPE_IMM) 800 TYPE("GR32", TYPE_R32) 801 TYPE("GR32orGR64", TYPE_R32) 802 TYPE("i64mem", TYPE_M) 803 TYPE("i64i32imm", TYPE_IMM) 804 TYPE("i64i8imm", TYPE_IMM) 805 TYPE("GR64", TYPE_R64) 806 TYPE("i8mem", TYPE_M) 807 TYPE("i8imm", TYPE_IMM) 808 TYPE("u8imm", TYPE_UIMM8) 809 TYPE("i32u8imm", TYPE_UIMM8) 810 TYPE("GR8", TYPE_R8) 811 TYPE("VR128", TYPE_XMM) 812 TYPE("VR128X", TYPE_XMM) 813 TYPE("f128mem", TYPE_M) 814 TYPE("f256mem", TYPE_M) 815 TYPE("f512mem", TYPE_M) 816 TYPE("FR128", TYPE_XMM) 817 TYPE("FR64", TYPE_XMM) 818 TYPE("FR64X", TYPE_XMM) 819 TYPE("f64mem", TYPE_M) 820 TYPE("sdmem", TYPE_M) 821 TYPE("FR32", TYPE_XMM) 822 TYPE("FR32X", TYPE_XMM) 823 TYPE("f32mem", TYPE_M) 824 TYPE("ssmem", TYPE_M) 825 TYPE("RST", TYPE_ST) 826 TYPE("i128mem", TYPE_M) 827 TYPE("i256mem", TYPE_M) 828 TYPE("i512mem", TYPE_M) 829 TYPE("i64i32imm_pcrel", TYPE_REL) 830 TYPE("i16imm_pcrel", TYPE_REL) 831 TYPE("i32imm_pcrel", TYPE_REL) 832 TYPE("SSECC", TYPE_IMM3) 833 TYPE("XOPCC", TYPE_IMM3) 834 TYPE("AVXCC", TYPE_IMM5) 835 TYPE("AVX512ICC", TYPE_AVX512ICC) 836 TYPE("AVX512RC", TYPE_IMM) 837 TYPE("brtarget32", TYPE_REL) 838 TYPE("brtarget16", TYPE_REL) 839 TYPE("brtarget8", TYPE_REL) 840 TYPE("f80mem", TYPE_M) 841 TYPE("lea64_32mem", TYPE_M) 842 TYPE("lea64mem", TYPE_M) 843 TYPE("VR64", TYPE_MM64) 844 TYPE("i64imm", TYPE_IMM) 845 TYPE("anymem", TYPE_M) 846 TYPE("opaque32mem", TYPE_M) 847 TYPE("opaque48mem", TYPE_M) 848 TYPE("opaque80mem", TYPE_M) 849 TYPE("opaque512mem", TYPE_M) 850 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 851 TYPE("DEBUG_REG", TYPE_DEBUGREG) 852 TYPE("CONTROL_REG", TYPE_CONTROLREG) 853 TYPE("srcidx8", TYPE_SRCIDX) 854 TYPE("srcidx16", TYPE_SRCIDX) 855 TYPE("srcidx32", TYPE_SRCIDX) 856 TYPE("srcidx64", TYPE_SRCIDX) 857 TYPE("dstidx8", TYPE_DSTIDX) 858 TYPE("dstidx16", TYPE_DSTIDX) 859 TYPE("dstidx32", TYPE_DSTIDX) 860 TYPE("dstidx64", TYPE_DSTIDX) 861 TYPE("offset16_8", TYPE_MOFFS) 862 TYPE("offset16_16", TYPE_MOFFS) 863 TYPE("offset16_32", TYPE_MOFFS) 864 TYPE("offset32_8", TYPE_MOFFS) 865 TYPE("offset32_16", TYPE_MOFFS) 866 TYPE("offset32_32", TYPE_MOFFS) 867 TYPE("offset32_64", TYPE_MOFFS) 868 TYPE("offset64_8", TYPE_MOFFS) 869 TYPE("offset64_16", TYPE_MOFFS) 870 TYPE("offset64_32", TYPE_MOFFS) 871 TYPE("offset64_64", TYPE_MOFFS) 872 TYPE("VR256", TYPE_YMM) 873 TYPE("VR256X", TYPE_YMM) 874 TYPE("VR512", TYPE_ZMM) 875 TYPE("VK1", TYPE_VK) 876 TYPE("VK1WM", TYPE_VK) 877 TYPE("VK2", TYPE_VK) 878 TYPE("VK2WM", TYPE_VK) 879 TYPE("VK4", TYPE_VK) 880 TYPE("VK4WM", TYPE_VK) 881 TYPE("VK8", TYPE_VK) 882 TYPE("VK8WM", TYPE_VK) 883 TYPE("VK16", TYPE_VK) 884 TYPE("VK16WM", TYPE_VK) 885 TYPE("VK32", TYPE_VK) 886 TYPE("VK32WM", TYPE_VK) 887 TYPE("VK64", TYPE_VK) 888 TYPE("VK64WM", TYPE_VK) 889 TYPE("vx64mem", TYPE_MVSIBX) 890 TYPE("vx128mem", TYPE_MVSIBX) 891 TYPE("vx256mem", TYPE_MVSIBX) 892 TYPE("vy128mem", TYPE_MVSIBY) 893 TYPE("vy256mem", TYPE_MVSIBY) 894 TYPE("vx64xmem", TYPE_MVSIBX) 895 TYPE("vx128xmem", TYPE_MVSIBX) 896 TYPE("vx256xmem", TYPE_MVSIBX) 897 TYPE("vy128xmem", TYPE_MVSIBY) 898 TYPE("vy256xmem", TYPE_MVSIBY) 899 TYPE("vy512mem", TYPE_MVSIBY) 900 TYPE("vz256xmem", TYPE_MVSIBZ) 901 TYPE("vz512mem", TYPE_MVSIBZ) 902 TYPE("BNDR", TYPE_BNDR) 903 errs() << "Unhandled type string " << s << "\n"; 904 llvm_unreachable("Unhandled type string"); 905 } 906 #undef TYPE 907 908 #define ENCODING(str, encoding) if (s == str) return encoding; 909 OperandEncoding 910 RecognizableInstr::immediateEncodingFromString(const std::string &s, 911 uint8_t OpSize) { 912 if(OpSize != X86Local::OpSize16) { 913 // For instructions without an OpSize prefix, a declared 16-bit register or 914 // immediate encoding is special. 915 ENCODING("i16imm", ENCODING_IW) 916 } 917 ENCODING("i32i8imm", ENCODING_IB) 918 ENCODING("SSECC", ENCODING_IB) 919 ENCODING("XOPCC", ENCODING_IB) 920 ENCODING("AVXCC", ENCODING_IB) 921 ENCODING("AVX512ICC", ENCODING_IB) 922 ENCODING("AVX512RC", ENCODING_IRC) 923 ENCODING("i16imm", ENCODING_Iv) 924 ENCODING("i16i8imm", ENCODING_IB) 925 ENCODING("i32imm", ENCODING_Iv) 926 ENCODING("i64i32imm", ENCODING_ID) 927 ENCODING("i64i8imm", ENCODING_IB) 928 ENCODING("i8imm", ENCODING_IB) 929 ENCODING("u8imm", ENCODING_IB) 930 ENCODING("i32u8imm", ENCODING_IB) 931 // This is not a typo. Instructions like BLENDVPD put 932 // register IDs in 8-bit immediates nowadays. 933 ENCODING("FR32", ENCODING_IB) 934 ENCODING("FR64", ENCODING_IB) 935 ENCODING("FR128", ENCODING_IB) 936 ENCODING("VR128", ENCODING_IB) 937 ENCODING("VR256", ENCODING_IB) 938 ENCODING("FR32X", ENCODING_IB) 939 ENCODING("FR64X", ENCODING_IB) 940 ENCODING("VR128X", ENCODING_IB) 941 ENCODING("VR256X", ENCODING_IB) 942 ENCODING("VR512", ENCODING_IB) 943 errs() << "Unhandled immediate encoding " << s << "\n"; 944 llvm_unreachable("Unhandled immediate encoding"); 945 } 946 947 OperandEncoding 948 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 949 uint8_t OpSize) { 950 ENCODING("RST", ENCODING_FP) 951 ENCODING("GR16", ENCODING_RM) 952 ENCODING("GR32", ENCODING_RM) 953 ENCODING("GR32orGR64", ENCODING_RM) 954 ENCODING("GR64", ENCODING_RM) 955 ENCODING("GR8", ENCODING_RM) 956 ENCODING("VR128", ENCODING_RM) 957 ENCODING("VR128X", ENCODING_RM) 958 ENCODING("FR128", ENCODING_RM) 959 ENCODING("FR64", ENCODING_RM) 960 ENCODING("FR32", ENCODING_RM) 961 ENCODING("FR64X", ENCODING_RM) 962 ENCODING("FR32X", ENCODING_RM) 963 ENCODING("VR64", ENCODING_RM) 964 ENCODING("VR256", ENCODING_RM) 965 ENCODING("VR256X", ENCODING_RM) 966 ENCODING("VR512", ENCODING_RM) 967 ENCODING("VK1", ENCODING_RM) 968 ENCODING("VK2", ENCODING_RM) 969 ENCODING("VK4", ENCODING_RM) 970 ENCODING("VK8", ENCODING_RM) 971 ENCODING("VK16", ENCODING_RM) 972 ENCODING("VK32", ENCODING_RM) 973 ENCODING("VK64", ENCODING_RM) 974 ENCODING("BNDR", ENCODING_RM) 975 errs() << "Unhandled R/M register encoding " << s << "\n"; 976 llvm_unreachable("Unhandled R/M register encoding"); 977 } 978 979 OperandEncoding 980 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 981 uint8_t OpSize) { 982 ENCODING("GR16", ENCODING_REG) 983 ENCODING("GR32", ENCODING_REG) 984 ENCODING("GR32orGR64", ENCODING_REG) 985 ENCODING("GR64", ENCODING_REG) 986 ENCODING("GR8", ENCODING_REG) 987 ENCODING("VR128", ENCODING_REG) 988 ENCODING("FR128", ENCODING_REG) 989 ENCODING("FR64", ENCODING_REG) 990 ENCODING("FR32", ENCODING_REG) 991 ENCODING("VR64", ENCODING_REG) 992 ENCODING("SEGMENT_REG", ENCODING_REG) 993 ENCODING("DEBUG_REG", ENCODING_REG) 994 ENCODING("CONTROL_REG", ENCODING_REG) 995 ENCODING("VR256", ENCODING_REG) 996 ENCODING("VR256X", ENCODING_REG) 997 ENCODING("VR128X", ENCODING_REG) 998 ENCODING("FR64X", ENCODING_REG) 999 ENCODING("FR32X", ENCODING_REG) 1000 ENCODING("VR512", ENCODING_REG) 1001 ENCODING("VK1", ENCODING_REG) 1002 ENCODING("VK2", ENCODING_REG) 1003 ENCODING("VK4", ENCODING_REG) 1004 ENCODING("VK8", ENCODING_REG) 1005 ENCODING("VK16", ENCODING_REG) 1006 ENCODING("VK32", ENCODING_REG) 1007 ENCODING("VK64", ENCODING_REG) 1008 ENCODING("VK1WM", ENCODING_REG) 1009 ENCODING("VK2WM", ENCODING_REG) 1010 ENCODING("VK4WM", ENCODING_REG) 1011 ENCODING("VK8WM", ENCODING_REG) 1012 ENCODING("VK16WM", ENCODING_REG) 1013 ENCODING("VK32WM", ENCODING_REG) 1014 ENCODING("VK64WM", ENCODING_REG) 1015 ENCODING("BNDR", ENCODING_REG) 1016 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1017 llvm_unreachable("Unhandled reg/opcode register encoding"); 1018 } 1019 1020 OperandEncoding 1021 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1022 uint8_t OpSize) { 1023 ENCODING("GR32", ENCODING_VVVV) 1024 ENCODING("GR64", ENCODING_VVVV) 1025 ENCODING("FR32", ENCODING_VVVV) 1026 ENCODING("FR128", ENCODING_VVVV) 1027 ENCODING("FR64", ENCODING_VVVV) 1028 ENCODING("VR128", ENCODING_VVVV) 1029 ENCODING("VR256", ENCODING_VVVV) 1030 ENCODING("FR32X", ENCODING_VVVV) 1031 ENCODING("FR64X", ENCODING_VVVV) 1032 ENCODING("VR128X", ENCODING_VVVV) 1033 ENCODING("VR256X", ENCODING_VVVV) 1034 ENCODING("VR512", ENCODING_VVVV) 1035 ENCODING("VK1", ENCODING_VVVV) 1036 ENCODING("VK2", ENCODING_VVVV) 1037 ENCODING("VK4", ENCODING_VVVV) 1038 ENCODING("VK8", ENCODING_VVVV) 1039 ENCODING("VK16", ENCODING_VVVV) 1040 ENCODING("VK32", ENCODING_VVVV) 1041 ENCODING("VK64", ENCODING_VVVV) 1042 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1043 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1044 } 1045 1046 OperandEncoding 1047 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1048 uint8_t OpSize) { 1049 ENCODING("VK1WM", ENCODING_WRITEMASK) 1050 ENCODING("VK2WM", ENCODING_WRITEMASK) 1051 ENCODING("VK4WM", ENCODING_WRITEMASK) 1052 ENCODING("VK8WM", ENCODING_WRITEMASK) 1053 ENCODING("VK16WM", ENCODING_WRITEMASK) 1054 ENCODING("VK32WM", ENCODING_WRITEMASK) 1055 ENCODING("VK64WM", ENCODING_WRITEMASK) 1056 errs() << "Unhandled mask register encoding " << s << "\n"; 1057 llvm_unreachable("Unhandled mask register encoding"); 1058 } 1059 1060 OperandEncoding 1061 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1062 uint8_t OpSize) { 1063 ENCODING("i16mem", ENCODING_RM) 1064 ENCODING("i32mem", ENCODING_RM) 1065 ENCODING("i64mem", ENCODING_RM) 1066 ENCODING("i8mem", ENCODING_RM) 1067 ENCODING("ssmem", ENCODING_RM) 1068 ENCODING("sdmem", ENCODING_RM) 1069 ENCODING("f128mem", ENCODING_RM) 1070 ENCODING("f256mem", ENCODING_RM) 1071 ENCODING("f512mem", ENCODING_RM) 1072 ENCODING("f64mem", ENCODING_RM) 1073 ENCODING("f32mem", ENCODING_RM) 1074 ENCODING("i128mem", ENCODING_RM) 1075 ENCODING("i256mem", ENCODING_RM) 1076 ENCODING("i512mem", ENCODING_RM) 1077 ENCODING("f80mem", ENCODING_RM) 1078 ENCODING("lea64_32mem", ENCODING_RM) 1079 ENCODING("lea64mem", ENCODING_RM) 1080 ENCODING("anymem", ENCODING_RM) 1081 ENCODING("opaque32mem", ENCODING_RM) 1082 ENCODING("opaque48mem", ENCODING_RM) 1083 ENCODING("opaque80mem", ENCODING_RM) 1084 ENCODING("opaque512mem", ENCODING_RM) 1085 ENCODING("vx64mem", ENCODING_VSIB) 1086 ENCODING("vx128mem", ENCODING_VSIB) 1087 ENCODING("vx256mem", ENCODING_VSIB) 1088 ENCODING("vy128mem", ENCODING_VSIB) 1089 ENCODING("vy256mem", ENCODING_VSIB) 1090 ENCODING("vx64xmem", ENCODING_VSIB) 1091 ENCODING("vx128xmem", ENCODING_VSIB) 1092 ENCODING("vx256xmem", ENCODING_VSIB) 1093 ENCODING("vy128xmem", ENCODING_VSIB) 1094 ENCODING("vy256xmem", ENCODING_VSIB) 1095 ENCODING("vy512mem", ENCODING_VSIB) 1096 ENCODING("vz256xmem", ENCODING_VSIB) 1097 ENCODING("vz512mem", ENCODING_VSIB) 1098 errs() << "Unhandled memory encoding " << s << "\n"; 1099 llvm_unreachable("Unhandled memory encoding"); 1100 } 1101 1102 OperandEncoding 1103 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1104 uint8_t OpSize) { 1105 if(OpSize != X86Local::OpSize16) { 1106 // For instructions without an OpSize prefix, a declared 16-bit register or 1107 // immediate encoding is special. 1108 ENCODING("i16imm", ENCODING_IW) 1109 } 1110 ENCODING("i16imm", ENCODING_Iv) 1111 ENCODING("i16i8imm", ENCODING_IB) 1112 ENCODING("i32imm", ENCODING_Iv) 1113 ENCODING("i32i8imm", ENCODING_IB) 1114 ENCODING("i64i32imm", ENCODING_ID) 1115 ENCODING("i64i8imm", ENCODING_IB) 1116 ENCODING("i8imm", ENCODING_IB) 1117 ENCODING("u8imm", ENCODING_IB) 1118 ENCODING("i32u8imm", ENCODING_IB) 1119 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1120 ENCODING("i16imm_pcrel", ENCODING_IW) 1121 ENCODING("i32imm_pcrel", ENCODING_ID) 1122 ENCODING("brtarget32", ENCODING_Iv) 1123 ENCODING("brtarget16", ENCODING_Iv) 1124 ENCODING("brtarget8", ENCODING_IB) 1125 ENCODING("i64imm", ENCODING_IO) 1126 ENCODING("offset16_8", ENCODING_Ia) 1127 ENCODING("offset16_16", ENCODING_Ia) 1128 ENCODING("offset16_32", ENCODING_Ia) 1129 ENCODING("offset32_8", ENCODING_Ia) 1130 ENCODING("offset32_16", ENCODING_Ia) 1131 ENCODING("offset32_32", ENCODING_Ia) 1132 ENCODING("offset32_64", ENCODING_Ia) 1133 ENCODING("offset64_8", ENCODING_Ia) 1134 ENCODING("offset64_16", ENCODING_Ia) 1135 ENCODING("offset64_32", ENCODING_Ia) 1136 ENCODING("offset64_64", ENCODING_Ia) 1137 ENCODING("srcidx8", ENCODING_SI) 1138 ENCODING("srcidx16", ENCODING_SI) 1139 ENCODING("srcidx32", ENCODING_SI) 1140 ENCODING("srcidx64", ENCODING_SI) 1141 ENCODING("dstidx8", ENCODING_DI) 1142 ENCODING("dstidx16", ENCODING_DI) 1143 ENCODING("dstidx32", ENCODING_DI) 1144 ENCODING("dstidx64", ENCODING_DI) 1145 errs() << "Unhandled relocation encoding " << s << "\n"; 1146 llvm_unreachable("Unhandled relocation encoding"); 1147 } 1148 1149 OperandEncoding 1150 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1151 uint8_t OpSize) { 1152 ENCODING("GR32", ENCODING_Rv) 1153 ENCODING("GR64", ENCODING_RO) 1154 ENCODING("GR16", ENCODING_Rv) 1155 ENCODING("GR8", ENCODING_RB) 1156 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1157 llvm_unreachable("Unhandled opcode modifier encoding"); 1158 } 1159 #undef ENCODING 1160