1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22 
23 using namespace llvm;
24 
25 #define MRM_MAPPING     \
26   MAP(C1, 33)           \
27   MAP(C2, 34)           \
28   MAP(C3, 35)           \
29   MAP(C4, 36)           \
30   MAP(C8, 37)           \
31   MAP(C9, 38)           \
32   MAP(CA, 39)           \
33   MAP(CB, 40)           \
34   MAP(E8, 41)           \
35   MAP(F0, 42)           \
36   MAP(F8, 45)           \
37   MAP(F9, 46)           \
38   MAP(D0, 47)           \
39   MAP(D1, 48)           \
40   MAP(D4, 49)           \
41   MAP(D5, 50)           \
42   MAP(D6, 51)           \
43   MAP(D8, 52)           \
44   MAP(D9, 53)           \
45   MAP(DA, 54)           \
46   MAP(DB, 55)           \
47   MAP(DC, 56)           \
48   MAP(DD, 57)           \
49   MAP(DE, 58)           \
50   MAP(DF, 59)
51 
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54   enum {
55     Pseudo      = 0,
56     RawFrm      = 1,
57     AddRegFrm   = 2,
58     MRMDestReg  = 3,
59     MRMDestMem  = 4,
60     MRMSrcReg   = 5,
61     MRMSrcMem   = 6,
62     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66     MRMInitReg  = 32,
67     RawFrmImm8  = 43,
68     RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70     MRM_MAPPING
71 #undef MAP
72     lastMRM
73   };
74 
75   enum {
76     TB  = 1,
77     REP = 2,
78     D8 = 3, D9 = 4, DA = 5, DB = 6,
79     DC = 7, DD = 8, DE = 9, DF = 10,
80     XD = 11,  XS = 12,
81     T8 = 13,  P_TA = 14,
82     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83     XOP8 = 20, XOP9 = 21, XOPA = 22
84   };
85 }
86 
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
103 
104 #define ONE_BYTE_EXTENSION_TABLES \
105   EXTENSION_TABLE(80)             \
106   EXTENSION_TABLE(81)             \
107   EXTENSION_TABLE(82)             \
108   EXTENSION_TABLE(83)             \
109   EXTENSION_TABLE(8f)             \
110   EXTENSION_TABLE(c0)             \
111   EXTENSION_TABLE(c1)             \
112   EXTENSION_TABLE(c6)             \
113   EXTENSION_TABLE(c7)             \
114   EXTENSION_TABLE(d0)             \
115   EXTENSION_TABLE(d1)             \
116   EXTENSION_TABLE(d2)             \
117   EXTENSION_TABLE(d3)             \
118   EXTENSION_TABLE(f6)             \
119   EXTENSION_TABLE(f7)             \
120   EXTENSION_TABLE(fe)             \
121   EXTENSION_TABLE(ff)
122 
123 #define TWO_BYTE_EXTENSION_TABLES \
124   EXTENSION_TABLE(00)             \
125   EXTENSION_TABLE(01)             \
126   EXTENSION_TABLE(0d)             \
127   EXTENSION_TABLE(18)             \
128   EXTENSION_TABLE(71)             \
129   EXTENSION_TABLE(72)             \
130   EXTENSION_TABLE(73)             \
131   EXTENSION_TABLE(ae)             \
132   EXTENSION_TABLE(ba)             \
133   EXTENSION_TABLE(c7)
134 
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136   EXTENSION_TABLE(F3)
137 
138 #define XOP9_MAP_EXTENSION_TABLES \
139   EXTENSION_TABLE(01)             \
140   EXTENSION_TABLE(02)
141 
142 using namespace X86Disassembler;
143 
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
146 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 ///   0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return     - true if the form implies that a ModR/M byte is required, false
151 ///               otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153   if (form == X86Local::MRMDestReg    ||
154      form == X86Local::MRMDestMem    ||
155      form == X86Local::MRMSrcReg     ||
156      form == X86Local::MRMSrcMem     ||
157      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159     return true;
160   else
161     return false;
162 }
163 
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 ///   the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return     - true if the form implies that Mod must be 0b11, false
169 ///               otherwise.
170 static bool isRegFormat(uint8_t form) {
171   if (form == X86Local::MRMDestReg ||
172      form == X86Local::MRMSrcReg  ||
173      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174     return true;
175   else
176     return false;
177 }
178 
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 ///   Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return     - The field, with the first bit in the BitsInit as the lowest
184 ///               order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186   int width = init.getNumBits();
187 
188   assert(width <= 8 && "Field is too large for uint8_t!");
189 
190   int     index;
191   uint8_t mask = 0x01;
192 
193   uint8_t ret = 0;
194 
195   for (index = 0; index < width; index++) {
196     if (static_cast<BitInit*>(init.getBit(index))->getValue())
197       ret |= mask;
198 
199     mask <<= 1;
200   }
201 
202   return ret;
203 }
204 
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 ///   name of the field.
207 ///
208 /// @param rec  - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return     - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212   BitsInit* bits = rec->getValueAsBitsInit(name);
213   return byteFromBitsInit(*bits);
214 }
215 
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217                                      const CodeGenInstruction &insn,
218                                      InstrUID uid) {
219   UID = uid;
220 
221   Rec = insn.TheDef;
222   Name = Rec->getName();
223   Spec = &tables.specForUID(UID);
224 
225   if (!Rec->isSubClassOf("X86Inst")) {
226     ShouldBeEmitted = false;
227     return;
228   }
229 
230   Prefix   = byteFromRec(Rec, "Prefix");
231   Opcode   = byteFromRec(Rec, "Opcode");
232   Form     = byteFromRec(Rec, "FormBits");
233   SegOvr   = byteFromRec(Rec, "SegOvrBits");
234 
235   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
236   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
237   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
238   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
239   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
240   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
242   HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
243   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
244   HasEVEXPrefix    = Rec->getValueAsBit("hasEVEXPrefix");
245   HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246   HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
247   HasEVEX_KZ       = Rec->getValueAsBit("hasEVEX_Z");
248   HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
249   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
250   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
251 
252   Name      = Rec->getName();
253   AsmString = Rec->getValueAsString("AsmString");
254 
255   Operands = &insn.Operands.OperandList;
256 
257   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258                      (Name.find("CRC32") != Name.npos);
259   HasFROperands    = hasFROperands();
260   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
261 
262   // Check for 64-bit inst which does not require REX
263   Is32Bit = false;
264   Is64Bit = false;
265   // FIXME: Is there some better way to check for In64BitMode?
266   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268     if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
269 	Predicates[i]->getName().find("In32Bit") != Name.npos) {
270       Is32Bit = true;
271       break;
272     }
273     if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
274       Is64Bit = true;
275       break;
276     }
277   }
278   // FIXME: These instructions aren't marked as 64-bit in any way
279   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
280              Rec->getName() == "MASKMOVDQU64" ||
281              Rec->getName() == "POPFS64" ||
282              Rec->getName() == "POPGS64" ||
283              Rec->getName() == "PUSHFS64" ||
284              Rec->getName() == "PUSHGS64" ||
285              Rec->getName() == "REX64_PREFIX" ||
286              Rec->getName().find("MOV64") != Name.npos ||
287              Rec->getName().find("PUSH64") != Name.npos ||
288              Rec->getName().find("POP64") != Name.npos;
289 
290   ShouldBeEmitted  = true;
291 }
292 
293 void RecognizableInstr::processInstr(DisassemblerTables &tables,
294                                      const CodeGenInstruction &insn,
295                                      InstrUID uid)
296 {
297   // Ignore "asm parser only" instructions.
298   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
299     return;
300 
301   RecognizableInstr recogInstr(tables, insn, uid);
302 
303   recogInstr.emitInstructionSpecifier(tables);
304 
305   if (recogInstr.shouldBeEmitted())
306     recogInstr.emitDecodePath(tables);
307 }
308 
309 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
310                     (HasEVEX_K && HasEVEX_B ? n##_K_B : \
311                     (HasEVEX_KZ ? n##_KZ : \
312                     (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
313 
314 InstructionContext RecognizableInstr::insnContext() const {
315   InstructionContext insnContext;
316 
317   if (HasEVEXPrefix) {
318     if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
319       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
320       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
321     }
322     // VEX_L & VEX_W
323     if (HasVEX_LPrefix && HasVEX_WPrefix) {
324       if (HasOpSizePrefix)
325         insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
326       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
327         insnContext = EVEX_KB(IC_EVEX_L_W_XS);
328       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329                Prefix == X86Local::TAXD)
330         insnContext = EVEX_KB(IC_EVEX_L_W_XD);
331       else
332         insnContext = EVEX_KB(IC_EVEX_L_W);
333     } else if (HasVEX_LPrefix) {
334       // VEX_L
335       if (HasOpSizePrefix)
336         insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
337       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
338         insnContext = EVEX_KB(IC_EVEX_L_XS);
339       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
340                Prefix == X86Local::TAXD)
341         insnContext = EVEX_KB(IC_EVEX_L_XD);
342       else
343         insnContext = EVEX_KB(IC_EVEX_L);
344     }
345     else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
346       // EVEX_L2 & VEX_W
347       if (HasOpSizePrefix)
348         insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
349       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
350         insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
351       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
352                Prefix == X86Local::TAXD)
353         insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
354       else
355         insnContext = EVEX_KB(IC_EVEX_L2_W);
356     } else if (HasEVEX_L2Prefix) {
357       // EVEX_L2
358       if (HasOpSizePrefix)
359         insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
360       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
361           Prefix == X86Local::TAXD)
362         insnContext = EVEX_KB(IC_EVEX_L2_XD);
363       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364         insnContext = EVEX_KB(IC_EVEX_L2_XS);
365       else
366         insnContext = EVEX_KB(IC_EVEX_L2);
367     }
368     else if (HasVEX_WPrefix) {
369       // VEX_W
370       if (HasOpSizePrefix)
371         insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
372       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
373         insnContext = EVEX_KB(IC_EVEX_W_XS);
374       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
375                Prefix == X86Local::TAXD)
376         insnContext = EVEX_KB(IC_EVEX_W_XD);
377       else
378         insnContext = EVEX_KB(IC_EVEX_W);
379     }
380     // No L, no W
381     else if (HasOpSizePrefix)
382       insnContext = EVEX_KB(IC_EVEX_OPSIZE);
383     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
384              Prefix == X86Local::TAXD)
385       insnContext = EVEX_KB(IC_EVEX_XD);
386     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
387       insnContext = EVEX_KB(IC_EVEX_XS);
388     else
389       insnContext = EVEX_KB(IC_EVEX);
390     /// eof EVEX
391   } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
392     if (HasVEX_LPrefix && HasVEX_WPrefix) {
393       if (HasOpSizePrefix)
394         insnContext = IC_VEX_L_W_OPSIZE;
395       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
396         insnContext = IC_VEX_L_W_XS;
397       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
398                Prefix == X86Local::TAXD)
399         insnContext = IC_VEX_L_W_XD;
400       else
401         insnContext = IC_VEX_L_W;
402     } else if (HasOpSizePrefix && HasVEX_LPrefix)
403       insnContext = IC_VEX_L_OPSIZE;
404     else if (HasOpSizePrefix && HasVEX_WPrefix)
405       insnContext = IC_VEX_W_OPSIZE;
406     else if (HasOpSizePrefix)
407       insnContext = IC_VEX_OPSIZE;
408     else if (HasVEX_LPrefix &&
409              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
410       insnContext = IC_VEX_L_XS;
411     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
412                                 Prefix == X86Local::T8XD ||
413                                 Prefix == X86Local::TAXD))
414       insnContext = IC_VEX_L_XD;
415     else if (HasVEX_WPrefix &&
416              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
417       insnContext = IC_VEX_W_XS;
418     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
419                                 Prefix == X86Local::T8XD ||
420                                 Prefix == X86Local::TAXD))
421       insnContext = IC_VEX_W_XD;
422     else if (HasVEX_WPrefix)
423       insnContext = IC_VEX_W;
424     else if (HasVEX_LPrefix)
425       insnContext = IC_VEX_L;
426     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
427              Prefix == X86Local::TAXD)
428       insnContext = IC_VEX_XD;
429     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
430       insnContext = IC_VEX_XS;
431     else
432       insnContext = IC_VEX;
433   } else if (Is64Bit || HasREX_WPrefix) {
434     if (HasREX_WPrefix && HasOpSizePrefix)
435       insnContext = IC_64BIT_REXW_OPSIZE;
436     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
437                                  Prefix == X86Local::T8XD ||
438                                  Prefix == X86Local::TAXD))
439       insnContext = IC_64BIT_XD_OPSIZE;
440     else if (HasOpSizePrefix &&
441              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
442       insnContext = IC_64BIT_XS_OPSIZE;
443     else if (HasOpSizePrefix)
444       insnContext = IC_64BIT_OPSIZE;
445     else if (HasAdSizePrefix)
446       insnContext = IC_64BIT_ADSIZE;
447     else if (HasREX_WPrefix &&
448              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
449       insnContext = IC_64BIT_REXW_XS;
450     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
451                                 Prefix == X86Local::T8XD ||
452                                 Prefix == X86Local::TAXD))
453       insnContext = IC_64BIT_REXW_XD;
454     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
455              Prefix == X86Local::TAXD)
456       insnContext = IC_64BIT_XD;
457     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
458       insnContext = IC_64BIT_XS;
459     else if (HasREX_WPrefix)
460       insnContext = IC_64BIT_REXW;
461     else
462       insnContext = IC_64BIT;
463   } else {
464     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
465                             Prefix == X86Local::T8XD ||
466                             Prefix == X86Local::TAXD))
467       insnContext = IC_XD_OPSIZE;
468     else if (HasOpSizePrefix &&
469              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
470       insnContext = IC_XS_OPSIZE;
471     else if (HasOpSizePrefix)
472       insnContext = IC_OPSIZE;
473     else if (HasAdSizePrefix)
474       insnContext = IC_ADSIZE;
475     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
476              Prefix == X86Local::TAXD)
477       insnContext = IC_XD;
478     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
479              Prefix == X86Local::REP)
480       insnContext = IC_XS;
481     else
482       insnContext = IC;
483   }
484 
485   return insnContext;
486 }
487 
488 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
489   ///////////////////
490   // FILTER_STRONG
491   //
492 
493   // Filter out intrinsics
494 
495   assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
496 
497   if (Form == X86Local::Pseudo ||
498       (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
499        Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
500     return FILTER_STRONG;
501 
502 
503   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
504   // printed as a separate "instruction".
505 
506   if (Name.find("_Int") != Name.npos       ||
507       Name.find("Int_") != Name.npos)
508     return FILTER_STRONG;
509 
510   // Filter out instructions with segment override prefixes.
511   // They're too messy to handle now and we'll special case them if needed.
512 
513   if (SegOvr)
514     return FILTER_STRONG;
515 
516 
517   /////////////////
518   // FILTER_WEAK
519   //
520 
521 
522   // Filter out instructions with a LOCK prefix;
523   //   prefer forms that do not have the prefix
524   if (HasLockPrefix)
525     return FILTER_WEAK;
526 
527   // Filter out alternate forms of AVX instructions
528   if (Name.find("_alt") != Name.npos ||
529       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
530       Name.find("_64mr") != Name.npos ||
531       Name.find("rr64") != Name.npos)
532     return FILTER_WEAK;
533 
534   // Special cases.
535 
536   if (Name == "PUSH64i16"         ||
537       Name == "MOVPQI2QImr"       ||
538       Name == "VMOVPQI2QImr"      ||
539       Name == "VMASKMOVDQU64")
540     return FILTER_WEAK;
541 
542   // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
543   // For now, just prefer the REP versions.
544   if (Name == "XACQUIRE_PREFIX" ||
545       Name == "XRELEASE_PREFIX")
546     return FILTER_WEAK;
547 
548   return FILTER_NORMAL;
549 }
550 
551 bool RecognizableInstr::hasFROperands() const {
552   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
553   unsigned numOperands = OperandList.size();
554 
555   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
556     const std::string &recName = OperandList[operandIndex].Rec->getName();
557 
558     if (recName.find("FR") != recName.npos)
559       return true;
560   }
561   return false;
562 }
563 
564 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
565                                       unsigned &physicalOperandIndex,
566                                       unsigned &numPhysicalOperands,
567                                       const unsigned *operandMapping,
568                                       OperandEncoding (*encodingFromString)
569                                         (const std::string&,
570                                          bool hasOpSizePrefix)) {
571   if (optional) {
572     if (physicalOperandIndex >= numPhysicalOperands)
573       return;
574   } else {
575     assert(physicalOperandIndex < numPhysicalOperands);
576   }
577 
578   while (operandMapping[operandIndex] != operandIndex) {
579     Spec->operands[operandIndex].encoding = ENCODING_DUP;
580     Spec->operands[operandIndex].type =
581       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
582     ++operandIndex;
583   }
584 
585   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
586 
587   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
588                                                               HasOpSizePrefix);
589   Spec->operands[operandIndex].type = typeFromString(typeName,
590                                                      IsSSE,
591                                                      HasREX_WPrefix,
592                                                      HasOpSizePrefix);
593 
594   ++operandIndex;
595   ++physicalOperandIndex;
596 }
597 
598 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
599   Spec->name       = Name;
600 
601   if (!ShouldBeEmitted)
602     return;
603 
604   switch (filter()) {
605   case FILTER_WEAK:
606     Spec->filtered = true;
607     break;
608   case FILTER_STRONG:
609     ShouldBeEmitted = false;
610     return;
611   case FILTER_NORMAL:
612     break;
613   }
614 
615   Spec->insnContext = insnContext();
616 
617   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
618 
619   unsigned numOperands = OperandList.size();
620   unsigned numPhysicalOperands = 0;
621 
622   // operandMapping maps from operands in OperandList to their originals.
623   // If operandMapping[i] != i, then the entry is a duplicate.
624   unsigned operandMapping[X86_MAX_OPERANDS];
625   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
626 
627   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
628     if (OperandList[operandIndex].Constraints.size()) {
629       const CGIOperandList::ConstraintInfo &Constraint =
630         OperandList[operandIndex].Constraints[0];
631       if (Constraint.isTied()) {
632         operandMapping[operandIndex] = operandIndex;
633         operandMapping[Constraint.getTiedOperand()] = operandIndex;
634       } else {
635         ++numPhysicalOperands;
636         operandMapping[operandIndex] = operandIndex;
637       }
638     } else {
639       ++numPhysicalOperands;
640       operandMapping[operandIndex] = operandIndex;
641     }
642   }
643 
644 #define HANDLE_OPERAND(class)               \
645   handleOperand(false,                      \
646                 operandIndex,               \
647                 physicalOperandIndex,       \
648                 numPhysicalOperands,        \
649                 operandMapping,             \
650                 class##EncodingFromString);
651 
652 #define HANDLE_OPTIONAL(class)              \
653   handleOperand(true,                       \
654                 operandIndex,               \
655                 physicalOperandIndex,       \
656                 numPhysicalOperands,        \
657                 operandMapping,             \
658                 class##EncodingFromString);
659 
660   // operandIndex should always be < numOperands
661   unsigned operandIndex = 0;
662   // physicalOperandIndex should always be < numPhysicalOperands
663   unsigned physicalOperandIndex = 0;
664 
665   switch (Form) {
666   case X86Local::RawFrm:
667     // Operand 1 (optional) is an address or immediate.
668     // Operand 2 (optional) is an immediate.
669     assert(numPhysicalOperands <= 2 &&
670            "Unexpected number of operands for RawFrm");
671     HANDLE_OPTIONAL(relocation)
672     HANDLE_OPTIONAL(immediate)
673     break;
674   case X86Local::AddRegFrm:
675     // Operand 1 is added to the opcode.
676     // Operand 2 (optional) is an address.
677     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
678            "Unexpected number of operands for AddRegFrm");
679     HANDLE_OPERAND(opcodeModifier)
680     HANDLE_OPTIONAL(relocation)
681     break;
682   case X86Local::MRMDestReg:
683     // Operand 1 is a register operand in the R/M field.
684     // Operand 2 is a register operand in the Reg/Opcode field.
685     // - In AVX, there is a register operand in the VEX.vvvv field here -
686     // Operand 3 (optional) is an immediate.
687     if (HasVEX_4VPrefix)
688       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
689              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
690     else
691       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
692              "Unexpected number of operands for MRMDestRegFrm");
693 
694     HANDLE_OPERAND(rmRegister)
695 
696     if (HasVEX_4VPrefix)
697       // FIXME: In AVX, the register below becomes the one encoded
698       // in ModRMVEX and the one above the one in the VEX.VVVV field
699       HANDLE_OPERAND(vvvvRegister)
700 
701     HANDLE_OPERAND(roRegister)
702     HANDLE_OPTIONAL(immediate)
703     break;
704   case X86Local::MRMDestMem:
705     // Operand 1 is a memory operand (possibly SIB-extended)
706     // Operand 2 is a register operand in the Reg/Opcode field.
707     // - In AVX, there is a register operand in the VEX.vvvv field here -
708     // Operand 3 (optional) is an immediate.
709     if (HasVEX_4VPrefix)
710       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
711              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
712     else
713       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
714              "Unexpected number of operands for MRMDestMemFrm");
715     HANDLE_OPERAND(memory)
716 
717     if (HasEVEX_K)
718       HANDLE_OPERAND(writemaskRegister)
719 
720     if (HasVEX_4VPrefix)
721       // FIXME: In AVX, the register below becomes the one encoded
722       // in ModRMVEX and the one above the one in the VEX.VVVV field
723       HANDLE_OPERAND(vvvvRegister)
724 
725     HANDLE_OPERAND(roRegister)
726     HANDLE_OPTIONAL(immediate)
727     break;
728   case X86Local::MRMSrcReg:
729     // Operand 1 is a register operand in the Reg/Opcode field.
730     // Operand 2 is a register operand in the R/M field.
731     // - In AVX, there is a register operand in the VEX.vvvv field here -
732     // Operand 3 (optional) is an immediate.
733     // Operand 4 (optional) is an immediate.
734 
735     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
736       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
737              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
738     else
739       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
740              "Unexpected number of operands for MRMSrcRegFrm");
741 
742     HANDLE_OPERAND(roRegister)
743 
744     if (HasEVEX_K)
745       HANDLE_OPERAND(writemaskRegister)
746 
747     if (HasVEX_4VPrefix)
748       // FIXME: In AVX, the register below becomes the one encoded
749       // in ModRMVEX and the one above the one in the VEX.VVVV field
750       HANDLE_OPERAND(vvvvRegister)
751 
752     if (HasMemOp4Prefix)
753       HANDLE_OPERAND(immediate)
754 
755     HANDLE_OPERAND(rmRegister)
756 
757     if (HasVEX_4VOp3Prefix)
758       HANDLE_OPERAND(vvvvRegister)
759 
760     if (!HasMemOp4Prefix)
761       HANDLE_OPTIONAL(immediate)
762     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
763     HANDLE_OPTIONAL(immediate)
764     break;
765   case X86Local::MRMSrcMem:
766     // Operand 1 is a register operand in the Reg/Opcode field.
767     // Operand 2 is a memory operand (possibly SIB-extended)
768     // - In AVX, there is a register operand in the VEX.vvvv field here -
769     // Operand 3 (optional) is an immediate.
770 
771     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
772       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
773              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
774     else
775       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
776              "Unexpected number of operands for MRMSrcMemFrm");
777 
778     HANDLE_OPERAND(roRegister)
779 
780     if (HasEVEX_K)
781       HANDLE_OPERAND(writemaskRegister)
782 
783     if (HasVEX_4VPrefix)
784       // FIXME: In AVX, the register below becomes the one encoded
785       // in ModRMVEX and the one above the one in the VEX.VVVV field
786       HANDLE_OPERAND(vvvvRegister)
787 
788     if (HasMemOp4Prefix)
789       HANDLE_OPERAND(immediate)
790 
791     HANDLE_OPERAND(memory)
792 
793     if (HasVEX_4VOp3Prefix)
794       HANDLE_OPERAND(vvvvRegister)
795 
796     if (!HasMemOp4Prefix)
797       HANDLE_OPTIONAL(immediate)
798     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
799     break;
800   case X86Local::MRM0r:
801   case X86Local::MRM1r:
802   case X86Local::MRM2r:
803   case X86Local::MRM3r:
804   case X86Local::MRM4r:
805   case X86Local::MRM5r:
806   case X86Local::MRM6r:
807   case X86Local::MRM7r:
808     {
809       // Operand 1 is a register operand in the R/M field.
810       // Operand 2 (optional) is an immediate or relocation.
811       // Operand 3 (optional) is an immediate.
812       unsigned kOp = (HasEVEX_K) ? 1:0;
813       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
814       if (numPhysicalOperands > 3 + kOp + Op4v)
815         llvm_unreachable("Unexpected number of operands for MRMnr");
816     }
817     if (HasVEX_4VPrefix)
818       HANDLE_OPERAND(vvvvRegister)
819 
820     if (HasEVEX_K)
821       HANDLE_OPERAND(writemaskRegister)
822     HANDLE_OPTIONAL(rmRegister)
823     HANDLE_OPTIONAL(relocation)
824     HANDLE_OPTIONAL(immediate)
825     break;
826   case X86Local::MRM0m:
827   case X86Local::MRM1m:
828   case X86Local::MRM2m:
829   case X86Local::MRM3m:
830   case X86Local::MRM4m:
831   case X86Local::MRM5m:
832   case X86Local::MRM6m:
833   case X86Local::MRM7m:
834     {
835       // Operand 1 is a memory operand (possibly SIB-extended)
836       // Operand 2 (optional) is an immediate or relocation.
837       unsigned kOp = (HasEVEX_K) ? 1:0;
838       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
839       if (numPhysicalOperands < 1 + kOp + Op4v ||
840           numPhysicalOperands > 2 + kOp + Op4v)
841         llvm_unreachable("Unexpected number of operands for MRMnm");
842     }
843     if (HasVEX_4VPrefix)
844       HANDLE_OPERAND(vvvvRegister)
845     if (HasEVEX_K)
846       HANDLE_OPERAND(writemaskRegister)
847     HANDLE_OPERAND(memory)
848     HANDLE_OPTIONAL(relocation)
849     break;
850   case X86Local::RawFrmImm8:
851     // operand 1 is a 16-bit immediate
852     // operand 2 is an 8-bit immediate
853     assert(numPhysicalOperands == 2 &&
854            "Unexpected number of operands for X86Local::RawFrmImm8");
855     HANDLE_OPERAND(immediate)
856     HANDLE_OPERAND(immediate)
857     break;
858   case X86Local::RawFrmImm16:
859     // operand 1 is a 16-bit immediate
860     // operand 2 is a 16-bit immediate
861     HANDLE_OPERAND(immediate)
862     HANDLE_OPERAND(immediate)
863     break;
864   case X86Local::MRM_F8:
865     if (Opcode == 0xc6) {
866       assert(numPhysicalOperands == 1 &&
867              "Unexpected number of operands for X86Local::MRM_F8");
868       HANDLE_OPERAND(immediate)
869     } else if (Opcode == 0xc7) {
870       assert(numPhysicalOperands == 1 &&
871              "Unexpected number of operands for X86Local::MRM_F8");
872       HANDLE_OPERAND(relocation)
873     }
874     break;
875   case X86Local::MRMInitReg:
876     // Ignored.
877     break;
878   }
879 
880   #undef HANDLE_OPERAND
881   #undef HANDLE_OPTIONAL
882 }
883 
884 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
885   // Special cases where the LLVM tables are not complete
886 
887 #define MAP(from, to)                     \
888   case X86Local::MRM_##from:              \
889     filter = new ExactFilter(0x##from);   \
890     break;
891 
892   OpcodeType    opcodeType  = (OpcodeType)-1;
893 
894   ModRMFilter*  filter      = NULL;
895   uint8_t       opcodeToSet = 0;
896 
897   switch (Prefix) {
898   default: llvm_unreachable("Invalid prefix!");
899   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
900   case X86Local::XD:
901   case X86Local::XS:
902   case X86Local::TB:
903     opcodeType = TWOBYTE;
904 
905     switch (Opcode) {
906     default:
907       if (needsModRMForDecode(Form))
908         filter = new ModFilter(isRegFormat(Form));
909       else
910         filter = new DumbFilter();
911       break;
912 #define EXTENSION_TABLE(n) case 0x##n:
913     TWO_BYTE_EXTENSION_TABLES
914 #undef EXTENSION_TABLE
915       switch (Form) {
916       default:
917         llvm_unreachable("Unhandled two-byte extended opcode");
918       case X86Local::MRM0r:
919       case X86Local::MRM1r:
920       case X86Local::MRM2r:
921       case X86Local::MRM3r:
922       case X86Local::MRM4r:
923       case X86Local::MRM5r:
924       case X86Local::MRM6r:
925       case X86Local::MRM7r:
926         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
927         break;
928       case X86Local::MRM0m:
929       case X86Local::MRM1m:
930       case X86Local::MRM2m:
931       case X86Local::MRM3m:
932       case X86Local::MRM4m:
933       case X86Local::MRM5m:
934       case X86Local::MRM6m:
935       case X86Local::MRM7m:
936         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
937         break;
938       MRM_MAPPING
939       } // switch (Form)
940       break;
941     } // switch (Opcode)
942     opcodeToSet = Opcode;
943     break;
944   case X86Local::T8:
945   case X86Local::T8XD:
946   case X86Local::T8XS:
947     opcodeType = THREEBYTE_38;
948     switch (Opcode) {
949     default:
950       if (needsModRMForDecode(Form))
951         filter = new ModFilter(isRegFormat(Form));
952       else
953         filter = new DumbFilter();
954       break;
955 #define EXTENSION_TABLE(n) case 0x##n:
956     THREE_BYTE_38_EXTENSION_TABLES
957 #undef EXTENSION_TABLE
958       switch (Form) {
959       default:
960         llvm_unreachable("Unhandled two-byte extended opcode");
961       case X86Local::MRM0r:
962       case X86Local::MRM1r:
963       case X86Local::MRM2r:
964       case X86Local::MRM3r:
965       case X86Local::MRM4r:
966       case X86Local::MRM5r:
967       case X86Local::MRM6r:
968       case X86Local::MRM7r:
969         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
970         break;
971       case X86Local::MRM0m:
972       case X86Local::MRM1m:
973       case X86Local::MRM2m:
974       case X86Local::MRM3m:
975       case X86Local::MRM4m:
976       case X86Local::MRM5m:
977       case X86Local::MRM6m:
978       case X86Local::MRM7m:
979         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
980         break;
981       MRM_MAPPING
982       } // switch (Form)
983       break;
984     } // switch (Opcode)
985     opcodeToSet = Opcode;
986     break;
987   case X86Local::P_TA:
988   case X86Local::TAXD:
989     opcodeType = THREEBYTE_3A;
990     if (needsModRMForDecode(Form))
991       filter = new ModFilter(isRegFormat(Form));
992     else
993       filter = new DumbFilter();
994     opcodeToSet = Opcode;
995     break;
996   case X86Local::A6:
997     opcodeType = THREEBYTE_A6;
998     if (needsModRMForDecode(Form))
999       filter = new ModFilter(isRegFormat(Form));
1000     else
1001       filter = new DumbFilter();
1002     opcodeToSet = Opcode;
1003     break;
1004   case X86Local::A7:
1005     opcodeType = THREEBYTE_A7;
1006     if (needsModRMForDecode(Form))
1007       filter = new ModFilter(isRegFormat(Form));
1008     else
1009       filter = new DumbFilter();
1010     opcodeToSet = Opcode;
1011     break;
1012   case X86Local::XOP8:
1013     opcodeType = XOP8_MAP;
1014     if (needsModRMForDecode(Form))
1015       filter = new ModFilter(isRegFormat(Form));
1016     else
1017       filter = new DumbFilter();
1018     opcodeToSet = Opcode;
1019     break;
1020   case X86Local::XOP9:
1021     opcodeType = XOP9_MAP;
1022     switch (Opcode) {
1023     default:
1024       if (needsModRMForDecode(Form))
1025         filter = new ModFilter(isRegFormat(Form));
1026       else
1027         filter = new DumbFilter();
1028       break;
1029 #define EXTENSION_TABLE(n) case 0x##n:
1030     XOP9_MAP_EXTENSION_TABLES
1031 #undef EXTENSION_TABLE
1032       switch (Form) {
1033       default:
1034         llvm_unreachable("Unhandled XOP9 extended opcode");
1035       case X86Local::MRM0r:
1036       case X86Local::MRM1r:
1037       case X86Local::MRM2r:
1038       case X86Local::MRM3r:
1039       case X86Local::MRM4r:
1040       case X86Local::MRM5r:
1041       case X86Local::MRM6r:
1042       case X86Local::MRM7r:
1043         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1044         break;
1045       case X86Local::MRM0m:
1046       case X86Local::MRM1m:
1047       case X86Local::MRM2m:
1048       case X86Local::MRM3m:
1049       case X86Local::MRM4m:
1050       case X86Local::MRM5m:
1051       case X86Local::MRM6m:
1052       case X86Local::MRM7m:
1053         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1054         break;
1055       MRM_MAPPING
1056       } // switch (Form)
1057       break;
1058     } // switch (Opcode)
1059     opcodeToSet = Opcode;
1060     break;
1061   case X86Local::XOPA:
1062     opcodeType = XOPA_MAP;
1063     if (needsModRMForDecode(Form))
1064       filter = new ModFilter(isRegFormat(Form));
1065     else
1066       filter = new DumbFilter();
1067     opcodeToSet = Opcode;
1068     break;
1069   case X86Local::D8:
1070   case X86Local::D9:
1071   case X86Local::DA:
1072   case X86Local::DB:
1073   case X86Local::DC:
1074   case X86Local::DD:
1075   case X86Local::DE:
1076   case X86Local::DF:
1077     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1078     opcodeType = ONEBYTE;
1079     if (Form == X86Local::AddRegFrm) {
1080       Spec->modifierType = MODIFIER_MODRM;
1081       Spec->modifierBase = Opcode;
1082       filter = new AddRegEscapeFilter(Opcode);
1083     } else {
1084       filter = new EscapeFilter(true, Opcode);
1085     }
1086     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1087     break;
1088   case X86Local::REP:
1089   case 0:
1090     opcodeType = ONEBYTE;
1091     switch (Opcode) {
1092 #define EXTENSION_TABLE(n) case 0x##n:
1093     ONE_BYTE_EXTENSION_TABLES
1094 #undef EXTENSION_TABLE
1095       switch (Form) {
1096       default:
1097         llvm_unreachable("Fell through the cracks of a single-byte "
1098                          "extended opcode");
1099       case X86Local::MRM0r:
1100       case X86Local::MRM1r:
1101       case X86Local::MRM2r:
1102       case X86Local::MRM3r:
1103       case X86Local::MRM4r:
1104       case X86Local::MRM5r:
1105       case X86Local::MRM6r:
1106       case X86Local::MRM7r:
1107         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1108         break;
1109       case X86Local::MRM0m:
1110       case X86Local::MRM1m:
1111       case X86Local::MRM2m:
1112       case X86Local::MRM3m:
1113       case X86Local::MRM4m:
1114       case X86Local::MRM5m:
1115       case X86Local::MRM6m:
1116       case X86Local::MRM7m:
1117         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1118         break;
1119       MRM_MAPPING
1120       } // switch (Form)
1121       break;
1122     case 0xd8:
1123     case 0xd9:
1124     case 0xda:
1125     case 0xdb:
1126     case 0xdc:
1127     case 0xdd:
1128     case 0xde:
1129     case 0xdf:
1130       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1131       break;
1132     default:
1133       if (needsModRMForDecode(Form))
1134         filter = new ModFilter(isRegFormat(Form));
1135       else
1136         filter = new DumbFilter();
1137       break;
1138     } // switch (Opcode)
1139     opcodeToSet = Opcode;
1140   } // switch (Prefix)
1141 
1142   assert(opcodeType != (OpcodeType)-1 &&
1143          "Opcode type not set");
1144   assert(filter && "Filter not set");
1145 
1146   if (Form == X86Local::AddRegFrm) {
1147     if(Spec->modifierType != MODIFIER_MODRM) {
1148       assert(opcodeToSet < 0xf9 &&
1149              "Not enough room for all ADDREG_FRM operands");
1150 
1151       uint8_t currentOpcode;
1152 
1153       for (currentOpcode = opcodeToSet;
1154            currentOpcode < opcodeToSet + 8;
1155            ++currentOpcode)
1156         tables.setTableFields(opcodeType,
1157                               insnContext(),
1158                               currentOpcode,
1159                               *filter,
1160                               UID, Is32Bit, IgnoresVEX_L);
1161 
1162       Spec->modifierType = MODIFIER_OPCODE;
1163       Spec->modifierBase = opcodeToSet;
1164     } else {
1165       // modifierBase was set where MODIFIER_MODRM was set
1166       tables.setTableFields(opcodeType,
1167                             insnContext(),
1168                             opcodeToSet,
1169                             *filter,
1170                             UID, Is32Bit, IgnoresVEX_L);
1171     }
1172   } else {
1173     tables.setTableFields(opcodeType,
1174                           insnContext(),
1175                           opcodeToSet,
1176                           *filter,
1177                           UID, Is32Bit, IgnoresVEX_L);
1178 
1179     Spec->modifierType = MODIFIER_NONE;
1180     Spec->modifierBase = opcodeToSet;
1181   }
1182 
1183   delete filter;
1184 
1185 #undef MAP
1186 }
1187 
1188 #define TYPE(str, type) if (s == str) return type;
1189 OperandType RecognizableInstr::typeFromString(const std::string &s,
1190                                               bool isSSE,
1191                                               bool hasREX_WPrefix,
1192                                               bool hasOpSizePrefix) {
1193   if (isSSE) {
1194     // For SSE instructions, we ignore the OpSize prefix and force operand
1195     // sizes.
1196     TYPE("GR16",              TYPE_R16)
1197     TYPE("GR32",              TYPE_R32)
1198     TYPE("GR64",              TYPE_R64)
1199   }
1200   if(hasREX_WPrefix) {
1201     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1202     // is special.
1203     TYPE("GR32",              TYPE_R32)
1204   }
1205   if(!hasOpSizePrefix) {
1206     // For instructions without an OpSize prefix, a declared 16-bit register or
1207     // immediate encoding is special.
1208     TYPE("GR16",              TYPE_R16)
1209     TYPE("i16imm",            TYPE_IMM16)
1210   }
1211   TYPE("i16mem",              TYPE_Mv)
1212   TYPE("i16imm",              TYPE_IMMv)
1213   TYPE("i16i8imm",            TYPE_IMMv)
1214   TYPE("GR16",                TYPE_Rv)
1215   TYPE("i32mem",              TYPE_Mv)
1216   TYPE("i32imm",              TYPE_IMMv)
1217   TYPE("i32i8imm",            TYPE_IMM32)
1218   TYPE("u32u8imm",            TYPE_IMM32)
1219   TYPE("GR32",                TYPE_Rv)
1220   TYPE("GR32orGR64",          TYPE_R32)
1221   TYPE("i64mem",              TYPE_Mv)
1222   TYPE("i64i32imm",           TYPE_IMM64)
1223   TYPE("i64i8imm",            TYPE_IMM64)
1224   TYPE("GR64",                TYPE_R64)
1225   TYPE("i8mem",               TYPE_M8)
1226   TYPE("i8imm",               TYPE_IMM8)
1227   TYPE("GR8",                 TYPE_R8)
1228   TYPE("VR128",               TYPE_XMM128)
1229   TYPE("VR128X",              TYPE_XMM128)
1230   TYPE("f128mem",             TYPE_M128)
1231   TYPE("f256mem",             TYPE_M256)
1232   TYPE("f512mem",             TYPE_M512)
1233   TYPE("FR64",                TYPE_XMM64)
1234   TYPE("FR64X",               TYPE_XMM64)
1235   TYPE("f64mem",              TYPE_M64FP)
1236   TYPE("sdmem",               TYPE_M64FP)
1237   TYPE("FR32",                TYPE_XMM32)
1238   TYPE("FR32X",               TYPE_XMM32)
1239   TYPE("f32mem",              TYPE_M32FP)
1240   TYPE("ssmem",               TYPE_M32FP)
1241   TYPE("RST",                 TYPE_ST)
1242   TYPE("i128mem",             TYPE_M128)
1243   TYPE("i256mem",             TYPE_M256)
1244   TYPE("i512mem",             TYPE_M512)
1245   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1246   TYPE("i16imm_pcrel",        TYPE_REL16)
1247   TYPE("i32imm_pcrel",        TYPE_REL32)
1248   TYPE("SSECC",               TYPE_IMM3)
1249   TYPE("AVXCC",               TYPE_IMM5)
1250   TYPE("brtarget",            TYPE_RELv)
1251   TYPE("uncondbrtarget",      TYPE_RELv)
1252   TYPE("brtarget8",           TYPE_REL8)
1253   TYPE("f80mem",              TYPE_M80FP)
1254   TYPE("lea32mem",            TYPE_LEA)
1255   TYPE("lea64_32mem",         TYPE_LEA)
1256   TYPE("lea64mem",            TYPE_LEA)
1257   TYPE("VR64",                TYPE_MM64)
1258   TYPE("i64imm",              TYPE_IMMv)
1259   TYPE("opaque32mem",         TYPE_M1616)
1260   TYPE("opaque48mem",         TYPE_M1632)
1261   TYPE("opaque80mem",         TYPE_M1664)
1262   TYPE("opaque512mem",        TYPE_M512)
1263   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1264   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1265   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1266   TYPE("offset8",             TYPE_MOFFS8)
1267   TYPE("offset16",            TYPE_MOFFS16)
1268   TYPE("offset32",            TYPE_MOFFS32)
1269   TYPE("offset64",            TYPE_MOFFS64)
1270   TYPE("VR256",               TYPE_XMM256)
1271   TYPE("VR256X",              TYPE_XMM256)
1272   TYPE("VR512",               TYPE_XMM512)
1273   TYPE("VK1",                 TYPE_VK1)
1274   TYPE("VK1WM",               TYPE_VK1)
1275   TYPE("VK8",                 TYPE_VK8)
1276   TYPE("VK8WM",               TYPE_VK8)
1277   TYPE("VK16",                TYPE_VK16)
1278   TYPE("VK16WM",              TYPE_VK16)
1279   TYPE("GR16_NOAX",           TYPE_Rv)
1280   TYPE("GR32_NOAX",           TYPE_Rv)
1281   TYPE("GR64_NOAX",           TYPE_R64)
1282   TYPE("vx32mem",             TYPE_M32)
1283   TYPE("vy32mem",             TYPE_M32)
1284   TYPE("vz32mem",             TYPE_M32)
1285   TYPE("vx64mem",             TYPE_M64)
1286   TYPE("vy64mem",             TYPE_M64)
1287   TYPE("vy64xmem",            TYPE_M64)
1288   TYPE("vz64mem",             TYPE_M64)
1289   errs() << "Unhandled type string " << s << "\n";
1290   llvm_unreachable("Unhandled type string");
1291 }
1292 #undef TYPE
1293 
1294 #define ENCODING(str, encoding) if (s == str) return encoding;
1295 OperandEncoding RecognizableInstr::immediateEncodingFromString
1296   (const std::string &s,
1297    bool hasOpSizePrefix) {
1298   if(!hasOpSizePrefix) {
1299     // For instructions without an OpSize prefix, a declared 16-bit register or
1300     // immediate encoding is special.
1301     ENCODING("i16imm",        ENCODING_IW)
1302   }
1303   ENCODING("i32i8imm",        ENCODING_IB)
1304   ENCODING("u32u8imm",        ENCODING_IB)
1305   ENCODING("SSECC",           ENCODING_IB)
1306   ENCODING("AVXCC",           ENCODING_IB)
1307   ENCODING("i16imm",          ENCODING_Iv)
1308   ENCODING("i16i8imm",        ENCODING_IB)
1309   ENCODING("i32imm",          ENCODING_Iv)
1310   ENCODING("i64i32imm",       ENCODING_ID)
1311   ENCODING("i64i8imm",        ENCODING_IB)
1312   ENCODING("i8imm",           ENCODING_IB)
1313   // This is not a typo.  Instructions like BLENDVPD put
1314   // register IDs in 8-bit immediates nowadays.
1315   ENCODING("FR32",            ENCODING_IB)
1316   ENCODING("FR64",            ENCODING_IB)
1317   ENCODING("VR128",           ENCODING_IB)
1318   ENCODING("VR256",           ENCODING_IB)
1319   ENCODING("FR32X",           ENCODING_IB)
1320   ENCODING("FR64X",           ENCODING_IB)
1321   ENCODING("VR128X",          ENCODING_IB)
1322   ENCODING("VR256X",          ENCODING_IB)
1323   ENCODING("VR512",           ENCODING_IB)
1324   errs() << "Unhandled immediate encoding " << s << "\n";
1325   llvm_unreachable("Unhandled immediate encoding");
1326 }
1327 
1328 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1329   (const std::string &s,
1330    bool hasOpSizePrefix) {
1331   ENCODING("GR16",            ENCODING_RM)
1332   ENCODING("GR32",            ENCODING_RM)
1333   ENCODING("GR32orGR64",      ENCODING_RM)
1334   ENCODING("GR64",            ENCODING_RM)
1335   ENCODING("GR8",             ENCODING_RM)
1336   ENCODING("VR128",           ENCODING_RM)
1337   ENCODING("VR128X",          ENCODING_RM)
1338   ENCODING("FR64",            ENCODING_RM)
1339   ENCODING("FR32",            ENCODING_RM)
1340   ENCODING("FR64X",           ENCODING_RM)
1341   ENCODING("FR32X",           ENCODING_RM)
1342   ENCODING("VR64",            ENCODING_RM)
1343   ENCODING("VR256",           ENCODING_RM)
1344   ENCODING("VR256X",          ENCODING_RM)
1345   ENCODING("VR512",           ENCODING_RM)
1346   ENCODING("VK1",             ENCODING_RM)
1347   ENCODING("VK8",             ENCODING_RM)
1348   ENCODING("VK16",            ENCODING_RM)
1349   errs() << "Unhandled R/M register encoding " << s << "\n";
1350   llvm_unreachable("Unhandled R/M register encoding");
1351 }
1352 
1353 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1354   (const std::string &s,
1355    bool hasOpSizePrefix) {
1356   ENCODING("GR16",            ENCODING_REG)
1357   ENCODING("GR32",            ENCODING_REG)
1358   ENCODING("GR32orGR64",      ENCODING_REG)
1359   ENCODING("GR64",            ENCODING_REG)
1360   ENCODING("GR8",             ENCODING_REG)
1361   ENCODING("VR128",           ENCODING_REG)
1362   ENCODING("FR64",            ENCODING_REG)
1363   ENCODING("FR32",            ENCODING_REG)
1364   ENCODING("VR64",            ENCODING_REG)
1365   ENCODING("SEGMENT_REG",     ENCODING_REG)
1366   ENCODING("DEBUG_REG",       ENCODING_REG)
1367   ENCODING("CONTROL_REG",     ENCODING_REG)
1368   ENCODING("VR256",           ENCODING_REG)
1369   ENCODING("VR256X",          ENCODING_REG)
1370   ENCODING("VR128X",          ENCODING_REG)
1371   ENCODING("FR64X",           ENCODING_REG)
1372   ENCODING("FR32X",           ENCODING_REG)
1373   ENCODING("VR512",           ENCODING_REG)
1374   ENCODING("VK1",             ENCODING_REG)
1375   ENCODING("VK8",             ENCODING_REG)
1376   ENCODING("VK16",            ENCODING_REG)
1377   ENCODING("VK1WM",           ENCODING_REG)
1378   ENCODING("VK8WM",           ENCODING_REG)
1379   ENCODING("VK16WM",          ENCODING_REG)
1380   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1381   llvm_unreachable("Unhandled reg/opcode register encoding");
1382 }
1383 
1384 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1385   (const std::string &s,
1386    bool hasOpSizePrefix) {
1387   ENCODING("GR32",            ENCODING_VVVV)
1388   ENCODING("GR64",            ENCODING_VVVV)
1389   ENCODING("FR32",            ENCODING_VVVV)
1390   ENCODING("FR64",            ENCODING_VVVV)
1391   ENCODING("VR128",           ENCODING_VVVV)
1392   ENCODING("VR256",           ENCODING_VVVV)
1393   ENCODING("FR32X",           ENCODING_VVVV)
1394   ENCODING("FR64X",           ENCODING_VVVV)
1395   ENCODING("VR128X",          ENCODING_VVVV)
1396   ENCODING("VR256X",          ENCODING_VVVV)
1397   ENCODING("VR512",           ENCODING_VVVV)
1398   ENCODING("VK1",             ENCODING_VVVV)
1399   ENCODING("VK8",             ENCODING_VVVV)
1400   ENCODING("VK16",            ENCODING_VVVV)
1401   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1402   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1403 }
1404 
1405 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1406   (const std::string &s,
1407    bool hasOpSizePrefix) {
1408   ENCODING("VK1WM",           ENCODING_WRITEMASK)
1409   ENCODING("VK8WM",           ENCODING_WRITEMASK)
1410   ENCODING("VK16WM",          ENCODING_WRITEMASK)
1411   errs() << "Unhandled mask register encoding " << s << "\n";
1412   llvm_unreachable("Unhandled mask register encoding");
1413 }
1414 
1415 OperandEncoding RecognizableInstr::memoryEncodingFromString
1416   (const std::string &s,
1417    bool hasOpSizePrefix) {
1418   ENCODING("i16mem",          ENCODING_RM)
1419   ENCODING("i32mem",          ENCODING_RM)
1420   ENCODING("i64mem",          ENCODING_RM)
1421   ENCODING("i8mem",           ENCODING_RM)
1422   ENCODING("ssmem",           ENCODING_RM)
1423   ENCODING("sdmem",           ENCODING_RM)
1424   ENCODING("f128mem",         ENCODING_RM)
1425   ENCODING("f256mem",         ENCODING_RM)
1426   ENCODING("f512mem",         ENCODING_RM)
1427   ENCODING("f64mem",          ENCODING_RM)
1428   ENCODING("f32mem",          ENCODING_RM)
1429   ENCODING("i128mem",         ENCODING_RM)
1430   ENCODING("i256mem",         ENCODING_RM)
1431   ENCODING("i512mem",         ENCODING_RM)
1432   ENCODING("f80mem",          ENCODING_RM)
1433   ENCODING("lea32mem",        ENCODING_RM)
1434   ENCODING("lea64_32mem",     ENCODING_RM)
1435   ENCODING("lea64mem",        ENCODING_RM)
1436   ENCODING("opaque32mem",     ENCODING_RM)
1437   ENCODING("opaque48mem",     ENCODING_RM)
1438   ENCODING("opaque80mem",     ENCODING_RM)
1439   ENCODING("opaque512mem",    ENCODING_RM)
1440   ENCODING("vx32mem",         ENCODING_RM)
1441   ENCODING("vy32mem",         ENCODING_RM)
1442   ENCODING("vz32mem",         ENCODING_RM)
1443   ENCODING("vx64mem",         ENCODING_RM)
1444   ENCODING("vy64mem",         ENCODING_RM)
1445   ENCODING("vy64xmem",        ENCODING_RM)
1446   ENCODING("vz64mem",         ENCODING_RM)
1447   errs() << "Unhandled memory encoding " << s << "\n";
1448   llvm_unreachable("Unhandled memory encoding");
1449 }
1450 
1451 OperandEncoding RecognizableInstr::relocationEncodingFromString
1452   (const std::string &s,
1453    bool hasOpSizePrefix) {
1454   if(!hasOpSizePrefix) {
1455     // For instructions without an OpSize prefix, a declared 16-bit register or
1456     // immediate encoding is special.
1457     ENCODING("i16imm",        ENCODING_IW)
1458   }
1459   ENCODING("i16imm",          ENCODING_Iv)
1460   ENCODING("i16i8imm",        ENCODING_IB)
1461   ENCODING("i32imm",          ENCODING_Iv)
1462   ENCODING("i32i8imm",        ENCODING_IB)
1463   ENCODING("i64i32imm",       ENCODING_ID)
1464   ENCODING("i64i8imm",        ENCODING_IB)
1465   ENCODING("i8imm",           ENCODING_IB)
1466   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1467   ENCODING("i16imm_pcrel",    ENCODING_IW)
1468   ENCODING("i32imm_pcrel",    ENCODING_ID)
1469   ENCODING("brtarget",        ENCODING_Iv)
1470   ENCODING("brtarget8",       ENCODING_IB)
1471   ENCODING("i64imm",          ENCODING_IO)
1472   ENCODING("offset8",         ENCODING_Ia)
1473   ENCODING("offset16",        ENCODING_Ia)
1474   ENCODING("offset32",        ENCODING_Ia)
1475   ENCODING("offset64",        ENCODING_Ia)
1476   errs() << "Unhandled relocation encoding " << s << "\n";
1477   llvm_unreachable("Unhandled relocation encoding");
1478 }
1479 
1480 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1481   (const std::string &s,
1482    bool hasOpSizePrefix) {
1483   ENCODING("RST",             ENCODING_I)
1484   ENCODING("GR32",            ENCODING_Rv)
1485   ENCODING("GR64",            ENCODING_RO)
1486   ENCODING("GR16",            ENCODING_Rv)
1487   ENCODING("GR8",             ENCODING_RB)
1488   ENCODING("GR16_NOAX",       ENCODING_Rv)
1489   ENCODING("GR32_NOAX",       ENCODING_Rv)
1490   ENCODING("GR64_NOAX",       ENCODING_RO)
1491   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1492   llvm_unreachable("Unhandled opcode modifier encoding");
1493 }
1494 #undef ENCODING
1495