1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 25 #define MRM_MAPPING \ 26 MAP(C1, 33) \ 27 MAP(C2, 34) \ 28 MAP(C3, 35) \ 29 MAP(C4, 36) \ 30 MAP(C8, 37) \ 31 MAP(C9, 38) \ 32 MAP(CA, 39) \ 33 MAP(CB, 40) \ 34 MAP(E8, 41) \ 35 MAP(F0, 42) \ 36 MAP(F8, 45) \ 37 MAP(F9, 46) \ 38 MAP(D0, 47) \ 39 MAP(D1, 48) \ 40 MAP(D4, 49) \ 41 MAP(D5, 50) \ 42 MAP(D6, 51) \ 43 MAP(D8, 52) \ 44 MAP(D9, 53) \ 45 MAP(DA, 54) \ 46 MAP(DB, 55) \ 47 MAP(DC, 56) \ 48 MAP(DD, 57) \ 49 MAP(DE, 58) \ 50 MAP(DF, 59) 51 52 // A clone of X86 since we can't depend on something that is generated. 53 namespace X86Local { 54 enum { 55 Pseudo = 0, 56 RawFrm = 1, 57 AddRegFrm = 2, 58 MRMDestReg = 3, 59 MRMDestMem = 4, 60 MRMSrcReg = 5, 61 MRMSrcMem = 6, 62 RawFrmMemOffs = 7, 63 RawFrmSrc = 8, 64 RawFrmDst = 9, 65 RawFrmDstSrc = 10, 66 MRMXr = 14, MRMXm = 15, 67 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 68 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 69 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 70 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 71 RawFrmImm8 = 43, 72 RawFrmImm16 = 44, 73 #define MAP(from, to) MRM_##from = to, 74 MRM_MAPPING 75 #undef MAP 76 lastMRM 77 }; 78 79 enum { 80 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, 81 D8 = 7, D9 = 8, DA = 9, DB = 10, 82 DC = 11, DD = 12, DE = 13, DF = 14, 83 A6 = 15, A7 = 16 84 }; 85 86 enum { 87 PD = 1, XS = 2, XD = 3 88 }; 89 90 enum { 91 VEX = 1, XOP = 2, EVEX = 3 92 }; 93 94 enum { 95 OpSize16 = 1, OpSize32 = 2 96 }; 97 } 98 99 using namespace X86Disassembler; 100 101 /// isRegFormat - Indicates whether a particular form requires the Mod field of 102 /// the ModR/M byte to be 0b11. 103 /// 104 /// @param form - The form of the instruction. 105 /// @return - true if the form implies that Mod must be 0b11, false 106 /// otherwise. 107 static bool isRegFormat(uint8_t form) { 108 return (form == X86Local::MRMDestReg || 109 form == X86Local::MRMSrcReg || 110 form == X86Local::MRMXr || 111 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); 112 } 113 114 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 115 /// Useful for switch statements and the like. 116 /// 117 /// @param init - A reference to the BitsInit to be decoded. 118 /// @return - The field, with the first bit in the BitsInit as the lowest 119 /// order bit. 120 static uint8_t byteFromBitsInit(BitsInit &init) { 121 int width = init.getNumBits(); 122 123 assert(width <= 8 && "Field is too large for uint8_t!"); 124 125 int index; 126 uint8_t mask = 0x01; 127 128 uint8_t ret = 0; 129 130 for (index = 0; index < width; index++) { 131 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 132 ret |= mask; 133 134 mask <<= 1; 135 } 136 137 return ret; 138 } 139 140 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 141 /// name of the field. 142 /// 143 /// @param rec - The record from which to extract the value. 144 /// @param name - The name of the field in the record. 145 /// @return - The field, as translated by byteFromBitsInit(). 146 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 147 BitsInit* bits = rec->getValueAsBitsInit(name); 148 return byteFromBitsInit(*bits); 149 } 150 151 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 152 const CodeGenInstruction &insn, 153 InstrUID uid) { 154 UID = uid; 155 156 Rec = insn.TheDef; 157 Name = Rec->getName(); 158 Spec = &tables.specForUID(UID); 159 160 if (!Rec->isSubClassOf("X86Inst")) { 161 ShouldBeEmitted = false; 162 return; 163 } 164 165 OpPrefix = byteFromRec(Rec->getValueAsDef("OpPrefix"), "Value"); 166 OpMap = byteFromRec(Rec->getValueAsDef("OpMap"), "Value"); 167 Opcode = byteFromRec(Rec, "Opcode"); 168 Form = byteFromRec(Rec, "FormBits"); 169 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value"); 170 171 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value"); 172 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); 173 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 174 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 175 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3"); 176 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 177 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); 178 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 179 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 180 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 181 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 182 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 183 HasREPPrefix = Rec->getValueAsBit("hasREPPrefix"); 184 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 185 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 186 187 Name = Rec->getName(); 188 AsmString = Rec->getValueAsString("AsmString"); 189 190 Operands = &insn.Operands.OperandList; 191 192 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 193 194 // Check for 64-bit inst which does not require REX 195 Is32Bit = false; 196 Is64Bit = false; 197 // FIXME: Is there some better way to check for In64BitMode? 198 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 199 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 200 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 201 Predicates[i]->getName().find("In32Bit") != Name.npos) { 202 Is32Bit = true; 203 break; 204 } 205 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 206 Is64Bit = true; 207 break; 208 } 209 } 210 211 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 212 ShouldBeEmitted = false; 213 return; 214 } 215 216 // Special case since there is no attribute class for 64-bit and VEX 217 if (Name == "VMASKMOVDQU64") { 218 ShouldBeEmitted = false; 219 return; 220 } 221 222 ShouldBeEmitted = true; 223 } 224 225 void RecognizableInstr::processInstr(DisassemblerTables &tables, 226 const CodeGenInstruction &insn, 227 InstrUID uid) 228 { 229 // Ignore "asm parser only" instructions. 230 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 231 return; 232 233 RecognizableInstr recogInstr(tables, insn, uid); 234 235 if (recogInstr.shouldBeEmitted()) { 236 recogInstr.emitInstructionSpecifier(); 237 recogInstr.emitDecodePath(tables); 238 } 239 } 240 241 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 242 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 243 (HasEVEX_KZ ? n##_KZ : \ 244 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 245 246 InstructionContext RecognizableInstr::insnContext() const { 247 InstructionContext insnContext; 248 249 if (Encoding == X86Local::EVEX) { 250 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 251 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 252 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 253 } 254 // VEX_L & VEX_W 255 if (HasVEX_LPrefix && HasVEX_WPrefix) { 256 if (OpPrefix == X86Local::PD) 257 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 258 else if (OpPrefix == X86Local::XS) 259 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 260 else if (OpPrefix == X86Local::XD) 261 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 262 else 263 insnContext = EVEX_KB(IC_EVEX_L_W); 264 } else if (HasVEX_LPrefix) { 265 // VEX_L 266 if (OpPrefix == X86Local::PD) 267 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 268 else if (OpPrefix == X86Local::XS) 269 insnContext = EVEX_KB(IC_EVEX_L_XS); 270 else if (OpPrefix == X86Local::XD) 271 insnContext = EVEX_KB(IC_EVEX_L_XD); 272 else 273 insnContext = EVEX_KB(IC_EVEX_L); 274 } 275 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { 276 // EVEX_L2 & VEX_W 277 if (OpPrefix == X86Local::PD) 278 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 279 else if (OpPrefix == X86Local::XS) 280 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 281 else if (OpPrefix == X86Local::XD) 282 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 283 else 284 insnContext = EVEX_KB(IC_EVEX_L2_W); 285 } else if (HasEVEX_L2Prefix) { 286 // EVEX_L2 287 if (OpPrefix == X86Local::PD) 288 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 289 else if (OpPrefix == X86Local::XD) 290 insnContext = EVEX_KB(IC_EVEX_L2_XD); 291 else if (OpPrefix == X86Local::XS) 292 insnContext = EVEX_KB(IC_EVEX_L2_XS); 293 else 294 insnContext = EVEX_KB(IC_EVEX_L2); 295 } 296 else if (HasVEX_WPrefix) { 297 // VEX_W 298 if (OpPrefix == X86Local::PD) 299 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 300 else if (OpPrefix == X86Local::XS) 301 insnContext = EVEX_KB(IC_EVEX_W_XS); 302 else if (OpPrefix == X86Local::XD) 303 insnContext = EVEX_KB(IC_EVEX_W_XD); 304 else 305 insnContext = EVEX_KB(IC_EVEX_W); 306 } 307 // No L, no W 308 else if (OpPrefix == X86Local::PD) 309 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 310 else if (OpPrefix == X86Local::XD) 311 insnContext = EVEX_KB(IC_EVEX_XD); 312 else if (OpPrefix == X86Local::XS) 313 insnContext = EVEX_KB(IC_EVEX_XS); 314 else 315 insnContext = EVEX_KB(IC_EVEX); 316 /// eof EVEX 317 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 318 if (HasVEX_LPrefix && HasVEX_WPrefix) { 319 if (OpPrefix == X86Local::PD) 320 insnContext = IC_VEX_L_W_OPSIZE; 321 else if (OpPrefix == X86Local::XS) 322 insnContext = IC_VEX_L_W_XS; 323 else if (OpPrefix == X86Local::XD) 324 insnContext = IC_VEX_L_W_XD; 325 else 326 insnContext = IC_VEX_L_W; 327 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 328 insnContext = IC_VEX_L_OPSIZE; 329 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix) 330 insnContext = IC_VEX_W_OPSIZE; 331 else if (OpPrefix == X86Local::PD) 332 insnContext = IC_VEX_OPSIZE; 333 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 334 insnContext = IC_VEX_L_XS; 335 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 336 insnContext = IC_VEX_L_XD; 337 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS) 338 insnContext = IC_VEX_W_XS; 339 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD) 340 insnContext = IC_VEX_W_XD; 341 else if (HasVEX_WPrefix) 342 insnContext = IC_VEX_W; 343 else if (HasVEX_LPrefix) 344 insnContext = IC_VEX_L; 345 else if (OpPrefix == X86Local::XD) 346 insnContext = IC_VEX_XD; 347 else if (OpPrefix == X86Local::XS) 348 insnContext = IC_VEX_XS; 349 else 350 insnContext = IC_VEX; 351 } else if (Is64Bit || HasREX_WPrefix) { 352 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 353 insnContext = IC_64BIT_REXW_OPSIZE; 354 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 355 insnContext = IC_64BIT_XD_OPSIZE; 356 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 357 insnContext = IC_64BIT_XS_OPSIZE; 358 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 359 insnContext = IC_64BIT_OPSIZE; 360 else if (HasAdSizePrefix) 361 insnContext = IC_64BIT_ADSIZE; 362 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 363 insnContext = IC_64BIT_REXW_XS; 364 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 365 insnContext = IC_64BIT_REXW_XD; 366 else if (OpPrefix == X86Local::XD) 367 insnContext = IC_64BIT_XD; 368 else if (OpPrefix == X86Local::XS) 369 insnContext = IC_64BIT_XS; 370 else if (HasREX_WPrefix) 371 insnContext = IC_64BIT_REXW; 372 else 373 insnContext = IC_64BIT; 374 } else { 375 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 376 insnContext = IC_XD_OPSIZE; 377 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 378 insnContext = IC_XS_OPSIZE; 379 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 380 insnContext = IC_OPSIZE; 381 else if (HasAdSizePrefix) 382 insnContext = IC_ADSIZE; 383 else if (OpPrefix == X86Local::XD) 384 insnContext = IC_XD; 385 else if (OpPrefix == X86Local::XS || HasREPPrefix) 386 insnContext = IC_XS; 387 else 388 insnContext = IC; 389 } 390 391 return insnContext; 392 } 393 394 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 395 unsigned &physicalOperandIndex, 396 unsigned &numPhysicalOperands, 397 const unsigned *operandMapping, 398 OperandEncoding (*encodingFromString) 399 (const std::string&, 400 uint8_t OpSize)) { 401 if (optional) { 402 if (physicalOperandIndex >= numPhysicalOperands) 403 return; 404 } else { 405 assert(physicalOperandIndex < numPhysicalOperands); 406 } 407 408 while (operandMapping[operandIndex] != operandIndex) { 409 Spec->operands[operandIndex].encoding = ENCODING_DUP; 410 Spec->operands[operandIndex].type = 411 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 412 ++operandIndex; 413 } 414 415 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 416 417 Spec->operands[operandIndex].encoding = encodingFromString(typeName, 418 OpSize); 419 Spec->operands[operandIndex].type = typeFromString(typeName, 420 HasREX_WPrefix, OpSize); 421 422 ++operandIndex; 423 ++physicalOperandIndex; 424 } 425 426 void RecognizableInstr::emitInstructionSpecifier() { 427 Spec->name = Name; 428 429 Spec->insnContext = insnContext(); 430 431 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 432 433 unsigned numOperands = OperandList.size(); 434 unsigned numPhysicalOperands = 0; 435 436 // operandMapping maps from operands in OperandList to their originals. 437 // If operandMapping[i] != i, then the entry is a duplicate. 438 unsigned operandMapping[X86_MAX_OPERANDS]; 439 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 440 441 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 442 if (OperandList[operandIndex].Constraints.size()) { 443 const CGIOperandList::ConstraintInfo &Constraint = 444 OperandList[operandIndex].Constraints[0]; 445 if (Constraint.isTied()) { 446 operandMapping[operandIndex] = operandIndex; 447 operandMapping[Constraint.getTiedOperand()] = operandIndex; 448 } else { 449 ++numPhysicalOperands; 450 operandMapping[operandIndex] = operandIndex; 451 } 452 } else { 453 ++numPhysicalOperands; 454 operandMapping[operandIndex] = operandIndex; 455 } 456 } 457 458 #define HANDLE_OPERAND(class) \ 459 handleOperand(false, \ 460 operandIndex, \ 461 physicalOperandIndex, \ 462 numPhysicalOperands, \ 463 operandMapping, \ 464 class##EncodingFromString); 465 466 #define HANDLE_OPTIONAL(class) \ 467 handleOperand(true, \ 468 operandIndex, \ 469 physicalOperandIndex, \ 470 numPhysicalOperands, \ 471 operandMapping, \ 472 class##EncodingFromString); 473 474 // operandIndex should always be < numOperands 475 unsigned operandIndex = 0; 476 // physicalOperandIndex should always be < numPhysicalOperands 477 unsigned physicalOperandIndex = 0; 478 479 switch (Form) { 480 default: llvm_unreachable("Unhandled form"); 481 case X86Local::RawFrmSrc: 482 HANDLE_OPERAND(relocation); 483 return; 484 case X86Local::RawFrmDst: 485 HANDLE_OPERAND(relocation); 486 return; 487 case X86Local::RawFrmDstSrc: 488 HANDLE_OPERAND(relocation); 489 HANDLE_OPERAND(relocation); 490 return; 491 case X86Local::RawFrm: 492 // Operand 1 (optional) is an address or immediate. 493 // Operand 2 (optional) is an immediate. 494 assert(numPhysicalOperands <= 2 && 495 "Unexpected number of operands for RawFrm"); 496 HANDLE_OPTIONAL(relocation) 497 HANDLE_OPTIONAL(immediate) 498 break; 499 case X86Local::RawFrmMemOffs: 500 // Operand 1 is an address. 501 HANDLE_OPERAND(relocation); 502 break; 503 case X86Local::AddRegFrm: 504 // Operand 1 is added to the opcode. 505 // Operand 2 (optional) is an address. 506 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 507 "Unexpected number of operands for AddRegFrm"); 508 HANDLE_OPERAND(opcodeModifier) 509 HANDLE_OPTIONAL(relocation) 510 break; 511 case X86Local::MRMDestReg: 512 // Operand 1 is a register operand in the R/M field. 513 // Operand 2 is a register operand in the Reg/Opcode field. 514 // - In AVX, there is a register operand in the VEX.vvvv field here - 515 // Operand 3 (optional) is an immediate. 516 if (HasVEX_4V) 517 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 518 "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); 519 else 520 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 521 "Unexpected number of operands for MRMDestRegFrm"); 522 523 HANDLE_OPERAND(rmRegister) 524 525 if (HasVEX_4V) 526 // FIXME: In AVX, the register below becomes the one encoded 527 // in ModRMVEX and the one above the one in the VEX.VVVV field 528 HANDLE_OPERAND(vvvvRegister) 529 530 HANDLE_OPERAND(roRegister) 531 HANDLE_OPTIONAL(immediate) 532 break; 533 case X86Local::MRMDestMem: 534 // Operand 1 is a memory operand (possibly SIB-extended) 535 // Operand 2 is a register operand in the Reg/Opcode field. 536 // - In AVX, there is a register operand in the VEX.vvvv field here - 537 // Operand 3 (optional) is an immediate. 538 if (HasVEX_4V) 539 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 540 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 541 else 542 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 543 "Unexpected number of operands for MRMDestMemFrm"); 544 HANDLE_OPERAND(memory) 545 546 if (HasEVEX_K) 547 HANDLE_OPERAND(writemaskRegister) 548 549 if (HasVEX_4V) 550 // FIXME: In AVX, the register below becomes the one encoded 551 // in ModRMVEX and the one above the one in the VEX.VVVV field 552 HANDLE_OPERAND(vvvvRegister) 553 554 HANDLE_OPERAND(roRegister) 555 HANDLE_OPTIONAL(immediate) 556 break; 557 case X86Local::MRMSrcReg: 558 // Operand 1 is a register operand in the Reg/Opcode field. 559 // Operand 2 is a register operand in the R/M field. 560 // - In AVX, there is a register operand in the VEX.vvvv field here - 561 // Operand 3 (optional) is an immediate. 562 // Operand 4 (optional) is an immediate. 563 564 if (HasVEX_4V || HasVEX_4VOp3) 565 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 566 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 567 else 568 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 && 569 "Unexpected number of operands for MRMSrcRegFrm"); 570 571 HANDLE_OPERAND(roRegister) 572 573 if (HasEVEX_K) 574 HANDLE_OPERAND(writemaskRegister) 575 576 if (HasVEX_4V) 577 // FIXME: In AVX, the register below becomes the one encoded 578 // in ModRMVEX and the one above the one in the VEX.VVVV field 579 HANDLE_OPERAND(vvvvRegister) 580 581 if (HasMemOp4Prefix) 582 HANDLE_OPERAND(immediate) 583 584 HANDLE_OPERAND(rmRegister) 585 586 if (HasVEX_4VOp3) 587 HANDLE_OPERAND(vvvvRegister) 588 589 if (!HasMemOp4Prefix) 590 HANDLE_OPTIONAL(immediate) 591 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 592 HANDLE_OPTIONAL(immediate) 593 break; 594 case X86Local::MRMSrcMem: 595 // Operand 1 is a register operand in the Reg/Opcode field. 596 // Operand 2 is a memory operand (possibly SIB-extended) 597 // - In AVX, there is a register operand in the VEX.vvvv field here - 598 // Operand 3 (optional) is an immediate. 599 600 if (HasVEX_4V || HasVEX_4VOp3) 601 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 602 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 603 else 604 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 605 "Unexpected number of operands for MRMSrcMemFrm"); 606 607 HANDLE_OPERAND(roRegister) 608 609 if (HasEVEX_K) 610 HANDLE_OPERAND(writemaskRegister) 611 612 if (HasVEX_4V) 613 // FIXME: In AVX, the register below becomes the one encoded 614 // in ModRMVEX and the one above the one in the VEX.VVVV field 615 HANDLE_OPERAND(vvvvRegister) 616 617 if (HasMemOp4Prefix) 618 HANDLE_OPERAND(immediate) 619 620 HANDLE_OPERAND(memory) 621 622 if (HasVEX_4VOp3) 623 HANDLE_OPERAND(vvvvRegister) 624 625 if (!HasMemOp4Prefix) 626 HANDLE_OPTIONAL(immediate) 627 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 628 break; 629 case X86Local::MRMXr: 630 case X86Local::MRM0r: 631 case X86Local::MRM1r: 632 case X86Local::MRM2r: 633 case X86Local::MRM3r: 634 case X86Local::MRM4r: 635 case X86Local::MRM5r: 636 case X86Local::MRM6r: 637 case X86Local::MRM7r: 638 { 639 // Operand 1 is a register operand in the R/M field. 640 // Operand 2 (optional) is an immediate or relocation. 641 // Operand 3 (optional) is an immediate. 642 unsigned kOp = (HasEVEX_K) ? 1:0; 643 unsigned Op4v = (HasVEX_4V) ? 1:0; 644 if (numPhysicalOperands > 3 + kOp + Op4v) 645 llvm_unreachable("Unexpected number of operands for MRMnr"); 646 } 647 if (HasVEX_4V) 648 HANDLE_OPERAND(vvvvRegister) 649 650 if (HasEVEX_K) 651 HANDLE_OPERAND(writemaskRegister) 652 HANDLE_OPTIONAL(rmRegister) 653 HANDLE_OPTIONAL(relocation) 654 HANDLE_OPTIONAL(immediate) 655 break; 656 case X86Local::MRMXm: 657 case X86Local::MRM0m: 658 case X86Local::MRM1m: 659 case X86Local::MRM2m: 660 case X86Local::MRM3m: 661 case X86Local::MRM4m: 662 case X86Local::MRM5m: 663 case X86Local::MRM6m: 664 case X86Local::MRM7m: 665 { 666 // Operand 1 is a memory operand (possibly SIB-extended) 667 // Operand 2 (optional) is an immediate or relocation. 668 unsigned kOp = (HasEVEX_K) ? 1:0; 669 unsigned Op4v = (HasVEX_4V) ? 1:0; 670 if (numPhysicalOperands < 1 + kOp + Op4v || 671 numPhysicalOperands > 2 + kOp + Op4v) 672 llvm_unreachable("Unexpected number of operands for MRMnm"); 673 } 674 if (HasVEX_4V) 675 HANDLE_OPERAND(vvvvRegister) 676 if (HasEVEX_K) 677 HANDLE_OPERAND(writemaskRegister) 678 HANDLE_OPERAND(memory) 679 HANDLE_OPTIONAL(relocation) 680 break; 681 case X86Local::RawFrmImm8: 682 // operand 1 is a 16-bit immediate 683 // operand 2 is an 8-bit immediate 684 assert(numPhysicalOperands == 2 && 685 "Unexpected number of operands for X86Local::RawFrmImm8"); 686 HANDLE_OPERAND(immediate) 687 HANDLE_OPERAND(immediate) 688 break; 689 case X86Local::RawFrmImm16: 690 // operand 1 is a 16-bit immediate 691 // operand 2 is a 16-bit immediate 692 HANDLE_OPERAND(immediate) 693 HANDLE_OPERAND(immediate) 694 break; 695 case X86Local::MRM_F8: 696 if (Opcode == 0xc6) { 697 assert(numPhysicalOperands == 1 && 698 "Unexpected number of operands for X86Local::MRM_F8"); 699 HANDLE_OPERAND(immediate) 700 } else if (Opcode == 0xc7) { 701 assert(numPhysicalOperands == 1 && 702 "Unexpected number of operands for X86Local::MRM_F8"); 703 HANDLE_OPERAND(relocation) 704 } 705 break; 706 case X86Local::MRM_C1: 707 case X86Local::MRM_C2: 708 case X86Local::MRM_C3: 709 case X86Local::MRM_C4: 710 case X86Local::MRM_C8: 711 case X86Local::MRM_C9: 712 case X86Local::MRM_CA: 713 case X86Local::MRM_CB: 714 case X86Local::MRM_E8: 715 case X86Local::MRM_F0: 716 case X86Local::MRM_F9: 717 case X86Local::MRM_D0: 718 case X86Local::MRM_D1: 719 case X86Local::MRM_D4: 720 case X86Local::MRM_D5: 721 case X86Local::MRM_D6: 722 case X86Local::MRM_D8: 723 case X86Local::MRM_D9: 724 case X86Local::MRM_DA: 725 case X86Local::MRM_DB: 726 case X86Local::MRM_DC: 727 case X86Local::MRM_DD: 728 case X86Local::MRM_DE: 729 case X86Local::MRM_DF: 730 // Ignored. 731 break; 732 } 733 734 #undef HANDLE_OPERAND 735 #undef HANDLE_OPTIONAL 736 } 737 738 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 739 // Special cases where the LLVM tables are not complete 740 741 #define MAP(from, to) \ 742 case X86Local::MRM_##from: \ 743 filter = new ExactFilter(0x##from); \ 744 break; 745 746 OpcodeType opcodeType = (OpcodeType)-1; 747 748 ModRMFilter* filter = NULL; 749 uint8_t opcodeToSet = 0; 750 751 switch (OpMap) { 752 default: llvm_unreachable("Invalid map!"); 753 case X86Local::OB: 754 case X86Local::TB: 755 case X86Local::T8: 756 case X86Local::TA: 757 case X86Local::A6: 758 case X86Local::A7: 759 case X86Local::XOP8: 760 case X86Local::XOP9: 761 case X86Local::XOPA: 762 switch (OpMap) { 763 default: llvm_unreachable("Unexpected map!"); 764 case X86Local::OB: opcodeType = ONEBYTE; break; 765 case X86Local::TB: opcodeType = TWOBYTE; break; 766 case X86Local::T8: opcodeType = THREEBYTE_38; break; 767 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 768 case X86Local::A6: opcodeType = THREEBYTE_A6; break; 769 case X86Local::A7: opcodeType = THREEBYTE_A7; break; 770 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 771 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 772 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 773 } 774 775 switch (Form) { 776 default: 777 filter = new DumbFilter(); 778 break; 779 case X86Local::MRMDestReg: case X86Local::MRMDestMem: 780 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem: 781 case X86Local::MRMXr: case X86Local::MRMXm: 782 filter = new ModFilter(isRegFormat(Form)); 783 break; 784 case X86Local::MRM0r: case X86Local::MRM1r: 785 case X86Local::MRM2r: case X86Local::MRM3r: 786 case X86Local::MRM4r: case X86Local::MRM5r: 787 case X86Local::MRM6r: case X86Local::MRM7r: 788 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 789 break; 790 case X86Local::MRM0m: case X86Local::MRM1m: 791 case X86Local::MRM2m: case X86Local::MRM3m: 792 case X86Local::MRM4m: case X86Local::MRM5m: 793 case X86Local::MRM6m: case X86Local::MRM7m: 794 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 795 break; 796 MRM_MAPPING 797 } // switch (Form) 798 799 opcodeToSet = Opcode; 800 break; 801 case X86Local::D8: 802 case X86Local::D9: 803 case X86Local::DA: 804 case X86Local::DB: 805 case X86Local::DC: 806 case X86Local::DD: 807 case X86Local::DE: 808 case X86Local::DF: 809 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); 810 assert(Form == X86Local::RawFrm); 811 opcodeType = ONEBYTE; 812 filter = new ExactFilter(Opcode); 813 opcodeToSet = 0xd8 + (OpMap - X86Local::D8); 814 break; 815 } // switch (OpMap) 816 817 assert(opcodeType != (OpcodeType)-1 && 818 "Opcode type not set"); 819 assert(filter && "Filter not set"); 820 821 if (Form == X86Local::AddRegFrm) { 822 assert(((opcodeToSet & 7) == 0) && 823 "ADDREG_FRM opcode not aligned"); 824 825 uint8_t currentOpcode; 826 827 for (currentOpcode = opcodeToSet; 828 currentOpcode < opcodeToSet + 8; 829 ++currentOpcode) 830 tables.setTableFields(opcodeType, 831 insnContext(), 832 currentOpcode, 833 *filter, 834 UID, Is32Bit, IgnoresVEX_L); 835 } else { 836 tables.setTableFields(opcodeType, 837 insnContext(), 838 opcodeToSet, 839 *filter, 840 UID, Is32Bit, IgnoresVEX_L); 841 } 842 843 delete filter; 844 845 #undef MAP 846 } 847 848 #define TYPE(str, type) if (s == str) return type; 849 OperandType RecognizableInstr::typeFromString(const std::string &s, 850 bool hasREX_WPrefix, 851 uint8_t OpSize) { 852 if(hasREX_WPrefix) { 853 // For instructions with a REX_W prefix, a declared 32-bit register encoding 854 // is special. 855 TYPE("GR32", TYPE_R32) 856 } 857 if(OpSize == X86Local::OpSize16) { 858 // For OpSize16 instructions, a declared 16-bit register or 859 // immediate encoding is special. 860 TYPE("GR16", TYPE_Rv) 861 TYPE("i16imm", TYPE_IMMv) 862 } else if(OpSize == X86Local::OpSize32) { 863 // For OpSize32 instructions, a declared 32-bit register or 864 // immediate encoding is special. 865 TYPE("GR32", TYPE_Rv) 866 } 867 TYPE("i16mem", TYPE_Mv) 868 TYPE("i16imm", TYPE_IMM16) 869 TYPE("i16i8imm", TYPE_IMMv) 870 TYPE("GR16", TYPE_R16) 871 TYPE("i32mem", TYPE_Mv) 872 TYPE("i32imm", TYPE_IMMv) 873 TYPE("i32i8imm", TYPE_IMM32) 874 TYPE("u32u8imm", TYPE_IMM32) 875 TYPE("GR32", TYPE_R32) 876 TYPE("GR32orGR64", TYPE_R32) 877 TYPE("i64mem", TYPE_Mv) 878 TYPE("i64i32imm", TYPE_IMM64) 879 TYPE("i64i8imm", TYPE_IMM64) 880 TYPE("GR64", TYPE_R64) 881 TYPE("i8mem", TYPE_M8) 882 TYPE("i8imm", TYPE_IMM8) 883 TYPE("GR8", TYPE_R8) 884 TYPE("VR128", TYPE_XMM128) 885 TYPE("VR128X", TYPE_XMM128) 886 TYPE("f128mem", TYPE_M128) 887 TYPE("f256mem", TYPE_M256) 888 TYPE("f512mem", TYPE_M512) 889 TYPE("FR64", TYPE_XMM64) 890 TYPE("FR64X", TYPE_XMM64) 891 TYPE("f64mem", TYPE_M64FP) 892 TYPE("sdmem", TYPE_M64FP) 893 TYPE("FR32", TYPE_XMM32) 894 TYPE("FR32X", TYPE_XMM32) 895 TYPE("f32mem", TYPE_M32FP) 896 TYPE("ssmem", TYPE_M32FP) 897 TYPE("RST", TYPE_ST) 898 TYPE("i128mem", TYPE_M128) 899 TYPE("i256mem", TYPE_M256) 900 TYPE("i512mem", TYPE_M512) 901 TYPE("i64i32imm_pcrel", TYPE_REL64) 902 TYPE("i16imm_pcrel", TYPE_REL16) 903 TYPE("i32imm_pcrel", TYPE_REL32) 904 TYPE("SSECC", TYPE_IMM3) 905 TYPE("AVXCC", TYPE_IMM5) 906 TYPE("AVX512RC", TYPE_IMM32) 907 TYPE("brtarget", TYPE_RELv) 908 TYPE("uncondbrtarget", TYPE_RELv) 909 TYPE("brtarget8", TYPE_REL8) 910 TYPE("f80mem", TYPE_M80FP) 911 TYPE("lea32mem", TYPE_LEA) 912 TYPE("lea64_32mem", TYPE_LEA) 913 TYPE("lea64mem", TYPE_LEA) 914 TYPE("VR64", TYPE_MM64) 915 TYPE("i64imm", TYPE_IMMv) 916 TYPE("opaque32mem", TYPE_M1616) 917 TYPE("opaque48mem", TYPE_M1632) 918 TYPE("opaque80mem", TYPE_M1664) 919 TYPE("opaque512mem", TYPE_M512) 920 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 921 TYPE("DEBUG_REG", TYPE_DEBUGREG) 922 TYPE("CONTROL_REG", TYPE_CONTROLREG) 923 TYPE("srcidx8", TYPE_SRCIDX8) 924 TYPE("srcidx16", TYPE_SRCIDX16) 925 TYPE("srcidx32", TYPE_SRCIDX32) 926 TYPE("srcidx64", TYPE_SRCIDX64) 927 TYPE("dstidx8", TYPE_DSTIDX8) 928 TYPE("dstidx16", TYPE_DSTIDX16) 929 TYPE("dstidx32", TYPE_DSTIDX32) 930 TYPE("dstidx64", TYPE_DSTIDX64) 931 TYPE("offset8", TYPE_MOFFS8) 932 TYPE("offset16", TYPE_MOFFS16) 933 TYPE("offset32", TYPE_MOFFS32) 934 TYPE("offset64", TYPE_MOFFS64) 935 TYPE("VR256", TYPE_XMM256) 936 TYPE("VR256X", TYPE_XMM256) 937 TYPE("VR512", TYPE_XMM512) 938 TYPE("VK1", TYPE_VK1) 939 TYPE("VK1WM", TYPE_VK1) 940 TYPE("VK8", TYPE_VK8) 941 TYPE("VK8WM", TYPE_VK8) 942 TYPE("VK16", TYPE_VK16) 943 TYPE("VK16WM", TYPE_VK16) 944 TYPE("GR16_NOAX", TYPE_Rv) 945 TYPE("GR32_NOAX", TYPE_Rv) 946 TYPE("GR64_NOAX", TYPE_R64) 947 TYPE("vx32mem", TYPE_M32) 948 TYPE("vy32mem", TYPE_M32) 949 TYPE("vz32mem", TYPE_M32) 950 TYPE("vx64mem", TYPE_M64) 951 TYPE("vy64mem", TYPE_M64) 952 TYPE("vy64xmem", TYPE_M64) 953 TYPE("vz64mem", TYPE_M64) 954 errs() << "Unhandled type string " << s << "\n"; 955 llvm_unreachable("Unhandled type string"); 956 } 957 #undef TYPE 958 959 #define ENCODING(str, encoding) if (s == str) return encoding; 960 OperandEncoding 961 RecognizableInstr::immediateEncodingFromString(const std::string &s, 962 uint8_t OpSize) { 963 if(OpSize != X86Local::OpSize16) { 964 // For instructions without an OpSize prefix, a declared 16-bit register or 965 // immediate encoding is special. 966 ENCODING("i16imm", ENCODING_IW) 967 } 968 ENCODING("i32i8imm", ENCODING_IB) 969 ENCODING("u32u8imm", ENCODING_IB) 970 ENCODING("SSECC", ENCODING_IB) 971 ENCODING("AVXCC", ENCODING_IB) 972 ENCODING("AVX512RC", ENCODING_IB) 973 ENCODING("i16imm", ENCODING_Iv) 974 ENCODING("i16i8imm", ENCODING_IB) 975 ENCODING("i32imm", ENCODING_Iv) 976 ENCODING("i64i32imm", ENCODING_ID) 977 ENCODING("i64i8imm", ENCODING_IB) 978 ENCODING("i8imm", ENCODING_IB) 979 // This is not a typo. Instructions like BLENDVPD put 980 // register IDs in 8-bit immediates nowadays. 981 ENCODING("FR32", ENCODING_IB) 982 ENCODING("FR64", ENCODING_IB) 983 ENCODING("VR128", ENCODING_IB) 984 ENCODING("VR256", ENCODING_IB) 985 ENCODING("FR32X", ENCODING_IB) 986 ENCODING("FR64X", ENCODING_IB) 987 ENCODING("VR128X", ENCODING_IB) 988 ENCODING("VR256X", ENCODING_IB) 989 ENCODING("VR512", ENCODING_IB) 990 errs() << "Unhandled immediate encoding " << s << "\n"; 991 llvm_unreachable("Unhandled immediate encoding"); 992 } 993 994 OperandEncoding 995 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 996 uint8_t OpSize) { 997 ENCODING("RST", ENCODING_FP) 998 ENCODING("GR16", ENCODING_RM) 999 ENCODING("GR32", ENCODING_RM) 1000 ENCODING("GR32orGR64", ENCODING_RM) 1001 ENCODING("GR64", ENCODING_RM) 1002 ENCODING("GR8", ENCODING_RM) 1003 ENCODING("VR128", ENCODING_RM) 1004 ENCODING("VR128X", ENCODING_RM) 1005 ENCODING("FR64", ENCODING_RM) 1006 ENCODING("FR32", ENCODING_RM) 1007 ENCODING("FR64X", ENCODING_RM) 1008 ENCODING("FR32X", ENCODING_RM) 1009 ENCODING("VR64", ENCODING_RM) 1010 ENCODING("VR256", ENCODING_RM) 1011 ENCODING("VR256X", ENCODING_RM) 1012 ENCODING("VR512", ENCODING_RM) 1013 ENCODING("VK1", ENCODING_RM) 1014 ENCODING("VK8", ENCODING_RM) 1015 ENCODING("VK16", ENCODING_RM) 1016 errs() << "Unhandled R/M register encoding " << s << "\n"; 1017 llvm_unreachable("Unhandled R/M register encoding"); 1018 } 1019 1020 OperandEncoding 1021 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1022 uint8_t OpSize) { 1023 ENCODING("GR16", ENCODING_REG) 1024 ENCODING("GR32", ENCODING_REG) 1025 ENCODING("GR32orGR64", ENCODING_REG) 1026 ENCODING("GR64", ENCODING_REG) 1027 ENCODING("GR8", ENCODING_REG) 1028 ENCODING("VR128", ENCODING_REG) 1029 ENCODING("FR64", ENCODING_REG) 1030 ENCODING("FR32", ENCODING_REG) 1031 ENCODING("VR64", ENCODING_REG) 1032 ENCODING("SEGMENT_REG", ENCODING_REG) 1033 ENCODING("DEBUG_REG", ENCODING_REG) 1034 ENCODING("CONTROL_REG", ENCODING_REG) 1035 ENCODING("VR256", ENCODING_REG) 1036 ENCODING("VR256X", ENCODING_REG) 1037 ENCODING("VR128X", ENCODING_REG) 1038 ENCODING("FR64X", ENCODING_REG) 1039 ENCODING("FR32X", ENCODING_REG) 1040 ENCODING("VR512", ENCODING_REG) 1041 ENCODING("VK1", ENCODING_REG) 1042 ENCODING("VK8", ENCODING_REG) 1043 ENCODING("VK16", ENCODING_REG) 1044 ENCODING("VK1WM", ENCODING_REG) 1045 ENCODING("VK8WM", ENCODING_REG) 1046 ENCODING("VK16WM", ENCODING_REG) 1047 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1048 llvm_unreachable("Unhandled reg/opcode register encoding"); 1049 } 1050 1051 OperandEncoding 1052 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1053 uint8_t OpSize) { 1054 ENCODING("GR32", ENCODING_VVVV) 1055 ENCODING("GR64", ENCODING_VVVV) 1056 ENCODING("FR32", ENCODING_VVVV) 1057 ENCODING("FR64", ENCODING_VVVV) 1058 ENCODING("VR128", ENCODING_VVVV) 1059 ENCODING("VR256", ENCODING_VVVV) 1060 ENCODING("FR32X", ENCODING_VVVV) 1061 ENCODING("FR64X", ENCODING_VVVV) 1062 ENCODING("VR128X", ENCODING_VVVV) 1063 ENCODING("VR256X", ENCODING_VVVV) 1064 ENCODING("VR512", ENCODING_VVVV) 1065 ENCODING("VK1", ENCODING_VVVV) 1066 ENCODING("VK8", ENCODING_VVVV) 1067 ENCODING("VK16", ENCODING_VVVV) 1068 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1069 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1070 } 1071 1072 OperandEncoding 1073 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1074 uint8_t OpSize) { 1075 ENCODING("VK1WM", ENCODING_WRITEMASK) 1076 ENCODING("VK8WM", ENCODING_WRITEMASK) 1077 ENCODING("VK16WM", ENCODING_WRITEMASK) 1078 errs() << "Unhandled mask register encoding " << s << "\n"; 1079 llvm_unreachable("Unhandled mask register encoding"); 1080 } 1081 1082 OperandEncoding 1083 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1084 uint8_t OpSize) { 1085 ENCODING("i16mem", ENCODING_RM) 1086 ENCODING("i32mem", ENCODING_RM) 1087 ENCODING("i64mem", ENCODING_RM) 1088 ENCODING("i8mem", ENCODING_RM) 1089 ENCODING("ssmem", ENCODING_RM) 1090 ENCODING("sdmem", ENCODING_RM) 1091 ENCODING("f128mem", ENCODING_RM) 1092 ENCODING("f256mem", ENCODING_RM) 1093 ENCODING("f512mem", ENCODING_RM) 1094 ENCODING("f64mem", ENCODING_RM) 1095 ENCODING("f32mem", ENCODING_RM) 1096 ENCODING("i128mem", ENCODING_RM) 1097 ENCODING("i256mem", ENCODING_RM) 1098 ENCODING("i512mem", ENCODING_RM) 1099 ENCODING("f80mem", ENCODING_RM) 1100 ENCODING("lea32mem", ENCODING_RM) 1101 ENCODING("lea64_32mem", ENCODING_RM) 1102 ENCODING("lea64mem", ENCODING_RM) 1103 ENCODING("opaque32mem", ENCODING_RM) 1104 ENCODING("opaque48mem", ENCODING_RM) 1105 ENCODING("opaque80mem", ENCODING_RM) 1106 ENCODING("opaque512mem", ENCODING_RM) 1107 ENCODING("vx32mem", ENCODING_RM) 1108 ENCODING("vy32mem", ENCODING_RM) 1109 ENCODING("vz32mem", ENCODING_RM) 1110 ENCODING("vx64mem", ENCODING_RM) 1111 ENCODING("vy64mem", ENCODING_RM) 1112 ENCODING("vy64xmem", ENCODING_RM) 1113 ENCODING("vz64mem", ENCODING_RM) 1114 errs() << "Unhandled memory encoding " << s << "\n"; 1115 llvm_unreachable("Unhandled memory encoding"); 1116 } 1117 1118 OperandEncoding 1119 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1120 uint8_t OpSize) { 1121 if(OpSize != X86Local::OpSize16) { 1122 // For instructions without an OpSize prefix, a declared 16-bit register or 1123 // immediate encoding is special. 1124 ENCODING("i16imm", ENCODING_IW) 1125 } 1126 ENCODING("i16imm", ENCODING_Iv) 1127 ENCODING("i16i8imm", ENCODING_IB) 1128 ENCODING("i32imm", ENCODING_Iv) 1129 ENCODING("i32i8imm", ENCODING_IB) 1130 ENCODING("i64i32imm", ENCODING_ID) 1131 ENCODING("i64i8imm", ENCODING_IB) 1132 ENCODING("i8imm", ENCODING_IB) 1133 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1134 ENCODING("i16imm_pcrel", ENCODING_IW) 1135 ENCODING("i32imm_pcrel", ENCODING_ID) 1136 ENCODING("brtarget", ENCODING_Iv) 1137 ENCODING("brtarget8", ENCODING_IB) 1138 ENCODING("i64imm", ENCODING_IO) 1139 ENCODING("offset8", ENCODING_Ia) 1140 ENCODING("offset16", ENCODING_Ia) 1141 ENCODING("offset32", ENCODING_Ia) 1142 ENCODING("offset64", ENCODING_Ia) 1143 ENCODING("srcidx8", ENCODING_SI) 1144 ENCODING("srcidx16", ENCODING_SI) 1145 ENCODING("srcidx32", ENCODING_SI) 1146 ENCODING("srcidx64", ENCODING_SI) 1147 ENCODING("dstidx8", ENCODING_DI) 1148 ENCODING("dstidx16", ENCODING_DI) 1149 ENCODING("dstidx32", ENCODING_DI) 1150 ENCODING("dstidx64", ENCODING_DI) 1151 errs() << "Unhandled relocation encoding " << s << "\n"; 1152 llvm_unreachable("Unhandled relocation encoding"); 1153 } 1154 1155 OperandEncoding 1156 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1157 uint8_t OpSize) { 1158 ENCODING("GR32", ENCODING_Rv) 1159 ENCODING("GR64", ENCODING_RO) 1160 ENCODING("GR16", ENCODING_Rv) 1161 ENCODING("GR8", ENCODING_RB) 1162 ENCODING("GR16_NOAX", ENCODING_Rv) 1163 ENCODING("GR32_NOAX", ENCODING_Rv) 1164 ENCODING("GR64_NOAX", ENCODING_RO) 1165 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1166 llvm_unreachable("Unhandled opcode modifier encoding"); 1167 } 1168 #undef ENCODING 1169