1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)           \
40   MAP(D4, 47)           \
41   MAP(D8, 48)           \
42   MAP(D9, 49)           \
43   MAP(DA, 50)           \
44   MAP(DB, 51)           \
45   MAP(DC, 52)           \
46   MAP(DD, 53)           \
47   MAP(DE, 54)           \
48   MAP(DF, 55)
49 
50 // A clone of X86 since we can't depend on something that is generated.
51 namespace X86Local {
52   enum {
53     Pseudo      = 0,
54     RawFrm      = 1,
55     AddRegFrm   = 2,
56     MRMDestReg  = 3,
57     MRMDestMem  = 4,
58     MRMSrcReg   = 5,
59     MRMSrcMem   = 6,
60     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
61     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
62     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
63     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
64     MRMInitReg  = 32,
65 #define MAP(from, to) MRM_##from = to,
66     MRM_MAPPING
67 #undef MAP
68     RawFrmImm8  = 43,
69     RawFrmImm16 = 44,
70     lastMRM
71   };
72 
73   enum {
74     TB  = 1,
75     REP = 2,
76     D8 = 3, D9 = 4, DA = 5, DB = 6,
77     DC = 7, DD = 8, DE = 9, DF = 10,
78     XD = 11,  XS = 12,
79     T8 = 13,  P_TA = 14,
80     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
81   };
82 }
83 
84 // If rows are added to the opcode extension tables, then corresponding entries
85 // must be added here.
86 //
87 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
88 // that byte to ONE_BYTE_EXTENSION_TABLES.
89 //
90 // If the row corresponds to two bytes where the first is 0f, add an entry for
91 // the second byte to TWO_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to some other set of bytes, you will need to modify
94 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
95 // to the X86 TD files, except in two cases: if the first two bytes of such a
96 // new combination are 0f 38 or 0f 3a, you just have to add maps called
97 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
98 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
99 // in RecognizableInstr::emitDecodePath().
100 
101 #define ONE_BYTE_EXTENSION_TABLES \
102   EXTENSION_TABLE(80)             \
103   EXTENSION_TABLE(81)             \
104   EXTENSION_TABLE(82)             \
105   EXTENSION_TABLE(83)             \
106   EXTENSION_TABLE(8f)             \
107   EXTENSION_TABLE(c0)             \
108   EXTENSION_TABLE(c1)             \
109   EXTENSION_TABLE(c6)             \
110   EXTENSION_TABLE(c7)             \
111   EXTENSION_TABLE(d0)             \
112   EXTENSION_TABLE(d1)             \
113   EXTENSION_TABLE(d2)             \
114   EXTENSION_TABLE(d3)             \
115   EXTENSION_TABLE(f6)             \
116   EXTENSION_TABLE(f7)             \
117   EXTENSION_TABLE(fe)             \
118   EXTENSION_TABLE(ff)
119 
120 #define TWO_BYTE_EXTENSION_TABLES \
121   EXTENSION_TABLE(00)             \
122   EXTENSION_TABLE(01)             \
123   EXTENSION_TABLE(18)             \
124   EXTENSION_TABLE(71)             \
125   EXTENSION_TABLE(72)             \
126   EXTENSION_TABLE(73)             \
127   EXTENSION_TABLE(ae)             \
128   EXTENSION_TABLE(ba)             \
129   EXTENSION_TABLE(c7)
130 
131 #define THREE_BYTE_38_EXTENSION_TABLES \
132   EXTENSION_TABLE(F3)
133 
134 using namespace X86Disassembler;
135 
136 /// needsModRMForDecode - Indicates whether a particular instruction requires a
137 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
138 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
139 ///   0b11.
140 ///
141 /// @param form - The form of the instruction.
142 /// @return     - true if the form implies that a ModR/M byte is required, false
143 ///               otherwise.
144 static bool needsModRMForDecode(uint8_t form) {
145   if (form == X86Local::MRMDestReg    ||
146      form == X86Local::MRMDestMem    ||
147      form == X86Local::MRMSrcReg     ||
148      form == X86Local::MRMSrcMem     ||
149      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
150      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
151     return true;
152   else
153     return false;
154 }
155 
156 /// isRegFormat - Indicates whether a particular form requires the Mod field of
157 ///   the ModR/M byte to be 0b11.
158 ///
159 /// @param form - The form of the instruction.
160 /// @return     - true if the form implies that Mod must be 0b11, false
161 ///               otherwise.
162 static bool isRegFormat(uint8_t form) {
163   if (form == X86Local::MRMDestReg ||
164      form == X86Local::MRMSrcReg  ||
165      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
166     return true;
167   else
168     return false;
169 }
170 
171 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
172 ///   Useful for switch statements and the like.
173 ///
174 /// @param init - A reference to the BitsInit to be decoded.
175 /// @return     - The field, with the first bit in the BitsInit as the lowest
176 ///               order bit.
177 static uint8_t byteFromBitsInit(BitsInit &init) {
178   int width = init.getNumBits();
179 
180   assert(width <= 8 && "Field is too large for uint8_t!");
181 
182   int     index;
183   uint8_t mask = 0x01;
184 
185   uint8_t ret = 0;
186 
187   for (index = 0; index < width; index++) {
188     if (static_cast<BitInit*>(init.getBit(index))->getValue())
189       ret |= mask;
190 
191     mask <<= 1;
192   }
193 
194   return ret;
195 }
196 
197 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
198 ///   name of the field.
199 ///
200 /// @param rec  - The record from which to extract the value.
201 /// @param name - The name of the field in the record.
202 /// @return     - The field, as translated by byteFromBitsInit().
203 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
204   BitsInit* bits = rec->getValueAsBitsInit(name);
205   return byteFromBitsInit(*bits);
206 }
207 
208 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
209                                      const CodeGenInstruction &insn,
210                                      InstrUID uid) {
211   UID = uid;
212 
213   Rec = insn.TheDef;
214   Name = Rec->getName();
215   Spec = &tables.specForUID(UID);
216 
217   if (!Rec->isSubClassOf("X86Inst")) {
218     ShouldBeEmitted = false;
219     return;
220   }
221 
222   Prefix   = byteFromRec(Rec, "Prefix");
223   Opcode   = byteFromRec(Rec, "Opcode");
224   Form     = byteFromRec(Rec, "FormBits");
225   SegOvr   = byteFromRec(Rec, "SegOvrBits");
226 
227   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
228   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
229   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
230   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
231   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
232   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
233   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
234   HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
235   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
236   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
237   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
238 
239   Name      = Rec->getName();
240   AsmString = Rec->getValueAsString("AsmString");
241 
242   Operands = &insn.Operands.OperandList;
243 
244   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
245                      (Name.find("CRC32") != Name.npos);
246   HasFROperands    = hasFROperands();
247   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
248 
249   // Check for 64-bit inst which does not require REX
250   Is32Bit = false;
251   Is64Bit = false;
252   // FIXME: Is there some better way to check for In64BitMode?
253   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
254   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
255     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
256       Is32Bit = true;
257       break;
258     }
259     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
260       Is64Bit = true;
261       break;
262     }
263   }
264   // FIXME: These instructions aren't marked as 64-bit in any way
265   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
266              Rec->getName() == "MASKMOVDQU64" ||
267              Rec->getName() == "POPFS64" ||
268              Rec->getName() == "POPGS64" ||
269              Rec->getName() == "PUSHFS64" ||
270              Rec->getName() == "PUSHGS64" ||
271              Rec->getName() == "REX64_PREFIX" ||
272              Rec->getName().find("MOV64") != Name.npos ||
273              Rec->getName().find("PUSH64") != Name.npos ||
274              Rec->getName().find("POP64") != Name.npos;
275 
276   ShouldBeEmitted  = true;
277 }
278 
279 void RecognizableInstr::processInstr(DisassemblerTables &tables,
280 	const CodeGenInstruction &insn,
281                                    InstrUID uid)
282 {
283   // Ignore "asm parser only" instructions.
284   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
285     return;
286 
287   RecognizableInstr recogInstr(tables, insn, uid);
288 
289   recogInstr.emitInstructionSpecifier(tables);
290 
291   if (recogInstr.shouldBeEmitted())
292     recogInstr.emitDecodePath(tables);
293 }
294 
295 InstructionContext RecognizableInstr::insnContext() const {
296   InstructionContext insnContext;
297 
298   if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
299     if (HasVEX_LPrefix && HasVEX_WPrefix) {
300       if (HasOpSizePrefix)
301         insnContext = IC_VEX_L_W_OPSIZE;
302       else
303         llvm_unreachable("Don't support VEX.L and VEX.W together");
304     } else if (HasOpSizePrefix && HasVEX_LPrefix)
305       insnContext = IC_VEX_L_OPSIZE;
306     else if (HasOpSizePrefix && HasVEX_WPrefix)
307       insnContext = IC_VEX_W_OPSIZE;
308     else if (HasOpSizePrefix)
309       insnContext = IC_VEX_OPSIZE;
310     else if (HasVEX_LPrefix &&
311              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
312       insnContext = IC_VEX_L_XS;
313     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
314                                 Prefix == X86Local::T8XD ||
315                                 Prefix == X86Local::TAXD))
316       insnContext = IC_VEX_L_XD;
317     else if (HasVEX_WPrefix &&
318              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
319       insnContext = IC_VEX_W_XS;
320     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
321                                 Prefix == X86Local::T8XD ||
322                                 Prefix == X86Local::TAXD))
323       insnContext = IC_VEX_W_XD;
324     else if (HasVEX_WPrefix)
325       insnContext = IC_VEX_W;
326     else if (HasVEX_LPrefix)
327       insnContext = IC_VEX_L;
328     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329              Prefix == X86Local::TAXD)
330       insnContext = IC_VEX_XD;
331     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
332       insnContext = IC_VEX_XS;
333     else
334       insnContext = IC_VEX;
335   } else if (Is64Bit || HasREX_WPrefix) {
336     if (HasREX_WPrefix && HasOpSizePrefix)
337       insnContext = IC_64BIT_REXW_OPSIZE;
338     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
339                                  Prefix == X86Local::T8XD ||
340                                  Prefix == X86Local::TAXD))
341       insnContext = IC_64BIT_XD_OPSIZE;
342     else if (HasOpSizePrefix &&
343              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
344       insnContext = IC_64BIT_XS_OPSIZE;
345     else if (HasOpSizePrefix)
346       insnContext = IC_64BIT_OPSIZE;
347     else if (HasAdSizePrefix)
348       insnContext = IC_64BIT_ADSIZE;
349     else if (HasREX_WPrefix &&
350              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
351       insnContext = IC_64BIT_REXW_XS;
352     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
353                                 Prefix == X86Local::T8XD ||
354                                 Prefix == X86Local::TAXD))
355       insnContext = IC_64BIT_REXW_XD;
356     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357              Prefix == X86Local::TAXD)
358       insnContext = IC_64BIT_XD;
359     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360       insnContext = IC_64BIT_XS;
361     else if (HasREX_WPrefix)
362       insnContext = IC_64BIT_REXW;
363     else
364       insnContext = IC_64BIT;
365   } else {
366     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
367                             Prefix == X86Local::T8XD ||
368                             Prefix == X86Local::TAXD))
369       insnContext = IC_XD_OPSIZE;
370     else if (HasOpSizePrefix &&
371              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
372       insnContext = IC_XS_OPSIZE;
373     else if (HasOpSizePrefix)
374       insnContext = IC_OPSIZE;
375     else if (HasAdSizePrefix)
376       insnContext = IC_ADSIZE;
377     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378              Prefix == X86Local::TAXD)
379       insnContext = IC_XD;
380     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
381              Prefix == X86Local::REP)
382       insnContext = IC_XS;
383     else
384       insnContext = IC;
385   }
386 
387   return insnContext;
388 }
389 
390 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
391   ///////////////////
392   // FILTER_STRONG
393   //
394 
395   // Filter out intrinsics
396 
397   if (!Rec->isSubClassOf("X86Inst"))
398     return FILTER_STRONG;
399 
400   if (Form == X86Local::Pseudo ||
401       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
402     return FILTER_STRONG;
403 
404   if (Form == X86Local::MRMInitReg)
405     return FILTER_STRONG;
406 
407 
408   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
409   // printed as a separate "instruction".
410 
411   if (Name.find("_Int") != Name.npos       ||
412       Name.find("Int_") != Name.npos       ||
413       Name.find("_NOREX") != Name.npos     ||
414       Name.find("2SDL") != Name.npos)
415     return FILTER_STRONG;
416 
417   // Filter out instructions with segment override prefixes.
418   // They're too messy to handle now and we'll special case them if needed.
419 
420   if (SegOvr)
421     return FILTER_STRONG;
422 
423   // Filter out instructions that can't be printed.
424 
425   if (AsmString.size() == 0)
426     return FILTER_STRONG;
427 
428   // Filter out instructions with subreg operands.
429 
430   if (AsmString.find("subreg") != AsmString.npos)
431     return FILTER_STRONG;
432 
433   /////////////////
434   // FILTER_WEAK
435   //
436 
437 
438   // Filter out instructions with a LOCK prefix;
439   //   prefer forms that do not have the prefix
440   if (HasLockPrefix)
441     return FILTER_WEAK;
442 
443   // Filter out alternate forms of AVX instructions
444   if (Name.find("_alt") != Name.npos ||
445       Name.find("XrYr") != Name.npos ||
446       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
447       Name.find("_64mr") != Name.npos ||
448       Name.find("Xrr") != Name.npos ||
449       Name.find("rr64") != Name.npos)
450     return FILTER_WEAK;
451 
452   // Special cases.
453 
454   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
455     return FILTER_WEAK;
456   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
457     return FILTER_WEAK;
458 
459   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
460     return FILTER_WEAK;
461   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
462     return FILTER_WEAK;
463   if (Name.find("Fs") != Name.npos)
464     return FILTER_WEAK;
465   if (Name == "PUSH64i16"         ||
466       Name == "MOVPQI2QImr"       ||
467       Name == "VMOVPQI2QImr"      ||
468       Name == "MMX_MOVD64rrv164"  ||
469       Name == "MOV64ri64i32"      ||
470       Name == "VMASKMOVDQU64"     ||
471       Name == "VEXTRACTPSrr64"    ||
472       Name == "VMOVQd64rr"        ||
473       Name == "VMOVQs64rr")
474     return FILTER_WEAK;
475 
476   if (HasFROperands && Name.find("MOV") != Name.npos &&
477      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
478       (Name.find("to") != Name.npos)))
479     return FILTER_WEAK;
480 
481   return FILTER_NORMAL;
482 }
483 
484 bool RecognizableInstr::hasFROperands() const {
485   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
486   unsigned numOperands = OperandList.size();
487 
488   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
489     const std::string &recName = OperandList[operandIndex].Rec->getName();
490 
491     if (recName.find("FR") != recName.npos)
492       return true;
493   }
494   return false;
495 }
496 
497 bool RecognizableInstr::has256BitOperands() const {
498   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
499   unsigned numOperands = OperandList.size();
500 
501   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
502     const std::string &recName = OperandList[operandIndex].Rec->getName();
503 
504     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
505       return true;
506     }
507   }
508   return false;
509 }
510 
511 void RecognizableInstr::handleOperand(
512   bool optional,
513   unsigned &operandIndex,
514   unsigned &physicalOperandIndex,
515   unsigned &numPhysicalOperands,
516   unsigned *operandMapping,
517   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
518   if (optional) {
519     if (physicalOperandIndex >= numPhysicalOperands)
520       return;
521   } else {
522     assert(physicalOperandIndex < numPhysicalOperands);
523   }
524 
525   while (operandMapping[operandIndex] != operandIndex) {
526     Spec->operands[operandIndex].encoding = ENCODING_DUP;
527     Spec->operands[operandIndex].type =
528       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
529     ++operandIndex;
530   }
531 
532   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
533 
534   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
535                                                               HasOpSizePrefix);
536   Spec->operands[operandIndex].type = typeFromString(typeName,
537                                                      IsSSE,
538                                                      HasREX_WPrefix,
539                                                      HasOpSizePrefix);
540 
541   ++operandIndex;
542   ++physicalOperandIndex;
543 }
544 
545 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
546   Spec->name       = Name;
547 
548   if (!Rec->isSubClassOf("X86Inst"))
549     return;
550 
551   switch (filter()) {
552   case FILTER_WEAK:
553     Spec->filtered = true;
554     break;
555   case FILTER_STRONG:
556     ShouldBeEmitted = false;
557     return;
558   case FILTER_NORMAL:
559     break;
560   }
561 
562   Spec->insnContext = insnContext();
563 
564   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
565 
566   unsigned operandIndex;
567   unsigned numOperands = OperandList.size();
568   unsigned numPhysicalOperands = 0;
569 
570   // operandMapping maps from operands in OperandList to their originals.
571   // If operandMapping[i] != i, then the entry is a duplicate.
572   unsigned operandMapping[X86_MAX_OPERANDS];
573 
574   bool hasFROperands = false;
575 
576   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
577 
578   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
579     if (OperandList[operandIndex].Constraints.size()) {
580       const CGIOperandList::ConstraintInfo &Constraint =
581         OperandList[operandIndex].Constraints[0];
582       if (Constraint.isTied()) {
583         operandMapping[operandIndex] = Constraint.getTiedOperand();
584       } else {
585         ++numPhysicalOperands;
586         operandMapping[operandIndex] = operandIndex;
587       }
588     } else {
589       ++numPhysicalOperands;
590       operandMapping[operandIndex] = operandIndex;
591     }
592 
593     const std::string &recName = OperandList[operandIndex].Rec->getName();
594 
595     if (recName.find("FR") != recName.npos)
596       hasFROperands = true;
597   }
598 
599   if (hasFROperands && Name.find("MOV") != Name.npos &&
600      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
601       (Name.find("to") != Name.npos)))
602     ShouldBeEmitted = false;
603 
604   if (!ShouldBeEmitted)
605     return;
606 
607 #define HANDLE_OPERAND(class)               \
608   handleOperand(false,                      \
609                 operandIndex,               \
610                 physicalOperandIndex,       \
611                 numPhysicalOperands,        \
612                 operandMapping,             \
613                 class##EncodingFromString);
614 
615 #define HANDLE_OPTIONAL(class)              \
616   handleOperand(true,                       \
617                 operandIndex,               \
618                 physicalOperandIndex,       \
619                 numPhysicalOperands,        \
620                 operandMapping,             \
621                 class##EncodingFromString);
622 
623   // operandIndex should always be < numOperands
624   operandIndex = 0;
625   // physicalOperandIndex should always be < numPhysicalOperands
626   unsigned physicalOperandIndex = 0;
627 
628   switch (Form) {
629   case X86Local::RawFrm:
630     // Operand 1 (optional) is an address or immediate.
631     // Operand 2 (optional) is an immediate.
632     assert(numPhysicalOperands <= 2 &&
633            "Unexpected number of operands for RawFrm");
634     HANDLE_OPTIONAL(relocation)
635     HANDLE_OPTIONAL(immediate)
636     break;
637   case X86Local::AddRegFrm:
638     // Operand 1 is added to the opcode.
639     // Operand 2 (optional) is an address.
640     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
641            "Unexpected number of operands for AddRegFrm");
642     HANDLE_OPERAND(opcodeModifier)
643     HANDLE_OPTIONAL(relocation)
644     break;
645   case X86Local::MRMDestReg:
646     // Operand 1 is a register operand in the R/M field.
647     // Operand 2 is a register operand in the Reg/Opcode field.
648     // - In AVX, there is a register operand in the VEX.vvvv field here -
649     // Operand 3 (optional) is an immediate.
650     if (HasVEX_4VPrefix)
651       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
652              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
653     else
654       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
655              "Unexpected number of operands for MRMDestRegFrm");
656 
657     HANDLE_OPERAND(rmRegister)
658 
659     if (HasVEX_4VPrefix)
660       // FIXME: In AVX, the register below becomes the one encoded
661       // in ModRMVEX and the one above the one in the VEX.VVVV field
662       HANDLE_OPERAND(vvvvRegister)
663 
664     HANDLE_OPERAND(roRegister)
665     HANDLE_OPTIONAL(immediate)
666     break;
667   case X86Local::MRMDestMem:
668     // Operand 1 is a memory operand (possibly SIB-extended)
669     // Operand 2 is a register operand in the Reg/Opcode field.
670     // - In AVX, there is a register operand in the VEX.vvvv field here -
671     // Operand 3 (optional) is an immediate.
672     if (HasVEX_4VPrefix)
673       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
674              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
675     else
676       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
677              "Unexpected number of operands for MRMDestMemFrm");
678     HANDLE_OPERAND(memory)
679 
680     if (HasVEX_4VPrefix)
681       // FIXME: In AVX, the register below becomes the one encoded
682       // in ModRMVEX and the one above the one in the VEX.VVVV field
683       HANDLE_OPERAND(vvvvRegister)
684 
685     HANDLE_OPERAND(roRegister)
686     HANDLE_OPTIONAL(immediate)
687     break;
688   case X86Local::MRMSrcReg:
689     // Operand 1 is a register operand in the Reg/Opcode field.
690     // Operand 2 is a register operand in the R/M field.
691     // - In AVX, there is a register operand in the VEX.vvvv field here -
692     // Operand 3 (optional) is an immediate.
693     // Operand 4 (optional) is an immediate.
694 
695     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
696       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
697              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
698     else
699       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
700              "Unexpected number of operands for MRMSrcRegFrm");
701 
702     HANDLE_OPERAND(roRegister)
703 
704     if (HasVEX_4VPrefix)
705       // FIXME: In AVX, the register below becomes the one encoded
706       // in ModRMVEX and the one above the one in the VEX.VVVV field
707       HANDLE_OPERAND(vvvvRegister)
708 
709     if (HasMemOp4Prefix)
710       HANDLE_OPERAND(immediate)
711 
712     HANDLE_OPERAND(rmRegister)
713 
714     if (HasVEX_4VOp3Prefix)
715       HANDLE_OPERAND(vvvvRegister)
716 
717     if (!HasMemOp4Prefix)
718       HANDLE_OPTIONAL(immediate)
719     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
720     HANDLE_OPTIONAL(immediate)
721     break;
722   case X86Local::MRMSrcMem:
723     // Operand 1 is a register operand in the Reg/Opcode field.
724     // Operand 2 is a memory operand (possibly SIB-extended)
725     // - In AVX, there is a register operand in the VEX.vvvv field here -
726     // Operand 3 (optional) is an immediate.
727 
728     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
729       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
730              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
731     else
732       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
733              "Unexpected number of operands for MRMSrcMemFrm");
734 
735     HANDLE_OPERAND(roRegister)
736 
737     if (HasVEX_4VPrefix)
738       // FIXME: In AVX, the register below becomes the one encoded
739       // in ModRMVEX and the one above the one in the VEX.VVVV field
740       HANDLE_OPERAND(vvvvRegister)
741 
742     if (HasMemOp4Prefix)
743       HANDLE_OPERAND(immediate)
744 
745     HANDLE_OPERAND(memory)
746 
747     if (HasVEX_4VOp3Prefix)
748       HANDLE_OPERAND(vvvvRegister)
749 
750     if (!HasMemOp4Prefix)
751       HANDLE_OPTIONAL(immediate)
752     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
753     break;
754   case X86Local::MRM0r:
755   case X86Local::MRM1r:
756   case X86Local::MRM2r:
757   case X86Local::MRM3r:
758   case X86Local::MRM4r:
759   case X86Local::MRM5r:
760   case X86Local::MRM6r:
761   case X86Local::MRM7r:
762     // Operand 1 is a register operand in the R/M field.
763     // Operand 2 (optional) is an immediate or relocation.
764     // Operand 3 (optional) is an immediate.
765     if (HasVEX_4VPrefix)
766       assert(numPhysicalOperands <= 3 &&
767              "Unexpected number of operands for MRMnRFrm with VEX_4V");
768     else
769       assert(numPhysicalOperands <= 3 &&
770              "Unexpected number of operands for MRMnRFrm");
771     if (HasVEX_4VPrefix)
772       HANDLE_OPERAND(vvvvRegister)
773     HANDLE_OPTIONAL(rmRegister)
774     HANDLE_OPTIONAL(relocation)
775     HANDLE_OPTIONAL(immediate)
776     break;
777   case X86Local::MRM0m:
778   case X86Local::MRM1m:
779   case X86Local::MRM2m:
780   case X86Local::MRM3m:
781   case X86Local::MRM4m:
782   case X86Local::MRM5m:
783   case X86Local::MRM6m:
784   case X86Local::MRM7m:
785     // Operand 1 is a memory operand (possibly SIB-extended)
786     // Operand 2 (optional) is an immediate or relocation.
787     if (HasVEX_4VPrefix)
788       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
789              "Unexpected number of operands for MRMnMFrm");
790     else
791       assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
792              "Unexpected number of operands for MRMnMFrm");
793     if (HasVEX_4VPrefix)
794       HANDLE_OPERAND(vvvvRegister)
795     HANDLE_OPERAND(memory)
796     HANDLE_OPTIONAL(relocation)
797     break;
798   case X86Local::RawFrmImm8:
799     // operand 1 is a 16-bit immediate
800     // operand 2 is an 8-bit immediate
801     assert(numPhysicalOperands == 2 &&
802            "Unexpected number of operands for X86Local::RawFrmImm8");
803     HANDLE_OPERAND(immediate)
804     HANDLE_OPERAND(immediate)
805     break;
806   case X86Local::RawFrmImm16:
807     // operand 1 is a 16-bit immediate
808     // operand 2 is a 16-bit immediate
809     HANDLE_OPERAND(immediate)
810     HANDLE_OPERAND(immediate)
811     break;
812   case X86Local::MRMInitReg:
813     // Ignored.
814     break;
815   }
816 
817   #undef HANDLE_OPERAND
818   #undef HANDLE_OPTIONAL
819 }
820 
821 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
822   // Special cases where the LLVM tables are not complete
823 
824 #define MAP(from, to)                     \
825   case X86Local::MRM_##from:              \
826     filter = new ExactFilter(0x##from);   \
827     break;
828 
829   OpcodeType    opcodeType  = (OpcodeType)-1;
830 
831   ModRMFilter*  filter      = NULL;
832   uint8_t       opcodeToSet = 0;
833 
834   switch (Prefix) {
835   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
836   case X86Local::XD:
837   case X86Local::XS:
838   case X86Local::TB:
839     opcodeType = TWOBYTE;
840 
841     switch (Opcode) {
842     default:
843       if (needsModRMForDecode(Form))
844         filter = new ModFilter(isRegFormat(Form));
845       else
846         filter = new DumbFilter();
847       break;
848 #define EXTENSION_TABLE(n) case 0x##n:
849     TWO_BYTE_EXTENSION_TABLES
850 #undef EXTENSION_TABLE
851       switch (Form) {
852       default:
853         llvm_unreachable("Unhandled two-byte extended opcode");
854       case X86Local::MRM0r:
855       case X86Local::MRM1r:
856       case X86Local::MRM2r:
857       case X86Local::MRM3r:
858       case X86Local::MRM4r:
859       case X86Local::MRM5r:
860       case X86Local::MRM6r:
861       case X86Local::MRM7r:
862         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
863         break;
864       case X86Local::MRM0m:
865       case X86Local::MRM1m:
866       case X86Local::MRM2m:
867       case X86Local::MRM3m:
868       case X86Local::MRM4m:
869       case X86Local::MRM5m:
870       case X86Local::MRM6m:
871       case X86Local::MRM7m:
872         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
873         break;
874       MRM_MAPPING
875       } // switch (Form)
876       break;
877     } // switch (Opcode)
878     opcodeToSet = Opcode;
879     break;
880   case X86Local::T8:
881   case X86Local::T8XD:
882   case X86Local::T8XS:
883     opcodeType = THREEBYTE_38;
884     switch (Opcode) {
885     default:
886       if (needsModRMForDecode(Form))
887         filter = new ModFilter(isRegFormat(Form));
888       else
889         filter = new DumbFilter();
890       break;
891 #define EXTENSION_TABLE(n) case 0x##n:
892     THREE_BYTE_38_EXTENSION_TABLES
893 #undef EXTENSION_TABLE
894       switch (Form) {
895       default:
896         llvm_unreachable("Unhandled two-byte extended opcode");
897       case X86Local::MRM0r:
898       case X86Local::MRM1r:
899       case X86Local::MRM2r:
900       case X86Local::MRM3r:
901       case X86Local::MRM4r:
902       case X86Local::MRM5r:
903       case X86Local::MRM6r:
904       case X86Local::MRM7r:
905         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
906         break;
907       case X86Local::MRM0m:
908       case X86Local::MRM1m:
909       case X86Local::MRM2m:
910       case X86Local::MRM3m:
911       case X86Local::MRM4m:
912       case X86Local::MRM5m:
913       case X86Local::MRM6m:
914       case X86Local::MRM7m:
915         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
916         break;
917       MRM_MAPPING
918       } // switch (Form)
919       break;
920     } // switch (Opcode)
921     opcodeToSet = Opcode;
922     break;
923   case X86Local::P_TA:
924   case X86Local::TAXD:
925     opcodeType = THREEBYTE_3A;
926     if (needsModRMForDecode(Form))
927       filter = new ModFilter(isRegFormat(Form));
928     else
929       filter = new DumbFilter();
930     opcodeToSet = Opcode;
931     break;
932   case X86Local::A6:
933     opcodeType = THREEBYTE_A6;
934     if (needsModRMForDecode(Form))
935       filter = new ModFilter(isRegFormat(Form));
936     else
937       filter = new DumbFilter();
938     opcodeToSet = Opcode;
939     break;
940   case X86Local::A7:
941     opcodeType = THREEBYTE_A7;
942     if (needsModRMForDecode(Form))
943       filter = new ModFilter(isRegFormat(Form));
944     else
945       filter = new DumbFilter();
946     opcodeToSet = Opcode;
947     break;
948   case X86Local::D8:
949   case X86Local::D9:
950   case X86Local::DA:
951   case X86Local::DB:
952   case X86Local::DC:
953   case X86Local::DD:
954   case X86Local::DE:
955   case X86Local::DF:
956     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
957     opcodeType = ONEBYTE;
958     if (Form == X86Local::AddRegFrm) {
959       Spec->modifierType = MODIFIER_MODRM;
960       Spec->modifierBase = Opcode;
961       filter = new AddRegEscapeFilter(Opcode);
962     } else {
963       filter = new EscapeFilter(true, Opcode);
964     }
965     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
966     break;
967   case X86Local::REP:
968   default:
969     opcodeType = ONEBYTE;
970     switch (Opcode) {
971 #define EXTENSION_TABLE(n) case 0x##n:
972     ONE_BYTE_EXTENSION_TABLES
973 #undef EXTENSION_TABLE
974       switch (Form) {
975       default:
976         llvm_unreachable("Fell through the cracks of a single-byte "
977                          "extended opcode");
978       case X86Local::MRM0r:
979       case X86Local::MRM1r:
980       case X86Local::MRM2r:
981       case X86Local::MRM3r:
982       case X86Local::MRM4r:
983       case X86Local::MRM5r:
984       case X86Local::MRM6r:
985       case X86Local::MRM7r:
986         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
987         break;
988       case X86Local::MRM0m:
989       case X86Local::MRM1m:
990       case X86Local::MRM2m:
991       case X86Local::MRM3m:
992       case X86Local::MRM4m:
993       case X86Local::MRM5m:
994       case X86Local::MRM6m:
995       case X86Local::MRM7m:
996         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
997         break;
998       MRM_MAPPING
999       } // switch (Form)
1000       break;
1001     case 0xd8:
1002     case 0xd9:
1003     case 0xda:
1004     case 0xdb:
1005     case 0xdc:
1006     case 0xdd:
1007     case 0xde:
1008     case 0xdf:
1009       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1010       break;
1011     default:
1012       if (needsModRMForDecode(Form))
1013         filter = new ModFilter(isRegFormat(Form));
1014       else
1015         filter = new DumbFilter();
1016       break;
1017     } // switch (Opcode)
1018     opcodeToSet = Opcode;
1019   } // switch (Prefix)
1020 
1021   assert(opcodeType != (OpcodeType)-1 &&
1022          "Opcode type not set");
1023   assert(filter && "Filter not set");
1024 
1025   if (Form == X86Local::AddRegFrm) {
1026     if(Spec->modifierType != MODIFIER_MODRM) {
1027       assert(opcodeToSet < 0xf9 &&
1028              "Not enough room for all ADDREG_FRM operands");
1029 
1030       uint8_t currentOpcode;
1031 
1032       for (currentOpcode = opcodeToSet;
1033            currentOpcode < opcodeToSet + 8;
1034            ++currentOpcode)
1035         tables.setTableFields(opcodeType,
1036                               insnContext(),
1037                               currentOpcode,
1038                               *filter,
1039                               UID, Is32Bit, IgnoresVEX_L);
1040 
1041       Spec->modifierType = MODIFIER_OPCODE;
1042       Spec->modifierBase = opcodeToSet;
1043     } else {
1044       // modifierBase was set where MODIFIER_MODRM was set
1045       tables.setTableFields(opcodeType,
1046                             insnContext(),
1047                             opcodeToSet,
1048                             *filter,
1049                             UID, Is32Bit, IgnoresVEX_L);
1050     }
1051   } else {
1052     tables.setTableFields(opcodeType,
1053                           insnContext(),
1054                           opcodeToSet,
1055                           *filter,
1056                           UID, Is32Bit, IgnoresVEX_L);
1057 
1058     Spec->modifierType = MODIFIER_NONE;
1059     Spec->modifierBase = opcodeToSet;
1060   }
1061 
1062   delete filter;
1063 
1064 #undef MAP
1065 }
1066 
1067 #define TYPE(str, type) if (s == str) return type;
1068 OperandType RecognizableInstr::typeFromString(const std::string &s,
1069                                               bool isSSE,
1070                                               bool hasREX_WPrefix,
1071                                               bool hasOpSizePrefix) {
1072   if (isSSE) {
1073     // For SSE instructions, we ignore the OpSize prefix and force operand
1074     // sizes.
1075     TYPE("GR16",              TYPE_R16)
1076     TYPE("GR32",              TYPE_R32)
1077     TYPE("GR64",              TYPE_R64)
1078   }
1079   if(hasREX_WPrefix) {
1080     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1081     // is special.
1082     TYPE("GR32",              TYPE_R32)
1083   }
1084   if(!hasOpSizePrefix) {
1085     // For instructions without an OpSize prefix, a declared 16-bit register or
1086     // immediate encoding is special.
1087     TYPE("GR16",              TYPE_R16)
1088     TYPE("i16imm",            TYPE_IMM16)
1089   }
1090   TYPE("i16mem",              TYPE_Mv)
1091   TYPE("i16imm",              TYPE_IMMv)
1092   TYPE("i16i8imm",            TYPE_IMMv)
1093   TYPE("GR16",                TYPE_Rv)
1094   TYPE("i32mem",              TYPE_Mv)
1095   TYPE("i32imm",              TYPE_IMMv)
1096   TYPE("i32i8imm",            TYPE_IMM32)
1097   TYPE("u32u8imm",            TYPE_IMM32)
1098   TYPE("GR32",                TYPE_Rv)
1099   TYPE("i64mem",              TYPE_Mv)
1100   TYPE("i64i32imm",           TYPE_IMM64)
1101   TYPE("i64i8imm",            TYPE_IMM64)
1102   TYPE("GR64",                TYPE_R64)
1103   TYPE("i8mem",               TYPE_M8)
1104   TYPE("i8imm",               TYPE_IMM8)
1105   TYPE("GR8",                 TYPE_R8)
1106   TYPE("VR128",               TYPE_XMM128)
1107   TYPE("f128mem",             TYPE_M128)
1108   TYPE("f256mem",             TYPE_M256)
1109   TYPE("v128mem",             TYPE_M128)
1110   TYPE("v256mem",             TYPE_M256)
1111   TYPE("FR64",                TYPE_XMM64)
1112   TYPE("f64mem",              TYPE_M64FP)
1113   TYPE("sdmem",               TYPE_M64FP)
1114   TYPE("FR32",                TYPE_XMM32)
1115   TYPE("f32mem",              TYPE_M32FP)
1116   TYPE("ssmem",               TYPE_M32FP)
1117   TYPE("RST",                 TYPE_ST)
1118   TYPE("i128mem",             TYPE_M128)
1119   TYPE("i256mem",             TYPE_M256)
1120   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1121   TYPE("i16imm_pcrel",        TYPE_REL16)
1122   TYPE("i32imm_pcrel",        TYPE_REL32)
1123   TYPE("SSECC",               TYPE_IMM3)
1124   TYPE("AVXCC",               TYPE_IMM5)
1125   TYPE("brtarget",            TYPE_RELv)
1126   TYPE("uncondbrtarget",      TYPE_RELv)
1127   TYPE("brtarget8",           TYPE_REL8)
1128   TYPE("f80mem",              TYPE_M80FP)
1129   TYPE("lea32mem",            TYPE_LEA)
1130   TYPE("lea64_32mem",         TYPE_LEA)
1131   TYPE("lea64mem",            TYPE_LEA)
1132   TYPE("VR64",                TYPE_MM64)
1133   TYPE("i64imm",              TYPE_IMMv)
1134   TYPE("opaque32mem",         TYPE_M1616)
1135   TYPE("opaque48mem",         TYPE_M1632)
1136   TYPE("opaque80mem",         TYPE_M1664)
1137   TYPE("opaque512mem",        TYPE_M512)
1138   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1139   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1140   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1141   TYPE("offset8",             TYPE_MOFFS8)
1142   TYPE("offset16",            TYPE_MOFFS16)
1143   TYPE("offset32",            TYPE_MOFFS32)
1144   TYPE("offset64",            TYPE_MOFFS64)
1145   TYPE("VR256",               TYPE_XMM256)
1146   TYPE("GR16_NOAX",           TYPE_Rv)
1147   TYPE("GR32_NOAX",           TYPE_Rv)
1148   TYPE("GR64_NOAX",           TYPE_R64)
1149   errs() << "Unhandled type string " << s << "\n";
1150   llvm_unreachable("Unhandled type string");
1151 }
1152 #undef TYPE
1153 
1154 #define ENCODING(str, encoding) if (s == str) return encoding;
1155 OperandEncoding RecognizableInstr::immediateEncodingFromString
1156   (const std::string &s,
1157    bool hasOpSizePrefix) {
1158   if(!hasOpSizePrefix) {
1159     // For instructions without an OpSize prefix, a declared 16-bit register or
1160     // immediate encoding is special.
1161     ENCODING("i16imm",        ENCODING_IW)
1162   }
1163   ENCODING("i32i8imm",        ENCODING_IB)
1164   ENCODING("u32u8imm",        ENCODING_IB)
1165   ENCODING("SSECC",           ENCODING_IB)
1166   ENCODING("AVXCC",           ENCODING_IB)
1167   ENCODING("i16imm",          ENCODING_Iv)
1168   ENCODING("i16i8imm",        ENCODING_IB)
1169   ENCODING("i32imm",          ENCODING_Iv)
1170   ENCODING("i64i32imm",       ENCODING_ID)
1171   ENCODING("i64i8imm",        ENCODING_IB)
1172   ENCODING("i8imm",           ENCODING_IB)
1173   // This is not a typo.  Instructions like BLENDVPD put
1174   // register IDs in 8-bit immediates nowadays.
1175   ENCODING("VR256",           ENCODING_IB)
1176   ENCODING("VR128",           ENCODING_IB)
1177   errs() << "Unhandled immediate encoding " << s << "\n";
1178   llvm_unreachable("Unhandled immediate encoding");
1179 }
1180 
1181 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1182   (const std::string &s,
1183    bool hasOpSizePrefix) {
1184   ENCODING("GR16",            ENCODING_RM)
1185   ENCODING("GR32",            ENCODING_RM)
1186   ENCODING("GR64",            ENCODING_RM)
1187   ENCODING("GR8",             ENCODING_RM)
1188   ENCODING("VR128",           ENCODING_RM)
1189   ENCODING("FR64",            ENCODING_RM)
1190   ENCODING("FR32",            ENCODING_RM)
1191   ENCODING("VR64",            ENCODING_RM)
1192   ENCODING("VR256",           ENCODING_RM)
1193   errs() << "Unhandled R/M register encoding " << s << "\n";
1194   llvm_unreachable("Unhandled R/M register encoding");
1195 }
1196 
1197 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1198   (const std::string &s,
1199    bool hasOpSizePrefix) {
1200   ENCODING("GR16",            ENCODING_REG)
1201   ENCODING("GR32",            ENCODING_REG)
1202   ENCODING("GR64",            ENCODING_REG)
1203   ENCODING("GR8",             ENCODING_REG)
1204   ENCODING("VR128",           ENCODING_REG)
1205   ENCODING("FR64",            ENCODING_REG)
1206   ENCODING("FR32",            ENCODING_REG)
1207   ENCODING("VR64",            ENCODING_REG)
1208   ENCODING("SEGMENT_REG",     ENCODING_REG)
1209   ENCODING("DEBUG_REG",       ENCODING_REG)
1210   ENCODING("CONTROL_REG",     ENCODING_REG)
1211   ENCODING("VR256",           ENCODING_REG)
1212   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1213   llvm_unreachable("Unhandled reg/opcode register encoding");
1214 }
1215 
1216 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1217   (const std::string &s,
1218    bool hasOpSizePrefix) {
1219   ENCODING("GR32",            ENCODING_VVVV)
1220   ENCODING("GR64",            ENCODING_VVVV)
1221   ENCODING("FR32",            ENCODING_VVVV)
1222   ENCODING("FR64",            ENCODING_VVVV)
1223   ENCODING("VR128",           ENCODING_VVVV)
1224   ENCODING("VR256",           ENCODING_VVVV)
1225   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1226   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1227 }
1228 
1229 OperandEncoding RecognizableInstr::memoryEncodingFromString
1230   (const std::string &s,
1231    bool hasOpSizePrefix) {
1232   ENCODING("i16mem",          ENCODING_RM)
1233   ENCODING("i32mem",          ENCODING_RM)
1234   ENCODING("i64mem",          ENCODING_RM)
1235   ENCODING("i8mem",           ENCODING_RM)
1236   ENCODING("ssmem",           ENCODING_RM)
1237   ENCODING("sdmem",           ENCODING_RM)
1238   ENCODING("f128mem",         ENCODING_RM)
1239   ENCODING("f256mem",         ENCODING_RM)
1240   ENCODING("v128mem",         ENCODING_RM)
1241   ENCODING("v256mem",         ENCODING_RM)
1242   ENCODING("f64mem",          ENCODING_RM)
1243   ENCODING("f32mem",          ENCODING_RM)
1244   ENCODING("i128mem",         ENCODING_RM)
1245   ENCODING("i256mem",         ENCODING_RM)
1246   ENCODING("f80mem",          ENCODING_RM)
1247   ENCODING("lea32mem",        ENCODING_RM)
1248   ENCODING("lea64_32mem",     ENCODING_RM)
1249   ENCODING("lea64mem",        ENCODING_RM)
1250   ENCODING("opaque32mem",     ENCODING_RM)
1251   ENCODING("opaque48mem",     ENCODING_RM)
1252   ENCODING("opaque80mem",     ENCODING_RM)
1253   ENCODING("opaque512mem",    ENCODING_RM)
1254   errs() << "Unhandled memory encoding " << s << "\n";
1255   llvm_unreachable("Unhandled memory encoding");
1256 }
1257 
1258 OperandEncoding RecognizableInstr::relocationEncodingFromString
1259   (const std::string &s,
1260    bool hasOpSizePrefix) {
1261   if(!hasOpSizePrefix) {
1262     // For instructions without an OpSize prefix, a declared 16-bit register or
1263     // immediate encoding is special.
1264     ENCODING("i16imm",        ENCODING_IW)
1265   }
1266   ENCODING("i16imm",          ENCODING_Iv)
1267   ENCODING("i16i8imm",        ENCODING_IB)
1268   ENCODING("i32imm",          ENCODING_Iv)
1269   ENCODING("i32i8imm",        ENCODING_IB)
1270   ENCODING("i64i32imm",       ENCODING_ID)
1271   ENCODING("i64i8imm",        ENCODING_IB)
1272   ENCODING("i8imm",           ENCODING_IB)
1273   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1274   ENCODING("i16imm_pcrel",    ENCODING_IW)
1275   ENCODING("i32imm_pcrel",    ENCODING_ID)
1276   ENCODING("brtarget",        ENCODING_Iv)
1277   ENCODING("brtarget8",       ENCODING_IB)
1278   ENCODING("i64imm",          ENCODING_IO)
1279   ENCODING("offset8",         ENCODING_Ia)
1280   ENCODING("offset16",        ENCODING_Ia)
1281   ENCODING("offset32",        ENCODING_Ia)
1282   ENCODING("offset64",        ENCODING_Ia)
1283   errs() << "Unhandled relocation encoding " << s << "\n";
1284   llvm_unreachable("Unhandled relocation encoding");
1285 }
1286 
1287 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1288   (const std::string &s,
1289    bool hasOpSizePrefix) {
1290   ENCODING("RST",             ENCODING_I)
1291   ENCODING("GR32",            ENCODING_Rv)
1292   ENCODING("GR64",            ENCODING_RO)
1293   ENCODING("GR16",            ENCODING_Rv)
1294   ENCODING("GR8",             ENCODING_RB)
1295   ENCODING("GR16_NOAX",       ENCODING_Rv)
1296   ENCODING("GR32_NOAX",       ENCODING_Rv)
1297   ENCODING("GR64_NOAX",       ENCODING_RO)
1298   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1299   llvm_unreachable("Unhandled opcode modifier encoding");
1300 }
1301 #undef ENCODING
1302