1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) { 28 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 29 StringRef Mnemonic(AsmString); 30 // Extract a mnemonic assuming it's separated by \t 31 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 32 33 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 34 // Replace it with "CC" in-place. 35 size_t CondPos = Mnemonic.find("${cond}"); 36 if (CondPos != StringRef::npos) 37 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 38 return Mnemonic.upper(); 39 } 40 41 bool X86Disassembler::isRegisterOperand(const Record *Rec) { 42 return Rec->isSubClassOf("RegisterClass") || 43 Rec->isSubClassOf("RegisterOperand"); 44 } 45 46 bool X86Disassembler::isMemoryOperand(const Record *Rec) { 47 return Rec->isSubClassOf("Operand") && 48 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY"; 49 } 50 51 bool X86Disassembler::isImmediateOperand(const Record *Rec) { 52 return Rec->isSubClassOf("Operand") && 53 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE"; 54 } 55 56 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) { 57 if (RegRec->isSubClassOf("RegisterClass")) 58 return RegRec->getValueAsInt("Alignment"); 59 if (RegRec->isSubClassOf("RegisterOperand")) 60 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment"); 61 62 llvm_unreachable("Register operand's size not known!"); 63 } 64 65 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) { 66 if (MemRec->isSubClassOf("Operand")) { 67 StringRef Name = 68 MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name"); 69 if (Name == "Mem8") 70 return 8; 71 if (Name == "Mem16") 72 return 16; 73 if (Name == "Mem32") 74 return 32; 75 if (Name == "Mem64") 76 return 64; 77 if (Name == "Mem80") 78 return 80; 79 if (Name == "Mem128") 80 return 128; 81 if (Name == "Mem256") 82 return 256; 83 if (Name == "Mem512") 84 return 512; 85 } 86 87 llvm_unreachable("Memory operand's size not known!"); 88 } 89 90 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 91 /// Useful for switch statements and the like. 92 /// 93 /// @param init - A reference to the BitsInit to be decoded. 94 /// @return - The field, with the first bit in the BitsInit as the lowest 95 /// order bit. 96 static uint8_t byteFromBitsInit(BitsInit &init) { 97 int width = init.getNumBits(); 98 99 assert(width <= 8 && "Field is too large for uint8_t!"); 100 101 int index; 102 uint8_t mask = 0x01; 103 104 uint8_t ret = 0; 105 106 for (index = 0; index < width; index++) { 107 if (cast<BitInit>(init.getBit(index))->getValue()) 108 ret |= mask; 109 110 mask <<= 1; 111 } 112 113 return ret; 114 } 115 116 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 117 /// name of the field. 118 /// 119 /// @param rec - The record from which to extract the value. 120 /// @param name - The name of the field in the record. 121 /// @return - The field, as translated by byteFromBitsInit(). 122 static uint8_t byteFromRec(const Record* rec, StringRef name) { 123 BitsInit* bits = rec->getValueAsBitsInit(name); 124 return byteFromBitsInit(*bits); 125 } 126 127 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) { 128 const Record *Rec = insn.TheDef; 129 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction"); 130 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 131 OpMap = byteFromRec(Rec, "OpMapBits"); 132 Opcode = byteFromRec(Rec, "Opcode"); 133 Form = byteFromRec(Rec, "FormBits"); 134 Encoding = byteFromRec(Rec, "OpEncBits"); 135 OpSize = byteFromRec(Rec, "OpSizeBits"); 136 AdSize = byteFromRec(Rec, "AdSizeBits"); 137 HasREX_W = Rec->getValueAsBit("hasREX_W"); 138 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 139 HasVEX_W = Rec->getValueAsBit("HasVEX_W"); 140 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); 141 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 142 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); 143 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 144 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 145 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 146 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 147 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly"); 148 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 149 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 150 HasVEX_L = Rec->getValueAsBit("hasVEX_L"); 151 152 EncodeRC = HasEVEX_B && 153 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 154 } 155 156 bool RecognizableInstrBase::shouldBeEmitted() const { 157 return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) && 158 !IsAsmParserOnly; 159 } 160 161 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 162 const CodeGenInstruction &insn, 163 InstrUID uid) 164 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()), 165 Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList), 166 UID(uid), Spec(&tables.specForUID(uid)) { 167 // Check for 64-bit inst which does not require REX 168 // FIXME: Is there some better way to check for In64BitMode? 169 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates"); 170 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 171 if (Predicates[i]->getName().contains("Not64Bit") || 172 Predicates[i]->getName().contains("In32Bit")) { 173 Is32Bit = true; 174 break; 175 } 176 if (Predicates[i]->getName().contains("In64Bit")) { 177 Is64Bit = true; 178 break; 179 } 180 } 181 } 182 183 void RecognizableInstr::processInstr(DisassemblerTables &tables, 184 const CodeGenInstruction &insn, 185 InstrUID uid) { 186 if (!insn.TheDef->isSubClassOf("X86Inst")) 187 return; 188 RecognizableInstr recogInstr(tables, insn, uid); 189 190 if (!recogInstr.shouldBeEmitted()) 191 return; 192 recogInstr.emitInstructionSpecifier(); 193 recogInstr.emitDecodePath(tables); 194 } 195 196 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 197 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 198 (HasEVEX_KZ ? n##_KZ : \ 199 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 200 201 InstructionContext RecognizableInstr::insnContext() const { 202 InstructionContext insnContext; 203 204 if (Encoding == X86Local::EVEX) { 205 if (HasVEX_L && HasEVEX_L2) { 206 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 207 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 208 } 209 // VEX_L & VEX_W 210 if (!EncodeRC && HasVEX_L && HasVEX_W) { 211 if (OpPrefix == X86Local::PD) 212 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 213 else if (OpPrefix == X86Local::XS) 214 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 215 else if (OpPrefix == X86Local::XD) 216 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 217 else if (OpPrefix == X86Local::PS) 218 insnContext = EVEX_KB(IC_EVEX_L_W); 219 else { 220 errs() << "Instruction does not use a prefix: " << Name << "\n"; 221 llvm_unreachable("Invalid prefix"); 222 } 223 } else if (!EncodeRC && HasVEX_L) { 224 // VEX_L 225 if (OpPrefix == X86Local::PD) 226 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 227 else if (OpPrefix == X86Local::XS) 228 insnContext = EVEX_KB(IC_EVEX_L_XS); 229 else if (OpPrefix == X86Local::XD) 230 insnContext = EVEX_KB(IC_EVEX_L_XD); 231 else if (OpPrefix == X86Local::PS) 232 insnContext = EVEX_KB(IC_EVEX_L); 233 else { 234 errs() << "Instruction does not use a prefix: " << Name << "\n"; 235 llvm_unreachable("Invalid prefix"); 236 } 237 } else if (!EncodeRC && HasEVEX_L2 && HasVEX_W) { 238 // EVEX_L2 & VEX_W 239 if (OpPrefix == X86Local::PD) 240 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 241 else if (OpPrefix == X86Local::XS) 242 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 243 else if (OpPrefix == X86Local::XD) 244 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 245 else if (OpPrefix == X86Local::PS) 246 insnContext = EVEX_KB(IC_EVEX_L2_W); 247 else { 248 errs() << "Instruction does not use a prefix: " << Name << "\n"; 249 llvm_unreachable("Invalid prefix"); 250 } 251 } else if (!EncodeRC && HasEVEX_L2) { 252 // EVEX_L2 253 if (OpPrefix == X86Local::PD) 254 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 255 else if (OpPrefix == X86Local::XD) 256 insnContext = EVEX_KB(IC_EVEX_L2_XD); 257 else if (OpPrefix == X86Local::XS) 258 insnContext = EVEX_KB(IC_EVEX_L2_XS); 259 else if (OpPrefix == X86Local::PS) 260 insnContext = EVEX_KB(IC_EVEX_L2); 261 else { 262 errs() << "Instruction does not use a prefix: " << Name << "\n"; 263 llvm_unreachable("Invalid prefix"); 264 } 265 } 266 else if (HasVEX_W) { 267 // VEX_W 268 if (OpPrefix == X86Local::PD) 269 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 270 else if (OpPrefix == X86Local::XS) 271 insnContext = EVEX_KB(IC_EVEX_W_XS); 272 else if (OpPrefix == X86Local::XD) 273 insnContext = EVEX_KB(IC_EVEX_W_XD); 274 else if (OpPrefix == X86Local::PS) 275 insnContext = EVEX_KB(IC_EVEX_W); 276 else { 277 errs() << "Instruction does not use a prefix: " << Name << "\n"; 278 llvm_unreachable("Invalid prefix"); 279 } 280 } 281 // No L, no W 282 else if (OpPrefix == X86Local::PD) 283 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 284 else if (OpPrefix == X86Local::XD) 285 insnContext = EVEX_KB(IC_EVEX_XD); 286 else if (OpPrefix == X86Local::XS) 287 insnContext = EVEX_KB(IC_EVEX_XS); 288 else if (OpPrefix == X86Local::PS) 289 insnContext = EVEX_KB(IC_EVEX); 290 else { 291 errs() << "Instruction does not use a prefix: " << Name << "\n"; 292 llvm_unreachable("Invalid prefix"); 293 } 294 /// eof EVEX 295 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 296 if (HasVEX_L && HasVEX_W) { 297 if (OpPrefix == X86Local::PD) 298 insnContext = IC_VEX_L_W_OPSIZE; 299 else if (OpPrefix == X86Local::XS) 300 insnContext = IC_VEX_L_W_XS; 301 else if (OpPrefix == X86Local::XD) 302 insnContext = IC_VEX_L_W_XD; 303 else if (OpPrefix == X86Local::PS) 304 insnContext = IC_VEX_L_W; 305 else { 306 errs() << "Instruction does not use a prefix: " << Name << "\n"; 307 llvm_unreachable("Invalid prefix"); 308 } 309 } else if (OpPrefix == X86Local::PD && HasVEX_L) 310 insnContext = IC_VEX_L_OPSIZE; 311 else if (OpPrefix == X86Local::PD && HasVEX_W) 312 insnContext = IC_VEX_W_OPSIZE; 313 else if (OpPrefix == X86Local::PD) 314 insnContext = IC_VEX_OPSIZE; 315 else if (HasVEX_L && OpPrefix == X86Local::XS) 316 insnContext = IC_VEX_L_XS; 317 else if (HasVEX_L && OpPrefix == X86Local::XD) 318 insnContext = IC_VEX_L_XD; 319 else if (HasVEX_W && OpPrefix == X86Local::XS) 320 insnContext = IC_VEX_W_XS; 321 else if (HasVEX_W && OpPrefix == X86Local::XD) 322 insnContext = IC_VEX_W_XD; 323 else if (HasVEX_W && OpPrefix == X86Local::PS) 324 insnContext = IC_VEX_W; 325 else if (HasVEX_L && OpPrefix == X86Local::PS) 326 insnContext = IC_VEX_L; 327 else if (OpPrefix == X86Local::XD) 328 insnContext = IC_VEX_XD; 329 else if (OpPrefix == X86Local::XS) 330 insnContext = IC_VEX_XS; 331 else if (OpPrefix == X86Local::PS) 332 insnContext = IC_VEX; 333 else { 334 errs() << "Instruction does not use a prefix: " << Name << "\n"; 335 llvm_unreachable("Invalid prefix"); 336 } 337 } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) { 338 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 339 insnContext = IC_64BIT_REXW_OPSIZE; 340 else if (HasREX_W && AdSize == X86Local::AdSize32) 341 insnContext = IC_64BIT_REXW_ADSIZE; 342 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 343 insnContext = IC_64BIT_XD_OPSIZE; 344 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 345 insnContext = IC_64BIT_XS_OPSIZE; 346 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 347 insnContext = IC_64BIT_OPSIZE_ADSIZE; 348 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 349 insnContext = IC_64BIT_OPSIZE_ADSIZE; 350 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 351 insnContext = IC_64BIT_OPSIZE; 352 else if (AdSize == X86Local::AdSize32) 353 insnContext = IC_64BIT_ADSIZE; 354 else if (HasREX_W && OpPrefix == X86Local::XS) 355 insnContext = IC_64BIT_REXW_XS; 356 else if (HasREX_W && OpPrefix == X86Local::XD) 357 insnContext = IC_64BIT_REXW_XD; 358 else if (OpPrefix == X86Local::XD) 359 insnContext = IC_64BIT_XD; 360 else if (OpPrefix == X86Local::XS) 361 insnContext = IC_64BIT_XS; 362 else if (HasREX_W) 363 insnContext = IC_64BIT_REXW; 364 else 365 insnContext = IC_64BIT; 366 } else { 367 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 368 insnContext = IC_XD_OPSIZE; 369 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 370 insnContext = IC_XS_OPSIZE; 371 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 372 insnContext = IC_XD_ADSIZE; 373 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 374 insnContext = IC_XS_ADSIZE; 375 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 376 insnContext = IC_OPSIZE_ADSIZE; 377 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 378 insnContext = IC_OPSIZE_ADSIZE; 379 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 380 insnContext = IC_OPSIZE; 381 else if (AdSize == X86Local::AdSize16) 382 insnContext = IC_ADSIZE; 383 else if (OpPrefix == X86Local::XD) 384 insnContext = IC_XD; 385 else if (OpPrefix == X86Local::XS) 386 insnContext = IC_XS; 387 else 388 insnContext = IC; 389 } 390 391 return insnContext; 392 } 393 394 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 395 // The scaling factor for AVX512 compressed displacement encoding is an 396 // instruction attribute. Adjust the ModRM encoding type to include the 397 // scale for compressed displacement. 398 if ((encoding != ENCODING_RM && 399 encoding != ENCODING_VSIB && 400 encoding != ENCODING_SIB) ||CD8_Scale == 0) 401 return; 402 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 403 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 404 (encoding == ENCODING_SIB) || 405 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 406 "Invalid CDisp scaling"); 407 } 408 409 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 410 unsigned &physicalOperandIndex, 411 unsigned numPhysicalOperands, 412 const unsigned *operandMapping, 413 OperandEncoding (*encodingFromString) 414 (const std::string&, 415 uint8_t OpSize)) { 416 if (optional) { 417 if (physicalOperandIndex >= numPhysicalOperands) 418 return; 419 } else { 420 assert(physicalOperandIndex < numPhysicalOperands); 421 } 422 423 while (operandMapping[operandIndex] != operandIndex) { 424 Spec->operands[operandIndex].encoding = ENCODING_DUP; 425 Spec->operands[operandIndex].type = 426 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 427 ++operandIndex; 428 } 429 430 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 431 432 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 433 // Adjust the encoding type for an operand based on the instruction. 434 adjustOperandEncoding(encoding); 435 Spec->operands[operandIndex].encoding = encoding; 436 Spec->operands[operandIndex].type = 437 typeFromString(std::string(typeName), HasREX_W, OpSize); 438 439 ++operandIndex; 440 ++physicalOperandIndex; 441 } 442 443 void RecognizableInstr::emitInstructionSpecifier() { 444 Spec->name = Name; 445 446 Spec->insnContext = insnContext(); 447 448 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 449 450 unsigned numOperands = OperandList.size(); 451 unsigned numPhysicalOperands = 0; 452 453 // operandMapping maps from operands in OperandList to their originals. 454 // If operandMapping[i] != i, then the entry is a duplicate. 455 unsigned operandMapping[X86_MAX_OPERANDS]; 456 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 457 458 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 459 if (!OperandList[operandIndex].Constraints.empty()) { 460 const CGIOperandList::ConstraintInfo &Constraint = 461 OperandList[operandIndex].Constraints[0]; 462 if (Constraint.isTied()) { 463 operandMapping[operandIndex] = operandIndex; 464 operandMapping[Constraint.getTiedOperand()] = operandIndex; 465 } else { 466 ++numPhysicalOperands; 467 operandMapping[operandIndex] = operandIndex; 468 } 469 } else { 470 ++numPhysicalOperands; 471 operandMapping[operandIndex] = operandIndex; 472 } 473 } 474 475 #define HANDLE_OPERAND(class) \ 476 handleOperand(false, \ 477 operandIndex, \ 478 physicalOperandIndex, \ 479 numPhysicalOperands, \ 480 operandMapping, \ 481 class##EncodingFromString); 482 483 #define HANDLE_OPTIONAL(class) \ 484 handleOperand(true, \ 485 operandIndex, \ 486 physicalOperandIndex, \ 487 numPhysicalOperands, \ 488 operandMapping, \ 489 class##EncodingFromString); 490 491 // operandIndex should always be < numOperands 492 unsigned operandIndex = 0; 493 // physicalOperandIndex should always be < numPhysicalOperands 494 unsigned physicalOperandIndex = 0; 495 496 #ifndef NDEBUG 497 // Given the set of prefix bits, how many additional operands does the 498 // instruction have? 499 unsigned additionalOperands = 0; 500 if (HasVEX_4V) 501 ++additionalOperands; 502 if (HasEVEX_K) 503 ++additionalOperands; 504 #endif 505 506 switch (Form) { 507 default: llvm_unreachable("Unhandled form"); 508 case X86Local::PrefixByte: 509 return; 510 case X86Local::RawFrmSrc: 511 HANDLE_OPERAND(relocation); 512 return; 513 case X86Local::RawFrmDst: 514 HANDLE_OPERAND(relocation); 515 return; 516 case X86Local::RawFrmDstSrc: 517 HANDLE_OPERAND(relocation); 518 HANDLE_OPERAND(relocation); 519 return; 520 case X86Local::RawFrm: 521 // Operand 1 (optional) is an address or immediate. 522 assert(numPhysicalOperands <= 1 && 523 "Unexpected number of operands for RawFrm"); 524 HANDLE_OPTIONAL(relocation) 525 break; 526 case X86Local::RawFrmMemOffs: 527 // Operand 1 is an address. 528 HANDLE_OPERAND(relocation); 529 break; 530 case X86Local::AddRegFrm: 531 // Operand 1 is added to the opcode. 532 // Operand 2 (optional) is an address. 533 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 534 "Unexpected number of operands for AddRegFrm"); 535 HANDLE_OPERAND(opcodeModifier) 536 HANDLE_OPTIONAL(relocation) 537 break; 538 case X86Local::AddCCFrm: 539 // Operand 1 (optional) is an address or immediate. 540 assert(numPhysicalOperands == 2 && 541 "Unexpected number of operands for AddCCFrm"); 542 HANDLE_OPERAND(relocation) 543 HANDLE_OPERAND(opcodeModifier) 544 break; 545 case X86Local::MRMDestReg: 546 // Operand 1 is a register operand in the R/M field. 547 // - In AVX512 there may be a mask operand here - 548 // Operand 2 is a register operand in the Reg/Opcode field. 549 // - In AVX, there is a register operand in the VEX.vvvv field here - 550 // Operand 3 (optional) is an immediate. 551 assert(numPhysicalOperands >= 2 + additionalOperands && 552 numPhysicalOperands <= 3 + additionalOperands && 553 "Unexpected number of operands for MRMDestRegFrm"); 554 555 HANDLE_OPERAND(rmRegister) 556 if (HasEVEX_K) 557 HANDLE_OPERAND(writemaskRegister) 558 559 if (HasVEX_4V) 560 // FIXME: In AVX, the register below becomes the one encoded 561 // in ModRMVEX and the one above the one in the VEX.VVVV field 562 HANDLE_OPERAND(vvvvRegister) 563 564 HANDLE_OPERAND(roRegister) 565 HANDLE_OPTIONAL(immediate) 566 break; 567 case X86Local::MRMDestMem: 568 case X86Local::MRMDestMemFSIB: 569 // Operand 1 is a memory operand (possibly SIB-extended) 570 // Operand 2 is a register operand in the Reg/Opcode field. 571 // - In AVX, there is a register operand in the VEX.vvvv field here - 572 // Operand 3 (optional) is an immediate. 573 assert(numPhysicalOperands >= 2 + additionalOperands && 574 numPhysicalOperands <= 3 + additionalOperands && 575 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 576 577 HANDLE_OPERAND(memory) 578 579 if (HasEVEX_K) 580 HANDLE_OPERAND(writemaskRegister) 581 582 if (HasVEX_4V) 583 // FIXME: In AVX, the register below becomes the one encoded 584 // in ModRMVEX and the one above the one in the VEX.VVVV field 585 HANDLE_OPERAND(vvvvRegister) 586 587 HANDLE_OPERAND(roRegister) 588 HANDLE_OPTIONAL(immediate) 589 break; 590 case X86Local::MRMSrcReg: 591 // Operand 1 is a register operand in the Reg/Opcode field. 592 // Operand 2 is a register operand in the R/M field. 593 // - In AVX, there is a register operand in the VEX.vvvv field here - 594 // Operand 3 (optional) is an immediate. 595 // Operand 4 (optional) is an immediate. 596 597 assert(numPhysicalOperands >= 2 + additionalOperands && 598 numPhysicalOperands <= 4 + additionalOperands && 599 "Unexpected number of operands for MRMSrcRegFrm"); 600 601 HANDLE_OPERAND(roRegister) 602 603 if (HasEVEX_K) 604 HANDLE_OPERAND(writemaskRegister) 605 606 if (HasVEX_4V) 607 // FIXME: In AVX, the register below becomes the one encoded 608 // in ModRMVEX and the one above the one in the VEX.VVVV field 609 HANDLE_OPERAND(vvvvRegister) 610 611 HANDLE_OPERAND(rmRegister) 612 HANDLE_OPTIONAL(immediate) 613 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 614 break; 615 case X86Local::MRMSrcReg4VOp3: 616 assert(numPhysicalOperands == 3 && 617 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 618 HANDLE_OPERAND(roRegister) 619 HANDLE_OPERAND(rmRegister) 620 HANDLE_OPERAND(vvvvRegister) 621 break; 622 case X86Local::MRMSrcRegOp4: 623 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 624 "Unexpected number of operands for MRMSrcRegOp4Frm"); 625 HANDLE_OPERAND(roRegister) 626 HANDLE_OPERAND(vvvvRegister) 627 HANDLE_OPERAND(immediate) // Register in imm[7:4] 628 HANDLE_OPERAND(rmRegister) 629 HANDLE_OPTIONAL(immediate) 630 break; 631 case X86Local::MRMSrcRegCC: 632 assert(numPhysicalOperands == 3 && 633 "Unexpected number of operands for MRMSrcRegCC"); 634 HANDLE_OPERAND(roRegister) 635 HANDLE_OPERAND(rmRegister) 636 HANDLE_OPERAND(opcodeModifier) 637 break; 638 case X86Local::MRMSrcMem: 639 case X86Local::MRMSrcMemFSIB: 640 // Operand 1 is a register operand in the Reg/Opcode field. 641 // Operand 2 is a memory operand (possibly SIB-extended) 642 // - In AVX, there is a register operand in the VEX.vvvv field here - 643 // Operand 3 (optional) is an immediate. 644 645 assert(numPhysicalOperands >= 2 + additionalOperands && 646 numPhysicalOperands <= 4 + additionalOperands && 647 "Unexpected number of operands for MRMSrcMemFrm"); 648 649 HANDLE_OPERAND(roRegister) 650 651 if (HasEVEX_K) 652 HANDLE_OPERAND(writemaskRegister) 653 654 if (HasVEX_4V) 655 // FIXME: In AVX, the register below becomes the one encoded 656 // in ModRMVEX and the one above the one in the VEX.VVVV field 657 HANDLE_OPERAND(vvvvRegister) 658 659 HANDLE_OPERAND(memory) 660 HANDLE_OPTIONAL(immediate) 661 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 662 break; 663 case X86Local::MRMSrcMem4VOp3: 664 assert(numPhysicalOperands == 3 && 665 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 666 HANDLE_OPERAND(roRegister) 667 HANDLE_OPERAND(memory) 668 HANDLE_OPERAND(vvvvRegister) 669 break; 670 case X86Local::MRMSrcMemOp4: 671 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 672 "Unexpected number of operands for MRMSrcMemOp4Frm"); 673 HANDLE_OPERAND(roRegister) 674 HANDLE_OPERAND(vvvvRegister) 675 HANDLE_OPERAND(immediate) // Register in imm[7:4] 676 HANDLE_OPERAND(memory) 677 HANDLE_OPTIONAL(immediate) 678 break; 679 case X86Local::MRMSrcMemCC: 680 assert(numPhysicalOperands == 3 && 681 "Unexpected number of operands for MRMSrcMemCC"); 682 HANDLE_OPERAND(roRegister) 683 HANDLE_OPERAND(memory) 684 HANDLE_OPERAND(opcodeModifier) 685 break; 686 case X86Local::MRMXrCC: 687 assert(numPhysicalOperands == 2 && 688 "Unexpected number of operands for MRMXrCC"); 689 HANDLE_OPERAND(rmRegister) 690 HANDLE_OPERAND(opcodeModifier) 691 break; 692 case X86Local::MRMr0: 693 // Operand 1 is a register operand in the R/M field. 694 HANDLE_OPERAND(roRegister) 695 break; 696 case X86Local::MRMXr: 697 case X86Local::MRM0r: 698 case X86Local::MRM1r: 699 case X86Local::MRM2r: 700 case X86Local::MRM3r: 701 case X86Local::MRM4r: 702 case X86Local::MRM5r: 703 case X86Local::MRM6r: 704 case X86Local::MRM7r: 705 // Operand 1 is a register operand in the R/M field. 706 // Operand 2 (optional) is an immediate or relocation. 707 // Operand 3 (optional) is an immediate. 708 assert(numPhysicalOperands >= 0 + additionalOperands && 709 numPhysicalOperands <= 3 + additionalOperands && 710 "Unexpected number of operands for MRMnr"); 711 712 if (HasVEX_4V) 713 HANDLE_OPERAND(vvvvRegister) 714 715 if (HasEVEX_K) 716 HANDLE_OPERAND(writemaskRegister) 717 HANDLE_OPTIONAL(rmRegister) 718 HANDLE_OPTIONAL(relocation) 719 HANDLE_OPTIONAL(immediate) 720 break; 721 case X86Local::MRMXmCC: 722 assert(numPhysicalOperands == 2 && 723 "Unexpected number of operands for MRMXm"); 724 HANDLE_OPERAND(memory) 725 HANDLE_OPERAND(opcodeModifier) 726 break; 727 case X86Local::MRMXm: 728 case X86Local::MRM0m: 729 case X86Local::MRM1m: 730 case X86Local::MRM2m: 731 case X86Local::MRM3m: 732 case X86Local::MRM4m: 733 case X86Local::MRM5m: 734 case X86Local::MRM6m: 735 case X86Local::MRM7m: 736 // Operand 1 is a memory operand (possibly SIB-extended) 737 // Operand 2 (optional) is an immediate or relocation. 738 assert(numPhysicalOperands >= 1 + additionalOperands && 739 numPhysicalOperands <= 2 + additionalOperands && 740 "Unexpected number of operands for MRMnm"); 741 742 if (HasVEX_4V) 743 HANDLE_OPERAND(vvvvRegister) 744 if (HasEVEX_K) 745 HANDLE_OPERAND(writemaskRegister) 746 HANDLE_OPERAND(memory) 747 HANDLE_OPTIONAL(relocation) 748 break; 749 case X86Local::RawFrmImm8: 750 // operand 1 is a 16-bit immediate 751 // operand 2 is an 8-bit immediate 752 assert(numPhysicalOperands == 2 && 753 "Unexpected number of operands for X86Local::RawFrmImm8"); 754 HANDLE_OPERAND(immediate) 755 HANDLE_OPERAND(immediate) 756 break; 757 case X86Local::RawFrmImm16: 758 // operand 1 is a 16-bit immediate 759 // operand 2 is a 16-bit immediate 760 HANDLE_OPERAND(immediate) 761 HANDLE_OPERAND(immediate) 762 break; 763 case X86Local::MRM0X: 764 case X86Local::MRM1X: 765 case X86Local::MRM2X: 766 case X86Local::MRM3X: 767 case X86Local::MRM4X: 768 case X86Local::MRM5X: 769 case X86Local::MRM6X: 770 case X86Local::MRM7X: 771 #define MAP(from, to) case X86Local::MRM_##from: 772 X86_INSTR_MRM_MAPPING 773 #undef MAP 774 HANDLE_OPTIONAL(relocation) 775 break; 776 } 777 778 #undef HANDLE_OPERAND 779 #undef HANDLE_OPTIONAL 780 } 781 782 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 783 // Special cases where the LLVM tables are not complete 784 785 #define MAP(from, to) \ 786 case X86Local::MRM_##from: 787 788 llvm::Optional<OpcodeType> opcodeType; 789 switch (OpMap) { 790 default: llvm_unreachable("Invalid map!"); 791 case X86Local::OB: opcodeType = ONEBYTE; break; 792 case X86Local::TB: opcodeType = TWOBYTE; break; 793 case X86Local::T8: opcodeType = THREEBYTE_38; break; 794 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 795 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 796 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 797 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 798 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 799 case X86Local::T_MAP5: opcodeType = MAP5; break; 800 case X86Local::T_MAP6: opcodeType = MAP6; break; 801 } 802 803 std::unique_ptr<ModRMFilter> filter; 804 switch (Form) { 805 default: llvm_unreachable("Invalid form!"); 806 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 807 case X86Local::RawFrm: 808 case X86Local::AddRegFrm: 809 case X86Local::RawFrmMemOffs: 810 case X86Local::RawFrmSrc: 811 case X86Local::RawFrmDst: 812 case X86Local::RawFrmDstSrc: 813 case X86Local::RawFrmImm8: 814 case X86Local::RawFrmImm16: 815 case X86Local::AddCCFrm: 816 case X86Local::PrefixByte: 817 filter = std::make_unique<DumbFilter>(); 818 break; 819 case X86Local::MRMDestReg: 820 case X86Local::MRMSrcReg: 821 case X86Local::MRMSrcReg4VOp3: 822 case X86Local::MRMSrcRegOp4: 823 case X86Local::MRMSrcRegCC: 824 case X86Local::MRMXrCC: 825 case X86Local::MRMXr: 826 filter = std::make_unique<ModFilter>(true); 827 break; 828 case X86Local::MRMDestMem: 829 case X86Local::MRMDestMemFSIB: 830 case X86Local::MRMSrcMem: 831 case X86Local::MRMSrcMemFSIB: 832 case X86Local::MRMSrcMem4VOp3: 833 case X86Local::MRMSrcMemOp4: 834 case X86Local::MRMSrcMemCC: 835 case X86Local::MRMXmCC: 836 case X86Local::MRMXm: 837 filter = std::make_unique<ModFilter>(false); 838 break; 839 case X86Local::MRM0r: case X86Local::MRM1r: 840 case X86Local::MRM2r: case X86Local::MRM3r: 841 case X86Local::MRM4r: case X86Local::MRM5r: 842 case X86Local::MRM6r: case X86Local::MRM7r: 843 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 844 break; 845 case X86Local::MRM0X: case X86Local::MRM1X: 846 case X86Local::MRM2X: case X86Local::MRM3X: 847 case X86Local::MRM4X: case X86Local::MRM5X: 848 case X86Local::MRM6X: case X86Local::MRM7X: 849 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 850 break; 851 case X86Local::MRMr0: 852 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 853 break; 854 case X86Local::MRM0m: case X86Local::MRM1m: 855 case X86Local::MRM2m: case X86Local::MRM3m: 856 case X86Local::MRM4m: case X86Local::MRM5m: 857 case X86Local::MRM6m: case X86Local::MRM7m: 858 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 859 break; 860 X86_INSTR_MRM_MAPPING 861 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 862 break; 863 } // switch (Form) 864 865 uint8_t opcodeToSet = Opcode; 866 867 unsigned AddressSize = 0; 868 switch (AdSize) { 869 case X86Local::AdSize16: AddressSize = 16; break; 870 case X86Local::AdSize32: AddressSize = 32; break; 871 case X86Local::AdSize64: AddressSize = 64; break; 872 } 873 874 assert(opcodeType && "Opcode type not set"); 875 assert(filter && "Filter not set"); 876 877 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 878 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 879 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { 880 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 881 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 882 883 uint8_t currentOpcode; 884 885 for (currentOpcode = opcodeToSet; 886 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 887 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 888 UID, Is32Bit, OpPrefix == 0, 889 IgnoresVEX_L || EncodeRC, 890 IgnoresVEX_W, AddressSize); 891 } else { 892 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 893 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 894 IgnoresVEX_W, AddressSize); 895 } 896 897 #undef MAP 898 } 899 900 #define TYPE(str, type) if (s == str) return type; 901 OperandType RecognizableInstr::typeFromString(const std::string &s, 902 bool hasREX_W, 903 uint8_t OpSize) { 904 if(hasREX_W) { 905 // For instructions with a REX_W prefix, a declared 32-bit register encoding 906 // is special. 907 TYPE("GR32", TYPE_R32) 908 } 909 if(OpSize == X86Local::OpSize16) { 910 // For OpSize16 instructions, a declared 16-bit register or 911 // immediate encoding is special. 912 TYPE("GR16", TYPE_Rv) 913 } else if(OpSize == X86Local::OpSize32) { 914 // For OpSize32 instructions, a declared 32-bit register or 915 // immediate encoding is special. 916 TYPE("GR32", TYPE_Rv) 917 } 918 TYPE("i16mem", TYPE_M) 919 TYPE("i16imm", TYPE_IMM) 920 TYPE("i16i8imm", TYPE_IMM) 921 TYPE("GR16", TYPE_R16) 922 TYPE("GR16orGR32orGR64", TYPE_R16) 923 TYPE("i32mem", TYPE_M) 924 TYPE("i32imm", TYPE_IMM) 925 TYPE("i32i8imm", TYPE_IMM) 926 TYPE("GR32", TYPE_R32) 927 TYPE("GR32orGR64", TYPE_R32) 928 TYPE("i64mem", TYPE_M) 929 TYPE("i64i32imm", TYPE_IMM) 930 TYPE("i64i8imm", TYPE_IMM) 931 TYPE("GR64", TYPE_R64) 932 TYPE("i8mem", TYPE_M) 933 TYPE("i8imm", TYPE_IMM) 934 TYPE("u4imm", TYPE_UIMM8) 935 TYPE("u8imm", TYPE_UIMM8) 936 TYPE("i16u8imm", TYPE_UIMM8) 937 TYPE("i32u8imm", TYPE_UIMM8) 938 TYPE("i64u8imm", TYPE_UIMM8) 939 TYPE("GR8", TYPE_R8) 940 TYPE("VR128", TYPE_XMM) 941 TYPE("VR128X", TYPE_XMM) 942 TYPE("f128mem", TYPE_M) 943 TYPE("f256mem", TYPE_M) 944 TYPE("f512mem", TYPE_M) 945 TYPE("FR128", TYPE_XMM) 946 TYPE("FR64", TYPE_XMM) 947 TYPE("FR64X", TYPE_XMM) 948 TYPE("f64mem", TYPE_M) 949 TYPE("sdmem", TYPE_M) 950 TYPE("FR16X", TYPE_XMM) 951 TYPE("FR32", TYPE_XMM) 952 TYPE("FR32X", TYPE_XMM) 953 TYPE("f32mem", TYPE_M) 954 TYPE("f16mem", TYPE_M) 955 TYPE("ssmem", TYPE_M) 956 TYPE("shmem", TYPE_M) 957 TYPE("RST", TYPE_ST) 958 TYPE("RSTi", TYPE_ST) 959 TYPE("i128mem", TYPE_M) 960 TYPE("i256mem", TYPE_M) 961 TYPE("i512mem", TYPE_M) 962 TYPE("i64i32imm_brtarget", TYPE_REL) 963 TYPE("i16imm_brtarget", TYPE_REL) 964 TYPE("i32imm_brtarget", TYPE_REL) 965 TYPE("ccode", TYPE_IMM) 966 TYPE("AVX512RC", TYPE_IMM) 967 TYPE("brtarget32", TYPE_REL) 968 TYPE("brtarget16", TYPE_REL) 969 TYPE("brtarget8", TYPE_REL) 970 TYPE("f80mem", TYPE_M) 971 TYPE("lea64_32mem", TYPE_M) 972 TYPE("lea64mem", TYPE_M) 973 TYPE("VR64", TYPE_MM64) 974 TYPE("i64imm", TYPE_IMM) 975 TYPE("anymem", TYPE_M) 976 TYPE("opaquemem", TYPE_M) 977 TYPE("sibmem", TYPE_MSIB) 978 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 979 TYPE("DEBUG_REG", TYPE_DEBUGREG) 980 TYPE("CONTROL_REG", TYPE_CONTROLREG) 981 TYPE("srcidx8", TYPE_SRCIDX) 982 TYPE("srcidx16", TYPE_SRCIDX) 983 TYPE("srcidx32", TYPE_SRCIDX) 984 TYPE("srcidx64", TYPE_SRCIDX) 985 TYPE("dstidx8", TYPE_DSTIDX) 986 TYPE("dstidx16", TYPE_DSTIDX) 987 TYPE("dstidx32", TYPE_DSTIDX) 988 TYPE("dstidx64", TYPE_DSTIDX) 989 TYPE("offset16_8", TYPE_MOFFS) 990 TYPE("offset16_16", TYPE_MOFFS) 991 TYPE("offset16_32", TYPE_MOFFS) 992 TYPE("offset32_8", TYPE_MOFFS) 993 TYPE("offset32_16", TYPE_MOFFS) 994 TYPE("offset32_32", TYPE_MOFFS) 995 TYPE("offset32_64", TYPE_MOFFS) 996 TYPE("offset64_8", TYPE_MOFFS) 997 TYPE("offset64_16", TYPE_MOFFS) 998 TYPE("offset64_32", TYPE_MOFFS) 999 TYPE("offset64_64", TYPE_MOFFS) 1000 TYPE("VR256", TYPE_YMM) 1001 TYPE("VR256X", TYPE_YMM) 1002 TYPE("VR512", TYPE_ZMM) 1003 TYPE("VK1", TYPE_VK) 1004 TYPE("VK1WM", TYPE_VK) 1005 TYPE("VK2", TYPE_VK) 1006 TYPE("VK2WM", TYPE_VK) 1007 TYPE("VK4", TYPE_VK) 1008 TYPE("VK4WM", TYPE_VK) 1009 TYPE("VK8", TYPE_VK) 1010 TYPE("VK8WM", TYPE_VK) 1011 TYPE("VK16", TYPE_VK) 1012 TYPE("VK16WM", TYPE_VK) 1013 TYPE("VK32", TYPE_VK) 1014 TYPE("VK32WM", TYPE_VK) 1015 TYPE("VK64", TYPE_VK) 1016 TYPE("VK64WM", TYPE_VK) 1017 TYPE("VK1Pair", TYPE_VK_PAIR) 1018 TYPE("VK2Pair", TYPE_VK_PAIR) 1019 TYPE("VK4Pair", TYPE_VK_PAIR) 1020 TYPE("VK8Pair", TYPE_VK_PAIR) 1021 TYPE("VK16Pair", TYPE_VK_PAIR) 1022 TYPE("vx64mem", TYPE_MVSIBX) 1023 TYPE("vx128mem", TYPE_MVSIBX) 1024 TYPE("vx256mem", TYPE_MVSIBX) 1025 TYPE("vy128mem", TYPE_MVSIBY) 1026 TYPE("vy256mem", TYPE_MVSIBY) 1027 TYPE("vx64xmem", TYPE_MVSIBX) 1028 TYPE("vx128xmem", TYPE_MVSIBX) 1029 TYPE("vx256xmem", TYPE_MVSIBX) 1030 TYPE("vy128xmem", TYPE_MVSIBY) 1031 TYPE("vy256xmem", TYPE_MVSIBY) 1032 TYPE("vy512xmem", TYPE_MVSIBY) 1033 TYPE("vz256mem", TYPE_MVSIBZ) 1034 TYPE("vz512mem", TYPE_MVSIBZ) 1035 TYPE("BNDR", TYPE_BNDR) 1036 TYPE("TILE", TYPE_TMM) 1037 errs() << "Unhandled type string " << s << "\n"; 1038 llvm_unreachable("Unhandled type string"); 1039 } 1040 #undef TYPE 1041 1042 #define ENCODING(str, encoding) if (s == str) return encoding; 1043 OperandEncoding 1044 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1045 uint8_t OpSize) { 1046 if(OpSize != X86Local::OpSize16) { 1047 // For instructions without an OpSize prefix, a declared 16-bit register or 1048 // immediate encoding is special. 1049 ENCODING("i16imm", ENCODING_IW) 1050 } 1051 ENCODING("i32i8imm", ENCODING_IB) 1052 ENCODING("AVX512RC", ENCODING_IRC) 1053 ENCODING("i16imm", ENCODING_Iv) 1054 ENCODING("i16i8imm", ENCODING_IB) 1055 ENCODING("i32imm", ENCODING_Iv) 1056 ENCODING("i64i32imm", ENCODING_ID) 1057 ENCODING("i64i8imm", ENCODING_IB) 1058 ENCODING("i8imm", ENCODING_IB) 1059 ENCODING("u4imm", ENCODING_IB) 1060 ENCODING("u8imm", ENCODING_IB) 1061 ENCODING("i16u8imm", ENCODING_IB) 1062 ENCODING("i32u8imm", ENCODING_IB) 1063 ENCODING("i64u8imm", ENCODING_IB) 1064 // This is not a typo. Instructions like BLENDVPD put 1065 // register IDs in 8-bit immediates nowadays. 1066 ENCODING("FR32", ENCODING_IB) 1067 ENCODING("FR64", ENCODING_IB) 1068 ENCODING("FR128", ENCODING_IB) 1069 ENCODING("VR128", ENCODING_IB) 1070 ENCODING("VR256", ENCODING_IB) 1071 ENCODING("FR16X", ENCODING_IB) 1072 ENCODING("FR32X", ENCODING_IB) 1073 ENCODING("FR64X", ENCODING_IB) 1074 ENCODING("VR128X", ENCODING_IB) 1075 ENCODING("VR256X", ENCODING_IB) 1076 ENCODING("VR512", ENCODING_IB) 1077 ENCODING("TILE", ENCODING_IB) 1078 errs() << "Unhandled immediate encoding " << s << "\n"; 1079 llvm_unreachable("Unhandled immediate encoding"); 1080 } 1081 1082 OperandEncoding 1083 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1084 uint8_t OpSize) { 1085 ENCODING("RST", ENCODING_FP) 1086 ENCODING("RSTi", ENCODING_FP) 1087 ENCODING("GR16", ENCODING_RM) 1088 ENCODING("GR16orGR32orGR64",ENCODING_RM) 1089 ENCODING("GR32", ENCODING_RM) 1090 ENCODING("GR32orGR64", ENCODING_RM) 1091 ENCODING("GR64", ENCODING_RM) 1092 ENCODING("GR8", ENCODING_RM) 1093 ENCODING("VR128", ENCODING_RM) 1094 ENCODING("VR128X", ENCODING_RM) 1095 ENCODING("FR128", ENCODING_RM) 1096 ENCODING("FR64", ENCODING_RM) 1097 ENCODING("FR32", ENCODING_RM) 1098 ENCODING("FR64X", ENCODING_RM) 1099 ENCODING("FR32X", ENCODING_RM) 1100 ENCODING("FR16X", ENCODING_RM) 1101 ENCODING("VR64", ENCODING_RM) 1102 ENCODING("VR256", ENCODING_RM) 1103 ENCODING("VR256X", ENCODING_RM) 1104 ENCODING("VR512", ENCODING_RM) 1105 ENCODING("VK1", ENCODING_RM) 1106 ENCODING("VK2", ENCODING_RM) 1107 ENCODING("VK4", ENCODING_RM) 1108 ENCODING("VK8", ENCODING_RM) 1109 ENCODING("VK16", ENCODING_RM) 1110 ENCODING("VK32", ENCODING_RM) 1111 ENCODING("VK64", ENCODING_RM) 1112 ENCODING("BNDR", ENCODING_RM) 1113 ENCODING("TILE", ENCODING_RM) 1114 errs() << "Unhandled R/M register encoding " << s << "\n"; 1115 llvm_unreachable("Unhandled R/M register encoding"); 1116 } 1117 1118 OperandEncoding 1119 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1120 uint8_t OpSize) { 1121 ENCODING("GR16", ENCODING_REG) 1122 ENCODING("GR16orGR32orGR64",ENCODING_REG) 1123 ENCODING("GR32", ENCODING_REG) 1124 ENCODING("GR32orGR64", ENCODING_REG) 1125 ENCODING("GR64", ENCODING_REG) 1126 ENCODING("GR8", ENCODING_REG) 1127 ENCODING("VR128", ENCODING_REG) 1128 ENCODING("FR128", ENCODING_REG) 1129 ENCODING("FR64", ENCODING_REG) 1130 ENCODING("FR32", ENCODING_REG) 1131 ENCODING("VR64", ENCODING_REG) 1132 ENCODING("SEGMENT_REG", ENCODING_REG) 1133 ENCODING("DEBUG_REG", ENCODING_REG) 1134 ENCODING("CONTROL_REG", ENCODING_REG) 1135 ENCODING("VR256", ENCODING_REG) 1136 ENCODING("VR256X", ENCODING_REG) 1137 ENCODING("VR128X", ENCODING_REG) 1138 ENCODING("FR64X", ENCODING_REG) 1139 ENCODING("FR32X", ENCODING_REG) 1140 ENCODING("FR16X", ENCODING_REG) 1141 ENCODING("VR512", ENCODING_REG) 1142 ENCODING("VK1", ENCODING_REG) 1143 ENCODING("VK2", ENCODING_REG) 1144 ENCODING("VK4", ENCODING_REG) 1145 ENCODING("VK8", ENCODING_REG) 1146 ENCODING("VK16", ENCODING_REG) 1147 ENCODING("VK32", ENCODING_REG) 1148 ENCODING("VK64", ENCODING_REG) 1149 ENCODING("VK1Pair", ENCODING_REG) 1150 ENCODING("VK2Pair", ENCODING_REG) 1151 ENCODING("VK4Pair", ENCODING_REG) 1152 ENCODING("VK8Pair", ENCODING_REG) 1153 ENCODING("VK16Pair", ENCODING_REG) 1154 ENCODING("VK1WM", ENCODING_REG) 1155 ENCODING("VK2WM", ENCODING_REG) 1156 ENCODING("VK4WM", ENCODING_REG) 1157 ENCODING("VK8WM", ENCODING_REG) 1158 ENCODING("VK16WM", ENCODING_REG) 1159 ENCODING("VK32WM", ENCODING_REG) 1160 ENCODING("VK64WM", ENCODING_REG) 1161 ENCODING("BNDR", ENCODING_REG) 1162 ENCODING("TILE", ENCODING_REG) 1163 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1164 llvm_unreachable("Unhandled reg/opcode register encoding"); 1165 } 1166 1167 OperandEncoding 1168 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1169 uint8_t OpSize) { 1170 ENCODING("GR32", ENCODING_VVVV) 1171 ENCODING("GR64", ENCODING_VVVV) 1172 ENCODING("FR32", ENCODING_VVVV) 1173 ENCODING("FR128", ENCODING_VVVV) 1174 ENCODING("FR64", ENCODING_VVVV) 1175 ENCODING("VR128", ENCODING_VVVV) 1176 ENCODING("VR256", ENCODING_VVVV) 1177 ENCODING("FR16X", ENCODING_VVVV) 1178 ENCODING("FR32X", ENCODING_VVVV) 1179 ENCODING("FR64X", ENCODING_VVVV) 1180 ENCODING("VR128X", ENCODING_VVVV) 1181 ENCODING("VR256X", ENCODING_VVVV) 1182 ENCODING("VR512", ENCODING_VVVV) 1183 ENCODING("VK1", ENCODING_VVVV) 1184 ENCODING("VK2", ENCODING_VVVV) 1185 ENCODING("VK4", ENCODING_VVVV) 1186 ENCODING("VK8", ENCODING_VVVV) 1187 ENCODING("VK16", ENCODING_VVVV) 1188 ENCODING("VK32", ENCODING_VVVV) 1189 ENCODING("VK64", ENCODING_VVVV) 1190 ENCODING("TILE", ENCODING_VVVV) 1191 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1192 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1193 } 1194 1195 OperandEncoding 1196 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1197 uint8_t OpSize) { 1198 ENCODING("VK1WM", ENCODING_WRITEMASK) 1199 ENCODING("VK2WM", ENCODING_WRITEMASK) 1200 ENCODING("VK4WM", ENCODING_WRITEMASK) 1201 ENCODING("VK8WM", ENCODING_WRITEMASK) 1202 ENCODING("VK16WM", ENCODING_WRITEMASK) 1203 ENCODING("VK32WM", ENCODING_WRITEMASK) 1204 ENCODING("VK64WM", ENCODING_WRITEMASK) 1205 errs() << "Unhandled mask register encoding " << s << "\n"; 1206 llvm_unreachable("Unhandled mask register encoding"); 1207 } 1208 1209 OperandEncoding 1210 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1211 uint8_t OpSize) { 1212 ENCODING("i16mem", ENCODING_RM) 1213 ENCODING("i32mem", ENCODING_RM) 1214 ENCODING("i64mem", ENCODING_RM) 1215 ENCODING("i8mem", ENCODING_RM) 1216 ENCODING("shmem", ENCODING_RM) 1217 ENCODING("ssmem", ENCODING_RM) 1218 ENCODING("sdmem", ENCODING_RM) 1219 ENCODING("f128mem", ENCODING_RM) 1220 ENCODING("f256mem", ENCODING_RM) 1221 ENCODING("f512mem", ENCODING_RM) 1222 ENCODING("f64mem", ENCODING_RM) 1223 ENCODING("f32mem", ENCODING_RM) 1224 ENCODING("f16mem", ENCODING_RM) 1225 ENCODING("i128mem", ENCODING_RM) 1226 ENCODING("i256mem", ENCODING_RM) 1227 ENCODING("i512mem", ENCODING_RM) 1228 ENCODING("f80mem", ENCODING_RM) 1229 ENCODING("lea64_32mem", ENCODING_RM) 1230 ENCODING("lea64mem", ENCODING_RM) 1231 ENCODING("anymem", ENCODING_RM) 1232 ENCODING("opaquemem", ENCODING_RM) 1233 ENCODING("sibmem", ENCODING_SIB) 1234 ENCODING("vx64mem", ENCODING_VSIB) 1235 ENCODING("vx128mem", ENCODING_VSIB) 1236 ENCODING("vx256mem", ENCODING_VSIB) 1237 ENCODING("vy128mem", ENCODING_VSIB) 1238 ENCODING("vy256mem", ENCODING_VSIB) 1239 ENCODING("vx64xmem", ENCODING_VSIB) 1240 ENCODING("vx128xmem", ENCODING_VSIB) 1241 ENCODING("vx256xmem", ENCODING_VSIB) 1242 ENCODING("vy128xmem", ENCODING_VSIB) 1243 ENCODING("vy256xmem", ENCODING_VSIB) 1244 ENCODING("vy512xmem", ENCODING_VSIB) 1245 ENCODING("vz256mem", ENCODING_VSIB) 1246 ENCODING("vz512mem", ENCODING_VSIB) 1247 errs() << "Unhandled memory encoding " << s << "\n"; 1248 llvm_unreachable("Unhandled memory encoding"); 1249 } 1250 1251 OperandEncoding 1252 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1253 uint8_t OpSize) { 1254 if(OpSize != X86Local::OpSize16) { 1255 // For instructions without an OpSize prefix, a declared 16-bit register or 1256 // immediate encoding is special. 1257 ENCODING("i16imm", ENCODING_IW) 1258 } 1259 ENCODING("i16imm", ENCODING_Iv) 1260 ENCODING("i16i8imm", ENCODING_IB) 1261 ENCODING("i32imm", ENCODING_Iv) 1262 ENCODING("i32i8imm", ENCODING_IB) 1263 ENCODING("i64i32imm", ENCODING_ID) 1264 ENCODING("i64i8imm", ENCODING_IB) 1265 ENCODING("i8imm", ENCODING_IB) 1266 ENCODING("u8imm", ENCODING_IB) 1267 ENCODING("i16u8imm", ENCODING_IB) 1268 ENCODING("i32u8imm", ENCODING_IB) 1269 ENCODING("i64u8imm", ENCODING_IB) 1270 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1271 ENCODING("i16imm_brtarget", ENCODING_IW) 1272 ENCODING("i32imm_brtarget", ENCODING_ID) 1273 ENCODING("brtarget32", ENCODING_ID) 1274 ENCODING("brtarget16", ENCODING_IW) 1275 ENCODING("brtarget8", ENCODING_IB) 1276 ENCODING("i64imm", ENCODING_IO) 1277 ENCODING("offset16_8", ENCODING_Ia) 1278 ENCODING("offset16_16", ENCODING_Ia) 1279 ENCODING("offset16_32", ENCODING_Ia) 1280 ENCODING("offset32_8", ENCODING_Ia) 1281 ENCODING("offset32_16", ENCODING_Ia) 1282 ENCODING("offset32_32", ENCODING_Ia) 1283 ENCODING("offset32_64", ENCODING_Ia) 1284 ENCODING("offset64_8", ENCODING_Ia) 1285 ENCODING("offset64_16", ENCODING_Ia) 1286 ENCODING("offset64_32", ENCODING_Ia) 1287 ENCODING("offset64_64", ENCODING_Ia) 1288 ENCODING("srcidx8", ENCODING_SI) 1289 ENCODING("srcidx16", ENCODING_SI) 1290 ENCODING("srcidx32", ENCODING_SI) 1291 ENCODING("srcidx64", ENCODING_SI) 1292 ENCODING("dstidx8", ENCODING_DI) 1293 ENCODING("dstidx16", ENCODING_DI) 1294 ENCODING("dstidx32", ENCODING_DI) 1295 ENCODING("dstidx64", ENCODING_DI) 1296 errs() << "Unhandled relocation encoding " << s << "\n"; 1297 llvm_unreachable("Unhandled relocation encoding"); 1298 } 1299 1300 OperandEncoding 1301 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1302 uint8_t OpSize) { 1303 ENCODING("GR32", ENCODING_Rv) 1304 ENCODING("GR64", ENCODING_RO) 1305 ENCODING("GR16", ENCODING_Rv) 1306 ENCODING("GR8", ENCODING_RB) 1307 ENCODING("ccode", ENCODING_CC) 1308 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1309 llvm_unreachable("Unhandled opcode modifier encoding"); 1310 } 1311 #undef ENCODING 1312