1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22 
23 using namespace llvm;
24 
25 #define MRM_MAPPING     \
26   MAP(C1, 33)           \
27   MAP(C2, 34)           \
28   MAP(C3, 35)           \
29   MAP(C4, 36)           \
30   MAP(C8, 37)           \
31   MAP(C9, 38)           \
32   MAP(CA, 39)           \
33   MAP(CB, 40)           \
34   MAP(E8, 41)           \
35   MAP(F0, 42)           \
36   MAP(F8, 45)           \
37   MAP(F9, 46)           \
38   MAP(D0, 47)           \
39   MAP(D1, 48)           \
40   MAP(D4, 49)           \
41   MAP(D5, 50)           \
42   MAP(D6, 51)           \
43   MAP(D8, 52)           \
44   MAP(D9, 53)           \
45   MAP(DA, 54)           \
46   MAP(DB, 55)           \
47   MAP(DC, 56)           \
48   MAP(DD, 57)           \
49   MAP(DE, 58)           \
50   MAP(DF, 59)
51 
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54   enum {
55     Pseudo      = 0,
56     RawFrm      = 1,
57     AddRegFrm   = 2,
58     MRMDestReg  = 3,
59     MRMDestMem  = 4,
60     MRMSrcReg   = 5,
61     MRMSrcMem   = 6,
62     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66     MRMInitReg  = 32,
67     RawFrmImm8  = 43,
68     RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70     MRM_MAPPING
71 #undef MAP
72     lastMRM
73   };
74 
75   enum {
76     TB  = 1,
77     REP = 2,
78     D8 = 3, D9 = 4, DA = 5, DB = 6,
79     DC = 7, DD = 8, DE = 9, DF = 10,
80     XD = 11,  XS = 12,
81     T8 = 13,  P_TA = 14,
82     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83     XOP8 = 20, XOP9 = 21, XOPA = 22
84   };
85 }
86 
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
103 
104 #define ONE_BYTE_EXTENSION_TABLES \
105   EXTENSION_TABLE(80)             \
106   EXTENSION_TABLE(81)             \
107   EXTENSION_TABLE(82)             \
108   EXTENSION_TABLE(83)             \
109   EXTENSION_TABLE(8f)             \
110   EXTENSION_TABLE(c0)             \
111   EXTENSION_TABLE(c1)             \
112   EXTENSION_TABLE(c6)             \
113   EXTENSION_TABLE(c7)             \
114   EXTENSION_TABLE(d0)             \
115   EXTENSION_TABLE(d1)             \
116   EXTENSION_TABLE(d2)             \
117   EXTENSION_TABLE(d3)             \
118   EXTENSION_TABLE(f6)             \
119   EXTENSION_TABLE(f7)             \
120   EXTENSION_TABLE(fe)             \
121   EXTENSION_TABLE(ff)
122 
123 #define TWO_BYTE_EXTENSION_TABLES \
124   EXTENSION_TABLE(00)             \
125   EXTENSION_TABLE(01)             \
126   EXTENSION_TABLE(0d)             \
127   EXTENSION_TABLE(18)             \
128   EXTENSION_TABLE(71)             \
129   EXTENSION_TABLE(72)             \
130   EXTENSION_TABLE(73)             \
131   EXTENSION_TABLE(ae)             \
132   EXTENSION_TABLE(ba)             \
133   EXTENSION_TABLE(c7)
134 
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136   EXTENSION_TABLE(F3)
137 
138 #define XOP9_MAP_EXTENSION_TABLES \
139   EXTENSION_TABLE(01)             \
140   EXTENSION_TABLE(02)
141 
142 using namespace X86Disassembler;
143 
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
146 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 ///   0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return     - true if the form implies that a ModR/M byte is required, false
151 ///               otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153   if (form == X86Local::MRMDestReg    ||
154      form == X86Local::MRMDestMem    ||
155      form == X86Local::MRMSrcReg     ||
156      form == X86Local::MRMSrcMem     ||
157      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159     return true;
160   else
161     return false;
162 }
163 
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 ///   the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return     - true if the form implies that Mod must be 0b11, false
169 ///               otherwise.
170 static bool isRegFormat(uint8_t form) {
171   if (form == X86Local::MRMDestReg ||
172      form == X86Local::MRMSrcReg  ||
173      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174     return true;
175   else
176     return false;
177 }
178 
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 ///   Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return     - The field, with the first bit in the BitsInit as the lowest
184 ///               order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186   int width = init.getNumBits();
187 
188   assert(width <= 8 && "Field is too large for uint8_t!");
189 
190   int     index;
191   uint8_t mask = 0x01;
192 
193   uint8_t ret = 0;
194 
195   for (index = 0; index < width; index++) {
196     if (static_cast<BitInit*>(init.getBit(index))->getValue())
197       ret |= mask;
198 
199     mask <<= 1;
200   }
201 
202   return ret;
203 }
204 
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 ///   name of the field.
207 ///
208 /// @param rec  - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return     - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212   BitsInit* bits = rec->getValueAsBitsInit(name);
213   return byteFromBitsInit(*bits);
214 }
215 
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217                                      const CodeGenInstruction &insn,
218                                      InstrUID uid) {
219   UID = uid;
220 
221   Rec = insn.TheDef;
222   Name = Rec->getName();
223   Spec = &tables.specForUID(UID);
224 
225   if (!Rec->isSubClassOf("X86Inst")) {
226     ShouldBeEmitted = false;
227     return;
228   }
229 
230   Prefix   = byteFromRec(Rec, "Prefix");
231   Opcode   = byteFromRec(Rec, "Opcode");
232   Form     = byteFromRec(Rec, "FormBits");
233   SegOvr   = byteFromRec(Rec, "SegOvrBits");
234 
235   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
236   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
237   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
238   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
239   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
240   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
242   HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
243   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
244   HasEVEXPrefix    = Rec->getValueAsBit("hasEVEXPrefix");
245   HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246   HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
247   HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
248   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
249   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
250 
251   Name      = Rec->getName();
252   AsmString = Rec->getValueAsString("AsmString");
253 
254   Operands = &insn.Operands.OperandList;
255 
256   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
257                      (Name.find("CRC32") != Name.npos);
258   HasFROperands    = hasFROperands();
259   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
260 
261   // Check for 64-bit inst which does not require REX
262   Is32Bit = false;
263   Is64Bit = false;
264   // FIXME: Is there some better way to check for In64BitMode?
265   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
268       Is32Bit = true;
269       break;
270     }
271     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
272       Is64Bit = true;
273       break;
274     }
275   }
276   // FIXME: These instructions aren't marked as 64-bit in any way
277   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
278              Rec->getName() == "MASKMOVDQU64" ||
279              Rec->getName() == "POPFS64" ||
280              Rec->getName() == "POPGS64" ||
281              Rec->getName() == "PUSHFS64" ||
282              Rec->getName() == "PUSHGS64" ||
283              Rec->getName() == "REX64_PREFIX" ||
284              Rec->getName().find("MOV64") != Name.npos ||
285              Rec->getName().find("PUSH64") != Name.npos ||
286              Rec->getName().find("POP64") != Name.npos;
287 
288   ShouldBeEmitted  = true;
289 }
290 
291 void RecognizableInstr::processInstr(DisassemblerTables &tables,
292                                      const CodeGenInstruction &insn,
293                                      InstrUID uid)
294 {
295   // Ignore "asm parser only" instructions.
296   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
297     return;
298 
299   RecognizableInstr recogInstr(tables, insn, uid);
300 
301   recogInstr.emitInstructionSpecifier(tables);
302 
303   if (recogInstr.shouldBeEmitted())
304     recogInstr.emitDecodePath(tables);
305 }
306 
307 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
308                     (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
309 
310 InstructionContext RecognizableInstr::insnContext() const {
311   InstructionContext insnContext;
312 
313   if (HasEVEXPrefix) {
314     if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
315       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
316       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
317     }
318     // VEX_L & VEX_W
319     if (HasVEX_LPrefix && HasVEX_WPrefix) {
320       if (HasOpSizePrefix)
321         insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
322       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
323         insnContext = EVEX_KB(IC_EVEX_L_W_XS);
324       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
325                Prefix == X86Local::TAXD)
326         insnContext = EVEX_KB(IC_EVEX_L_W_XD);
327       else
328         insnContext = EVEX_KB(IC_EVEX_L_W);
329     } else if (HasVEX_LPrefix) {
330       // VEX_L
331       if (HasOpSizePrefix)
332         insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
333       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
334         insnContext = EVEX_KB(IC_EVEX_L_XS);
335       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
336                Prefix == X86Local::TAXD)
337         insnContext = EVEX_KB(IC_EVEX_L_XD);
338       else
339         insnContext = EVEX_KB(IC_EVEX_L);
340     }
341     else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
342       // EVEX_L2 & VEX_W
343       if (HasOpSizePrefix)
344         insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
345       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
346         insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
347       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
348                Prefix == X86Local::TAXD)
349         insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
350       else
351         insnContext = EVEX_KB(IC_EVEX_L2_W);
352     } else if (HasEVEX_L2Prefix) {
353       // EVEX_L2
354       if (HasOpSizePrefix)
355         insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
356       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357           Prefix == X86Local::TAXD)
358         insnContext = EVEX_KB(IC_EVEX_L2_XD);
359       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360         insnContext = EVEX_KB(IC_EVEX_L2_XS);
361       else
362         insnContext = EVEX_KB(IC_EVEX_L2);
363     }
364     else if (HasVEX_WPrefix) {
365       // VEX_W
366       if (HasOpSizePrefix)
367         insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
368       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
369         insnContext = EVEX_KB(IC_EVEX_W_XS);
370       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
371                Prefix == X86Local::TAXD)
372         insnContext = EVEX_KB(IC_EVEX_W_XD);
373       else
374         insnContext = EVEX_KB(IC_EVEX_W);
375     }
376     // No L, no W
377     else if (HasOpSizePrefix)
378       insnContext = EVEX_KB(IC_EVEX_OPSIZE);
379     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
380              Prefix == X86Local::TAXD)
381       insnContext = EVEX_KB(IC_EVEX_XD);
382     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
383       insnContext = EVEX_KB(IC_EVEX_XS);
384     else
385       insnContext = EVEX_KB(IC_EVEX);
386     /// eof EVEX
387   } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
388     if (HasVEX_LPrefix && HasVEX_WPrefix) {
389       if (HasOpSizePrefix)
390         insnContext = IC_VEX_L_W_OPSIZE;
391       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392         insnContext = IC_VEX_L_W_XS;
393       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394                Prefix == X86Local::TAXD)
395         insnContext = IC_VEX_L_W_XD;
396       else
397         insnContext = IC_VEX_L_W;
398     } else if (HasOpSizePrefix && HasVEX_LPrefix)
399       insnContext = IC_VEX_L_OPSIZE;
400     else if (HasOpSizePrefix && HasVEX_WPrefix)
401       insnContext = IC_VEX_W_OPSIZE;
402     else if (HasOpSizePrefix)
403       insnContext = IC_VEX_OPSIZE;
404     else if (HasVEX_LPrefix &&
405              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406       insnContext = IC_VEX_L_XS;
407     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
408                                 Prefix == X86Local::T8XD ||
409                                 Prefix == X86Local::TAXD))
410       insnContext = IC_VEX_L_XD;
411     else if (HasVEX_WPrefix &&
412              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
413       insnContext = IC_VEX_W_XS;
414     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
415                                 Prefix == X86Local::T8XD ||
416                                 Prefix == X86Local::TAXD))
417       insnContext = IC_VEX_W_XD;
418     else if (HasVEX_WPrefix)
419       insnContext = IC_VEX_W;
420     else if (HasVEX_LPrefix)
421       insnContext = IC_VEX_L;
422     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
423              Prefix == X86Local::TAXD)
424       insnContext = IC_VEX_XD;
425     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
426       insnContext = IC_VEX_XS;
427     else
428       insnContext = IC_VEX;
429   } else if (Is64Bit || HasREX_WPrefix) {
430     if (HasREX_WPrefix && HasOpSizePrefix)
431       insnContext = IC_64BIT_REXW_OPSIZE;
432     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
433                                  Prefix == X86Local::T8XD ||
434                                  Prefix == X86Local::TAXD))
435       insnContext = IC_64BIT_XD_OPSIZE;
436     else if (HasOpSizePrefix &&
437              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438       insnContext = IC_64BIT_XS_OPSIZE;
439     else if (HasOpSizePrefix)
440       insnContext = IC_64BIT_OPSIZE;
441     else if (HasAdSizePrefix)
442       insnContext = IC_64BIT_ADSIZE;
443     else if (HasREX_WPrefix &&
444              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
445       insnContext = IC_64BIT_REXW_XS;
446     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
447                                 Prefix == X86Local::T8XD ||
448                                 Prefix == X86Local::TAXD))
449       insnContext = IC_64BIT_REXW_XD;
450     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
451              Prefix == X86Local::TAXD)
452       insnContext = IC_64BIT_XD;
453     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
454       insnContext = IC_64BIT_XS;
455     else if (HasREX_WPrefix)
456       insnContext = IC_64BIT_REXW;
457     else
458       insnContext = IC_64BIT;
459   } else {
460     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
461                             Prefix == X86Local::T8XD ||
462                             Prefix == X86Local::TAXD))
463       insnContext = IC_XD_OPSIZE;
464     else if (HasOpSizePrefix &&
465              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
466       insnContext = IC_XS_OPSIZE;
467     else if (HasOpSizePrefix)
468       insnContext = IC_OPSIZE;
469     else if (HasAdSizePrefix)
470       insnContext = IC_ADSIZE;
471     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
472              Prefix == X86Local::TAXD)
473       insnContext = IC_XD;
474     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
475              Prefix == X86Local::REP)
476       insnContext = IC_XS;
477     else
478       insnContext = IC;
479   }
480 
481   return insnContext;
482 }
483 
484 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
485   ///////////////////
486   // FILTER_STRONG
487   //
488 
489   // Filter out intrinsics
490 
491   assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
492 
493   if (Form == X86Local::Pseudo ||
494       (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
495        Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
496     return FILTER_STRONG;
497 
498 
499   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
500   // printed as a separate "instruction".
501 
502   if (Name.find("_Int") != Name.npos       ||
503       Name.find("Int_") != Name.npos)
504     return FILTER_STRONG;
505 
506   // Filter out instructions with segment override prefixes.
507   // They're too messy to handle now and we'll special case them if needed.
508 
509   if (SegOvr)
510     return FILTER_STRONG;
511 
512 
513   /////////////////
514   // FILTER_WEAK
515   //
516 
517 
518   // Filter out instructions with a LOCK prefix;
519   //   prefer forms that do not have the prefix
520   if (HasLockPrefix)
521     return FILTER_WEAK;
522 
523   // Filter out alternate forms of AVX instructions
524   if (Name.find("_alt") != Name.npos ||
525       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
526       Name.find("_64mr") != Name.npos ||
527       Name.find("rr64") != Name.npos)
528     return FILTER_WEAK;
529 
530   // Special cases.
531 
532   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
533     return FILTER_WEAK;
534   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos &&
535       Name != "MOVZPQILo2PQIrr")
536     return FILTER_WEAK;
537   if (Name.find("Fs") != Name.npos)
538     return FILTER_WEAK;
539   if (Name == "PUSH64i16"         ||
540       Name == "MOVPQI2QImr"       ||
541       Name == "VMOVPQI2QImr"      ||
542       Name == "VMASKMOVDQU64")
543     return FILTER_WEAK;
544 
545   // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
546   // For now, just prefer the REP versions.
547   if (Name == "XACQUIRE_PREFIX" ||
548       Name == "XRELEASE_PREFIX")
549     return FILTER_WEAK;
550 
551   if (HasFROperands && Name.find("MOV") != Name.npos &&
552      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
553       (Name.find("to") != Name.npos)))
554     return FILTER_STRONG;
555 
556   return FILTER_NORMAL;
557 }
558 
559 bool RecognizableInstr::hasFROperands() const {
560   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
561   unsigned numOperands = OperandList.size();
562 
563   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
564     const std::string &recName = OperandList[operandIndex].Rec->getName();
565 
566     if (recName.find("FR") != recName.npos)
567       return true;
568   }
569   return false;
570 }
571 
572 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
573                                       unsigned &physicalOperandIndex,
574                                       unsigned &numPhysicalOperands,
575                                       const unsigned *operandMapping,
576                                       OperandEncoding (*encodingFromString)
577                                         (const std::string&,
578                                          bool hasOpSizePrefix)) {
579   if (optional) {
580     if (physicalOperandIndex >= numPhysicalOperands)
581       return;
582   } else {
583     assert(physicalOperandIndex < numPhysicalOperands);
584   }
585 
586   while (operandMapping[operandIndex] != operandIndex) {
587     Spec->operands[operandIndex].encoding = ENCODING_DUP;
588     Spec->operands[operandIndex].type =
589       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
590     ++operandIndex;
591   }
592 
593   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
594 
595   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
596                                                               HasOpSizePrefix);
597   Spec->operands[operandIndex].type = typeFromString(typeName,
598                                                      IsSSE,
599                                                      HasREX_WPrefix,
600                                                      HasOpSizePrefix);
601 
602   ++operandIndex;
603   ++physicalOperandIndex;
604 }
605 
606 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
607   Spec->name       = Name;
608 
609   if (!ShouldBeEmitted)
610     return;
611 
612   switch (filter()) {
613   case FILTER_WEAK:
614     Spec->filtered = true;
615     break;
616   case FILTER_STRONG:
617     ShouldBeEmitted = false;
618     return;
619   case FILTER_NORMAL:
620     break;
621   }
622 
623   Spec->insnContext = insnContext();
624 
625   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
626 
627   unsigned numOperands = OperandList.size();
628   unsigned numPhysicalOperands = 0;
629 
630   // operandMapping maps from operands in OperandList to their originals.
631   // If operandMapping[i] != i, then the entry is a duplicate.
632   unsigned operandMapping[X86_MAX_OPERANDS];
633   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
634 
635   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
636     if (OperandList[operandIndex].Constraints.size()) {
637       const CGIOperandList::ConstraintInfo &Constraint =
638         OperandList[operandIndex].Constraints[0];
639       if (Constraint.isTied()) {
640         operandMapping[operandIndex] = operandIndex;
641         operandMapping[Constraint.getTiedOperand()] = operandIndex;
642       } else {
643         ++numPhysicalOperands;
644         operandMapping[operandIndex] = operandIndex;
645       }
646     } else {
647       ++numPhysicalOperands;
648       operandMapping[operandIndex] = operandIndex;
649     }
650   }
651 
652 #define HANDLE_OPERAND(class)               \
653   handleOperand(false,                      \
654                 operandIndex,               \
655                 physicalOperandIndex,       \
656                 numPhysicalOperands,        \
657                 operandMapping,             \
658                 class##EncodingFromString);
659 
660 #define HANDLE_OPTIONAL(class)              \
661   handleOperand(true,                       \
662                 operandIndex,               \
663                 physicalOperandIndex,       \
664                 numPhysicalOperands,        \
665                 operandMapping,             \
666                 class##EncodingFromString);
667 
668   // operandIndex should always be < numOperands
669   unsigned operandIndex = 0;
670   // physicalOperandIndex should always be < numPhysicalOperands
671   unsigned physicalOperandIndex = 0;
672 
673   switch (Form) {
674   case X86Local::RawFrm:
675     // Operand 1 (optional) is an address or immediate.
676     // Operand 2 (optional) is an immediate.
677     assert(numPhysicalOperands <= 2 &&
678            "Unexpected number of operands for RawFrm");
679     HANDLE_OPTIONAL(relocation)
680     HANDLE_OPTIONAL(immediate)
681     break;
682   case X86Local::AddRegFrm:
683     // Operand 1 is added to the opcode.
684     // Operand 2 (optional) is an address.
685     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
686            "Unexpected number of operands for AddRegFrm");
687     HANDLE_OPERAND(opcodeModifier)
688     HANDLE_OPTIONAL(relocation)
689     break;
690   case X86Local::MRMDestReg:
691     // Operand 1 is a register operand in the R/M field.
692     // Operand 2 is a register operand in the Reg/Opcode field.
693     // - In AVX, there is a register operand in the VEX.vvvv field here -
694     // Operand 3 (optional) is an immediate.
695     if (HasVEX_4VPrefix)
696       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
697              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
698     else
699       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
700              "Unexpected number of operands for MRMDestRegFrm");
701 
702     HANDLE_OPERAND(rmRegister)
703 
704     if (HasVEX_4VPrefix)
705       // FIXME: In AVX, the register below becomes the one encoded
706       // in ModRMVEX and the one above the one in the VEX.VVVV field
707       HANDLE_OPERAND(vvvvRegister)
708 
709     HANDLE_OPERAND(roRegister)
710     HANDLE_OPTIONAL(immediate)
711     break;
712   case X86Local::MRMDestMem:
713     // Operand 1 is a memory operand (possibly SIB-extended)
714     // Operand 2 is a register operand in the Reg/Opcode field.
715     // - In AVX, there is a register operand in the VEX.vvvv field here -
716     // Operand 3 (optional) is an immediate.
717     if (HasVEX_4VPrefix)
718       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
719              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
720     else
721       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
722              "Unexpected number of operands for MRMDestMemFrm");
723     HANDLE_OPERAND(memory)
724 
725     if (HasEVEX_K)
726       HANDLE_OPERAND(writemaskRegister)
727 
728     if (HasVEX_4VPrefix)
729       // FIXME: In AVX, the register below becomes the one encoded
730       // in ModRMVEX and the one above the one in the VEX.VVVV field
731       HANDLE_OPERAND(vvvvRegister)
732 
733     HANDLE_OPERAND(roRegister)
734     HANDLE_OPTIONAL(immediate)
735     break;
736   case X86Local::MRMSrcReg:
737     // Operand 1 is a register operand in the Reg/Opcode field.
738     // Operand 2 is a register operand in the R/M field.
739     // - In AVX, there is a register operand in the VEX.vvvv field here -
740     // Operand 3 (optional) is an immediate.
741     // Operand 4 (optional) is an immediate.
742 
743     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
744       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
745              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
746     else
747       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
748              "Unexpected number of operands for MRMSrcRegFrm");
749 
750     HANDLE_OPERAND(roRegister)
751 
752     if (HasEVEX_K)
753       HANDLE_OPERAND(writemaskRegister)
754 
755     if (HasVEX_4VPrefix)
756       // FIXME: In AVX, the register below becomes the one encoded
757       // in ModRMVEX and the one above the one in the VEX.VVVV field
758       HANDLE_OPERAND(vvvvRegister)
759 
760     if (HasMemOp4Prefix)
761       HANDLE_OPERAND(immediate)
762 
763     HANDLE_OPERAND(rmRegister)
764 
765     if (HasVEX_4VOp3Prefix)
766       HANDLE_OPERAND(vvvvRegister)
767 
768     if (!HasMemOp4Prefix)
769       HANDLE_OPTIONAL(immediate)
770     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
771     HANDLE_OPTIONAL(immediate)
772     break;
773   case X86Local::MRMSrcMem:
774     // Operand 1 is a register operand in the Reg/Opcode field.
775     // Operand 2 is a memory operand (possibly SIB-extended)
776     // - In AVX, there is a register operand in the VEX.vvvv field here -
777     // Operand 3 (optional) is an immediate.
778 
779     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
780       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
781              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
782     else
783       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
784              "Unexpected number of operands for MRMSrcMemFrm");
785 
786     HANDLE_OPERAND(roRegister)
787 
788     if (HasEVEX_K)
789       HANDLE_OPERAND(writemaskRegister)
790 
791     if (HasVEX_4VPrefix)
792       // FIXME: In AVX, the register below becomes the one encoded
793       // in ModRMVEX and the one above the one in the VEX.VVVV field
794       HANDLE_OPERAND(vvvvRegister)
795 
796     if (HasMemOp4Prefix)
797       HANDLE_OPERAND(immediate)
798 
799     HANDLE_OPERAND(memory)
800 
801     if (HasVEX_4VOp3Prefix)
802       HANDLE_OPERAND(vvvvRegister)
803 
804     if (!HasMemOp4Prefix)
805       HANDLE_OPTIONAL(immediate)
806     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
807     break;
808   case X86Local::MRM0r:
809   case X86Local::MRM1r:
810   case X86Local::MRM2r:
811   case X86Local::MRM3r:
812   case X86Local::MRM4r:
813   case X86Local::MRM5r:
814   case X86Local::MRM6r:
815   case X86Local::MRM7r:
816     {
817       // Operand 1 is a register operand in the R/M field.
818       // Operand 2 (optional) is an immediate or relocation.
819       // Operand 3 (optional) is an immediate.
820       unsigned kOp = (HasEVEX_K) ? 1:0;
821       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
822       if (numPhysicalOperands > 3 + kOp + Op4v)
823         llvm_unreachable("Unexpected number of operands for MRMnr");
824     }
825     if (HasVEX_4VPrefix)
826       HANDLE_OPERAND(vvvvRegister)
827 
828     if (HasEVEX_K)
829       HANDLE_OPERAND(writemaskRegister)
830     HANDLE_OPTIONAL(rmRegister)
831     HANDLE_OPTIONAL(relocation)
832     HANDLE_OPTIONAL(immediate)
833     break;
834   case X86Local::MRM0m:
835   case X86Local::MRM1m:
836   case X86Local::MRM2m:
837   case X86Local::MRM3m:
838   case X86Local::MRM4m:
839   case X86Local::MRM5m:
840   case X86Local::MRM6m:
841   case X86Local::MRM7m:
842     {
843       // Operand 1 is a memory operand (possibly SIB-extended)
844       // Operand 2 (optional) is an immediate or relocation.
845       unsigned kOp = (HasEVEX_K) ? 1:0;
846       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
847       if (numPhysicalOperands < 1 + kOp + Op4v ||
848           numPhysicalOperands > 2 + kOp + Op4v)
849         llvm_unreachable("Unexpected number of operands for MRMnm");
850     }
851     if (HasVEX_4VPrefix)
852       HANDLE_OPERAND(vvvvRegister)
853     if (HasEVEX_K)
854       HANDLE_OPERAND(writemaskRegister)
855     HANDLE_OPERAND(memory)
856     HANDLE_OPTIONAL(relocation)
857     break;
858   case X86Local::RawFrmImm8:
859     // operand 1 is a 16-bit immediate
860     // operand 2 is an 8-bit immediate
861     assert(numPhysicalOperands == 2 &&
862            "Unexpected number of operands for X86Local::RawFrmImm8");
863     HANDLE_OPERAND(immediate)
864     HANDLE_OPERAND(immediate)
865     break;
866   case X86Local::RawFrmImm16:
867     // operand 1 is a 16-bit immediate
868     // operand 2 is a 16-bit immediate
869     HANDLE_OPERAND(immediate)
870     HANDLE_OPERAND(immediate)
871     break;
872   case X86Local::MRM_F8:
873     if (Opcode == 0xc6) {
874       assert(numPhysicalOperands == 1 &&
875              "Unexpected number of operands for X86Local::MRM_F8");
876       HANDLE_OPERAND(immediate)
877     } else if (Opcode == 0xc7) {
878       assert(numPhysicalOperands == 1 &&
879              "Unexpected number of operands for X86Local::MRM_F8");
880       HANDLE_OPERAND(relocation)
881     }
882     break;
883   case X86Local::MRMInitReg:
884     // Ignored.
885     break;
886   }
887 
888   #undef HANDLE_OPERAND
889   #undef HANDLE_OPTIONAL
890 }
891 
892 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
893   // Special cases where the LLVM tables are not complete
894 
895 #define MAP(from, to)                     \
896   case X86Local::MRM_##from:              \
897     filter = new ExactFilter(0x##from);   \
898     break;
899 
900   OpcodeType    opcodeType  = (OpcodeType)-1;
901 
902   ModRMFilter*  filter      = NULL;
903   uint8_t       opcodeToSet = 0;
904 
905   switch (Prefix) {
906   default: llvm_unreachable("Invalid prefix!");
907   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
908   case X86Local::XD:
909   case X86Local::XS:
910   case X86Local::TB:
911     opcodeType = TWOBYTE;
912 
913     switch (Opcode) {
914     default:
915       if (needsModRMForDecode(Form))
916         filter = new ModFilter(isRegFormat(Form));
917       else
918         filter = new DumbFilter();
919       break;
920 #define EXTENSION_TABLE(n) case 0x##n:
921     TWO_BYTE_EXTENSION_TABLES
922 #undef EXTENSION_TABLE
923       switch (Form) {
924       default:
925         llvm_unreachable("Unhandled two-byte extended opcode");
926       case X86Local::MRM0r:
927       case X86Local::MRM1r:
928       case X86Local::MRM2r:
929       case X86Local::MRM3r:
930       case X86Local::MRM4r:
931       case X86Local::MRM5r:
932       case X86Local::MRM6r:
933       case X86Local::MRM7r:
934         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
935         break;
936       case X86Local::MRM0m:
937       case X86Local::MRM1m:
938       case X86Local::MRM2m:
939       case X86Local::MRM3m:
940       case X86Local::MRM4m:
941       case X86Local::MRM5m:
942       case X86Local::MRM6m:
943       case X86Local::MRM7m:
944         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
945         break;
946       MRM_MAPPING
947       } // switch (Form)
948       break;
949     } // switch (Opcode)
950     opcodeToSet = Opcode;
951     break;
952   case X86Local::T8:
953   case X86Local::T8XD:
954   case X86Local::T8XS:
955     opcodeType = THREEBYTE_38;
956     switch (Opcode) {
957     default:
958       if (needsModRMForDecode(Form))
959         filter = new ModFilter(isRegFormat(Form));
960       else
961         filter = new DumbFilter();
962       break;
963 #define EXTENSION_TABLE(n) case 0x##n:
964     THREE_BYTE_38_EXTENSION_TABLES
965 #undef EXTENSION_TABLE
966       switch (Form) {
967       default:
968         llvm_unreachable("Unhandled two-byte extended opcode");
969       case X86Local::MRM0r:
970       case X86Local::MRM1r:
971       case X86Local::MRM2r:
972       case X86Local::MRM3r:
973       case X86Local::MRM4r:
974       case X86Local::MRM5r:
975       case X86Local::MRM6r:
976       case X86Local::MRM7r:
977         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
978         break;
979       case X86Local::MRM0m:
980       case X86Local::MRM1m:
981       case X86Local::MRM2m:
982       case X86Local::MRM3m:
983       case X86Local::MRM4m:
984       case X86Local::MRM5m:
985       case X86Local::MRM6m:
986       case X86Local::MRM7m:
987         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
988         break;
989       MRM_MAPPING
990       } // switch (Form)
991       break;
992     } // switch (Opcode)
993     opcodeToSet = Opcode;
994     break;
995   case X86Local::P_TA:
996   case X86Local::TAXD:
997     opcodeType = THREEBYTE_3A;
998     if (needsModRMForDecode(Form))
999       filter = new ModFilter(isRegFormat(Form));
1000     else
1001       filter = new DumbFilter();
1002     opcodeToSet = Opcode;
1003     break;
1004   case X86Local::A6:
1005     opcodeType = THREEBYTE_A6;
1006     if (needsModRMForDecode(Form))
1007       filter = new ModFilter(isRegFormat(Form));
1008     else
1009       filter = new DumbFilter();
1010     opcodeToSet = Opcode;
1011     break;
1012   case X86Local::A7:
1013     opcodeType = THREEBYTE_A7;
1014     if (needsModRMForDecode(Form))
1015       filter = new ModFilter(isRegFormat(Form));
1016     else
1017       filter = new DumbFilter();
1018     opcodeToSet = Opcode;
1019     break;
1020   case X86Local::XOP8:
1021     opcodeType = XOP8_MAP;
1022     if (needsModRMForDecode(Form))
1023       filter = new ModFilter(isRegFormat(Form));
1024     else
1025       filter = new DumbFilter();
1026     opcodeToSet = Opcode;
1027     break;
1028   case X86Local::XOP9:
1029     opcodeType = XOP9_MAP;
1030     switch (Opcode) {
1031     default:
1032       if (needsModRMForDecode(Form))
1033         filter = new ModFilter(isRegFormat(Form));
1034       else
1035         filter = new DumbFilter();
1036       break;
1037 #define EXTENSION_TABLE(n) case 0x##n:
1038     XOP9_MAP_EXTENSION_TABLES
1039 #undef EXTENSION_TABLE
1040       switch (Form) {
1041       default:
1042         llvm_unreachable("Unhandled XOP9 extended opcode");
1043       case X86Local::MRM0r:
1044       case X86Local::MRM1r:
1045       case X86Local::MRM2r:
1046       case X86Local::MRM3r:
1047       case X86Local::MRM4r:
1048       case X86Local::MRM5r:
1049       case X86Local::MRM6r:
1050       case X86Local::MRM7r:
1051         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1052         break;
1053       case X86Local::MRM0m:
1054       case X86Local::MRM1m:
1055       case X86Local::MRM2m:
1056       case X86Local::MRM3m:
1057       case X86Local::MRM4m:
1058       case X86Local::MRM5m:
1059       case X86Local::MRM6m:
1060       case X86Local::MRM7m:
1061         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1062         break;
1063       MRM_MAPPING
1064       } // switch (Form)
1065       break;
1066     } // switch (Opcode)
1067     opcodeToSet = Opcode;
1068     break;
1069   case X86Local::XOPA:
1070     opcodeType = XOPA_MAP;
1071     if (needsModRMForDecode(Form))
1072       filter = new ModFilter(isRegFormat(Form));
1073     else
1074       filter = new DumbFilter();
1075     opcodeToSet = Opcode;
1076     break;
1077   case X86Local::D8:
1078   case X86Local::D9:
1079   case X86Local::DA:
1080   case X86Local::DB:
1081   case X86Local::DC:
1082   case X86Local::DD:
1083   case X86Local::DE:
1084   case X86Local::DF:
1085     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1086     opcodeType = ONEBYTE;
1087     if (Form == X86Local::AddRegFrm) {
1088       Spec->modifierType = MODIFIER_MODRM;
1089       Spec->modifierBase = Opcode;
1090       filter = new AddRegEscapeFilter(Opcode);
1091     } else {
1092       filter = new EscapeFilter(true, Opcode);
1093     }
1094     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1095     break;
1096   case X86Local::REP:
1097   case 0:
1098     opcodeType = ONEBYTE;
1099     switch (Opcode) {
1100 #define EXTENSION_TABLE(n) case 0x##n:
1101     ONE_BYTE_EXTENSION_TABLES
1102 #undef EXTENSION_TABLE
1103       switch (Form) {
1104       default:
1105         llvm_unreachable("Fell through the cracks of a single-byte "
1106                          "extended opcode");
1107       case X86Local::MRM0r:
1108       case X86Local::MRM1r:
1109       case X86Local::MRM2r:
1110       case X86Local::MRM3r:
1111       case X86Local::MRM4r:
1112       case X86Local::MRM5r:
1113       case X86Local::MRM6r:
1114       case X86Local::MRM7r:
1115         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1116         break;
1117       case X86Local::MRM0m:
1118       case X86Local::MRM1m:
1119       case X86Local::MRM2m:
1120       case X86Local::MRM3m:
1121       case X86Local::MRM4m:
1122       case X86Local::MRM5m:
1123       case X86Local::MRM6m:
1124       case X86Local::MRM7m:
1125         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1126         break;
1127       MRM_MAPPING
1128       } // switch (Form)
1129       break;
1130     case 0xd8:
1131     case 0xd9:
1132     case 0xda:
1133     case 0xdb:
1134     case 0xdc:
1135     case 0xdd:
1136     case 0xde:
1137     case 0xdf:
1138       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1139       break;
1140     default:
1141       if (needsModRMForDecode(Form))
1142         filter = new ModFilter(isRegFormat(Form));
1143       else
1144         filter = new DumbFilter();
1145       break;
1146     } // switch (Opcode)
1147     opcodeToSet = Opcode;
1148   } // switch (Prefix)
1149 
1150   assert(opcodeType != (OpcodeType)-1 &&
1151          "Opcode type not set");
1152   assert(filter && "Filter not set");
1153 
1154   if (Form == X86Local::AddRegFrm) {
1155     if(Spec->modifierType != MODIFIER_MODRM) {
1156       assert(opcodeToSet < 0xf9 &&
1157              "Not enough room for all ADDREG_FRM operands");
1158 
1159       uint8_t currentOpcode;
1160 
1161       for (currentOpcode = opcodeToSet;
1162            currentOpcode < opcodeToSet + 8;
1163            ++currentOpcode)
1164         tables.setTableFields(opcodeType,
1165                               insnContext(),
1166                               currentOpcode,
1167                               *filter,
1168                               UID, Is32Bit, IgnoresVEX_L);
1169 
1170       Spec->modifierType = MODIFIER_OPCODE;
1171       Spec->modifierBase = opcodeToSet;
1172     } else {
1173       // modifierBase was set where MODIFIER_MODRM was set
1174       tables.setTableFields(opcodeType,
1175                             insnContext(),
1176                             opcodeToSet,
1177                             *filter,
1178                             UID, Is32Bit, IgnoresVEX_L);
1179     }
1180   } else {
1181     tables.setTableFields(opcodeType,
1182                           insnContext(),
1183                           opcodeToSet,
1184                           *filter,
1185                           UID, Is32Bit, IgnoresVEX_L);
1186 
1187     Spec->modifierType = MODIFIER_NONE;
1188     Spec->modifierBase = opcodeToSet;
1189   }
1190 
1191   delete filter;
1192 
1193 #undef MAP
1194 }
1195 
1196 #define TYPE(str, type) if (s == str) return type;
1197 OperandType RecognizableInstr::typeFromString(const std::string &s,
1198                                               bool isSSE,
1199                                               bool hasREX_WPrefix,
1200                                               bool hasOpSizePrefix) {
1201   if (isSSE) {
1202     // For SSE instructions, we ignore the OpSize prefix and force operand
1203     // sizes.
1204     TYPE("GR16",              TYPE_R16)
1205     TYPE("GR32",              TYPE_R32)
1206     TYPE("GR64",              TYPE_R64)
1207   }
1208   if(hasREX_WPrefix) {
1209     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1210     // is special.
1211     TYPE("GR32",              TYPE_R32)
1212   }
1213   if(!hasOpSizePrefix) {
1214     // For instructions without an OpSize prefix, a declared 16-bit register or
1215     // immediate encoding is special.
1216     TYPE("GR16",              TYPE_R16)
1217     TYPE("i16imm",            TYPE_IMM16)
1218   }
1219   TYPE("i16mem",              TYPE_Mv)
1220   TYPE("i16imm",              TYPE_IMMv)
1221   TYPE("i16i8imm",            TYPE_IMMv)
1222   TYPE("GR16",                TYPE_Rv)
1223   TYPE("i32mem",              TYPE_Mv)
1224   TYPE("i32imm",              TYPE_IMMv)
1225   TYPE("i32i8imm",            TYPE_IMM32)
1226   TYPE("u32u8imm",            TYPE_IMM32)
1227   TYPE("GR32",                TYPE_Rv)
1228   TYPE("i64mem",              TYPE_Mv)
1229   TYPE("i64i32imm",           TYPE_IMM64)
1230   TYPE("i64i8imm",            TYPE_IMM64)
1231   TYPE("GR64",                TYPE_R64)
1232   TYPE("i8mem",               TYPE_M8)
1233   TYPE("i8imm",               TYPE_IMM8)
1234   TYPE("GR8",                 TYPE_R8)
1235   TYPE("VR128",               TYPE_XMM128)
1236   TYPE("VR128X",              TYPE_XMM128)
1237   TYPE("f128mem",             TYPE_M128)
1238   TYPE("f256mem",             TYPE_M256)
1239   TYPE("f512mem",             TYPE_M512)
1240   TYPE("FR64",                TYPE_XMM64)
1241   TYPE("FR64X",               TYPE_XMM64)
1242   TYPE("f64mem",              TYPE_M64FP)
1243   TYPE("sdmem",               TYPE_M64FP)
1244   TYPE("FR32",                TYPE_XMM32)
1245   TYPE("FR32X",               TYPE_XMM32)
1246   TYPE("f32mem",              TYPE_M32FP)
1247   TYPE("ssmem",               TYPE_M32FP)
1248   TYPE("RST",                 TYPE_ST)
1249   TYPE("i128mem",             TYPE_M128)
1250   TYPE("i256mem",             TYPE_M256)
1251   TYPE("i512mem",             TYPE_M512)
1252   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1253   TYPE("i16imm_pcrel",        TYPE_REL16)
1254   TYPE("i32imm_pcrel",        TYPE_REL32)
1255   TYPE("SSECC",               TYPE_IMM3)
1256   TYPE("AVXCC",               TYPE_IMM5)
1257   TYPE("brtarget",            TYPE_RELv)
1258   TYPE("uncondbrtarget",      TYPE_RELv)
1259   TYPE("brtarget8",           TYPE_REL8)
1260   TYPE("f80mem",              TYPE_M80FP)
1261   TYPE("lea32mem",            TYPE_LEA)
1262   TYPE("lea64_32mem",         TYPE_LEA)
1263   TYPE("lea64mem",            TYPE_LEA)
1264   TYPE("VR64",                TYPE_MM64)
1265   TYPE("i64imm",              TYPE_IMMv)
1266   TYPE("opaque32mem",         TYPE_M1616)
1267   TYPE("opaque48mem",         TYPE_M1632)
1268   TYPE("opaque80mem",         TYPE_M1664)
1269   TYPE("opaque512mem",        TYPE_M512)
1270   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1271   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1272   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1273   TYPE("offset8",             TYPE_MOFFS8)
1274   TYPE("offset16",            TYPE_MOFFS16)
1275   TYPE("offset32",            TYPE_MOFFS32)
1276   TYPE("offset64",            TYPE_MOFFS64)
1277   TYPE("VR256",               TYPE_XMM256)
1278   TYPE("VR256X",              TYPE_XMM256)
1279   TYPE("VR512",               TYPE_XMM512)
1280   TYPE("VK8",                 TYPE_VK8)
1281   TYPE("VK8WM",               TYPE_VK8)
1282   TYPE("VK16",                TYPE_VK16)
1283   TYPE("VK16WM",              TYPE_VK16)
1284   TYPE("GR16_NOAX",           TYPE_Rv)
1285   TYPE("GR32_NOAX",           TYPE_Rv)
1286   TYPE("GR64_NOAX",           TYPE_R64)
1287   TYPE("vx32mem",             TYPE_M32)
1288   TYPE("vy32mem",             TYPE_M32)
1289   TYPE("vz32mem",             TYPE_M32)
1290   TYPE("vx64mem",             TYPE_M64)
1291   TYPE("vy64mem",             TYPE_M64)
1292   TYPE("vy64xmem",            TYPE_M64)
1293   TYPE("vz64mem",             TYPE_M64)
1294   errs() << "Unhandled type string " << s << "\n";
1295   llvm_unreachable("Unhandled type string");
1296 }
1297 #undef TYPE
1298 
1299 #define ENCODING(str, encoding) if (s == str) return encoding;
1300 OperandEncoding RecognizableInstr::immediateEncodingFromString
1301   (const std::string &s,
1302    bool hasOpSizePrefix) {
1303   if(!hasOpSizePrefix) {
1304     // For instructions without an OpSize prefix, a declared 16-bit register or
1305     // immediate encoding is special.
1306     ENCODING("i16imm",        ENCODING_IW)
1307   }
1308   ENCODING("i32i8imm",        ENCODING_IB)
1309   ENCODING("u32u8imm",        ENCODING_IB)
1310   ENCODING("SSECC",           ENCODING_IB)
1311   ENCODING("AVXCC",           ENCODING_IB)
1312   ENCODING("i16imm",          ENCODING_Iv)
1313   ENCODING("i16i8imm",        ENCODING_IB)
1314   ENCODING("i32imm",          ENCODING_Iv)
1315   ENCODING("i64i32imm",       ENCODING_ID)
1316   ENCODING("i64i8imm",        ENCODING_IB)
1317   ENCODING("i8imm",           ENCODING_IB)
1318   // This is not a typo.  Instructions like BLENDVPD put
1319   // register IDs in 8-bit immediates nowadays.
1320   ENCODING("FR32",            ENCODING_IB)
1321   ENCODING("FR64",            ENCODING_IB)
1322   ENCODING("VR128",           ENCODING_IB)
1323   ENCODING("VR256",           ENCODING_IB)
1324   ENCODING("FR32X",           ENCODING_IB)
1325   ENCODING("FR64X",           ENCODING_IB)
1326   ENCODING("VR128X",          ENCODING_IB)
1327   ENCODING("VR256X",          ENCODING_IB)
1328   ENCODING("VR512",           ENCODING_IB)
1329   errs() << "Unhandled immediate encoding " << s << "\n";
1330   llvm_unreachable("Unhandled immediate encoding");
1331 }
1332 
1333 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1334   (const std::string &s,
1335    bool hasOpSizePrefix) {
1336   ENCODING("GR16",            ENCODING_RM)
1337   ENCODING("GR32",            ENCODING_RM)
1338   ENCODING("GR64",            ENCODING_RM)
1339   ENCODING("GR8",             ENCODING_RM)
1340   ENCODING("VR128",           ENCODING_RM)
1341   ENCODING("VR128X",          ENCODING_RM)
1342   ENCODING("FR64",            ENCODING_RM)
1343   ENCODING("FR32",            ENCODING_RM)
1344   ENCODING("FR64X",           ENCODING_RM)
1345   ENCODING("FR32X",           ENCODING_RM)
1346   ENCODING("VR64",            ENCODING_RM)
1347   ENCODING("VR256",           ENCODING_RM)
1348   ENCODING("VR256X",          ENCODING_RM)
1349   ENCODING("VR512",           ENCODING_RM)
1350   ENCODING("VK8",             ENCODING_RM)
1351   ENCODING("VK16",            ENCODING_RM)
1352   errs() << "Unhandled R/M register encoding " << s << "\n";
1353   llvm_unreachable("Unhandled R/M register encoding");
1354 }
1355 
1356 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1357   (const std::string &s,
1358    bool hasOpSizePrefix) {
1359   ENCODING("GR16",            ENCODING_REG)
1360   ENCODING("GR32",            ENCODING_REG)
1361   ENCODING("GR64",            ENCODING_REG)
1362   ENCODING("GR8",             ENCODING_REG)
1363   ENCODING("VR128",           ENCODING_REG)
1364   ENCODING("FR64",            ENCODING_REG)
1365   ENCODING("FR32",            ENCODING_REG)
1366   ENCODING("VR64",            ENCODING_REG)
1367   ENCODING("SEGMENT_REG",     ENCODING_REG)
1368   ENCODING("DEBUG_REG",       ENCODING_REG)
1369   ENCODING("CONTROL_REG",     ENCODING_REG)
1370   ENCODING("VR256",           ENCODING_REG)
1371   ENCODING("VR256X",          ENCODING_REG)
1372   ENCODING("VR128X",          ENCODING_REG)
1373   ENCODING("FR64X",           ENCODING_REG)
1374   ENCODING("FR32X",           ENCODING_REG)
1375   ENCODING("VR512",           ENCODING_REG)
1376   ENCODING("VK8",             ENCODING_REG)
1377   ENCODING("VK16",            ENCODING_REG)
1378   ENCODING("VK8WM",           ENCODING_REG)
1379   ENCODING("VK16WM",          ENCODING_REG)
1380   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1381   llvm_unreachable("Unhandled reg/opcode register encoding");
1382 }
1383 
1384 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1385   (const std::string &s,
1386    bool hasOpSizePrefix) {
1387   ENCODING("GR32",            ENCODING_VVVV)
1388   ENCODING("GR64",            ENCODING_VVVV)
1389   ENCODING("FR32",            ENCODING_VVVV)
1390   ENCODING("FR64",            ENCODING_VVVV)
1391   ENCODING("VR128",           ENCODING_VVVV)
1392   ENCODING("VR256",           ENCODING_VVVV)
1393   ENCODING("FR32X",           ENCODING_VVVV)
1394   ENCODING("FR64X",           ENCODING_VVVV)
1395   ENCODING("VR128X",          ENCODING_VVVV)
1396   ENCODING("VR256X",          ENCODING_VVVV)
1397   ENCODING("VR512",           ENCODING_VVVV)
1398   ENCODING("VK8",             ENCODING_VVVV)
1399   ENCODING("VK16",            ENCODING_VVVV)
1400   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1401   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1402 }
1403 
1404 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1405   (const std::string &s,
1406    bool hasOpSizePrefix) {
1407   ENCODING("VK8WM",           ENCODING_WRITEMASK)
1408   ENCODING("VK16WM",          ENCODING_WRITEMASK)
1409   errs() << "Unhandled mask register encoding " << s << "\n";
1410   llvm_unreachable("Unhandled mask register encoding");
1411 }
1412 
1413 OperandEncoding RecognizableInstr::memoryEncodingFromString
1414   (const std::string &s,
1415    bool hasOpSizePrefix) {
1416   ENCODING("i16mem",          ENCODING_RM)
1417   ENCODING("i32mem",          ENCODING_RM)
1418   ENCODING("i64mem",          ENCODING_RM)
1419   ENCODING("i8mem",           ENCODING_RM)
1420   ENCODING("ssmem",           ENCODING_RM)
1421   ENCODING("sdmem",           ENCODING_RM)
1422   ENCODING("f128mem",         ENCODING_RM)
1423   ENCODING("f256mem",         ENCODING_RM)
1424   ENCODING("f512mem",         ENCODING_RM)
1425   ENCODING("f64mem",          ENCODING_RM)
1426   ENCODING("f32mem",          ENCODING_RM)
1427   ENCODING("i128mem",         ENCODING_RM)
1428   ENCODING("i256mem",         ENCODING_RM)
1429   ENCODING("i512mem",         ENCODING_RM)
1430   ENCODING("f80mem",          ENCODING_RM)
1431   ENCODING("lea32mem",        ENCODING_RM)
1432   ENCODING("lea64_32mem",     ENCODING_RM)
1433   ENCODING("lea64mem",        ENCODING_RM)
1434   ENCODING("opaque32mem",     ENCODING_RM)
1435   ENCODING("opaque48mem",     ENCODING_RM)
1436   ENCODING("opaque80mem",     ENCODING_RM)
1437   ENCODING("opaque512mem",    ENCODING_RM)
1438   ENCODING("vx32mem",         ENCODING_RM)
1439   ENCODING("vy32mem",         ENCODING_RM)
1440   ENCODING("vz32mem",         ENCODING_RM)
1441   ENCODING("vx64mem",         ENCODING_RM)
1442   ENCODING("vy64mem",         ENCODING_RM)
1443   ENCODING("vy64xmem",        ENCODING_RM)
1444   ENCODING("vz64mem",         ENCODING_RM)
1445   errs() << "Unhandled memory encoding " << s << "\n";
1446   llvm_unreachable("Unhandled memory encoding");
1447 }
1448 
1449 OperandEncoding RecognizableInstr::relocationEncodingFromString
1450   (const std::string &s,
1451    bool hasOpSizePrefix) {
1452   if(!hasOpSizePrefix) {
1453     // For instructions without an OpSize prefix, a declared 16-bit register or
1454     // immediate encoding is special.
1455     ENCODING("i16imm",        ENCODING_IW)
1456   }
1457   ENCODING("i16imm",          ENCODING_Iv)
1458   ENCODING("i16i8imm",        ENCODING_IB)
1459   ENCODING("i32imm",          ENCODING_Iv)
1460   ENCODING("i32i8imm",        ENCODING_IB)
1461   ENCODING("i64i32imm",       ENCODING_ID)
1462   ENCODING("i64i8imm",        ENCODING_IB)
1463   ENCODING("i8imm",           ENCODING_IB)
1464   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1465   ENCODING("i16imm_pcrel",    ENCODING_IW)
1466   ENCODING("i32imm_pcrel",    ENCODING_ID)
1467   ENCODING("brtarget",        ENCODING_Iv)
1468   ENCODING("brtarget8",       ENCODING_IB)
1469   ENCODING("i64imm",          ENCODING_IO)
1470   ENCODING("offset8",         ENCODING_Ia)
1471   ENCODING("offset16",        ENCODING_Ia)
1472   ENCODING("offset32",        ENCODING_Ia)
1473   ENCODING("offset64",        ENCODING_Ia)
1474   errs() << "Unhandled relocation encoding " << s << "\n";
1475   llvm_unreachable("Unhandled relocation encoding");
1476 }
1477 
1478 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1479   (const std::string &s,
1480    bool hasOpSizePrefix) {
1481   ENCODING("RST",             ENCODING_I)
1482   ENCODING("GR32",            ENCODING_Rv)
1483   ENCODING("GR64",            ENCODING_RO)
1484   ENCODING("GR16",            ENCODING_Rv)
1485   ENCODING("GR8",             ENCODING_RB)
1486   ENCODING("GR16_NOAX",       ENCODING_Rv)
1487   ENCODING("GR32_NOAX",       ENCODING_Rv)
1488   ENCODING("GR64_NOAX",       ENCODING_RO)
1489   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1490   llvm_unreachable("Unhandled opcode modifier encoding");
1491 }
1492 #undef ENCODING
1493