1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86DisassemblerShared.h" 18 #include "X86RecognizableInstr.h" 19 #include "X86ModRMFilters.h" 20 21 #include "llvm/Support/ErrorHandling.h" 22 23 #include <string> 24 25 using namespace llvm; 26 27 #define MRM_MAPPING \ 28 MAP(C1, 33) \ 29 MAP(C2, 34) \ 30 MAP(C3, 35) \ 31 MAP(C4, 36) \ 32 MAP(C8, 37) \ 33 MAP(C9, 38) \ 34 MAP(E8, 39) \ 35 MAP(F0, 40) \ 36 MAP(F8, 41) \ 37 MAP(F9, 42) 38 39 // A clone of X86 since we can't depend on something that is generated. 40 namespace X86Local { 41 enum { 42 Pseudo = 0, 43 RawFrm = 1, 44 AddRegFrm = 2, 45 MRMDestReg = 3, 46 MRMDestMem = 4, 47 MRMSrcReg = 5, 48 MRMSrcMem = 6, 49 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 50 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 51 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 52 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 53 MRMInitReg = 32, 54 #define MAP(from, to) MRM_##from = to, 55 MRM_MAPPING 56 #undef MAP 57 RawFrmImm8 = 43, 58 RawFrmImm16 = 44, 59 lastMRM 60 }; 61 62 enum { 63 TB = 1, 64 REP = 2, 65 D8 = 3, D9 = 4, DA = 5, DB = 6, 66 DC = 7, DD = 8, DE = 9, DF = 10, 67 XD = 11, XS = 12, 68 T8 = 13, P_TA = 14, 69 P_0F_AE = 16, P_0F_01 = 17 70 }; 71 } 72 73 // If rows are added to the opcode extension tables, then corresponding entries 74 // must be added here. 75 // 76 // If the row corresponds to a single byte (i.e., 8f), then add an entry for 77 // that byte to ONE_BYTE_EXTENSION_TABLES. 78 // 79 // If the row corresponds to two bytes where the first is 0f, add an entry for 80 // the second byte to TWO_BYTE_EXTENSION_TABLES. 81 // 82 // If the row corresponds to some other set of bytes, you will need to modify 83 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes 84 // to the X86 TD files, except in two cases: if the first two bytes of such a 85 // new combination are 0f 38 or 0f 3a, you just have to add maps called 86 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a 87 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line 88 // in RecognizableInstr::emitDecodePath(). 89 90 #define ONE_BYTE_EXTENSION_TABLES \ 91 EXTENSION_TABLE(80) \ 92 EXTENSION_TABLE(81) \ 93 EXTENSION_TABLE(82) \ 94 EXTENSION_TABLE(83) \ 95 EXTENSION_TABLE(8f) \ 96 EXTENSION_TABLE(c0) \ 97 EXTENSION_TABLE(c1) \ 98 EXTENSION_TABLE(c6) \ 99 EXTENSION_TABLE(c7) \ 100 EXTENSION_TABLE(d0) \ 101 EXTENSION_TABLE(d1) \ 102 EXTENSION_TABLE(d2) \ 103 EXTENSION_TABLE(d3) \ 104 EXTENSION_TABLE(f6) \ 105 EXTENSION_TABLE(f7) \ 106 EXTENSION_TABLE(fe) \ 107 EXTENSION_TABLE(ff) 108 109 #define TWO_BYTE_EXTENSION_TABLES \ 110 EXTENSION_TABLE(00) \ 111 EXTENSION_TABLE(01) \ 112 EXTENSION_TABLE(18) \ 113 EXTENSION_TABLE(71) \ 114 EXTENSION_TABLE(72) \ 115 EXTENSION_TABLE(73) \ 116 EXTENSION_TABLE(ae) \ 117 EXTENSION_TABLE(ba) \ 118 EXTENSION_TABLE(c7) 119 120 using namespace X86Disassembler; 121 122 /// needsModRMForDecode - Indicates whether a particular instruction requires a 123 /// ModR/M byte for the instruction to be properly decoded. For example, a 124 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to 125 /// 0b11. 126 /// 127 /// @param form - The form of the instruction. 128 /// @return - true if the form implies that a ModR/M byte is required, false 129 /// otherwise. 130 static bool needsModRMForDecode(uint8_t form) { 131 if (form == X86Local::MRMDestReg || 132 form == X86Local::MRMDestMem || 133 form == X86Local::MRMSrcReg || 134 form == X86Local::MRMSrcMem || 135 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) || 136 (form >= X86Local::MRM0m && form <= X86Local::MRM7m)) 137 return true; 138 else 139 return false; 140 } 141 142 /// isRegFormat - Indicates whether a particular form requires the Mod field of 143 /// the ModR/M byte to be 0b11. 144 /// 145 /// @param form - The form of the instruction. 146 /// @return - true if the form implies that Mod must be 0b11, false 147 /// otherwise. 148 static bool isRegFormat(uint8_t form) { 149 if (form == X86Local::MRMDestReg || 150 form == X86Local::MRMSrcReg || 151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)) 152 return true; 153 else 154 return false; 155 } 156 157 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 158 /// Useful for switch statements and the like. 159 /// 160 /// @param init - A reference to the BitsInit to be decoded. 161 /// @return - The field, with the first bit in the BitsInit as the lowest 162 /// order bit. 163 static uint8_t byteFromBitsInit(BitsInit &init) { 164 int width = init.getNumBits(); 165 166 assert(width <= 8 && "Field is too large for uint8_t!"); 167 168 int index; 169 uint8_t mask = 0x01; 170 171 uint8_t ret = 0; 172 173 for (index = 0; index < width; index++) { 174 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 175 ret |= mask; 176 177 mask <<= 1; 178 } 179 180 return ret; 181 } 182 183 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 184 /// name of the field. 185 /// 186 /// @param rec - The record from which to extract the value. 187 /// @param name - The name of the field in the record. 188 /// @return - The field, as translated by byteFromBitsInit(). 189 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 190 BitsInit* bits = rec->getValueAsBitsInit(name); 191 return byteFromBitsInit(*bits); 192 } 193 194 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 195 const CodeGenInstruction &insn, 196 InstrUID uid) { 197 UID = uid; 198 199 Rec = insn.TheDef; 200 Name = Rec->getName(); 201 Spec = &tables.specForUID(UID); 202 203 if (!Rec->isSubClassOf("X86Inst")) { 204 ShouldBeEmitted = false; 205 return; 206 } 207 208 Prefix = byteFromRec(Rec, "Prefix"); 209 Opcode = byteFromRec(Rec, "Opcode"); 210 Form = byteFromRec(Rec, "FormBits"); 211 SegOvr = byteFromRec(Rec, "SegOvrBits"); 212 213 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); 214 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 215 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); 216 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); 217 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 218 219 Name = Rec->getName(); 220 AsmString = Rec->getValueAsString("AsmString"); 221 222 Operands = &insn.Operands.OperandList; 223 224 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos); 225 HasFROperands = false; 226 227 ShouldBeEmitted = true; 228 } 229 230 void RecognizableInstr::processInstr(DisassemblerTables &tables, 231 const CodeGenInstruction &insn, 232 InstrUID uid) 233 { 234 // Ignore "asm parser only" instructions. 235 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 236 return; 237 238 RecognizableInstr recogInstr(tables, insn, uid); 239 240 recogInstr.emitInstructionSpecifier(tables); 241 242 if (recogInstr.shouldBeEmitted()) 243 recogInstr.emitDecodePath(tables); 244 } 245 246 InstructionContext RecognizableInstr::insnContext() const { 247 InstructionContext insnContext; 248 249 if (Name.find("64") != Name.npos || HasREX_WPrefix) { 250 if (HasREX_WPrefix && HasOpSizePrefix) 251 insnContext = IC_64BIT_REXW_OPSIZE; 252 else if (HasOpSizePrefix) 253 insnContext = IC_64BIT_OPSIZE; 254 else if (HasREX_WPrefix && Prefix == X86Local::XS) 255 insnContext = IC_64BIT_REXW_XS; 256 else if (HasREX_WPrefix && Prefix == X86Local::XD) 257 insnContext = IC_64BIT_REXW_XD; 258 else if (Prefix == X86Local::XD) 259 insnContext = IC_64BIT_XD; 260 else if (Prefix == X86Local::XS) 261 insnContext = IC_64BIT_XS; 262 else if (HasREX_WPrefix) 263 insnContext = IC_64BIT_REXW; 264 else 265 insnContext = IC_64BIT; 266 } else { 267 if (HasOpSizePrefix) 268 insnContext = IC_OPSIZE; 269 else if (Prefix == X86Local::XD) 270 insnContext = IC_XD; 271 else if (Prefix == X86Local::XS) 272 insnContext = IC_XS; 273 else 274 insnContext = IC; 275 } 276 277 return insnContext; 278 } 279 280 RecognizableInstr::filter_ret RecognizableInstr::filter() const { 281 // Filter out intrinsics 282 283 if (!Rec->isSubClassOf("X86Inst")) 284 return FILTER_STRONG; 285 286 if (Form == X86Local::Pseudo || 287 IsCodeGenOnly) 288 return FILTER_STRONG; 289 290 if (Form == X86Local::MRMInitReg) 291 return FILTER_STRONG; 292 293 294 // Filter out instructions with a LOCK prefix; 295 // prefer forms that do not have the prefix 296 if (HasLockPrefix) 297 return FILTER_WEAK; 298 299 // Filter out artificial instructions 300 301 if (Name.find("TAILJMP") != Name.npos || 302 Name.find("_Int") != Name.npos || 303 Name.find("_int") != Name.npos || 304 Name.find("Int_") != Name.npos || 305 Name.find("_NOREX") != Name.npos || 306 Name.find("_TC") != Name.npos || 307 Name.find("EH_RETURN") != Name.npos || 308 Name.find("V_SET") != Name.npos || 309 Name.find("LOCK_") != Name.npos || 310 Name.find("WIN") != Name.npos) 311 return FILTER_STRONG; 312 313 // Special cases. 314 315 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI") 316 return FILTER_WEAK; 317 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI") 318 return FILTER_WEAK; 319 320 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos) 321 return FILTER_WEAK; 322 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos) 323 return FILTER_WEAK; 324 if (Name.find("Fs") != Name.npos) 325 return FILTER_WEAK; 326 if (Name == "MOVLPDrr" || 327 Name == "MOVLPSrr" || 328 Name == "PUSHFQ" || 329 Name == "BSF16rr" || 330 Name == "BSF16rm" || 331 Name == "BSR16rr" || 332 Name == "BSR16rm" || 333 Name == "MOVSX16rm8" || 334 Name == "MOVSX16rr8" || 335 Name == "MOVZX16rm8" || 336 Name == "MOVZX16rr8" || 337 Name == "PUSH32i16" || 338 Name == "PUSH64i16" || 339 Name == "MOVPQI2QImr" || 340 Name == "MOVSDmr" || 341 Name == "MOVSDrm" || 342 Name == "MOVSSmr" || 343 Name == "MOVSSrm" || 344 Name == "MMX_MOVD64rrv164" || 345 Name == "CRC32m16" || 346 Name == "MOV64ri64i32" || 347 Name == "CRC32r16") 348 return FILTER_WEAK; 349 350 // Filter out instructions with segment override prefixes. 351 // They're too messy to handle now and we'll special case them if needed. 352 353 if (SegOvr) 354 return FILTER_STRONG; 355 356 // Filter out instructions that can't be printed. 357 358 if (AsmString.size() == 0) 359 return FILTER_STRONG; 360 361 // Filter out instructions with subreg operands. 362 363 if (AsmString.find("subreg") != AsmString.npos) 364 return FILTER_STRONG; 365 366 if (HasFROperands && Name.find("MOV") != Name.npos && 367 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 368 (Name.find("to") != Name.npos))) 369 return FILTER_WEAK; 370 371 return FILTER_NORMAL; 372 } 373 374 void RecognizableInstr::handleOperand( 375 bool optional, 376 unsigned &operandIndex, 377 unsigned &physicalOperandIndex, 378 unsigned &numPhysicalOperands, 379 unsigned *operandMapping, 380 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) { 381 if (optional) { 382 if (physicalOperandIndex >= numPhysicalOperands) 383 return; 384 } else { 385 assert(physicalOperandIndex < numPhysicalOperands); 386 } 387 388 while (operandMapping[operandIndex] != operandIndex) { 389 Spec->operands[operandIndex].encoding = ENCODING_DUP; 390 Spec->operands[operandIndex].type = 391 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 392 ++operandIndex; 393 } 394 395 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 396 397 Spec->operands[operandIndex].encoding = encodingFromString(typeName, 398 HasOpSizePrefix); 399 Spec->operands[operandIndex].type = typeFromString(typeName, 400 IsSSE, 401 HasREX_WPrefix, 402 HasOpSizePrefix); 403 404 ++operandIndex; 405 ++physicalOperandIndex; 406 } 407 408 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { 409 Spec->name = Name; 410 411 if (!Rec->isSubClassOf("X86Inst")) 412 return; 413 414 switch (filter()) { 415 case FILTER_WEAK: 416 Spec->filtered = true; 417 break; 418 case FILTER_STRONG: 419 ShouldBeEmitted = false; 420 return; 421 case FILTER_NORMAL: 422 break; 423 } 424 425 Spec->insnContext = insnContext(); 426 427 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 428 429 unsigned operandIndex; 430 unsigned numOperands = OperandList.size(); 431 unsigned numPhysicalOperands = 0; 432 433 // operandMapping maps from operands in OperandList to their originals. 434 // If operandMapping[i] != i, then the entry is a duplicate. 435 unsigned operandMapping[X86_MAX_OPERANDS]; 436 437 bool hasFROperands = false; 438 439 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 440 441 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 442 if (OperandList[operandIndex].Constraints.size()) { 443 const CGIOperandList::ConstraintInfo &Constraint = 444 OperandList[operandIndex].Constraints[0]; 445 if (Constraint.isTied()) { 446 operandMapping[operandIndex] = Constraint.getTiedOperand(); 447 } else { 448 ++numPhysicalOperands; 449 operandMapping[operandIndex] = operandIndex; 450 } 451 } else { 452 ++numPhysicalOperands; 453 operandMapping[operandIndex] = operandIndex; 454 } 455 456 const std::string &recName = OperandList[operandIndex].Rec->getName(); 457 458 if (recName.find("FR") != recName.npos) 459 hasFROperands = true; 460 } 461 462 if (hasFROperands && Name.find("MOV") != Name.npos && 463 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || 464 (Name.find("to") != Name.npos))) 465 ShouldBeEmitted = false; 466 467 if (!ShouldBeEmitted) 468 return; 469 470 #define HANDLE_OPERAND(class) \ 471 handleOperand(false, \ 472 operandIndex, \ 473 physicalOperandIndex, \ 474 numPhysicalOperands, \ 475 operandMapping, \ 476 class##EncodingFromString); 477 478 #define HANDLE_OPTIONAL(class) \ 479 handleOperand(true, \ 480 operandIndex, \ 481 physicalOperandIndex, \ 482 numPhysicalOperands, \ 483 operandMapping, \ 484 class##EncodingFromString); 485 486 // operandIndex should always be < numOperands 487 operandIndex = 0; 488 // physicalOperandIndex should always be < numPhysicalOperands 489 unsigned physicalOperandIndex = 0; 490 491 switch (Form) { 492 case X86Local::RawFrm: 493 // Operand 1 (optional) is an address or immediate. 494 // Operand 2 (optional) is an immediate. 495 assert(numPhysicalOperands <= 2 && 496 "Unexpected number of operands for RawFrm"); 497 HANDLE_OPTIONAL(relocation) 498 HANDLE_OPTIONAL(immediate) 499 break; 500 case X86Local::AddRegFrm: 501 // Operand 1 is added to the opcode. 502 // Operand 2 (optional) is an address. 503 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 504 "Unexpected number of operands for AddRegFrm"); 505 HANDLE_OPERAND(opcodeModifier) 506 HANDLE_OPTIONAL(relocation) 507 break; 508 case X86Local::MRMDestReg: 509 // Operand 1 is a register operand in the R/M field. 510 // Operand 2 is a register operand in the Reg/Opcode field. 511 // Operand 3 (optional) is an immediate. 512 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 513 "Unexpected number of operands for MRMDestRegFrm"); 514 HANDLE_OPERAND(rmRegister) 515 HANDLE_OPERAND(roRegister) 516 HANDLE_OPTIONAL(immediate) 517 break; 518 case X86Local::MRMDestMem: 519 // Operand 1 is a memory operand (possibly SIB-extended) 520 // Operand 2 is a register operand in the Reg/Opcode field. 521 // Operand 3 (optional) is an immediate. 522 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 523 "Unexpected number of operands for MRMDestMemFrm"); 524 HANDLE_OPERAND(memory) 525 HANDLE_OPERAND(roRegister) 526 HANDLE_OPTIONAL(immediate) 527 break; 528 case X86Local::MRMSrcReg: 529 // Operand 1 is a register operand in the Reg/Opcode field. 530 // Operand 2 is a register operand in the R/M field. 531 // Operand 3 (optional) is an immediate. 532 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 533 "Unexpected number of operands for MRMSrcRegFrm"); 534 HANDLE_OPERAND(roRegister) 535 HANDLE_OPERAND(rmRegister) 536 537 if (HasVEX_4VPrefix) 538 // FIXME: In AVX, the register below becomes the one encoded 539 // in ModRMVEX and the one above the one in the VEX.VVVV field 540 HANDLE_OPTIONAL(rmRegister) 541 else 542 HANDLE_OPTIONAL(immediate) 543 break; 544 case X86Local::MRMSrcMem: 545 // Operand 1 is a register operand in the Reg/Opcode field. 546 // Operand 2 is a memory operand (possibly SIB-extended) 547 // Operand 3 (optional) is an immediate. 548 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 549 "Unexpected number of operands for MRMSrcMemFrm"); 550 HANDLE_OPERAND(roRegister) 551 552 if (HasVEX_4VPrefix) 553 // FIXME: In AVX, the register below becomes the one encoded 554 // in ModRMVEX and the one above the one in the VEX.VVVV field 555 HANDLE_OPTIONAL(rmRegister) 556 557 HANDLE_OPERAND(memory) 558 HANDLE_OPTIONAL(immediate) 559 break; 560 case X86Local::MRM0r: 561 case X86Local::MRM1r: 562 case X86Local::MRM2r: 563 case X86Local::MRM3r: 564 case X86Local::MRM4r: 565 case X86Local::MRM5r: 566 case X86Local::MRM6r: 567 case X86Local::MRM7r: 568 // Operand 1 is a register operand in the R/M field. 569 // Operand 2 (optional) is an immediate or relocation. 570 assert(numPhysicalOperands <= 2 && 571 "Unexpected number of operands for MRMnRFrm"); 572 HANDLE_OPTIONAL(rmRegister) 573 HANDLE_OPTIONAL(relocation) 574 break; 575 case X86Local::MRM0m: 576 case X86Local::MRM1m: 577 case X86Local::MRM2m: 578 case X86Local::MRM3m: 579 case X86Local::MRM4m: 580 case X86Local::MRM5m: 581 case X86Local::MRM6m: 582 case X86Local::MRM7m: 583 // Operand 1 is a memory operand (possibly SIB-extended) 584 // Operand 2 (optional) is an immediate or relocation. 585 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 586 "Unexpected number of operands for MRMnMFrm"); 587 HANDLE_OPERAND(memory) 588 HANDLE_OPTIONAL(relocation) 589 break; 590 case X86Local::RawFrmImm8: 591 // operand 1 is a 16-bit immediate 592 // operand 2 is an 8-bit immediate 593 assert(numPhysicalOperands == 2 && 594 "Unexpected number of operands for X86Local::RawFrmImm8"); 595 HANDLE_OPERAND(immediate) 596 HANDLE_OPERAND(immediate) 597 break; 598 case X86Local::RawFrmImm16: 599 // operand 1 is a 16-bit immediate 600 // operand 2 is a 16-bit immediate 601 HANDLE_OPERAND(immediate) 602 HANDLE_OPERAND(immediate) 603 break; 604 case X86Local::MRMInitReg: 605 // Ignored. 606 break; 607 } 608 609 #undef HANDLE_OPERAND 610 #undef HANDLE_OPTIONAL 611 } 612 613 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 614 // Special cases where the LLVM tables are not complete 615 616 #define MAP(from, to) \ 617 case X86Local::MRM_##from: \ 618 filter = new ExactFilter(0x##from); \ 619 break; 620 621 OpcodeType opcodeType = (OpcodeType)-1; 622 623 ModRMFilter* filter = NULL; 624 uint8_t opcodeToSet = 0; 625 626 switch (Prefix) { 627 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f 628 case X86Local::XD: 629 case X86Local::XS: 630 case X86Local::TB: 631 opcodeType = TWOBYTE; 632 633 switch (Opcode) { 634 default: 635 if (needsModRMForDecode(Form)) 636 filter = new ModFilter(isRegFormat(Form)); 637 else 638 filter = new DumbFilter(); 639 break; 640 #define EXTENSION_TABLE(n) case 0x##n: 641 TWO_BYTE_EXTENSION_TABLES 642 #undef EXTENSION_TABLE 643 switch (Form) { 644 default: 645 llvm_unreachable("Unhandled two-byte extended opcode"); 646 case X86Local::MRM0r: 647 case X86Local::MRM1r: 648 case X86Local::MRM2r: 649 case X86Local::MRM3r: 650 case X86Local::MRM4r: 651 case X86Local::MRM5r: 652 case X86Local::MRM6r: 653 case X86Local::MRM7r: 654 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 655 break; 656 case X86Local::MRM0m: 657 case X86Local::MRM1m: 658 case X86Local::MRM2m: 659 case X86Local::MRM3m: 660 case X86Local::MRM4m: 661 case X86Local::MRM5m: 662 case X86Local::MRM6m: 663 case X86Local::MRM7m: 664 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 665 break; 666 MRM_MAPPING 667 } // switch (Form) 668 break; 669 } // switch (Opcode) 670 opcodeToSet = Opcode; 671 break; 672 case X86Local::T8: 673 opcodeType = THREEBYTE_38; 674 if (needsModRMForDecode(Form)) 675 filter = new ModFilter(isRegFormat(Form)); 676 else 677 filter = new DumbFilter(); 678 opcodeToSet = Opcode; 679 break; 680 case X86Local::P_TA: 681 opcodeType = THREEBYTE_3A; 682 if (needsModRMForDecode(Form)) 683 filter = new ModFilter(isRegFormat(Form)); 684 else 685 filter = new DumbFilter(); 686 opcodeToSet = Opcode; 687 break; 688 case X86Local::D8: 689 case X86Local::D9: 690 case X86Local::DA: 691 case X86Local::DB: 692 case X86Local::DC: 693 case X86Local::DD: 694 case X86Local::DE: 695 case X86Local::DF: 696 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); 697 opcodeType = ONEBYTE; 698 if (Form == X86Local::AddRegFrm) { 699 Spec->modifierType = MODIFIER_MODRM; 700 Spec->modifierBase = Opcode; 701 filter = new AddRegEscapeFilter(Opcode); 702 } else { 703 filter = new EscapeFilter(true, Opcode); 704 } 705 opcodeToSet = 0xd8 + (Prefix - X86Local::D8); 706 break; 707 default: 708 opcodeType = ONEBYTE; 709 switch (Opcode) { 710 #define EXTENSION_TABLE(n) case 0x##n: 711 ONE_BYTE_EXTENSION_TABLES 712 #undef EXTENSION_TABLE 713 switch (Form) { 714 default: 715 llvm_unreachable("Fell through the cracks of a single-byte " 716 "extended opcode"); 717 case X86Local::MRM0r: 718 case X86Local::MRM1r: 719 case X86Local::MRM2r: 720 case X86Local::MRM3r: 721 case X86Local::MRM4r: 722 case X86Local::MRM5r: 723 case X86Local::MRM6r: 724 case X86Local::MRM7r: 725 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 726 break; 727 case X86Local::MRM0m: 728 case X86Local::MRM1m: 729 case X86Local::MRM2m: 730 case X86Local::MRM3m: 731 case X86Local::MRM4m: 732 case X86Local::MRM5m: 733 case X86Local::MRM6m: 734 case X86Local::MRM7m: 735 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 736 break; 737 MRM_MAPPING 738 } // switch (Form) 739 break; 740 case 0xd8: 741 case 0xd9: 742 case 0xda: 743 case 0xdb: 744 case 0xdc: 745 case 0xdd: 746 case 0xde: 747 case 0xdf: 748 filter = new EscapeFilter(false, Form - X86Local::MRM0m); 749 break; 750 default: 751 if (needsModRMForDecode(Form)) 752 filter = new ModFilter(isRegFormat(Form)); 753 else 754 filter = new DumbFilter(); 755 break; 756 } // switch (Opcode) 757 opcodeToSet = Opcode; 758 } // switch (Prefix) 759 760 assert(opcodeType != (OpcodeType)-1 && 761 "Opcode type not set"); 762 assert(filter && "Filter not set"); 763 764 if (Form == X86Local::AddRegFrm) { 765 if(Spec->modifierType != MODIFIER_MODRM) { 766 assert(opcodeToSet < 0xf9 && 767 "Not enough room for all ADDREG_FRM operands"); 768 769 uint8_t currentOpcode; 770 771 for (currentOpcode = opcodeToSet; 772 currentOpcode < opcodeToSet + 8; 773 ++currentOpcode) 774 tables.setTableFields(opcodeType, 775 insnContext(), 776 currentOpcode, 777 *filter, 778 UID); 779 780 Spec->modifierType = MODIFIER_OPCODE; 781 Spec->modifierBase = opcodeToSet; 782 } else { 783 // modifierBase was set where MODIFIER_MODRM was set 784 tables.setTableFields(opcodeType, 785 insnContext(), 786 opcodeToSet, 787 *filter, 788 UID); 789 } 790 } else { 791 tables.setTableFields(opcodeType, 792 insnContext(), 793 opcodeToSet, 794 *filter, 795 UID); 796 797 Spec->modifierType = MODIFIER_NONE; 798 Spec->modifierBase = opcodeToSet; 799 } 800 801 delete filter; 802 803 #undef MAP 804 } 805 806 #define TYPE(str, type) if (s == str) return type; 807 OperandType RecognizableInstr::typeFromString(const std::string &s, 808 bool isSSE, 809 bool hasREX_WPrefix, 810 bool hasOpSizePrefix) { 811 if (isSSE) { 812 // For SSE instructions, we ignore the OpSize prefix and force operand 813 // sizes. 814 TYPE("GR16", TYPE_R16) 815 TYPE("GR32", TYPE_R32) 816 TYPE("GR64", TYPE_R64) 817 } 818 if(hasREX_WPrefix) { 819 // For instructions with a REX_W prefix, a declared 32-bit register encoding 820 // is special. 821 TYPE("GR32", TYPE_R32) 822 } 823 if(!hasOpSizePrefix) { 824 // For instructions without an OpSize prefix, a declared 16-bit register or 825 // immediate encoding is special. 826 TYPE("GR16", TYPE_R16) 827 TYPE("i16imm", TYPE_IMM16) 828 } 829 TYPE("i16mem", TYPE_Mv) 830 TYPE("i16imm", TYPE_IMMv) 831 TYPE("i16i8imm", TYPE_IMMv) 832 TYPE("GR16", TYPE_Rv) 833 TYPE("i32mem", TYPE_Mv) 834 TYPE("i32imm", TYPE_IMMv) 835 TYPE("i32i8imm", TYPE_IMM32) 836 TYPE("GR32", TYPE_Rv) 837 TYPE("i64mem", TYPE_Mv) 838 TYPE("i64i32imm", TYPE_IMM64) 839 TYPE("i64i8imm", TYPE_IMM64) 840 TYPE("GR64", TYPE_R64) 841 TYPE("i8mem", TYPE_M8) 842 TYPE("i8imm", TYPE_IMM8) 843 TYPE("GR8", TYPE_R8) 844 TYPE("VR128", TYPE_XMM128) 845 TYPE("f128mem", TYPE_M128) 846 TYPE("f256mem", TYPE_M256) 847 TYPE("FR64", TYPE_XMM64) 848 TYPE("f64mem", TYPE_M64FP) 849 TYPE("sdmem", TYPE_M64FP) 850 TYPE("FR32", TYPE_XMM32) 851 TYPE("f32mem", TYPE_M32FP) 852 TYPE("ssmem", TYPE_M32FP) 853 TYPE("RST", TYPE_ST) 854 TYPE("i128mem", TYPE_M128) 855 TYPE("i64i32imm_pcrel", TYPE_REL64) 856 TYPE("i16imm_pcrel", TYPE_REL16) 857 TYPE("i32imm_pcrel", TYPE_REL32) 858 TYPE("SSECC", TYPE_IMM3) 859 TYPE("brtarget", TYPE_RELv) 860 TYPE("uncondbrtarget", TYPE_RELv) 861 TYPE("brtarget8", TYPE_REL8) 862 TYPE("f80mem", TYPE_M80FP) 863 TYPE("lea32mem", TYPE_LEA) 864 TYPE("lea64_32mem", TYPE_LEA) 865 TYPE("lea64mem", TYPE_LEA) 866 TYPE("VR64", TYPE_MM64) 867 TYPE("i64imm", TYPE_IMMv) 868 TYPE("opaque32mem", TYPE_M1616) 869 TYPE("opaque48mem", TYPE_M1632) 870 TYPE("opaque80mem", TYPE_M1664) 871 TYPE("opaque512mem", TYPE_M512) 872 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 873 TYPE("DEBUG_REG", TYPE_DEBUGREG) 874 TYPE("CONTROL_REG", TYPE_CONTROLREG) 875 TYPE("offset8", TYPE_MOFFS8) 876 TYPE("offset16", TYPE_MOFFS16) 877 TYPE("offset32", TYPE_MOFFS32) 878 TYPE("offset64", TYPE_MOFFS64) 879 errs() << "Unhandled type string " << s << "\n"; 880 llvm_unreachable("Unhandled type string"); 881 } 882 #undef TYPE 883 884 #define ENCODING(str, encoding) if (s == str) return encoding; 885 OperandEncoding RecognizableInstr::immediateEncodingFromString 886 (const std::string &s, 887 bool hasOpSizePrefix) { 888 if(!hasOpSizePrefix) { 889 // For instructions without an OpSize prefix, a declared 16-bit register or 890 // immediate encoding is special. 891 ENCODING("i16imm", ENCODING_IW) 892 } 893 ENCODING("i32i8imm", ENCODING_IB) 894 ENCODING("SSECC", ENCODING_IB) 895 ENCODING("i16imm", ENCODING_Iv) 896 ENCODING("i16i8imm", ENCODING_IB) 897 ENCODING("i32imm", ENCODING_Iv) 898 ENCODING("i64i32imm", ENCODING_ID) 899 ENCODING("i64i8imm", ENCODING_IB) 900 ENCODING("i8imm", ENCODING_IB) 901 errs() << "Unhandled immediate encoding " << s << "\n"; 902 llvm_unreachable("Unhandled immediate encoding"); 903 } 904 905 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString 906 (const std::string &s, 907 bool hasOpSizePrefix) { 908 ENCODING("GR16", ENCODING_RM) 909 ENCODING("GR32", ENCODING_RM) 910 ENCODING("GR64", ENCODING_RM) 911 ENCODING("GR8", ENCODING_RM) 912 ENCODING("VR128", ENCODING_RM) 913 ENCODING("FR64", ENCODING_RM) 914 ENCODING("FR32", ENCODING_RM) 915 ENCODING("VR64", ENCODING_RM) 916 errs() << "Unhandled R/M register encoding " << s << "\n"; 917 llvm_unreachable("Unhandled R/M register encoding"); 918 } 919 920 OperandEncoding RecognizableInstr::roRegisterEncodingFromString 921 (const std::string &s, 922 bool hasOpSizePrefix) { 923 ENCODING("GR16", ENCODING_REG) 924 ENCODING("GR32", ENCODING_REG) 925 ENCODING("GR64", ENCODING_REG) 926 ENCODING("GR8", ENCODING_REG) 927 ENCODING("VR128", ENCODING_REG) 928 ENCODING("FR64", ENCODING_REG) 929 ENCODING("FR32", ENCODING_REG) 930 ENCODING("VR64", ENCODING_REG) 931 ENCODING("SEGMENT_REG", ENCODING_REG) 932 ENCODING("DEBUG_REG", ENCODING_REG) 933 ENCODING("CONTROL_REG", ENCODING_REG) 934 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 935 llvm_unreachable("Unhandled reg/opcode register encoding"); 936 } 937 938 OperandEncoding RecognizableInstr::memoryEncodingFromString 939 (const std::string &s, 940 bool hasOpSizePrefix) { 941 ENCODING("i16mem", ENCODING_RM) 942 ENCODING("i32mem", ENCODING_RM) 943 ENCODING("i64mem", ENCODING_RM) 944 ENCODING("i8mem", ENCODING_RM) 945 ENCODING("ssmem", ENCODING_RM) 946 ENCODING("sdmem", ENCODING_RM) 947 ENCODING("f128mem", ENCODING_RM) 948 ENCODING("f256mem", ENCODING_RM) 949 ENCODING("f64mem", ENCODING_RM) 950 ENCODING("f32mem", ENCODING_RM) 951 ENCODING("i128mem", ENCODING_RM) 952 ENCODING("f80mem", ENCODING_RM) 953 ENCODING("lea32mem", ENCODING_RM) 954 ENCODING("lea64_32mem", ENCODING_RM) 955 ENCODING("lea64mem", ENCODING_RM) 956 ENCODING("opaque32mem", ENCODING_RM) 957 ENCODING("opaque48mem", ENCODING_RM) 958 ENCODING("opaque80mem", ENCODING_RM) 959 ENCODING("opaque512mem", ENCODING_RM) 960 errs() << "Unhandled memory encoding " << s << "\n"; 961 llvm_unreachable("Unhandled memory encoding"); 962 } 963 964 OperandEncoding RecognizableInstr::relocationEncodingFromString 965 (const std::string &s, 966 bool hasOpSizePrefix) { 967 if(!hasOpSizePrefix) { 968 // For instructions without an OpSize prefix, a declared 16-bit register or 969 // immediate encoding is special. 970 ENCODING("i16imm", ENCODING_IW) 971 } 972 ENCODING("i16imm", ENCODING_Iv) 973 ENCODING("i16i8imm", ENCODING_IB) 974 ENCODING("i32imm", ENCODING_Iv) 975 ENCODING("i32i8imm", ENCODING_IB) 976 ENCODING("i64i32imm", ENCODING_ID) 977 ENCODING("i64i8imm", ENCODING_IB) 978 ENCODING("i8imm", ENCODING_IB) 979 ENCODING("i64i32imm_pcrel", ENCODING_ID) 980 ENCODING("i16imm_pcrel", ENCODING_IW) 981 ENCODING("i32imm_pcrel", ENCODING_ID) 982 ENCODING("brtarget", ENCODING_Iv) 983 ENCODING("brtarget8", ENCODING_IB) 984 ENCODING("i64imm", ENCODING_IO) 985 ENCODING("offset8", ENCODING_Ia) 986 ENCODING("offset16", ENCODING_Ia) 987 ENCODING("offset32", ENCODING_Ia) 988 ENCODING("offset64", ENCODING_Ia) 989 errs() << "Unhandled relocation encoding " << s << "\n"; 990 llvm_unreachable("Unhandled relocation encoding"); 991 } 992 993 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString 994 (const std::string &s, 995 bool hasOpSizePrefix) { 996 ENCODING("RST", ENCODING_I) 997 ENCODING("GR32", ENCODING_Rv) 998 ENCODING("GR64", ENCODING_RO) 999 ENCODING("GR16", ENCODING_Rv) 1000 ENCODING("GR8", ENCODING_RB) 1001 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1002 llvm_unreachable("Unhandled opcode modifier encoding"); 1003 } 1004 #undef ENCODING 1005