1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 25 #define MRM_MAPPING \ 26 MAP(C0, 64) \ 27 MAP(C1, 65) \ 28 MAP(C2, 66) \ 29 MAP(C3, 67) \ 30 MAP(C4, 68) \ 31 MAP(C5, 69) \ 32 MAP(C6, 70) \ 33 MAP(C7, 71) \ 34 MAP(C8, 72) \ 35 MAP(C9, 73) \ 36 MAP(CA, 74) \ 37 MAP(CB, 75) \ 38 MAP(CC, 76) \ 39 MAP(CD, 77) \ 40 MAP(CE, 78) \ 41 MAP(CF, 79) \ 42 MAP(D0, 80) \ 43 MAP(D1, 81) \ 44 MAP(D2, 82) \ 45 MAP(D3, 83) \ 46 MAP(D4, 84) \ 47 MAP(D5, 85) \ 48 MAP(D6, 86) \ 49 MAP(D7, 87) \ 50 MAP(D8, 88) \ 51 MAP(D9, 89) \ 52 MAP(DA, 90) \ 53 MAP(DB, 91) \ 54 MAP(DC, 92) \ 55 MAP(DD, 93) \ 56 MAP(DE, 94) \ 57 MAP(DF, 95) \ 58 MAP(E0, 96) \ 59 MAP(E1, 97) \ 60 MAP(E2, 98) \ 61 MAP(E3, 99) \ 62 MAP(E4, 100) \ 63 MAP(E5, 101) \ 64 MAP(E6, 102) \ 65 MAP(E7, 103) \ 66 MAP(E8, 104) \ 67 MAP(E9, 105) \ 68 MAP(EA, 106) \ 69 MAP(EB, 107) \ 70 MAP(EC, 108) \ 71 MAP(ED, 109) \ 72 MAP(EE, 110) \ 73 MAP(EF, 111) \ 74 MAP(F0, 112) \ 75 MAP(F1, 113) \ 76 MAP(F2, 114) \ 77 MAP(F3, 115) \ 78 MAP(F4, 116) \ 79 MAP(F5, 117) \ 80 MAP(F6, 118) \ 81 MAP(F7, 119) \ 82 MAP(F8, 120) \ 83 MAP(F9, 121) \ 84 MAP(FA, 122) \ 85 MAP(FB, 123) \ 86 MAP(FC, 124) \ 87 MAP(FD, 125) \ 88 MAP(FE, 126) \ 89 MAP(FF, 127) 90 91 // A clone of X86 since we can't depend on something that is generated. 92 namespace X86Local { 93 enum { 94 Pseudo = 0, 95 RawFrm = 1, 96 AddRegFrm = 2, 97 RawFrmMemOffs = 3, 98 RawFrmSrc = 4, 99 RawFrmDst = 5, 100 RawFrmDstSrc = 6, 101 RawFrmImm8 = 7, 102 RawFrmImm16 = 8, 103 MRMDestMem = 32, 104 MRMSrcMem = 33, 105 MRMSrcMem4VOp3 = 34, 106 MRMSrcMemOp4 = 35, 107 MRMXm = 39, 108 MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, 109 MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, 110 MRMDestReg = 48, 111 MRMSrcReg = 49, 112 MRMSrcReg4VOp3 = 50, 113 MRMSrcRegOp4 = 51, 114 MRMXr = 55, 115 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, 116 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, 117 #define MAP(from, to) MRM_##from = to, 118 MRM_MAPPING 119 #undef MAP 120 }; 121 122 enum { 123 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 124 }; 125 126 enum { 127 PS = 1, PD = 2, XS = 3, XD = 4 128 }; 129 130 enum { 131 VEX = 1, XOP = 2, EVEX = 3 132 }; 133 134 enum { 135 OpSize16 = 1, OpSize32 = 2 136 }; 137 138 enum { 139 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 140 }; 141 } 142 143 using namespace X86Disassembler; 144 145 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 146 /// Useful for switch statements and the like. 147 /// 148 /// @param init - A reference to the BitsInit to be decoded. 149 /// @return - The field, with the first bit in the BitsInit as the lowest 150 /// order bit. 151 static uint8_t byteFromBitsInit(BitsInit &init) { 152 int width = init.getNumBits(); 153 154 assert(width <= 8 && "Field is too large for uint8_t!"); 155 156 int index; 157 uint8_t mask = 0x01; 158 159 uint8_t ret = 0; 160 161 for (index = 0; index < width; index++) { 162 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 163 ret |= mask; 164 165 mask <<= 1; 166 } 167 168 return ret; 169 } 170 171 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 172 /// name of the field. 173 /// 174 /// @param rec - The record from which to extract the value. 175 /// @param name - The name of the field in the record. 176 /// @return - The field, as translated by byteFromBitsInit(). 177 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 178 BitsInit* bits = rec->getValueAsBitsInit(name); 179 return byteFromBitsInit(*bits); 180 } 181 182 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 183 const CodeGenInstruction &insn, 184 InstrUID uid) { 185 UID = uid; 186 187 Rec = insn.TheDef; 188 Name = Rec->getName(); 189 Spec = &tables.specForUID(UID); 190 191 if (!Rec->isSubClassOf("X86Inst")) { 192 ShouldBeEmitted = false; 193 return; 194 } 195 196 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 197 OpMap = byteFromRec(Rec, "OpMapBits"); 198 Opcode = byteFromRec(Rec, "Opcode"); 199 Form = byteFromRec(Rec, "FormBits"); 200 Encoding = byteFromRec(Rec, "OpEncBits"); 201 202 OpSize = byteFromRec(Rec, "OpSizeBits"); 203 AdSize = byteFromRec(Rec, "AdSizeBits"); 204 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 205 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 206 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 207 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 208 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 209 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 210 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 211 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 212 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 213 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 214 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 215 216 Name = Rec->getName(); 217 218 Operands = &insn.Operands.OperandList; 219 220 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 221 222 // Check for 64-bit inst which does not require REX 223 Is32Bit = false; 224 Is64Bit = false; 225 // FIXME: Is there some better way to check for In64BitMode? 226 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 227 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 228 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 229 Predicates[i]->getName().find("In32Bit") != Name.npos) { 230 Is32Bit = true; 231 break; 232 } 233 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 234 Is64Bit = true; 235 break; 236 } 237 } 238 239 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 240 ShouldBeEmitted = false; 241 return; 242 } 243 244 // Special case since there is no attribute class for 64-bit and VEX 245 if (Name == "VMASKMOVDQU64") { 246 ShouldBeEmitted = false; 247 return; 248 } 249 250 ShouldBeEmitted = true; 251 } 252 253 void RecognizableInstr::processInstr(DisassemblerTables &tables, 254 const CodeGenInstruction &insn, 255 InstrUID uid) 256 { 257 // Ignore "asm parser only" instructions. 258 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 259 return; 260 261 RecognizableInstr recogInstr(tables, insn, uid); 262 263 if (recogInstr.shouldBeEmitted()) { 264 recogInstr.emitInstructionSpecifier(); 265 recogInstr.emitDecodePath(tables); 266 } 267 } 268 269 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 270 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 271 (HasEVEX_KZ ? n##_KZ : \ 272 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 273 274 InstructionContext RecognizableInstr::insnContext() const { 275 InstructionContext insnContext; 276 277 if (Encoding == X86Local::EVEX) { 278 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 279 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 280 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 281 } 282 // VEX_L & VEX_W 283 if (HasVEX_LPrefix && HasVEX_WPrefix) { 284 if (OpPrefix == X86Local::PD) 285 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 286 else if (OpPrefix == X86Local::XS) 287 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 288 else if (OpPrefix == X86Local::XD) 289 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 290 else if (OpPrefix == X86Local::PS) 291 insnContext = EVEX_KB(IC_EVEX_L_W); 292 else { 293 errs() << "Instruction does not use a prefix: " << Name << "\n"; 294 llvm_unreachable("Invalid prefix"); 295 } 296 } else if (HasVEX_LPrefix) { 297 // VEX_L 298 if (OpPrefix == X86Local::PD) 299 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 300 else if (OpPrefix == X86Local::XS) 301 insnContext = EVEX_KB(IC_EVEX_L_XS); 302 else if (OpPrefix == X86Local::XD) 303 insnContext = EVEX_KB(IC_EVEX_L_XD); 304 else if (OpPrefix == X86Local::PS) 305 insnContext = EVEX_KB(IC_EVEX_L); 306 else { 307 errs() << "Instruction does not use a prefix: " << Name << "\n"; 308 llvm_unreachable("Invalid prefix"); 309 } 310 } 311 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { 312 // EVEX_L2 & VEX_W 313 if (OpPrefix == X86Local::PD) 314 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 315 else if (OpPrefix == X86Local::XS) 316 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 317 else if (OpPrefix == X86Local::XD) 318 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 319 else if (OpPrefix == X86Local::PS) 320 insnContext = EVEX_KB(IC_EVEX_L2_W); 321 else { 322 errs() << "Instruction does not use a prefix: " << Name << "\n"; 323 llvm_unreachable("Invalid prefix"); 324 } 325 } else if (HasEVEX_L2Prefix) { 326 // EVEX_L2 327 if (OpPrefix == X86Local::PD) 328 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 329 else if (OpPrefix == X86Local::XD) 330 insnContext = EVEX_KB(IC_EVEX_L2_XD); 331 else if (OpPrefix == X86Local::XS) 332 insnContext = EVEX_KB(IC_EVEX_L2_XS); 333 else if (OpPrefix == X86Local::PS) 334 insnContext = EVEX_KB(IC_EVEX_L2); 335 else { 336 errs() << "Instruction does not use a prefix: " << Name << "\n"; 337 llvm_unreachable("Invalid prefix"); 338 } 339 } 340 else if (HasVEX_WPrefix) { 341 // VEX_W 342 if (OpPrefix == X86Local::PD) 343 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 344 else if (OpPrefix == X86Local::XS) 345 insnContext = EVEX_KB(IC_EVEX_W_XS); 346 else if (OpPrefix == X86Local::XD) 347 insnContext = EVEX_KB(IC_EVEX_W_XD); 348 else if (OpPrefix == X86Local::PS) 349 insnContext = EVEX_KB(IC_EVEX_W); 350 else { 351 errs() << "Instruction does not use a prefix: " << Name << "\n"; 352 llvm_unreachable("Invalid prefix"); 353 } 354 } 355 // No L, no W 356 else if (OpPrefix == X86Local::PD) 357 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 358 else if (OpPrefix == X86Local::XD) 359 insnContext = EVEX_KB(IC_EVEX_XD); 360 else if (OpPrefix == X86Local::XS) 361 insnContext = EVEX_KB(IC_EVEX_XS); 362 else 363 insnContext = EVEX_KB(IC_EVEX); 364 /// eof EVEX 365 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 366 if (HasVEX_LPrefix && HasVEX_WPrefix) { 367 if (OpPrefix == X86Local::PD) 368 insnContext = IC_VEX_L_W_OPSIZE; 369 else if (OpPrefix == X86Local::XS) 370 insnContext = IC_VEX_L_W_XS; 371 else if (OpPrefix == X86Local::XD) 372 insnContext = IC_VEX_L_W_XD; 373 else if (OpPrefix == X86Local::PS) 374 insnContext = IC_VEX_L_W; 375 else { 376 errs() << "Instruction does not use a prefix: " << Name << "\n"; 377 llvm_unreachable("Invalid prefix"); 378 } 379 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 380 insnContext = IC_VEX_L_OPSIZE; 381 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix) 382 insnContext = IC_VEX_W_OPSIZE; 383 else if (OpPrefix == X86Local::PD) 384 insnContext = IC_VEX_OPSIZE; 385 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 386 insnContext = IC_VEX_L_XS; 387 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 388 insnContext = IC_VEX_L_XD; 389 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS) 390 insnContext = IC_VEX_W_XS; 391 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD) 392 insnContext = IC_VEX_W_XD; 393 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS) 394 insnContext = IC_VEX_W; 395 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 396 insnContext = IC_VEX_L; 397 else if (OpPrefix == X86Local::XD) 398 insnContext = IC_VEX_XD; 399 else if (OpPrefix == X86Local::XS) 400 insnContext = IC_VEX_XS; 401 else if (OpPrefix == X86Local::PS) 402 insnContext = IC_VEX; 403 else { 404 errs() << "Instruction does not use a prefix: " << Name << "\n"; 405 llvm_unreachable("Invalid prefix"); 406 } 407 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 408 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 409 insnContext = IC_64BIT_REXW_OPSIZE; 410 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 411 insnContext = IC_64BIT_REXW_ADSIZE; 412 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 413 insnContext = IC_64BIT_XD_OPSIZE; 414 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 415 insnContext = IC_64BIT_XS_OPSIZE; 416 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 417 insnContext = IC_64BIT_OPSIZE_ADSIZE; 418 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 419 insnContext = IC_64BIT_OPSIZE; 420 else if (AdSize == X86Local::AdSize32) 421 insnContext = IC_64BIT_ADSIZE; 422 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 423 insnContext = IC_64BIT_REXW_XS; 424 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 425 insnContext = IC_64BIT_REXW_XD; 426 else if (OpPrefix == X86Local::XD) 427 insnContext = IC_64BIT_XD; 428 else if (OpPrefix == X86Local::XS) 429 insnContext = IC_64BIT_XS; 430 else if (HasREX_WPrefix) 431 insnContext = IC_64BIT_REXW; 432 else 433 insnContext = IC_64BIT; 434 } else { 435 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 436 insnContext = IC_XD_OPSIZE; 437 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 438 insnContext = IC_XS_OPSIZE; 439 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 440 insnContext = IC_OPSIZE_ADSIZE; 441 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 442 insnContext = IC_OPSIZE; 443 else if (AdSize == X86Local::AdSize16) 444 insnContext = IC_ADSIZE; 445 else if (OpPrefix == X86Local::XD) 446 insnContext = IC_XD; 447 else if (OpPrefix == X86Local::XS) 448 insnContext = IC_XS; 449 else 450 insnContext = IC; 451 } 452 453 return insnContext; 454 } 455 456 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 457 // The scaling factor for AVX512 compressed displacement encoding is an 458 // instruction attribute. Adjust the ModRM encoding type to include the 459 // scale for compressed displacement. 460 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 461 return; 462 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 463 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 464 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 465 "Invalid CDisp scaling"); 466 } 467 468 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 469 unsigned &physicalOperandIndex, 470 unsigned numPhysicalOperands, 471 const unsigned *operandMapping, 472 OperandEncoding (*encodingFromString) 473 (const std::string&, 474 uint8_t OpSize)) { 475 if (optional) { 476 if (physicalOperandIndex >= numPhysicalOperands) 477 return; 478 } else { 479 assert(physicalOperandIndex < numPhysicalOperands); 480 } 481 482 while (operandMapping[operandIndex] != operandIndex) { 483 Spec->operands[operandIndex].encoding = ENCODING_DUP; 484 Spec->operands[operandIndex].type = 485 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 486 ++operandIndex; 487 } 488 489 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 490 491 OperandEncoding encoding = encodingFromString(typeName, OpSize); 492 // Adjust the encoding type for an operand based on the instruction. 493 adjustOperandEncoding(encoding); 494 Spec->operands[operandIndex].encoding = encoding; 495 Spec->operands[operandIndex].type = typeFromString(typeName, 496 HasREX_WPrefix, OpSize); 497 498 ++operandIndex; 499 ++physicalOperandIndex; 500 } 501 502 void RecognizableInstr::emitInstructionSpecifier() { 503 Spec->name = Name; 504 505 Spec->insnContext = insnContext(); 506 507 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 508 509 unsigned numOperands = OperandList.size(); 510 unsigned numPhysicalOperands = 0; 511 512 // operandMapping maps from operands in OperandList to their originals. 513 // If operandMapping[i] != i, then the entry is a duplicate. 514 unsigned operandMapping[X86_MAX_OPERANDS]; 515 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 516 517 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 518 if (!OperandList[operandIndex].Constraints.empty()) { 519 const CGIOperandList::ConstraintInfo &Constraint = 520 OperandList[operandIndex].Constraints[0]; 521 if (Constraint.isTied()) { 522 operandMapping[operandIndex] = operandIndex; 523 operandMapping[Constraint.getTiedOperand()] = operandIndex; 524 } else { 525 ++numPhysicalOperands; 526 operandMapping[operandIndex] = operandIndex; 527 } 528 } else { 529 ++numPhysicalOperands; 530 operandMapping[operandIndex] = operandIndex; 531 } 532 } 533 534 #define HANDLE_OPERAND(class) \ 535 handleOperand(false, \ 536 operandIndex, \ 537 physicalOperandIndex, \ 538 numPhysicalOperands, \ 539 operandMapping, \ 540 class##EncodingFromString); 541 542 #define HANDLE_OPTIONAL(class) \ 543 handleOperand(true, \ 544 operandIndex, \ 545 physicalOperandIndex, \ 546 numPhysicalOperands, \ 547 operandMapping, \ 548 class##EncodingFromString); 549 550 // operandIndex should always be < numOperands 551 unsigned operandIndex = 0; 552 // physicalOperandIndex should always be < numPhysicalOperands 553 unsigned physicalOperandIndex = 0; 554 555 #ifndef NDEBUG 556 // Given the set of prefix bits, how many additional operands does the 557 // instruction have? 558 unsigned additionalOperands = 0; 559 if (HasVEX_4V) 560 ++additionalOperands; 561 if (HasEVEX_K) 562 ++additionalOperands; 563 #endif 564 565 switch (Form) { 566 default: llvm_unreachable("Unhandled form"); 567 case X86Local::RawFrmSrc: 568 HANDLE_OPERAND(relocation); 569 return; 570 case X86Local::RawFrmDst: 571 HANDLE_OPERAND(relocation); 572 return; 573 case X86Local::RawFrmDstSrc: 574 HANDLE_OPERAND(relocation); 575 HANDLE_OPERAND(relocation); 576 return; 577 case X86Local::RawFrm: 578 // Operand 1 (optional) is an address or immediate. 579 assert(numPhysicalOperands <= 1 && 580 "Unexpected number of operands for RawFrm"); 581 HANDLE_OPTIONAL(relocation) 582 break; 583 case X86Local::RawFrmMemOffs: 584 // Operand 1 is an address. 585 HANDLE_OPERAND(relocation); 586 break; 587 case X86Local::AddRegFrm: 588 // Operand 1 is added to the opcode. 589 // Operand 2 (optional) is an address. 590 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 591 "Unexpected number of operands for AddRegFrm"); 592 HANDLE_OPERAND(opcodeModifier) 593 HANDLE_OPTIONAL(relocation) 594 break; 595 case X86Local::MRMDestReg: 596 // Operand 1 is a register operand in the R/M field. 597 // - In AVX512 there may be a mask operand here - 598 // Operand 2 is a register operand in the Reg/Opcode field. 599 // - In AVX, there is a register operand in the VEX.vvvv field here - 600 // Operand 3 (optional) is an immediate. 601 assert(numPhysicalOperands >= 2 + additionalOperands && 602 numPhysicalOperands <= 3 + additionalOperands && 603 "Unexpected number of operands for MRMDestRegFrm"); 604 605 HANDLE_OPERAND(rmRegister) 606 if (HasEVEX_K) 607 HANDLE_OPERAND(writemaskRegister) 608 609 if (HasVEX_4V) 610 // FIXME: In AVX, the register below becomes the one encoded 611 // in ModRMVEX and the one above the one in the VEX.VVVV field 612 HANDLE_OPERAND(vvvvRegister) 613 614 HANDLE_OPERAND(roRegister) 615 HANDLE_OPTIONAL(immediate) 616 break; 617 case X86Local::MRMDestMem: 618 // Operand 1 is a memory operand (possibly SIB-extended) 619 // Operand 2 is a register operand in the Reg/Opcode field. 620 // - In AVX, there is a register operand in the VEX.vvvv field here - 621 // Operand 3 (optional) is an immediate. 622 assert(numPhysicalOperands >= 2 + additionalOperands && 623 numPhysicalOperands <= 3 + additionalOperands && 624 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 625 626 HANDLE_OPERAND(memory) 627 628 if (HasEVEX_K) 629 HANDLE_OPERAND(writemaskRegister) 630 631 if (HasVEX_4V) 632 // FIXME: In AVX, the register below becomes the one encoded 633 // in ModRMVEX and the one above the one in the VEX.VVVV field 634 HANDLE_OPERAND(vvvvRegister) 635 636 HANDLE_OPERAND(roRegister) 637 HANDLE_OPTIONAL(immediate) 638 break; 639 case X86Local::MRMSrcReg: 640 // Operand 1 is a register operand in the Reg/Opcode field. 641 // Operand 2 is a register operand in the R/M field. 642 // - In AVX, there is a register operand in the VEX.vvvv field here - 643 // Operand 3 (optional) is an immediate. 644 // Operand 4 (optional) is an immediate. 645 646 assert(numPhysicalOperands >= 2 + additionalOperands && 647 numPhysicalOperands <= 4 + additionalOperands && 648 "Unexpected number of operands for MRMSrcRegFrm"); 649 650 HANDLE_OPERAND(roRegister) 651 652 if (HasEVEX_K) 653 HANDLE_OPERAND(writemaskRegister) 654 655 if (HasVEX_4V) 656 // FIXME: In AVX, the register below becomes the one encoded 657 // in ModRMVEX and the one above the one in the VEX.VVVV field 658 HANDLE_OPERAND(vvvvRegister) 659 660 HANDLE_OPERAND(rmRegister) 661 HANDLE_OPTIONAL(immediate) 662 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 663 HANDLE_OPTIONAL(immediate) 664 break; 665 case X86Local::MRMSrcReg4VOp3: 666 assert(numPhysicalOperands == 3 && 667 "Unexpected number of operands for MRMSrcRegFrm"); 668 HANDLE_OPERAND(roRegister) 669 HANDLE_OPERAND(rmRegister) 670 HANDLE_OPERAND(vvvvRegister) 671 break; 672 case X86Local::MRMSrcRegOp4: 673 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 674 "Unexpected number of operands for MRMSrcRegOp4Frm"); 675 HANDLE_OPERAND(roRegister) 676 HANDLE_OPERAND(vvvvRegister) 677 HANDLE_OPERAND(immediate) // Register in imm[7:4] 678 HANDLE_OPERAND(rmRegister) 679 HANDLE_OPTIONAL(immediate) 680 break; 681 case X86Local::MRMSrcMem: 682 // Operand 1 is a register operand in the Reg/Opcode field. 683 // Operand 2 is a memory operand (possibly SIB-extended) 684 // - In AVX, there is a register operand in the VEX.vvvv field here - 685 // Operand 3 (optional) is an immediate. 686 687 assert(numPhysicalOperands >= 2 + additionalOperands && 688 numPhysicalOperands <= 4 + additionalOperands && 689 "Unexpected number of operands for MRMSrcMemFrm"); 690 691 HANDLE_OPERAND(roRegister) 692 693 if (HasEVEX_K) 694 HANDLE_OPERAND(writemaskRegister) 695 696 if (HasVEX_4V) 697 // FIXME: In AVX, the register below becomes the one encoded 698 // in ModRMVEX and the one above the one in the VEX.VVVV field 699 HANDLE_OPERAND(vvvvRegister) 700 701 HANDLE_OPERAND(memory) 702 HANDLE_OPTIONAL(immediate) 703 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 704 break; 705 case X86Local::MRMSrcMem4VOp3: 706 assert(numPhysicalOperands == 3 && 707 "Unexpected number of operands for MRMSrcMemFrm"); 708 HANDLE_OPERAND(roRegister) 709 HANDLE_OPERAND(memory) 710 HANDLE_OPERAND(vvvvRegister) 711 break; 712 case X86Local::MRMSrcMemOp4: 713 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 714 "Unexpected number of operands for MRMSrcMemOp4Frm"); 715 HANDLE_OPERAND(roRegister) 716 HANDLE_OPERAND(vvvvRegister) 717 HANDLE_OPERAND(immediate) // Register in imm[7:4] 718 HANDLE_OPERAND(memory) 719 HANDLE_OPTIONAL(immediate) 720 break; 721 case X86Local::MRMXr: 722 case X86Local::MRM0r: 723 case X86Local::MRM1r: 724 case X86Local::MRM2r: 725 case X86Local::MRM3r: 726 case X86Local::MRM4r: 727 case X86Local::MRM5r: 728 case X86Local::MRM6r: 729 case X86Local::MRM7r: 730 // Operand 1 is a register operand in the R/M field. 731 // Operand 2 (optional) is an immediate or relocation. 732 // Operand 3 (optional) is an immediate. 733 assert(numPhysicalOperands >= 0 + additionalOperands && 734 numPhysicalOperands <= 3 + additionalOperands && 735 "Unexpected number of operands for MRMnr"); 736 737 if (HasVEX_4V) 738 HANDLE_OPERAND(vvvvRegister) 739 740 if (HasEVEX_K) 741 HANDLE_OPERAND(writemaskRegister) 742 HANDLE_OPTIONAL(rmRegister) 743 HANDLE_OPTIONAL(relocation) 744 HANDLE_OPTIONAL(immediate) 745 break; 746 case X86Local::MRMXm: 747 case X86Local::MRM0m: 748 case X86Local::MRM1m: 749 case X86Local::MRM2m: 750 case X86Local::MRM3m: 751 case X86Local::MRM4m: 752 case X86Local::MRM5m: 753 case X86Local::MRM6m: 754 case X86Local::MRM7m: 755 // Operand 1 is a memory operand (possibly SIB-extended) 756 // Operand 2 (optional) is an immediate or relocation. 757 assert(numPhysicalOperands >= 1 + additionalOperands && 758 numPhysicalOperands <= 2 + additionalOperands && 759 "Unexpected number of operands for MRMnm"); 760 761 if (HasVEX_4V) 762 HANDLE_OPERAND(vvvvRegister) 763 if (HasEVEX_K) 764 HANDLE_OPERAND(writemaskRegister) 765 HANDLE_OPERAND(memory) 766 HANDLE_OPTIONAL(relocation) 767 break; 768 case X86Local::RawFrmImm8: 769 // operand 1 is a 16-bit immediate 770 // operand 2 is an 8-bit immediate 771 assert(numPhysicalOperands == 2 && 772 "Unexpected number of operands for X86Local::RawFrmImm8"); 773 HANDLE_OPERAND(immediate) 774 HANDLE_OPERAND(immediate) 775 break; 776 case X86Local::RawFrmImm16: 777 // operand 1 is a 16-bit immediate 778 // operand 2 is a 16-bit immediate 779 HANDLE_OPERAND(immediate) 780 HANDLE_OPERAND(immediate) 781 break; 782 case X86Local::MRM_F8: 783 if (Opcode == 0xc6) { 784 assert(numPhysicalOperands == 1 && 785 "Unexpected number of operands for X86Local::MRM_F8"); 786 HANDLE_OPERAND(immediate) 787 } else if (Opcode == 0xc7) { 788 assert(numPhysicalOperands == 1 && 789 "Unexpected number of operands for X86Local::MRM_F8"); 790 HANDLE_OPERAND(relocation) 791 } 792 break; 793 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 794 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 795 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 796 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1: 797 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6: 798 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9: 799 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC: 800 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF: 801 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2: 802 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5: 803 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA: 804 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED: 805 case X86Local::MRM_EE: case X86Local::MRM_EF: case X86Local::MRM_F0: 806 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: 807 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: 808 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: 809 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: 810 case X86Local::MRM_FE: case X86Local::MRM_FF: 811 // Ignored. 812 break; 813 } 814 815 #undef HANDLE_OPERAND 816 #undef HANDLE_OPTIONAL 817 } 818 819 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 820 // Special cases where the LLVM tables are not complete 821 822 #define MAP(from, to) \ 823 case X86Local::MRM_##from: 824 825 OpcodeType opcodeType = (OpcodeType)-1; 826 827 ModRMFilter* filter = nullptr; 828 uint8_t opcodeToSet = 0; 829 830 switch (OpMap) { 831 default: llvm_unreachable("Invalid map!"); 832 case X86Local::OB: 833 case X86Local::TB: 834 case X86Local::T8: 835 case X86Local::TA: 836 case X86Local::XOP8: 837 case X86Local::XOP9: 838 case X86Local::XOPA: 839 switch (OpMap) { 840 default: llvm_unreachable("Unexpected map!"); 841 case X86Local::OB: opcodeType = ONEBYTE; break; 842 case X86Local::TB: opcodeType = TWOBYTE; break; 843 case X86Local::T8: opcodeType = THREEBYTE_38; break; 844 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 845 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 846 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 847 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 848 } 849 850 switch (Form) { 851 default: llvm_unreachable("Invalid form!"); 852 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 853 case X86Local::RawFrm: 854 case X86Local::AddRegFrm: 855 case X86Local::RawFrmMemOffs: 856 case X86Local::RawFrmSrc: 857 case X86Local::RawFrmDst: 858 case X86Local::RawFrmDstSrc: 859 case X86Local::RawFrmImm8: 860 case X86Local::RawFrmImm16: 861 filter = new DumbFilter(); 862 break; 863 case X86Local::MRMDestReg: 864 case X86Local::MRMSrcReg: 865 case X86Local::MRMSrcReg4VOp3: 866 case X86Local::MRMSrcRegOp4: 867 case X86Local::MRMXr: 868 filter = new ModFilter(true); 869 break; 870 case X86Local::MRMDestMem: 871 case X86Local::MRMSrcMem: 872 case X86Local::MRMSrcMem4VOp3: 873 case X86Local::MRMSrcMemOp4: 874 case X86Local::MRMXm: 875 filter = new ModFilter(false); 876 break; 877 case X86Local::MRM0r: case X86Local::MRM1r: 878 case X86Local::MRM2r: case X86Local::MRM3r: 879 case X86Local::MRM4r: case X86Local::MRM5r: 880 case X86Local::MRM6r: case X86Local::MRM7r: 881 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 882 break; 883 case X86Local::MRM0m: case X86Local::MRM1m: 884 case X86Local::MRM2m: case X86Local::MRM3m: 885 case X86Local::MRM4m: case X86Local::MRM5m: 886 case X86Local::MRM6m: case X86Local::MRM7m: 887 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 888 break; 889 MRM_MAPPING 890 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \ 891 break; 892 } // switch (Form) 893 894 opcodeToSet = Opcode; 895 break; 896 } // switch (OpMap) 897 898 unsigned AddressSize = 0; 899 switch (AdSize) { 900 case X86Local::AdSize16: AddressSize = 16; break; 901 case X86Local::AdSize32: AddressSize = 32; break; 902 case X86Local::AdSize64: AddressSize = 64; break; 903 } 904 905 assert(opcodeType != (OpcodeType)-1 && 906 "Opcode type not set"); 907 assert(filter && "Filter not set"); 908 909 if (Form == X86Local::AddRegFrm) { 910 assert(((opcodeToSet & 7) == 0) && 911 "ADDREG_FRM opcode not aligned"); 912 913 uint8_t currentOpcode; 914 915 for (currentOpcode = opcodeToSet; 916 currentOpcode < opcodeToSet + 8; 917 ++currentOpcode) 918 tables.setTableFields(opcodeType, 919 insnContext(), 920 currentOpcode, 921 *filter, 922 UID, Is32Bit, IgnoresVEX_L, AddressSize); 923 } else { 924 tables.setTableFields(opcodeType, 925 insnContext(), 926 opcodeToSet, 927 *filter, 928 UID, Is32Bit, IgnoresVEX_L, AddressSize); 929 } 930 931 delete filter; 932 933 #undef MAP 934 } 935 936 #define TYPE(str, type) if (s == str) return type; 937 OperandType RecognizableInstr::typeFromString(const std::string &s, 938 bool hasREX_WPrefix, 939 uint8_t OpSize) { 940 if(hasREX_WPrefix) { 941 // For instructions with a REX_W prefix, a declared 32-bit register encoding 942 // is special. 943 TYPE("GR32", TYPE_R32) 944 } 945 if(OpSize == X86Local::OpSize16) { 946 // For OpSize16 instructions, a declared 16-bit register or 947 // immediate encoding is special. 948 TYPE("GR16", TYPE_Rv) 949 } else if(OpSize == X86Local::OpSize32) { 950 // For OpSize32 instructions, a declared 32-bit register or 951 // immediate encoding is special. 952 TYPE("GR32", TYPE_Rv) 953 } 954 TYPE("i16mem", TYPE_M) 955 TYPE("i16imm", TYPE_IMM) 956 TYPE("i16i8imm", TYPE_IMM) 957 TYPE("GR16", TYPE_R16) 958 TYPE("i32mem", TYPE_M) 959 TYPE("i32imm", TYPE_IMM) 960 TYPE("i32i8imm", TYPE_IMM) 961 TYPE("GR32", TYPE_R32) 962 TYPE("GR32orGR64", TYPE_R32) 963 TYPE("i64mem", TYPE_M) 964 TYPE("i64i32imm", TYPE_IMM) 965 TYPE("i64i8imm", TYPE_IMM) 966 TYPE("GR64", TYPE_R64) 967 TYPE("i8mem", TYPE_M) 968 TYPE("i8imm", TYPE_IMM) 969 TYPE("u8imm", TYPE_UIMM8) 970 TYPE("i32u8imm", TYPE_UIMM8) 971 TYPE("GR8", TYPE_R8) 972 TYPE("VR128", TYPE_XMM) 973 TYPE("VR128X", TYPE_XMM) 974 TYPE("f128mem", TYPE_M) 975 TYPE("f256mem", TYPE_M) 976 TYPE("f512mem", TYPE_M) 977 TYPE("FR128", TYPE_XMM) 978 TYPE("FR64", TYPE_XMM) 979 TYPE("FR64X", TYPE_XMM) 980 TYPE("f64mem", TYPE_M) 981 TYPE("sdmem", TYPE_M) 982 TYPE("FR32", TYPE_XMM) 983 TYPE("FR32X", TYPE_XMM) 984 TYPE("f32mem", TYPE_M) 985 TYPE("ssmem", TYPE_M) 986 TYPE("RST", TYPE_ST) 987 TYPE("i128mem", TYPE_M) 988 TYPE("i256mem", TYPE_M) 989 TYPE("i512mem", TYPE_M) 990 TYPE("i64i32imm_pcrel", TYPE_REL) 991 TYPE("i16imm_pcrel", TYPE_REL) 992 TYPE("i32imm_pcrel", TYPE_REL) 993 TYPE("SSECC", TYPE_IMM3) 994 TYPE("XOPCC", TYPE_IMM3) 995 TYPE("AVXCC", TYPE_IMM5) 996 TYPE("AVX512ICC", TYPE_AVX512ICC) 997 TYPE("AVX512RC", TYPE_IMM) 998 TYPE("brtarget32", TYPE_REL) 999 TYPE("brtarget16", TYPE_REL) 1000 TYPE("brtarget8", TYPE_REL) 1001 TYPE("f80mem", TYPE_M) 1002 TYPE("lea64_32mem", TYPE_M) 1003 TYPE("lea64mem", TYPE_M) 1004 TYPE("VR64", TYPE_MM64) 1005 TYPE("i64imm", TYPE_IMM) 1006 TYPE("anymem", TYPE_M) 1007 TYPE("opaque32mem", TYPE_M) 1008 TYPE("opaque48mem", TYPE_M) 1009 TYPE("opaque80mem", TYPE_M) 1010 TYPE("opaque512mem", TYPE_M) 1011 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1012 TYPE("DEBUG_REG", TYPE_DEBUGREG) 1013 TYPE("CONTROL_REG", TYPE_CONTROLREG) 1014 TYPE("srcidx8", TYPE_SRCIDX) 1015 TYPE("srcidx16", TYPE_SRCIDX) 1016 TYPE("srcidx32", TYPE_SRCIDX) 1017 TYPE("srcidx64", TYPE_SRCIDX) 1018 TYPE("dstidx8", TYPE_DSTIDX) 1019 TYPE("dstidx16", TYPE_DSTIDX) 1020 TYPE("dstidx32", TYPE_DSTIDX) 1021 TYPE("dstidx64", TYPE_DSTIDX) 1022 TYPE("offset16_8", TYPE_MOFFS) 1023 TYPE("offset16_16", TYPE_MOFFS) 1024 TYPE("offset16_32", TYPE_MOFFS) 1025 TYPE("offset32_8", TYPE_MOFFS) 1026 TYPE("offset32_16", TYPE_MOFFS) 1027 TYPE("offset32_32", TYPE_MOFFS) 1028 TYPE("offset32_64", TYPE_MOFFS) 1029 TYPE("offset64_8", TYPE_MOFFS) 1030 TYPE("offset64_16", TYPE_MOFFS) 1031 TYPE("offset64_32", TYPE_MOFFS) 1032 TYPE("offset64_64", TYPE_MOFFS) 1033 TYPE("VR256", TYPE_YMM) 1034 TYPE("VR256X", TYPE_YMM) 1035 TYPE("VR512", TYPE_ZMM) 1036 TYPE("VK1", TYPE_VK) 1037 TYPE("VK1WM", TYPE_VK) 1038 TYPE("VK2", TYPE_VK) 1039 TYPE("VK2WM", TYPE_VK) 1040 TYPE("VK4", TYPE_VK) 1041 TYPE("VK4WM", TYPE_VK) 1042 TYPE("VK8", TYPE_VK) 1043 TYPE("VK8WM", TYPE_VK) 1044 TYPE("VK16", TYPE_VK) 1045 TYPE("VK16WM", TYPE_VK) 1046 TYPE("VK32", TYPE_VK) 1047 TYPE("VK32WM", TYPE_VK) 1048 TYPE("VK64", TYPE_VK) 1049 TYPE("VK64WM", TYPE_VK) 1050 TYPE("GR32_NOAX", TYPE_Rv) 1051 TYPE("vx64mem", TYPE_M) 1052 TYPE("vx128mem", TYPE_M) 1053 TYPE("vx256mem", TYPE_M) 1054 TYPE("vy128mem", TYPE_M) 1055 TYPE("vy256mem", TYPE_M) 1056 TYPE("vx64xmem", TYPE_M) 1057 TYPE("vx128xmem", TYPE_M) 1058 TYPE("vx256xmem", TYPE_M) 1059 TYPE("vy128xmem", TYPE_M) 1060 TYPE("vy256xmem", TYPE_M) 1061 TYPE("vy512mem", TYPE_M) 1062 TYPE("vz256xmem", TYPE_M) 1063 TYPE("vz512mem", TYPE_M) 1064 TYPE("BNDR", TYPE_BNDR) 1065 errs() << "Unhandled type string " << s << "\n"; 1066 llvm_unreachable("Unhandled type string"); 1067 } 1068 #undef TYPE 1069 1070 #define ENCODING(str, encoding) if (s == str) return encoding; 1071 OperandEncoding 1072 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1073 uint8_t OpSize) { 1074 if(OpSize != X86Local::OpSize16) { 1075 // For instructions without an OpSize prefix, a declared 16-bit register or 1076 // immediate encoding is special. 1077 ENCODING("i16imm", ENCODING_IW) 1078 } 1079 ENCODING("i32i8imm", ENCODING_IB) 1080 ENCODING("SSECC", ENCODING_IB) 1081 ENCODING("XOPCC", ENCODING_IB) 1082 ENCODING("AVXCC", ENCODING_IB) 1083 ENCODING("AVX512ICC", ENCODING_IB) 1084 ENCODING("AVX512RC", ENCODING_IB) 1085 ENCODING("i16imm", ENCODING_Iv) 1086 ENCODING("i16i8imm", ENCODING_IB) 1087 ENCODING("i32imm", ENCODING_Iv) 1088 ENCODING("i64i32imm", ENCODING_ID) 1089 ENCODING("i64i8imm", ENCODING_IB) 1090 ENCODING("i8imm", ENCODING_IB) 1091 ENCODING("u8imm", ENCODING_IB) 1092 ENCODING("i32u8imm", ENCODING_IB) 1093 // This is not a typo. Instructions like BLENDVPD put 1094 // register IDs in 8-bit immediates nowadays. 1095 ENCODING("FR32", ENCODING_IB) 1096 ENCODING("FR64", ENCODING_IB) 1097 ENCODING("FR128", ENCODING_IB) 1098 ENCODING("VR128", ENCODING_IB) 1099 ENCODING("VR256", ENCODING_IB) 1100 ENCODING("FR32X", ENCODING_IB) 1101 ENCODING("FR64X", ENCODING_IB) 1102 ENCODING("VR128X", ENCODING_IB) 1103 ENCODING("VR256X", ENCODING_IB) 1104 ENCODING("VR512", ENCODING_IB) 1105 errs() << "Unhandled immediate encoding " << s << "\n"; 1106 llvm_unreachable("Unhandled immediate encoding"); 1107 } 1108 1109 OperandEncoding 1110 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1111 uint8_t OpSize) { 1112 ENCODING("RST", ENCODING_FP) 1113 ENCODING("GR16", ENCODING_RM) 1114 ENCODING("GR32", ENCODING_RM) 1115 ENCODING("GR32orGR64", ENCODING_RM) 1116 ENCODING("GR64", ENCODING_RM) 1117 ENCODING("GR8", ENCODING_RM) 1118 ENCODING("VR128", ENCODING_RM) 1119 ENCODING("VR128X", ENCODING_RM) 1120 ENCODING("FR128", ENCODING_RM) 1121 ENCODING("FR64", ENCODING_RM) 1122 ENCODING("FR32", ENCODING_RM) 1123 ENCODING("FR64X", ENCODING_RM) 1124 ENCODING("FR32X", ENCODING_RM) 1125 ENCODING("VR64", ENCODING_RM) 1126 ENCODING("VR256", ENCODING_RM) 1127 ENCODING("VR256X", ENCODING_RM) 1128 ENCODING("VR512", ENCODING_RM) 1129 ENCODING("VK1", ENCODING_RM) 1130 ENCODING("VK2", ENCODING_RM) 1131 ENCODING("VK4", ENCODING_RM) 1132 ENCODING("VK8", ENCODING_RM) 1133 ENCODING("VK16", ENCODING_RM) 1134 ENCODING("VK32", ENCODING_RM) 1135 ENCODING("VK64", ENCODING_RM) 1136 ENCODING("BNDR", ENCODING_RM) 1137 errs() << "Unhandled R/M register encoding " << s << "\n"; 1138 llvm_unreachable("Unhandled R/M register encoding"); 1139 } 1140 1141 OperandEncoding 1142 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1143 uint8_t OpSize) { 1144 ENCODING("GR16", ENCODING_REG) 1145 ENCODING("GR32", ENCODING_REG) 1146 ENCODING("GR32orGR64", ENCODING_REG) 1147 ENCODING("GR64", ENCODING_REG) 1148 ENCODING("GR8", ENCODING_REG) 1149 ENCODING("VR128", ENCODING_REG) 1150 ENCODING("FR128", ENCODING_REG) 1151 ENCODING("FR64", ENCODING_REG) 1152 ENCODING("FR32", ENCODING_REG) 1153 ENCODING("VR64", ENCODING_REG) 1154 ENCODING("SEGMENT_REG", ENCODING_REG) 1155 ENCODING("DEBUG_REG", ENCODING_REG) 1156 ENCODING("CONTROL_REG", ENCODING_REG) 1157 ENCODING("VR256", ENCODING_REG) 1158 ENCODING("VR256X", ENCODING_REG) 1159 ENCODING("VR128X", ENCODING_REG) 1160 ENCODING("FR64X", ENCODING_REG) 1161 ENCODING("FR32X", ENCODING_REG) 1162 ENCODING("VR512", ENCODING_REG) 1163 ENCODING("VK1", ENCODING_REG) 1164 ENCODING("VK2", ENCODING_REG) 1165 ENCODING("VK4", ENCODING_REG) 1166 ENCODING("VK8", ENCODING_REG) 1167 ENCODING("VK16", ENCODING_REG) 1168 ENCODING("VK32", ENCODING_REG) 1169 ENCODING("VK64", ENCODING_REG) 1170 ENCODING("VK1WM", ENCODING_REG) 1171 ENCODING("VK2WM", ENCODING_REG) 1172 ENCODING("VK4WM", ENCODING_REG) 1173 ENCODING("VK8WM", ENCODING_REG) 1174 ENCODING("VK16WM", ENCODING_REG) 1175 ENCODING("VK32WM", ENCODING_REG) 1176 ENCODING("VK64WM", ENCODING_REG) 1177 ENCODING("BNDR", ENCODING_REG) 1178 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1179 llvm_unreachable("Unhandled reg/opcode register encoding"); 1180 } 1181 1182 OperandEncoding 1183 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1184 uint8_t OpSize) { 1185 ENCODING("GR32", ENCODING_VVVV) 1186 ENCODING("GR64", ENCODING_VVVV) 1187 ENCODING("FR32", ENCODING_VVVV) 1188 ENCODING("FR128", ENCODING_VVVV) 1189 ENCODING("FR64", ENCODING_VVVV) 1190 ENCODING("VR128", ENCODING_VVVV) 1191 ENCODING("VR256", ENCODING_VVVV) 1192 ENCODING("FR32X", ENCODING_VVVV) 1193 ENCODING("FR64X", ENCODING_VVVV) 1194 ENCODING("VR128X", ENCODING_VVVV) 1195 ENCODING("VR256X", ENCODING_VVVV) 1196 ENCODING("VR512", ENCODING_VVVV) 1197 ENCODING("VK1", ENCODING_VVVV) 1198 ENCODING("VK2", ENCODING_VVVV) 1199 ENCODING("VK4", ENCODING_VVVV) 1200 ENCODING("VK8", ENCODING_VVVV) 1201 ENCODING("VK16", ENCODING_VVVV) 1202 ENCODING("VK32", ENCODING_VVVV) 1203 ENCODING("VK64", ENCODING_VVVV) 1204 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1205 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1206 } 1207 1208 OperandEncoding 1209 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1210 uint8_t OpSize) { 1211 ENCODING("VK1WM", ENCODING_WRITEMASK) 1212 ENCODING("VK2WM", ENCODING_WRITEMASK) 1213 ENCODING("VK4WM", ENCODING_WRITEMASK) 1214 ENCODING("VK8WM", ENCODING_WRITEMASK) 1215 ENCODING("VK16WM", ENCODING_WRITEMASK) 1216 ENCODING("VK32WM", ENCODING_WRITEMASK) 1217 ENCODING("VK64WM", ENCODING_WRITEMASK) 1218 errs() << "Unhandled mask register encoding " << s << "\n"; 1219 llvm_unreachable("Unhandled mask register encoding"); 1220 } 1221 1222 OperandEncoding 1223 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1224 uint8_t OpSize) { 1225 ENCODING("i16mem", ENCODING_RM) 1226 ENCODING("i32mem", ENCODING_RM) 1227 ENCODING("i64mem", ENCODING_RM) 1228 ENCODING("i8mem", ENCODING_RM) 1229 ENCODING("ssmem", ENCODING_RM) 1230 ENCODING("sdmem", ENCODING_RM) 1231 ENCODING("f128mem", ENCODING_RM) 1232 ENCODING("f256mem", ENCODING_RM) 1233 ENCODING("f512mem", ENCODING_RM) 1234 ENCODING("f64mem", ENCODING_RM) 1235 ENCODING("f32mem", ENCODING_RM) 1236 ENCODING("i128mem", ENCODING_RM) 1237 ENCODING("i256mem", ENCODING_RM) 1238 ENCODING("i512mem", ENCODING_RM) 1239 ENCODING("f80mem", ENCODING_RM) 1240 ENCODING("lea64_32mem", ENCODING_RM) 1241 ENCODING("lea64mem", ENCODING_RM) 1242 ENCODING("anymem", ENCODING_RM) 1243 ENCODING("opaque32mem", ENCODING_RM) 1244 ENCODING("opaque48mem", ENCODING_RM) 1245 ENCODING("opaque80mem", ENCODING_RM) 1246 ENCODING("opaque512mem", ENCODING_RM) 1247 ENCODING("vx64mem", ENCODING_VSIB) 1248 ENCODING("vx128mem", ENCODING_VSIB) 1249 ENCODING("vx256mem", ENCODING_VSIB) 1250 ENCODING("vy128mem", ENCODING_VSIB) 1251 ENCODING("vy256mem", ENCODING_VSIB) 1252 ENCODING("vx64xmem", ENCODING_VSIB) 1253 ENCODING("vx128xmem", ENCODING_VSIB) 1254 ENCODING("vx256xmem", ENCODING_VSIB) 1255 ENCODING("vy128xmem", ENCODING_VSIB) 1256 ENCODING("vy256xmem", ENCODING_VSIB) 1257 ENCODING("vy512mem", ENCODING_VSIB) 1258 ENCODING("vz256xmem", ENCODING_VSIB) 1259 ENCODING("vz512mem", ENCODING_VSIB) 1260 errs() << "Unhandled memory encoding " << s << "\n"; 1261 llvm_unreachable("Unhandled memory encoding"); 1262 } 1263 1264 OperandEncoding 1265 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1266 uint8_t OpSize) { 1267 if(OpSize != X86Local::OpSize16) { 1268 // For instructions without an OpSize prefix, a declared 16-bit register or 1269 // immediate encoding is special. 1270 ENCODING("i16imm", ENCODING_IW) 1271 } 1272 ENCODING("i16imm", ENCODING_Iv) 1273 ENCODING("i16i8imm", ENCODING_IB) 1274 ENCODING("i32imm", ENCODING_Iv) 1275 ENCODING("i32i8imm", ENCODING_IB) 1276 ENCODING("i64i32imm", ENCODING_ID) 1277 ENCODING("i64i8imm", ENCODING_IB) 1278 ENCODING("i8imm", ENCODING_IB) 1279 ENCODING("u8imm", ENCODING_IB) 1280 ENCODING("i32u8imm", ENCODING_IB) 1281 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1282 ENCODING("i16imm_pcrel", ENCODING_IW) 1283 ENCODING("i32imm_pcrel", ENCODING_ID) 1284 ENCODING("brtarget32", ENCODING_Iv) 1285 ENCODING("brtarget16", ENCODING_Iv) 1286 ENCODING("brtarget8", ENCODING_IB) 1287 ENCODING("i64imm", ENCODING_IO) 1288 ENCODING("offset16_8", ENCODING_Ia) 1289 ENCODING("offset16_16", ENCODING_Ia) 1290 ENCODING("offset16_32", ENCODING_Ia) 1291 ENCODING("offset32_8", ENCODING_Ia) 1292 ENCODING("offset32_16", ENCODING_Ia) 1293 ENCODING("offset32_32", ENCODING_Ia) 1294 ENCODING("offset32_64", ENCODING_Ia) 1295 ENCODING("offset64_8", ENCODING_Ia) 1296 ENCODING("offset64_16", ENCODING_Ia) 1297 ENCODING("offset64_32", ENCODING_Ia) 1298 ENCODING("offset64_64", ENCODING_Ia) 1299 ENCODING("srcidx8", ENCODING_SI) 1300 ENCODING("srcidx16", ENCODING_SI) 1301 ENCODING("srcidx32", ENCODING_SI) 1302 ENCODING("srcidx64", ENCODING_SI) 1303 ENCODING("dstidx8", ENCODING_DI) 1304 ENCODING("dstidx16", ENCODING_DI) 1305 ENCODING("dstidx32", ENCODING_DI) 1306 ENCODING("dstidx64", ENCODING_DI) 1307 errs() << "Unhandled relocation encoding " << s << "\n"; 1308 llvm_unreachable("Unhandled relocation encoding"); 1309 } 1310 1311 OperandEncoding 1312 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1313 uint8_t OpSize) { 1314 ENCODING("GR32", ENCODING_Rv) 1315 ENCODING("GR64", ENCODING_RO) 1316 ENCODING("GR16", ENCODING_Rv) 1317 ENCODING("GR8", ENCODING_RB) 1318 ENCODING("GR32_NOAX", ENCODING_Rv) 1319 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1320 llvm_unreachable("Unhandled opcode modifier encoding"); 1321 } 1322 #undef ENCODING 1323