1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 #define THREE_BYTE_38_EXTENSION_TABLES \
123   EXTENSION_TABLE(F3)
124 
125 using namespace X86Disassembler;
126 
127 /// needsModRMForDecode - Indicates whether a particular instruction requires a
128 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
129 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
130 ///   0b11.
131 ///
132 /// @param form - The form of the instruction.
133 /// @return     - true if the form implies that a ModR/M byte is required, false
134 ///               otherwise.
135 static bool needsModRMForDecode(uint8_t form) {
136   if (form == X86Local::MRMDestReg    ||
137      form == X86Local::MRMDestMem    ||
138      form == X86Local::MRMSrcReg     ||
139      form == X86Local::MRMSrcMem     ||
140      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
141      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142     return true;
143   else
144     return false;
145 }
146 
147 /// isRegFormat - Indicates whether a particular form requires the Mod field of
148 ///   the ModR/M byte to be 0b11.
149 ///
150 /// @param form - The form of the instruction.
151 /// @return     - true if the form implies that Mod must be 0b11, false
152 ///               otherwise.
153 static bool isRegFormat(uint8_t form) {
154   if (form == X86Local::MRMDestReg ||
155      form == X86Local::MRMSrcReg  ||
156      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157     return true;
158   else
159     return false;
160 }
161 
162 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
163 ///   Useful for switch statements and the like.
164 ///
165 /// @param init - A reference to the BitsInit to be decoded.
166 /// @return     - The field, with the first bit in the BitsInit as the lowest
167 ///               order bit.
168 static uint8_t byteFromBitsInit(BitsInit &init) {
169   int width = init.getNumBits();
170 
171   assert(width <= 8 && "Field is too large for uint8_t!");
172 
173   int     index;
174   uint8_t mask = 0x01;
175 
176   uint8_t ret = 0;
177 
178   for (index = 0; index < width; index++) {
179     if (static_cast<BitInit*>(init.getBit(index))->getValue())
180       ret |= mask;
181 
182     mask <<= 1;
183   }
184 
185   return ret;
186 }
187 
188 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
189 ///   name of the field.
190 ///
191 /// @param rec  - The record from which to extract the value.
192 /// @param name - The name of the field in the record.
193 /// @return     - The field, as translated by byteFromBitsInit().
194 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
195   BitsInit* bits = rec->getValueAsBitsInit(name);
196   return byteFromBitsInit(*bits);
197 }
198 
199 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
200                                      const CodeGenInstruction &insn,
201                                      InstrUID uid) {
202   UID = uid;
203 
204   Rec = insn.TheDef;
205   Name = Rec->getName();
206   Spec = &tables.specForUID(UID);
207 
208   if (!Rec->isSubClassOf("X86Inst")) {
209     ShouldBeEmitted = false;
210     return;
211   }
212 
213   Prefix   = byteFromRec(Rec, "Prefix");
214   Opcode   = byteFromRec(Rec, "Opcode");
215   Form     = byteFromRec(Rec, "FormBits");
216   SegOvr   = byteFromRec(Rec, "SegOvrBits");
217 
218   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
219   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
220   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
221   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
222   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
223   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
224   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
225   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
226   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
227 
228   Name      = Rec->getName();
229   AsmString = Rec->getValueAsString("AsmString");
230 
231   Operands = &insn.Operands.OperandList;
232 
233   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
234                      (Name.find("CRC32") != Name.npos);
235   HasFROperands    = hasFROperands();
236   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
237 
238   // Check for 64-bit inst which does not require REX
239   Is32Bit = false;
240   Is64Bit = false;
241   // FIXME: Is there some better way to check for In64BitMode?
242   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
243   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
244     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
245       Is32Bit = true;
246       break;
247     }
248     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
249       Is64Bit = true;
250       break;
251     }
252   }
253   // FIXME: These instructions aren't marked as 64-bit in any way
254   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
255              Rec->getName() == "MASKMOVDQU64" ||
256              Rec->getName() == "POPFS64" ||
257              Rec->getName() == "POPGS64" ||
258              Rec->getName() == "PUSHFS64" ||
259              Rec->getName() == "PUSHGS64" ||
260              Rec->getName() == "REX64_PREFIX" ||
261              Rec->getName().find("MOV64") != Name.npos ||
262              Rec->getName().find("PUSH64") != Name.npos ||
263              Rec->getName().find("POP64") != Name.npos;
264 
265   ShouldBeEmitted  = true;
266 }
267 
268 void RecognizableInstr::processInstr(DisassemblerTables &tables,
269 	const CodeGenInstruction &insn,
270                                    InstrUID uid)
271 {
272   // Ignore "asm parser only" instructions.
273   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
274     return;
275 
276   RecognizableInstr recogInstr(tables, insn, uid);
277 
278   recogInstr.emitInstructionSpecifier(tables);
279 
280   if (recogInstr.shouldBeEmitted())
281     recogInstr.emitDecodePath(tables);
282 }
283 
284 InstructionContext RecognizableInstr::insnContext() const {
285   InstructionContext insnContext;
286 
287   if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
288     if (HasVEX_LPrefix && HasVEX_WPrefix) {
289       if (HasOpSizePrefix)
290         insnContext = IC_VEX_L_W_OPSIZE;
291       else
292         llvm_unreachable("Don't support VEX.L and VEX.W together");
293     } else if (HasOpSizePrefix && HasVEX_LPrefix)
294       insnContext = IC_VEX_L_OPSIZE;
295     else if (HasOpSizePrefix && HasVEX_WPrefix)
296       insnContext = IC_VEX_W_OPSIZE;
297     else if (HasOpSizePrefix)
298       insnContext = IC_VEX_OPSIZE;
299     else if (HasVEX_LPrefix &&
300              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
301       insnContext = IC_VEX_L_XS;
302     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
303                                 Prefix == X86Local::T8XD ||
304                                 Prefix == X86Local::TAXD))
305       insnContext = IC_VEX_L_XD;
306     else if (HasVEX_WPrefix &&
307              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
308       insnContext = IC_VEX_W_XS;
309     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
310                                 Prefix == X86Local::T8XD ||
311                                 Prefix == X86Local::TAXD))
312       insnContext = IC_VEX_W_XD;
313     else if (HasVEX_WPrefix)
314       insnContext = IC_VEX_W;
315     else if (HasVEX_LPrefix)
316       insnContext = IC_VEX_L;
317     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
318              Prefix == X86Local::TAXD)
319       insnContext = IC_VEX_XD;
320     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
321       insnContext = IC_VEX_XS;
322     else
323       insnContext = IC_VEX;
324   } else if (Is64Bit || HasREX_WPrefix) {
325     if (HasREX_WPrefix && HasOpSizePrefix)
326       insnContext = IC_64BIT_REXW_OPSIZE;
327     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
328                                  Prefix == X86Local::T8XD ||
329                                  Prefix == X86Local::TAXD))
330       insnContext = IC_64BIT_XD_OPSIZE;
331     else if (HasOpSizePrefix &&
332              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
333       insnContext = IC_64BIT_XS_OPSIZE;
334     else if (HasOpSizePrefix)
335       insnContext = IC_64BIT_OPSIZE;
336     else if (HasREX_WPrefix &&
337              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
338       insnContext = IC_64BIT_REXW_XS;
339     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
340                                 Prefix == X86Local::T8XD ||
341                                 Prefix == X86Local::TAXD))
342       insnContext = IC_64BIT_REXW_XD;
343     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
344              Prefix == X86Local::TAXD)
345       insnContext = IC_64BIT_XD;
346     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
347       insnContext = IC_64BIT_XS;
348     else if (HasREX_WPrefix)
349       insnContext = IC_64BIT_REXW;
350     else
351       insnContext = IC_64BIT;
352   } else {
353     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
354                             Prefix == X86Local::T8XD ||
355                             Prefix == X86Local::TAXD))
356       insnContext = IC_XD_OPSIZE;
357     else if (HasOpSizePrefix &&
358              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
359       insnContext = IC_XS_OPSIZE;
360     else if (HasOpSizePrefix)
361       insnContext = IC_OPSIZE;
362     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
363              Prefix == X86Local::TAXD)
364       insnContext = IC_XD;
365     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
366              Prefix == X86Local::REP)
367       insnContext = IC_XS;
368     else
369       insnContext = IC;
370   }
371 
372   return insnContext;
373 }
374 
375 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
376   ///////////////////
377   // FILTER_STRONG
378   //
379 
380   // Filter out intrinsics
381 
382   if (!Rec->isSubClassOf("X86Inst"))
383     return FILTER_STRONG;
384 
385   if (Form == X86Local::Pseudo ||
386       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
387     return FILTER_STRONG;
388 
389   if (Form == X86Local::MRMInitReg)
390     return FILTER_STRONG;
391 
392 
393   // Filter out artificial instructions
394 
395   if (Name.find("TAILJMP") != Name.npos    ||
396       Name.find("_Int") != Name.npos       ||
397       Name.find("_int") != Name.npos       ||
398       Name.find("Int_") != Name.npos       ||
399       Name.find("_NOREX") != Name.npos     ||
400       Name.find("_TC") != Name.npos        ||
401       Name.find("EH_RETURN") != Name.npos  ||
402       Name.find("V_SET") != Name.npos      ||
403       Name.find("LOCK_") != Name.npos      ||
404       Name.find("WIN") != Name.npos        ||
405       Name.find("_AVX") != Name.npos       ||
406       Name.find("2SDL") != Name.npos)
407     return FILTER_STRONG;
408 
409   // Filter out instructions with segment override prefixes.
410   // They're too messy to handle now and we'll special case them if needed.
411 
412   if (SegOvr)
413     return FILTER_STRONG;
414 
415   // Filter out instructions that can't be printed.
416 
417   if (AsmString.size() == 0)
418     return FILTER_STRONG;
419 
420   // Filter out instructions with subreg operands.
421 
422   if (AsmString.find("subreg") != AsmString.npos)
423     return FILTER_STRONG;
424 
425   /////////////////
426   // FILTER_WEAK
427   //
428 
429 
430   // Filter out instructions with a LOCK prefix;
431   //   prefer forms that do not have the prefix
432   if (HasLockPrefix)
433     return FILTER_WEAK;
434 
435   // Filter out alternate forms of AVX instructions
436   if (Name.find("_alt") != Name.npos ||
437       Name.find("XrYr") != Name.npos ||
438       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
439       Name.find("_64mr") != Name.npos ||
440       Name.find("Xrr") != Name.npos ||
441       Name.find("rr64") != Name.npos)
442     return FILTER_WEAK;
443 
444   if (Name == "VMASKMOVDQU64"  ||
445       Name == "VEXTRACTPSrr64" ||
446       Name == "VMOVQd64rr"     ||
447       Name == "VMOVQs64rr")
448     return FILTER_WEAK;
449 
450   // Special cases.
451 
452   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
453     return FILTER_WEAK;
454   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
455     return FILTER_WEAK;
456 
457   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
458     return FILTER_WEAK;
459   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
460     return FILTER_WEAK;
461   if (Name.find("Fs") != Name.npos)
462     return FILTER_WEAK;
463   if (Name == "MOVLPDrr"          ||
464       Name == "MOVLPSrr"          ||
465       Name == "PUSHFQ"            ||
466       Name == "BSF16rr"           ||
467       Name == "BSF16rm"           ||
468       Name == "BSR16rr"           ||
469       Name == "BSR16rm"           ||
470       Name == "MOVSX16rm8"        ||
471       Name == "MOVSX16rr8"        ||
472       Name == "MOVZX16rm8"        ||
473       Name == "MOVZX16rr8"        ||
474       Name == "PUSH32i16"         ||
475       Name == "PUSH64i16"         ||
476       Name == "MOVPQI2QImr"       ||
477       Name == "VMOVPQI2QImr"      ||
478       Name == "MOVSDmr"           ||
479       Name == "MOVSDrm"           ||
480       Name == "MOVSSmr"           ||
481       Name == "MOVSSrm"           ||
482       Name == "MMX_MOVD64rrv164"  ||
483       Name == "CRC32m16"          ||
484       Name == "MOV64ri64i32"      ||
485       Name == "CRC32r16")
486     return FILTER_WEAK;
487 
488   if (HasFROperands && Name.find("MOV") != Name.npos &&
489      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
490       (Name.find("to") != Name.npos)))
491     return FILTER_WEAK;
492 
493   return FILTER_NORMAL;
494 }
495 
496 bool RecognizableInstr::hasFROperands() const {
497   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
498   unsigned numOperands = OperandList.size();
499 
500   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
501     const std::string &recName = OperandList[operandIndex].Rec->getName();
502 
503     if (recName.find("FR") != recName.npos)
504       return true;
505   }
506   return false;
507 }
508 
509 bool RecognizableInstr::has256BitOperands() const {
510   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
511   unsigned numOperands = OperandList.size();
512 
513   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
514     const std::string &recName = OperandList[operandIndex].Rec->getName();
515 
516     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
517       return true;
518     }
519   }
520   return false;
521 }
522 
523 void RecognizableInstr::handleOperand(
524   bool optional,
525   unsigned &operandIndex,
526   unsigned &physicalOperandIndex,
527   unsigned &numPhysicalOperands,
528   unsigned *operandMapping,
529   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
530   if (optional) {
531     if (physicalOperandIndex >= numPhysicalOperands)
532       return;
533   } else {
534     assert(physicalOperandIndex < numPhysicalOperands);
535   }
536 
537   while (operandMapping[operandIndex] != operandIndex) {
538     Spec->operands[operandIndex].encoding = ENCODING_DUP;
539     Spec->operands[operandIndex].type =
540       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
541     ++operandIndex;
542   }
543 
544   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
545 
546   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
547                                                               HasOpSizePrefix);
548   Spec->operands[operandIndex].type = typeFromString(typeName,
549                                                      IsSSE,
550                                                      HasREX_WPrefix,
551                                                      HasOpSizePrefix);
552 
553   ++operandIndex;
554   ++physicalOperandIndex;
555 }
556 
557 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
558   Spec->name       = Name;
559 
560   if (!Rec->isSubClassOf("X86Inst"))
561     return;
562 
563   switch (filter()) {
564   case FILTER_WEAK:
565     Spec->filtered = true;
566     break;
567   case FILTER_STRONG:
568     ShouldBeEmitted = false;
569     return;
570   case FILTER_NORMAL:
571     break;
572   }
573 
574   Spec->insnContext = insnContext();
575 
576   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
577 
578   unsigned operandIndex;
579   unsigned numOperands = OperandList.size();
580   unsigned numPhysicalOperands = 0;
581 
582   // operandMapping maps from operands in OperandList to their originals.
583   // If operandMapping[i] != i, then the entry is a duplicate.
584   unsigned operandMapping[X86_MAX_OPERANDS];
585 
586   bool hasFROperands = false;
587 
588   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
589 
590   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
591     if (OperandList[operandIndex].Constraints.size()) {
592       const CGIOperandList::ConstraintInfo &Constraint =
593         OperandList[operandIndex].Constraints[0];
594       if (Constraint.isTied()) {
595         operandMapping[operandIndex] = Constraint.getTiedOperand();
596       } else {
597         ++numPhysicalOperands;
598         operandMapping[operandIndex] = operandIndex;
599       }
600     } else {
601       ++numPhysicalOperands;
602       operandMapping[operandIndex] = operandIndex;
603     }
604 
605     const std::string &recName = OperandList[operandIndex].Rec->getName();
606 
607     if (recName.find("FR") != recName.npos)
608       hasFROperands = true;
609   }
610 
611   if (hasFROperands && Name.find("MOV") != Name.npos &&
612      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
613       (Name.find("to") != Name.npos)))
614     ShouldBeEmitted = false;
615 
616   if (!ShouldBeEmitted)
617     return;
618 
619 #define HANDLE_OPERAND(class)               \
620   handleOperand(false,                      \
621                 operandIndex,               \
622                 physicalOperandIndex,       \
623                 numPhysicalOperands,        \
624                 operandMapping,             \
625                 class##EncodingFromString);
626 
627 #define HANDLE_OPTIONAL(class)              \
628   handleOperand(true,                       \
629                 operandIndex,               \
630                 physicalOperandIndex,       \
631                 numPhysicalOperands,        \
632                 operandMapping,             \
633                 class##EncodingFromString);
634 
635   // operandIndex should always be < numOperands
636   operandIndex = 0;
637   // physicalOperandIndex should always be < numPhysicalOperands
638   unsigned physicalOperandIndex = 0;
639 
640   switch (Form) {
641   case X86Local::RawFrm:
642     // Operand 1 (optional) is an address or immediate.
643     // Operand 2 (optional) is an immediate.
644     assert(numPhysicalOperands <= 2 &&
645            "Unexpected number of operands for RawFrm");
646     HANDLE_OPTIONAL(relocation)
647     HANDLE_OPTIONAL(immediate)
648     break;
649   case X86Local::AddRegFrm:
650     // Operand 1 is added to the opcode.
651     // Operand 2 (optional) is an address.
652     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
653            "Unexpected number of operands for AddRegFrm");
654     HANDLE_OPERAND(opcodeModifier)
655     HANDLE_OPTIONAL(relocation)
656     break;
657   case X86Local::MRMDestReg:
658     // Operand 1 is a register operand in the R/M field.
659     // Operand 2 is a register operand in the Reg/Opcode field.
660     // - In AVX, there is a register operand in the VEX.vvvv field here -
661     // Operand 3 (optional) is an immediate.
662     if (HasVEX_4VPrefix)
663       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
664              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
665     else
666       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
667              "Unexpected number of operands for MRMDestRegFrm");
668 
669     HANDLE_OPERAND(rmRegister)
670 
671     if (HasVEX_4VPrefix)
672       // FIXME: In AVX, the register below becomes the one encoded
673       // in ModRMVEX and the one above the one in the VEX.VVVV field
674       HANDLE_OPERAND(vvvvRegister)
675 
676     HANDLE_OPERAND(roRegister)
677     HANDLE_OPTIONAL(immediate)
678     break;
679   case X86Local::MRMDestMem:
680     // Operand 1 is a memory operand (possibly SIB-extended)
681     // Operand 2 is a register operand in the Reg/Opcode field.
682     // - In AVX, there is a register operand in the VEX.vvvv field here -
683     // Operand 3 (optional) is an immediate.
684     if (HasVEX_4VPrefix)
685       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
686              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
687     else
688       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
689              "Unexpected number of operands for MRMDestMemFrm");
690     HANDLE_OPERAND(memory)
691 
692     if (HasVEX_4VPrefix)
693       // FIXME: In AVX, the register below becomes the one encoded
694       // in ModRMVEX and the one above the one in the VEX.VVVV field
695       HANDLE_OPERAND(vvvvRegister)
696 
697     HANDLE_OPERAND(roRegister)
698     HANDLE_OPTIONAL(immediate)
699     break;
700   case X86Local::MRMSrcReg:
701     // Operand 1 is a register operand in the Reg/Opcode field.
702     // Operand 2 is a register operand in the R/M field.
703     // - In AVX, there is a register operand in the VEX.vvvv field here -
704     // Operand 3 (optional) is an immediate.
705 
706     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
707       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
708              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
709     else
710       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
711              "Unexpected number of operands for MRMSrcRegFrm");
712 
713     HANDLE_OPERAND(roRegister)
714 
715     if (HasVEX_4VPrefix)
716       // FIXME: In AVX, the register below becomes the one encoded
717       // in ModRMVEX and the one above the one in the VEX.VVVV field
718       HANDLE_OPERAND(vvvvRegister)
719 
720     HANDLE_OPERAND(rmRegister)
721 
722     if (HasVEX_4VOp3Prefix)
723       HANDLE_OPERAND(vvvvRegister)
724 
725     HANDLE_OPTIONAL(immediate)
726     break;
727   case X86Local::MRMSrcMem:
728     // Operand 1 is a register operand in the Reg/Opcode field.
729     // Operand 2 is a memory operand (possibly SIB-extended)
730     // - In AVX, there is a register operand in the VEX.vvvv field here -
731     // Operand 3 (optional) is an immediate.
732 
733     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
734       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
735              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
736     else
737       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
738              "Unexpected number of operands for MRMSrcMemFrm");
739 
740     HANDLE_OPERAND(roRegister)
741 
742     if (HasVEX_4VPrefix)
743       // FIXME: In AVX, the register below becomes the one encoded
744       // in ModRMVEX and the one above the one in the VEX.VVVV field
745       HANDLE_OPERAND(vvvvRegister)
746 
747     HANDLE_OPERAND(memory)
748 
749     if (HasVEX_4VOp3Prefix)
750       HANDLE_OPERAND(vvvvRegister)
751 
752     HANDLE_OPTIONAL(immediate)
753     break;
754   case X86Local::MRM0r:
755   case X86Local::MRM1r:
756   case X86Local::MRM2r:
757   case X86Local::MRM3r:
758   case X86Local::MRM4r:
759   case X86Local::MRM5r:
760   case X86Local::MRM6r:
761   case X86Local::MRM7r:
762     // Operand 1 is a register operand in the R/M field.
763     // Operand 2 (optional) is an immediate or relocation.
764     if (HasVEX_4VPrefix)
765       assert(numPhysicalOperands <= 3 &&
766              "Unexpected number of operands for MRMnRFrm with VEX_4V");
767     else
768       assert(numPhysicalOperands <= 2 &&
769              "Unexpected number of operands for MRMnRFrm");
770     if (HasVEX_4VPrefix)
771       HANDLE_OPERAND(vvvvRegister)
772     HANDLE_OPTIONAL(rmRegister)
773     HANDLE_OPTIONAL(relocation)
774     break;
775   case X86Local::MRM0m:
776   case X86Local::MRM1m:
777   case X86Local::MRM2m:
778   case X86Local::MRM3m:
779   case X86Local::MRM4m:
780   case X86Local::MRM5m:
781   case X86Local::MRM6m:
782   case X86Local::MRM7m:
783     // Operand 1 is a memory operand (possibly SIB-extended)
784     // Operand 2 (optional) is an immediate or relocation.
785     if (HasVEX_4VPrefix)
786       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
787              "Unexpected number of operands for MRMnMFrm");
788     else
789       assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
790              "Unexpected number of operands for MRMnMFrm");
791     if (HasVEX_4VPrefix)
792       HANDLE_OPERAND(vvvvRegister)
793     HANDLE_OPERAND(memory)
794     HANDLE_OPTIONAL(relocation)
795     break;
796   case X86Local::RawFrmImm8:
797     // operand 1 is a 16-bit immediate
798     // operand 2 is an 8-bit immediate
799     assert(numPhysicalOperands == 2 &&
800            "Unexpected number of operands for X86Local::RawFrmImm8");
801     HANDLE_OPERAND(immediate)
802     HANDLE_OPERAND(immediate)
803     break;
804   case X86Local::RawFrmImm16:
805     // operand 1 is a 16-bit immediate
806     // operand 2 is a 16-bit immediate
807     HANDLE_OPERAND(immediate)
808     HANDLE_OPERAND(immediate)
809     break;
810   case X86Local::MRMInitReg:
811     // Ignored.
812     break;
813   }
814 
815   #undef HANDLE_OPERAND
816   #undef HANDLE_OPTIONAL
817 }
818 
819 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
820   // Special cases where the LLVM tables are not complete
821 
822 #define MAP(from, to)                     \
823   case X86Local::MRM_##from:              \
824     filter = new ExactFilter(0x##from);   \
825     break;
826 
827   OpcodeType    opcodeType  = (OpcodeType)-1;
828 
829   ModRMFilter*  filter      = NULL;
830   uint8_t       opcodeToSet = 0;
831 
832   switch (Prefix) {
833   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
834   case X86Local::XD:
835   case X86Local::XS:
836   case X86Local::TB:
837     opcodeType = TWOBYTE;
838 
839     switch (Opcode) {
840     default:
841       if (needsModRMForDecode(Form))
842         filter = new ModFilter(isRegFormat(Form));
843       else
844         filter = new DumbFilter();
845       break;
846 #define EXTENSION_TABLE(n) case 0x##n:
847     TWO_BYTE_EXTENSION_TABLES
848 #undef EXTENSION_TABLE
849       switch (Form) {
850       default:
851         llvm_unreachable("Unhandled two-byte extended opcode");
852       case X86Local::MRM0r:
853       case X86Local::MRM1r:
854       case X86Local::MRM2r:
855       case X86Local::MRM3r:
856       case X86Local::MRM4r:
857       case X86Local::MRM5r:
858       case X86Local::MRM6r:
859       case X86Local::MRM7r:
860         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
861         break;
862       case X86Local::MRM0m:
863       case X86Local::MRM1m:
864       case X86Local::MRM2m:
865       case X86Local::MRM3m:
866       case X86Local::MRM4m:
867       case X86Local::MRM5m:
868       case X86Local::MRM6m:
869       case X86Local::MRM7m:
870         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
871         break;
872       MRM_MAPPING
873       } // switch (Form)
874       break;
875     } // switch (Opcode)
876     opcodeToSet = Opcode;
877     break;
878   case X86Local::T8:
879   case X86Local::T8XD:
880   case X86Local::T8XS:
881     opcodeType = THREEBYTE_38;
882     switch (Opcode) {
883     default:
884       if (needsModRMForDecode(Form))
885         filter = new ModFilter(isRegFormat(Form));
886       else
887         filter = new DumbFilter();
888       break;
889 #define EXTENSION_TABLE(n) case 0x##n:
890     THREE_BYTE_38_EXTENSION_TABLES
891 #undef EXTENSION_TABLE
892       switch (Form) {
893       default:
894         llvm_unreachable("Unhandled two-byte extended opcode");
895       case X86Local::MRM0r:
896       case X86Local::MRM1r:
897       case X86Local::MRM2r:
898       case X86Local::MRM3r:
899       case X86Local::MRM4r:
900       case X86Local::MRM5r:
901       case X86Local::MRM6r:
902       case X86Local::MRM7r:
903         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
904         break;
905       case X86Local::MRM0m:
906       case X86Local::MRM1m:
907       case X86Local::MRM2m:
908       case X86Local::MRM3m:
909       case X86Local::MRM4m:
910       case X86Local::MRM5m:
911       case X86Local::MRM6m:
912       case X86Local::MRM7m:
913         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
914         break;
915       MRM_MAPPING
916       } // switch (Form)
917       break;
918     } // switch (Opcode)
919     opcodeToSet = Opcode;
920     break;
921   case X86Local::P_TA:
922   case X86Local::TAXD:
923     opcodeType = THREEBYTE_3A;
924     if (needsModRMForDecode(Form))
925       filter = new ModFilter(isRegFormat(Form));
926     else
927       filter = new DumbFilter();
928     opcodeToSet = Opcode;
929     break;
930   case X86Local::A6:
931     opcodeType = THREEBYTE_A6;
932     if (needsModRMForDecode(Form))
933       filter = new ModFilter(isRegFormat(Form));
934     else
935       filter = new DumbFilter();
936     opcodeToSet = Opcode;
937     break;
938   case X86Local::A7:
939     opcodeType = THREEBYTE_A7;
940     if (needsModRMForDecode(Form))
941       filter = new ModFilter(isRegFormat(Form));
942     else
943       filter = new DumbFilter();
944     opcodeToSet = Opcode;
945     break;
946   case X86Local::D8:
947   case X86Local::D9:
948   case X86Local::DA:
949   case X86Local::DB:
950   case X86Local::DC:
951   case X86Local::DD:
952   case X86Local::DE:
953   case X86Local::DF:
954     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
955     opcodeType = ONEBYTE;
956     if (Form == X86Local::AddRegFrm) {
957       Spec->modifierType = MODIFIER_MODRM;
958       Spec->modifierBase = Opcode;
959       filter = new AddRegEscapeFilter(Opcode);
960     } else {
961       filter = new EscapeFilter(true, Opcode);
962     }
963     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
964     break;
965   case X86Local::REP:
966   default:
967     opcodeType = ONEBYTE;
968     switch (Opcode) {
969 #define EXTENSION_TABLE(n) case 0x##n:
970     ONE_BYTE_EXTENSION_TABLES
971 #undef EXTENSION_TABLE
972       switch (Form) {
973       default:
974         llvm_unreachable("Fell through the cracks of a single-byte "
975                          "extended opcode");
976       case X86Local::MRM0r:
977       case X86Local::MRM1r:
978       case X86Local::MRM2r:
979       case X86Local::MRM3r:
980       case X86Local::MRM4r:
981       case X86Local::MRM5r:
982       case X86Local::MRM6r:
983       case X86Local::MRM7r:
984         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
985         break;
986       case X86Local::MRM0m:
987       case X86Local::MRM1m:
988       case X86Local::MRM2m:
989       case X86Local::MRM3m:
990       case X86Local::MRM4m:
991       case X86Local::MRM5m:
992       case X86Local::MRM6m:
993       case X86Local::MRM7m:
994         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
995         break;
996       MRM_MAPPING
997       } // switch (Form)
998       break;
999     case 0xd8:
1000     case 0xd9:
1001     case 0xda:
1002     case 0xdb:
1003     case 0xdc:
1004     case 0xdd:
1005     case 0xde:
1006     case 0xdf:
1007       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1008       break;
1009     default:
1010       if (needsModRMForDecode(Form))
1011         filter = new ModFilter(isRegFormat(Form));
1012       else
1013         filter = new DumbFilter();
1014       break;
1015     } // switch (Opcode)
1016     opcodeToSet = Opcode;
1017   } // switch (Prefix)
1018 
1019   assert(opcodeType != (OpcodeType)-1 &&
1020          "Opcode type not set");
1021   assert(filter && "Filter not set");
1022 
1023   if (Form == X86Local::AddRegFrm) {
1024     if(Spec->modifierType != MODIFIER_MODRM) {
1025       assert(opcodeToSet < 0xf9 &&
1026              "Not enough room for all ADDREG_FRM operands");
1027 
1028       uint8_t currentOpcode;
1029 
1030       for (currentOpcode = opcodeToSet;
1031            currentOpcode < opcodeToSet + 8;
1032            ++currentOpcode)
1033         tables.setTableFields(opcodeType,
1034                               insnContext(),
1035                               currentOpcode,
1036                               *filter,
1037                               UID, Is32Bit, IgnoresVEX_L);
1038 
1039       Spec->modifierType = MODIFIER_OPCODE;
1040       Spec->modifierBase = opcodeToSet;
1041     } else {
1042       // modifierBase was set where MODIFIER_MODRM was set
1043       tables.setTableFields(opcodeType,
1044                             insnContext(),
1045                             opcodeToSet,
1046                             *filter,
1047                             UID, Is32Bit, IgnoresVEX_L);
1048     }
1049   } else {
1050     tables.setTableFields(opcodeType,
1051                           insnContext(),
1052                           opcodeToSet,
1053                           *filter,
1054                           UID, Is32Bit, IgnoresVEX_L);
1055 
1056     Spec->modifierType = MODIFIER_NONE;
1057     Spec->modifierBase = opcodeToSet;
1058   }
1059 
1060   delete filter;
1061 
1062 #undef MAP
1063 }
1064 
1065 #define TYPE(str, type) if (s == str) return type;
1066 OperandType RecognizableInstr::typeFromString(const std::string &s,
1067                                               bool isSSE,
1068                                               bool hasREX_WPrefix,
1069                                               bool hasOpSizePrefix) {
1070   if (isSSE) {
1071     // For SSE instructions, we ignore the OpSize prefix and force operand
1072     // sizes.
1073     TYPE("GR16",              TYPE_R16)
1074     TYPE("GR32",              TYPE_R32)
1075     TYPE("GR64",              TYPE_R64)
1076   }
1077   if(hasREX_WPrefix) {
1078     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1079     // is special.
1080     TYPE("GR32",              TYPE_R32)
1081   }
1082   if(!hasOpSizePrefix) {
1083     // For instructions without an OpSize prefix, a declared 16-bit register or
1084     // immediate encoding is special.
1085     TYPE("GR16",              TYPE_R16)
1086     TYPE("i16imm",            TYPE_IMM16)
1087   }
1088   TYPE("i16mem",              TYPE_Mv)
1089   TYPE("i16imm",              TYPE_IMMv)
1090   TYPE("i16i8imm",            TYPE_IMMv)
1091   TYPE("GR16",                TYPE_Rv)
1092   TYPE("i32mem",              TYPE_Mv)
1093   TYPE("i32imm",              TYPE_IMMv)
1094   TYPE("i32i8imm",            TYPE_IMM32)
1095   TYPE("u32u8imm",            TYPE_IMM32)
1096   TYPE("GR32",                TYPE_Rv)
1097   TYPE("i64mem",              TYPE_Mv)
1098   TYPE("i64i32imm",           TYPE_IMM64)
1099   TYPE("i64i8imm",            TYPE_IMM64)
1100   TYPE("GR64",                TYPE_R64)
1101   TYPE("i8mem",               TYPE_M8)
1102   TYPE("i8imm",               TYPE_IMM8)
1103   TYPE("GR8",                 TYPE_R8)
1104   TYPE("VR128",               TYPE_XMM128)
1105   TYPE("f128mem",             TYPE_M128)
1106   TYPE("f256mem",             TYPE_M256)
1107   TYPE("FR64",                TYPE_XMM64)
1108   TYPE("f64mem",              TYPE_M64FP)
1109   TYPE("sdmem",               TYPE_M64FP)
1110   TYPE("FR32",                TYPE_XMM32)
1111   TYPE("f32mem",              TYPE_M32FP)
1112   TYPE("ssmem",               TYPE_M32FP)
1113   TYPE("RST",                 TYPE_ST)
1114   TYPE("i128mem",             TYPE_M128)
1115   TYPE("i256mem",             TYPE_M256)
1116   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1117   TYPE("i16imm_pcrel",        TYPE_REL16)
1118   TYPE("i32imm_pcrel",        TYPE_REL32)
1119   TYPE("SSECC",               TYPE_IMM3)
1120   TYPE("brtarget",            TYPE_RELv)
1121   TYPE("uncondbrtarget",      TYPE_RELv)
1122   TYPE("brtarget8",           TYPE_REL8)
1123   TYPE("f80mem",              TYPE_M80FP)
1124   TYPE("lea32mem",            TYPE_LEA)
1125   TYPE("lea64_32mem",         TYPE_LEA)
1126   TYPE("lea64mem",            TYPE_LEA)
1127   TYPE("VR64",                TYPE_MM64)
1128   TYPE("i64imm",              TYPE_IMMv)
1129   TYPE("opaque32mem",         TYPE_M1616)
1130   TYPE("opaque48mem",         TYPE_M1632)
1131   TYPE("opaque80mem",         TYPE_M1664)
1132   TYPE("opaque512mem",        TYPE_M512)
1133   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1134   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1135   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1136   TYPE("offset8",             TYPE_MOFFS8)
1137   TYPE("offset16",            TYPE_MOFFS16)
1138   TYPE("offset32",            TYPE_MOFFS32)
1139   TYPE("offset64",            TYPE_MOFFS64)
1140   TYPE("VR256",               TYPE_XMM256)
1141   TYPE("GR16_NOAX",           TYPE_Rv)
1142   TYPE("GR32_NOAX",           TYPE_Rv)
1143   TYPE("GR64_NOAX",           TYPE_R64)
1144   errs() << "Unhandled type string " << s << "\n";
1145   llvm_unreachable("Unhandled type string");
1146 }
1147 #undef TYPE
1148 
1149 #define ENCODING(str, encoding) if (s == str) return encoding;
1150 OperandEncoding RecognizableInstr::immediateEncodingFromString
1151   (const std::string &s,
1152    bool hasOpSizePrefix) {
1153   if(!hasOpSizePrefix) {
1154     // For instructions without an OpSize prefix, a declared 16-bit register or
1155     // immediate encoding is special.
1156     ENCODING("i16imm",        ENCODING_IW)
1157   }
1158   ENCODING("i32i8imm",        ENCODING_IB)
1159   ENCODING("u32u8imm",        ENCODING_IB)
1160   ENCODING("SSECC",           ENCODING_IB)
1161   ENCODING("i16imm",          ENCODING_Iv)
1162   ENCODING("i16i8imm",        ENCODING_IB)
1163   ENCODING("i32imm",          ENCODING_Iv)
1164   ENCODING("i64i32imm",       ENCODING_ID)
1165   ENCODING("i64i8imm",        ENCODING_IB)
1166   ENCODING("i8imm",           ENCODING_IB)
1167   // This is not a typo.  Instructions like BLENDVPD put
1168   // register IDs in 8-bit immediates nowadays.
1169   ENCODING("VR256",           ENCODING_IB)
1170   ENCODING("VR128",           ENCODING_IB)
1171   errs() << "Unhandled immediate encoding " << s << "\n";
1172   llvm_unreachable("Unhandled immediate encoding");
1173 }
1174 
1175 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1176   (const std::string &s,
1177    bool hasOpSizePrefix) {
1178   ENCODING("GR16",            ENCODING_RM)
1179   ENCODING("GR32",            ENCODING_RM)
1180   ENCODING("GR64",            ENCODING_RM)
1181   ENCODING("GR8",             ENCODING_RM)
1182   ENCODING("VR128",           ENCODING_RM)
1183   ENCODING("FR64",            ENCODING_RM)
1184   ENCODING("FR32",            ENCODING_RM)
1185   ENCODING("VR64",            ENCODING_RM)
1186   ENCODING("VR256",           ENCODING_RM)
1187   errs() << "Unhandled R/M register encoding " << s << "\n";
1188   llvm_unreachable("Unhandled R/M register encoding");
1189 }
1190 
1191 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1192   (const std::string &s,
1193    bool hasOpSizePrefix) {
1194   ENCODING("GR16",            ENCODING_REG)
1195   ENCODING("GR32",            ENCODING_REG)
1196   ENCODING("GR64",            ENCODING_REG)
1197   ENCODING("GR8",             ENCODING_REG)
1198   ENCODING("VR128",           ENCODING_REG)
1199   ENCODING("FR64",            ENCODING_REG)
1200   ENCODING("FR32",            ENCODING_REG)
1201   ENCODING("VR64",            ENCODING_REG)
1202   ENCODING("SEGMENT_REG",     ENCODING_REG)
1203   ENCODING("DEBUG_REG",       ENCODING_REG)
1204   ENCODING("CONTROL_REG",     ENCODING_REG)
1205   ENCODING("VR256",           ENCODING_REG)
1206   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1207   llvm_unreachable("Unhandled reg/opcode register encoding");
1208 }
1209 
1210 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1211   (const std::string &s,
1212    bool hasOpSizePrefix) {
1213   ENCODING("GR32",            ENCODING_VVVV)
1214   ENCODING("GR64",            ENCODING_VVVV)
1215   ENCODING("FR32",            ENCODING_VVVV)
1216   ENCODING("FR64",            ENCODING_VVVV)
1217   ENCODING("VR128",           ENCODING_VVVV)
1218   ENCODING("VR256",           ENCODING_VVVV)
1219   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1220   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1221 }
1222 
1223 OperandEncoding RecognizableInstr::memoryEncodingFromString
1224   (const std::string &s,
1225    bool hasOpSizePrefix) {
1226   ENCODING("i16mem",          ENCODING_RM)
1227   ENCODING("i32mem",          ENCODING_RM)
1228   ENCODING("i64mem",          ENCODING_RM)
1229   ENCODING("i8mem",           ENCODING_RM)
1230   ENCODING("ssmem",           ENCODING_RM)
1231   ENCODING("sdmem",           ENCODING_RM)
1232   ENCODING("f128mem",         ENCODING_RM)
1233   ENCODING("f256mem",         ENCODING_RM)
1234   ENCODING("f64mem",          ENCODING_RM)
1235   ENCODING("f32mem",          ENCODING_RM)
1236   ENCODING("i128mem",         ENCODING_RM)
1237   ENCODING("i256mem",         ENCODING_RM)
1238   ENCODING("f80mem",          ENCODING_RM)
1239   ENCODING("lea32mem",        ENCODING_RM)
1240   ENCODING("lea64_32mem",     ENCODING_RM)
1241   ENCODING("lea64mem",        ENCODING_RM)
1242   ENCODING("opaque32mem",     ENCODING_RM)
1243   ENCODING("opaque48mem",     ENCODING_RM)
1244   ENCODING("opaque80mem",     ENCODING_RM)
1245   ENCODING("opaque512mem",    ENCODING_RM)
1246   errs() << "Unhandled memory encoding " << s << "\n";
1247   llvm_unreachable("Unhandled memory encoding");
1248 }
1249 
1250 OperandEncoding RecognizableInstr::relocationEncodingFromString
1251   (const std::string &s,
1252    bool hasOpSizePrefix) {
1253   if(!hasOpSizePrefix) {
1254     // For instructions without an OpSize prefix, a declared 16-bit register or
1255     // immediate encoding is special.
1256     ENCODING("i16imm",        ENCODING_IW)
1257   }
1258   ENCODING("i16imm",          ENCODING_Iv)
1259   ENCODING("i16i8imm",        ENCODING_IB)
1260   ENCODING("i32imm",          ENCODING_Iv)
1261   ENCODING("i32i8imm",        ENCODING_IB)
1262   ENCODING("i64i32imm",       ENCODING_ID)
1263   ENCODING("i64i8imm",        ENCODING_IB)
1264   ENCODING("i8imm",           ENCODING_IB)
1265   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1266   ENCODING("i16imm_pcrel",    ENCODING_IW)
1267   ENCODING("i32imm_pcrel",    ENCODING_ID)
1268   ENCODING("brtarget",        ENCODING_Iv)
1269   ENCODING("brtarget8",       ENCODING_IB)
1270   ENCODING("i64imm",          ENCODING_IO)
1271   ENCODING("offset8",         ENCODING_Ia)
1272   ENCODING("offset16",        ENCODING_Ia)
1273   ENCODING("offset32",        ENCODING_Ia)
1274   ENCODING("offset64",        ENCODING_Ia)
1275   errs() << "Unhandled relocation encoding " << s << "\n";
1276   llvm_unreachable("Unhandled relocation encoding");
1277 }
1278 
1279 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1280   (const std::string &s,
1281    bool hasOpSizePrefix) {
1282   ENCODING("RST",             ENCODING_I)
1283   ENCODING("GR32",            ENCODING_Rv)
1284   ENCODING("GR64",            ENCODING_RO)
1285   ENCODING("GR16",            ENCODING_Rv)
1286   ENCODING("GR8",             ENCODING_RB)
1287   ENCODING("GR16_NOAX",       ENCODING_Rv)
1288   ENCODING("GR32_NOAX",       ENCODING_Rv)
1289   ENCODING("GR64_NOAX",       ENCODING_RO)
1290   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1291   llvm_unreachable("Unhandled opcode modifier encoding");
1292 }
1293 #undef ENCODING
1294