1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22 
23 using namespace llvm;
24 
25 #define MRM_MAPPING     \
26   MAP(C1, 33)           \
27   MAP(C2, 34)           \
28   MAP(C3, 35)           \
29   MAP(C4, 36)           \
30   MAP(C8, 37)           \
31   MAP(C9, 38)           \
32   MAP(CA, 39)           \
33   MAP(CB, 40)           \
34   MAP(E8, 41)           \
35   MAP(F0, 42)           \
36   MAP(F8, 45)           \
37   MAP(F9, 46)           \
38   MAP(D0, 47)           \
39   MAP(D1, 48)           \
40   MAP(D4, 49)           \
41   MAP(D5, 50)           \
42   MAP(D6, 51)           \
43   MAP(D8, 52)           \
44   MAP(D9, 53)           \
45   MAP(DA, 54)           \
46   MAP(DB, 55)           \
47   MAP(DC, 56)           \
48   MAP(DD, 57)           \
49   MAP(DE, 58)           \
50   MAP(DF, 59)
51 
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54   enum {
55     Pseudo      = 0,
56     RawFrm      = 1,
57     AddRegFrm   = 2,
58     MRMDestReg  = 3,
59     MRMDestMem  = 4,
60     MRMSrcReg   = 5,
61     MRMSrcMem   = 6,
62     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66     MRMInitReg  = 32,
67     RawFrmImm8  = 43,
68     RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70     MRM_MAPPING
71 #undef MAP
72     lastMRM
73   };
74 
75   enum {
76     TB  = 1,
77     REP = 2,
78     D8 = 3, D9 = 4, DA = 5, DB = 6,
79     DC = 7, DD = 8, DE = 9, DF = 10,
80     XD = 11,  XS = 12,
81     T8 = 13,  P_TA = 14,
82     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83     XOP8 = 20, XOP9 = 21, XOPA = 22
84   };
85 }
86 
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
103 
104 #define ONE_BYTE_EXTENSION_TABLES \
105   EXTENSION_TABLE(80)             \
106   EXTENSION_TABLE(81)             \
107   EXTENSION_TABLE(82)             \
108   EXTENSION_TABLE(83)             \
109   EXTENSION_TABLE(8f)             \
110   EXTENSION_TABLE(c0)             \
111   EXTENSION_TABLE(c1)             \
112   EXTENSION_TABLE(c6)             \
113   EXTENSION_TABLE(c7)             \
114   EXTENSION_TABLE(d0)             \
115   EXTENSION_TABLE(d1)             \
116   EXTENSION_TABLE(d2)             \
117   EXTENSION_TABLE(d3)             \
118   EXTENSION_TABLE(f6)             \
119   EXTENSION_TABLE(f7)             \
120   EXTENSION_TABLE(fe)             \
121   EXTENSION_TABLE(ff)
122 
123 #define TWO_BYTE_EXTENSION_TABLES \
124   EXTENSION_TABLE(00)             \
125   EXTENSION_TABLE(01)             \
126   EXTENSION_TABLE(0d)             \
127   EXTENSION_TABLE(18)             \
128   EXTENSION_TABLE(71)             \
129   EXTENSION_TABLE(72)             \
130   EXTENSION_TABLE(73)             \
131   EXTENSION_TABLE(ae)             \
132   EXTENSION_TABLE(ba)             \
133   EXTENSION_TABLE(c7)
134 
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136   EXTENSION_TABLE(F3)
137 
138 #define XOP9_MAP_EXTENSION_TABLES \
139   EXTENSION_TABLE(01)             \
140   EXTENSION_TABLE(02)
141 
142 using namespace X86Disassembler;
143 
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
146 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 ///   0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return     - true if the form implies that a ModR/M byte is required, false
151 ///               otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153   if (form == X86Local::MRMDestReg    ||
154      form == X86Local::MRMDestMem    ||
155      form == X86Local::MRMSrcReg     ||
156      form == X86Local::MRMSrcMem     ||
157      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159     return true;
160   else
161     return false;
162 }
163 
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 ///   the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return     - true if the form implies that Mod must be 0b11, false
169 ///               otherwise.
170 static bool isRegFormat(uint8_t form) {
171   if (form == X86Local::MRMDestReg ||
172      form == X86Local::MRMSrcReg  ||
173      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174     return true;
175   else
176     return false;
177 }
178 
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 ///   Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return     - The field, with the first bit in the BitsInit as the lowest
184 ///               order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186   int width = init.getNumBits();
187 
188   assert(width <= 8 && "Field is too large for uint8_t!");
189 
190   int     index;
191   uint8_t mask = 0x01;
192 
193   uint8_t ret = 0;
194 
195   for (index = 0; index < width; index++) {
196     if (static_cast<BitInit*>(init.getBit(index))->getValue())
197       ret |= mask;
198 
199     mask <<= 1;
200   }
201 
202   return ret;
203 }
204 
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 ///   name of the field.
207 ///
208 /// @param rec  - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return     - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212   BitsInit* bits = rec->getValueAsBitsInit(name);
213   return byteFromBitsInit(*bits);
214 }
215 
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217                                      const CodeGenInstruction &insn,
218                                      InstrUID uid) {
219   UID = uid;
220 
221   Rec = insn.TheDef;
222   Name = Rec->getName();
223   Spec = &tables.specForUID(UID);
224 
225   if (!Rec->isSubClassOf("X86Inst")) {
226     ShouldBeEmitted = false;
227     return;
228   }
229 
230   Prefix   = byteFromRec(Rec, "Prefix");
231   Opcode   = byteFromRec(Rec, "Opcode");
232   Form     = byteFromRec(Rec, "FormBits");
233   SegOvr   = byteFromRec(Rec, "SegOvrBits");
234 
235   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
236   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
237   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
238   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
239   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
240   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
242   HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
243   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
244   HasEVEXPrefix    = Rec->getValueAsBit("hasEVEXPrefix");
245   HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246   HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
247   HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
248   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
249   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
250 
251   Name      = Rec->getName();
252   AsmString = Rec->getValueAsString("AsmString");
253 
254   Operands = &insn.Operands.OperandList;
255 
256   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
257                      (Name.find("CRC32") != Name.npos);
258   HasFROperands    = hasFROperands();
259   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
260 
261   // Check for 64-bit inst which does not require REX
262   Is32Bit = false;
263   Is64Bit = false;
264   // FIXME: Is there some better way to check for In64BitMode?
265   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
268       Is32Bit = true;
269       break;
270     }
271     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
272       Is64Bit = true;
273       break;
274     }
275   }
276   // FIXME: These instructions aren't marked as 64-bit in any way
277   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
278              Rec->getName() == "MASKMOVDQU64" ||
279              Rec->getName() == "POPFS64" ||
280              Rec->getName() == "POPGS64" ||
281              Rec->getName() == "PUSHFS64" ||
282              Rec->getName() == "PUSHGS64" ||
283              Rec->getName() == "REX64_PREFIX" ||
284              Rec->getName().find("MOV64") != Name.npos ||
285              Rec->getName().find("PUSH64") != Name.npos ||
286              Rec->getName().find("POP64") != Name.npos;
287 
288   ShouldBeEmitted  = true;
289 }
290 
291 void RecognizableInstr::processInstr(DisassemblerTables &tables,
292                                      const CodeGenInstruction &insn,
293                                      InstrUID uid)
294 {
295   // Ignore "asm parser only" instructions.
296   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
297     return;
298 
299   RecognizableInstr recogInstr(tables, insn, uid);
300 
301   recogInstr.emitInstructionSpecifier(tables);
302 
303   if (recogInstr.shouldBeEmitted())
304     recogInstr.emitDecodePath(tables);
305 }
306 
307 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
308                     (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
309 
310 InstructionContext RecognizableInstr::insnContext() const {
311   InstructionContext insnContext;
312 
313   if (HasEVEXPrefix) {
314     if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
315       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
316       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
317     }
318     // VEX_L & VEX_W
319     if (HasVEX_LPrefix && HasVEX_WPrefix) {
320       if (HasOpSizePrefix)
321         insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
322       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
323         insnContext = EVEX_KB(IC_EVEX_L_W_XS);
324       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
325                Prefix == X86Local::TAXD)
326         insnContext = EVEX_KB(IC_EVEX_L_W_XD);
327       else
328         insnContext = EVEX_KB(IC_EVEX_L_W);
329     } else if (HasVEX_LPrefix) {
330       // VEX_L
331       if (HasOpSizePrefix)
332         insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
333       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
334         insnContext = EVEX_KB(IC_EVEX_L_XS);
335       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
336                Prefix == X86Local::TAXD)
337         insnContext = EVEX_KB(IC_EVEX_L_XD);
338       else
339         insnContext = EVEX_KB(IC_EVEX_L);
340     }
341     else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
342       // EVEX_L2 & VEX_W
343       if (HasOpSizePrefix)
344         insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
345       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
346         insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
347       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
348                Prefix == X86Local::TAXD)
349         insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
350       else
351         insnContext = EVEX_KB(IC_EVEX_L2_W);
352     } else if (HasEVEX_L2Prefix) {
353       // EVEX_L2
354       if (HasOpSizePrefix)
355         insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
356       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357           Prefix == X86Local::TAXD)
358         insnContext = EVEX_KB(IC_EVEX_L2_XD);
359       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360         insnContext = EVEX_KB(IC_EVEX_L2_XS);
361       else
362         insnContext = EVEX_KB(IC_EVEX_L2);
363     }
364     else if (HasVEX_WPrefix) {
365       // VEX_W
366       if (HasOpSizePrefix)
367         insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
368       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
369         insnContext = EVEX_KB(IC_EVEX_W_XS);
370       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
371                Prefix == X86Local::TAXD)
372         insnContext = EVEX_KB(IC_EVEX_W_XD);
373       else
374         insnContext = EVEX_KB(IC_EVEX_W);
375     }
376     // No L, no W
377     else if (HasOpSizePrefix)
378       insnContext = EVEX_KB(IC_EVEX_OPSIZE);
379     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
380              Prefix == X86Local::TAXD)
381       insnContext = EVEX_KB(IC_EVEX_XD);
382     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
383       insnContext = EVEX_KB(IC_EVEX_XS);
384     else
385       insnContext = EVEX_KB(IC_EVEX);
386     /// eof EVEX
387   } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
388     if (HasVEX_LPrefix && HasVEX_WPrefix) {
389       if (HasOpSizePrefix)
390         insnContext = IC_VEX_L_W_OPSIZE;
391       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392         insnContext = IC_VEX_L_W_XS;
393       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394                Prefix == X86Local::TAXD)
395         insnContext = IC_VEX_L_W_XD;
396       else
397         insnContext = IC_VEX_L_W;
398     } else if (HasOpSizePrefix && HasVEX_LPrefix)
399       insnContext = IC_VEX_L_OPSIZE;
400     else if (HasOpSizePrefix && HasVEX_WPrefix)
401       insnContext = IC_VEX_W_OPSIZE;
402     else if (HasOpSizePrefix)
403       insnContext = IC_VEX_OPSIZE;
404     else if (HasVEX_LPrefix &&
405              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406       insnContext = IC_VEX_L_XS;
407     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
408                                 Prefix == X86Local::T8XD ||
409                                 Prefix == X86Local::TAXD))
410       insnContext = IC_VEX_L_XD;
411     else if (HasVEX_WPrefix &&
412              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
413       insnContext = IC_VEX_W_XS;
414     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
415                                 Prefix == X86Local::T8XD ||
416                                 Prefix == X86Local::TAXD))
417       insnContext = IC_VEX_W_XD;
418     else if (HasVEX_WPrefix)
419       insnContext = IC_VEX_W;
420     else if (HasVEX_LPrefix)
421       insnContext = IC_VEX_L;
422     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
423              Prefix == X86Local::TAXD)
424       insnContext = IC_VEX_XD;
425     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
426       insnContext = IC_VEX_XS;
427     else
428       insnContext = IC_VEX;
429   } else if (Is64Bit || HasREX_WPrefix) {
430     if (HasREX_WPrefix && HasOpSizePrefix)
431       insnContext = IC_64BIT_REXW_OPSIZE;
432     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
433                                  Prefix == X86Local::T8XD ||
434                                  Prefix == X86Local::TAXD))
435       insnContext = IC_64BIT_XD_OPSIZE;
436     else if (HasOpSizePrefix &&
437              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438       insnContext = IC_64BIT_XS_OPSIZE;
439     else if (HasOpSizePrefix)
440       insnContext = IC_64BIT_OPSIZE;
441     else if (HasAdSizePrefix)
442       insnContext = IC_64BIT_ADSIZE;
443     else if (HasREX_WPrefix &&
444              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
445       insnContext = IC_64BIT_REXW_XS;
446     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
447                                 Prefix == X86Local::T8XD ||
448                                 Prefix == X86Local::TAXD))
449       insnContext = IC_64BIT_REXW_XD;
450     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
451              Prefix == X86Local::TAXD)
452       insnContext = IC_64BIT_XD;
453     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
454       insnContext = IC_64BIT_XS;
455     else if (HasREX_WPrefix)
456       insnContext = IC_64BIT_REXW;
457     else
458       insnContext = IC_64BIT;
459   } else {
460     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
461                             Prefix == X86Local::T8XD ||
462                             Prefix == X86Local::TAXD))
463       insnContext = IC_XD_OPSIZE;
464     else if (HasOpSizePrefix &&
465              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
466       insnContext = IC_XS_OPSIZE;
467     else if (HasOpSizePrefix)
468       insnContext = IC_OPSIZE;
469     else if (HasAdSizePrefix)
470       insnContext = IC_ADSIZE;
471     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
472              Prefix == X86Local::TAXD)
473       insnContext = IC_XD;
474     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
475              Prefix == X86Local::REP)
476       insnContext = IC_XS;
477     else
478       insnContext = IC;
479   }
480 
481   return insnContext;
482 }
483 
484 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
485   ///////////////////
486   // FILTER_STRONG
487   //
488 
489   // Filter out intrinsics
490 
491   assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
492 
493   if (Form == X86Local::Pseudo ||
494       (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
495        Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
496     return FILTER_STRONG;
497 
498 
499   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
500   // printed as a separate "instruction".
501 
502   if (Name.find("_Int") != Name.npos       ||
503       Name.find("Int_") != Name.npos)
504     return FILTER_STRONG;
505 
506   // Filter out instructions with segment override prefixes.
507   // They're too messy to handle now and we'll special case them if needed.
508 
509   if (SegOvr)
510     return FILTER_STRONG;
511 
512 
513   /////////////////
514   // FILTER_WEAK
515   //
516 
517 
518   // Filter out instructions with a LOCK prefix;
519   //   prefer forms that do not have the prefix
520   if (HasLockPrefix)
521     return FILTER_WEAK;
522 
523   // Filter out alternate forms of AVX instructions
524   if (Name.find("_alt") != Name.npos ||
525       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
526       Name.find("_64mr") != Name.npos ||
527       Name.find("rr64") != Name.npos)
528     return FILTER_WEAK;
529 
530   // Special cases.
531 
532   if (Name == "PUSH64i16"         ||
533       Name == "MOVPQI2QImr"       ||
534       Name == "VMOVPQI2QImr"      ||
535       Name == "VMASKMOVDQU64")
536     return FILTER_WEAK;
537 
538   // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
539   // For now, just prefer the REP versions.
540   if (Name == "XACQUIRE_PREFIX" ||
541       Name == "XRELEASE_PREFIX")
542     return FILTER_WEAK;
543 
544   return FILTER_NORMAL;
545 }
546 
547 bool RecognizableInstr::hasFROperands() const {
548   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
549   unsigned numOperands = OperandList.size();
550 
551   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
552     const std::string &recName = OperandList[operandIndex].Rec->getName();
553 
554     if (recName.find("FR") != recName.npos)
555       return true;
556   }
557   return false;
558 }
559 
560 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
561                                       unsigned &physicalOperandIndex,
562                                       unsigned &numPhysicalOperands,
563                                       const unsigned *operandMapping,
564                                       OperandEncoding (*encodingFromString)
565                                         (const std::string&,
566                                          bool hasOpSizePrefix)) {
567   if (optional) {
568     if (physicalOperandIndex >= numPhysicalOperands)
569       return;
570   } else {
571     assert(physicalOperandIndex < numPhysicalOperands);
572   }
573 
574   while (operandMapping[operandIndex] != operandIndex) {
575     Spec->operands[operandIndex].encoding = ENCODING_DUP;
576     Spec->operands[operandIndex].type =
577       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
578     ++operandIndex;
579   }
580 
581   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
582 
583   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
584                                                               HasOpSizePrefix);
585   Spec->operands[operandIndex].type = typeFromString(typeName,
586                                                      IsSSE,
587                                                      HasREX_WPrefix,
588                                                      HasOpSizePrefix);
589 
590   ++operandIndex;
591   ++physicalOperandIndex;
592 }
593 
594 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
595   Spec->name       = Name;
596 
597   if (!ShouldBeEmitted)
598     return;
599 
600   switch (filter()) {
601   case FILTER_WEAK:
602     Spec->filtered = true;
603     break;
604   case FILTER_STRONG:
605     ShouldBeEmitted = false;
606     return;
607   case FILTER_NORMAL:
608     break;
609   }
610 
611   Spec->insnContext = insnContext();
612 
613   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
614 
615   unsigned numOperands = OperandList.size();
616   unsigned numPhysicalOperands = 0;
617 
618   // operandMapping maps from operands in OperandList to their originals.
619   // If operandMapping[i] != i, then the entry is a duplicate.
620   unsigned operandMapping[X86_MAX_OPERANDS];
621   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
622 
623   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
624     if (OperandList[operandIndex].Constraints.size()) {
625       const CGIOperandList::ConstraintInfo &Constraint =
626         OperandList[operandIndex].Constraints[0];
627       if (Constraint.isTied()) {
628         operandMapping[operandIndex] = operandIndex;
629         operandMapping[Constraint.getTiedOperand()] = operandIndex;
630       } else {
631         ++numPhysicalOperands;
632         operandMapping[operandIndex] = operandIndex;
633       }
634     } else {
635       ++numPhysicalOperands;
636       operandMapping[operandIndex] = operandIndex;
637     }
638   }
639 
640 #define HANDLE_OPERAND(class)               \
641   handleOperand(false,                      \
642                 operandIndex,               \
643                 physicalOperandIndex,       \
644                 numPhysicalOperands,        \
645                 operandMapping,             \
646                 class##EncodingFromString);
647 
648 #define HANDLE_OPTIONAL(class)              \
649   handleOperand(true,                       \
650                 operandIndex,               \
651                 physicalOperandIndex,       \
652                 numPhysicalOperands,        \
653                 operandMapping,             \
654                 class##EncodingFromString);
655 
656   // operandIndex should always be < numOperands
657   unsigned operandIndex = 0;
658   // physicalOperandIndex should always be < numPhysicalOperands
659   unsigned physicalOperandIndex = 0;
660 
661   switch (Form) {
662   case X86Local::RawFrm:
663     // Operand 1 (optional) is an address or immediate.
664     // Operand 2 (optional) is an immediate.
665     assert(numPhysicalOperands <= 2 &&
666            "Unexpected number of operands for RawFrm");
667     HANDLE_OPTIONAL(relocation)
668     HANDLE_OPTIONAL(immediate)
669     break;
670   case X86Local::AddRegFrm:
671     // Operand 1 is added to the opcode.
672     // Operand 2 (optional) is an address.
673     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
674            "Unexpected number of operands for AddRegFrm");
675     HANDLE_OPERAND(opcodeModifier)
676     HANDLE_OPTIONAL(relocation)
677     break;
678   case X86Local::MRMDestReg:
679     // Operand 1 is a register operand in the R/M field.
680     // Operand 2 is a register operand in the Reg/Opcode field.
681     // - In AVX, there is a register operand in the VEX.vvvv field here -
682     // Operand 3 (optional) is an immediate.
683     if (HasVEX_4VPrefix)
684       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
685              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
686     else
687       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
688              "Unexpected number of operands for MRMDestRegFrm");
689 
690     HANDLE_OPERAND(rmRegister)
691 
692     if (HasVEX_4VPrefix)
693       // FIXME: In AVX, the register below becomes the one encoded
694       // in ModRMVEX and the one above the one in the VEX.VVVV field
695       HANDLE_OPERAND(vvvvRegister)
696 
697     HANDLE_OPERAND(roRegister)
698     HANDLE_OPTIONAL(immediate)
699     break;
700   case X86Local::MRMDestMem:
701     // Operand 1 is a memory operand (possibly SIB-extended)
702     // Operand 2 is a register operand in the Reg/Opcode field.
703     // - In AVX, there is a register operand in the VEX.vvvv field here -
704     // Operand 3 (optional) is an immediate.
705     if (HasVEX_4VPrefix)
706       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
707              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
708     else
709       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
710              "Unexpected number of operands for MRMDestMemFrm");
711     HANDLE_OPERAND(memory)
712 
713     if (HasEVEX_K)
714       HANDLE_OPERAND(writemaskRegister)
715 
716     if (HasVEX_4VPrefix)
717       // FIXME: In AVX, the register below becomes the one encoded
718       // in ModRMVEX and the one above the one in the VEX.VVVV field
719       HANDLE_OPERAND(vvvvRegister)
720 
721     HANDLE_OPERAND(roRegister)
722     HANDLE_OPTIONAL(immediate)
723     break;
724   case X86Local::MRMSrcReg:
725     // Operand 1 is a register operand in the Reg/Opcode field.
726     // Operand 2 is a register operand in the R/M field.
727     // - In AVX, there is a register operand in the VEX.vvvv field here -
728     // Operand 3 (optional) is an immediate.
729     // Operand 4 (optional) is an immediate.
730 
731     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
732       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
733              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
734     else
735       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
736              "Unexpected number of operands for MRMSrcRegFrm");
737 
738     HANDLE_OPERAND(roRegister)
739 
740     if (HasEVEX_K)
741       HANDLE_OPERAND(writemaskRegister)
742 
743     if (HasVEX_4VPrefix)
744       // FIXME: In AVX, the register below becomes the one encoded
745       // in ModRMVEX and the one above the one in the VEX.VVVV field
746       HANDLE_OPERAND(vvvvRegister)
747 
748     if (HasMemOp4Prefix)
749       HANDLE_OPERAND(immediate)
750 
751     HANDLE_OPERAND(rmRegister)
752 
753     if (HasVEX_4VOp3Prefix)
754       HANDLE_OPERAND(vvvvRegister)
755 
756     if (!HasMemOp4Prefix)
757       HANDLE_OPTIONAL(immediate)
758     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
759     HANDLE_OPTIONAL(immediate)
760     break;
761   case X86Local::MRMSrcMem:
762     // Operand 1 is a register operand in the Reg/Opcode field.
763     // Operand 2 is a memory operand (possibly SIB-extended)
764     // - In AVX, there is a register operand in the VEX.vvvv field here -
765     // Operand 3 (optional) is an immediate.
766 
767     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
768       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
769              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
770     else
771       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
772              "Unexpected number of operands for MRMSrcMemFrm");
773 
774     HANDLE_OPERAND(roRegister)
775 
776     if (HasEVEX_K)
777       HANDLE_OPERAND(writemaskRegister)
778 
779     if (HasVEX_4VPrefix)
780       // FIXME: In AVX, the register below becomes the one encoded
781       // in ModRMVEX and the one above the one in the VEX.VVVV field
782       HANDLE_OPERAND(vvvvRegister)
783 
784     if (HasMemOp4Prefix)
785       HANDLE_OPERAND(immediate)
786 
787     HANDLE_OPERAND(memory)
788 
789     if (HasVEX_4VOp3Prefix)
790       HANDLE_OPERAND(vvvvRegister)
791 
792     if (!HasMemOp4Prefix)
793       HANDLE_OPTIONAL(immediate)
794     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
795     break;
796   case X86Local::MRM0r:
797   case X86Local::MRM1r:
798   case X86Local::MRM2r:
799   case X86Local::MRM3r:
800   case X86Local::MRM4r:
801   case X86Local::MRM5r:
802   case X86Local::MRM6r:
803   case X86Local::MRM7r:
804     {
805       // Operand 1 is a register operand in the R/M field.
806       // Operand 2 (optional) is an immediate or relocation.
807       // Operand 3 (optional) is an immediate.
808       unsigned kOp = (HasEVEX_K) ? 1:0;
809       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
810       if (numPhysicalOperands > 3 + kOp + Op4v)
811         llvm_unreachable("Unexpected number of operands for MRMnr");
812     }
813     if (HasVEX_4VPrefix)
814       HANDLE_OPERAND(vvvvRegister)
815 
816     if (HasEVEX_K)
817       HANDLE_OPERAND(writemaskRegister)
818     HANDLE_OPTIONAL(rmRegister)
819     HANDLE_OPTIONAL(relocation)
820     HANDLE_OPTIONAL(immediate)
821     break;
822   case X86Local::MRM0m:
823   case X86Local::MRM1m:
824   case X86Local::MRM2m:
825   case X86Local::MRM3m:
826   case X86Local::MRM4m:
827   case X86Local::MRM5m:
828   case X86Local::MRM6m:
829   case X86Local::MRM7m:
830     {
831       // Operand 1 is a memory operand (possibly SIB-extended)
832       // Operand 2 (optional) is an immediate or relocation.
833       unsigned kOp = (HasEVEX_K) ? 1:0;
834       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
835       if (numPhysicalOperands < 1 + kOp + Op4v ||
836           numPhysicalOperands > 2 + kOp + Op4v)
837         llvm_unreachable("Unexpected number of operands for MRMnm");
838     }
839     if (HasVEX_4VPrefix)
840       HANDLE_OPERAND(vvvvRegister)
841     if (HasEVEX_K)
842       HANDLE_OPERAND(writemaskRegister)
843     HANDLE_OPERAND(memory)
844     HANDLE_OPTIONAL(relocation)
845     break;
846   case X86Local::RawFrmImm8:
847     // operand 1 is a 16-bit immediate
848     // operand 2 is an 8-bit immediate
849     assert(numPhysicalOperands == 2 &&
850            "Unexpected number of operands for X86Local::RawFrmImm8");
851     HANDLE_OPERAND(immediate)
852     HANDLE_OPERAND(immediate)
853     break;
854   case X86Local::RawFrmImm16:
855     // operand 1 is a 16-bit immediate
856     // operand 2 is a 16-bit immediate
857     HANDLE_OPERAND(immediate)
858     HANDLE_OPERAND(immediate)
859     break;
860   case X86Local::MRM_F8:
861     if (Opcode == 0xc6) {
862       assert(numPhysicalOperands == 1 &&
863              "Unexpected number of operands for X86Local::MRM_F8");
864       HANDLE_OPERAND(immediate)
865     } else if (Opcode == 0xc7) {
866       assert(numPhysicalOperands == 1 &&
867              "Unexpected number of operands for X86Local::MRM_F8");
868       HANDLE_OPERAND(relocation)
869     }
870     break;
871   case X86Local::MRMInitReg:
872     // Ignored.
873     break;
874   }
875 
876   #undef HANDLE_OPERAND
877   #undef HANDLE_OPTIONAL
878 }
879 
880 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
881   // Special cases where the LLVM tables are not complete
882 
883 #define MAP(from, to)                     \
884   case X86Local::MRM_##from:              \
885     filter = new ExactFilter(0x##from);   \
886     break;
887 
888   OpcodeType    opcodeType  = (OpcodeType)-1;
889 
890   ModRMFilter*  filter      = NULL;
891   uint8_t       opcodeToSet = 0;
892 
893   switch (Prefix) {
894   default: llvm_unreachable("Invalid prefix!");
895   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
896   case X86Local::XD:
897   case X86Local::XS:
898   case X86Local::TB:
899     opcodeType = TWOBYTE;
900 
901     switch (Opcode) {
902     default:
903       if (needsModRMForDecode(Form))
904         filter = new ModFilter(isRegFormat(Form));
905       else
906         filter = new DumbFilter();
907       break;
908 #define EXTENSION_TABLE(n) case 0x##n:
909     TWO_BYTE_EXTENSION_TABLES
910 #undef EXTENSION_TABLE
911       switch (Form) {
912       default:
913         llvm_unreachable("Unhandled two-byte extended opcode");
914       case X86Local::MRM0r:
915       case X86Local::MRM1r:
916       case X86Local::MRM2r:
917       case X86Local::MRM3r:
918       case X86Local::MRM4r:
919       case X86Local::MRM5r:
920       case X86Local::MRM6r:
921       case X86Local::MRM7r:
922         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
923         break;
924       case X86Local::MRM0m:
925       case X86Local::MRM1m:
926       case X86Local::MRM2m:
927       case X86Local::MRM3m:
928       case X86Local::MRM4m:
929       case X86Local::MRM5m:
930       case X86Local::MRM6m:
931       case X86Local::MRM7m:
932         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
933         break;
934       MRM_MAPPING
935       } // switch (Form)
936       break;
937     } // switch (Opcode)
938     opcodeToSet = Opcode;
939     break;
940   case X86Local::T8:
941   case X86Local::T8XD:
942   case X86Local::T8XS:
943     opcodeType = THREEBYTE_38;
944     switch (Opcode) {
945     default:
946       if (needsModRMForDecode(Form))
947         filter = new ModFilter(isRegFormat(Form));
948       else
949         filter = new DumbFilter();
950       break;
951 #define EXTENSION_TABLE(n) case 0x##n:
952     THREE_BYTE_38_EXTENSION_TABLES
953 #undef EXTENSION_TABLE
954       switch (Form) {
955       default:
956         llvm_unreachable("Unhandled two-byte extended opcode");
957       case X86Local::MRM0r:
958       case X86Local::MRM1r:
959       case X86Local::MRM2r:
960       case X86Local::MRM3r:
961       case X86Local::MRM4r:
962       case X86Local::MRM5r:
963       case X86Local::MRM6r:
964       case X86Local::MRM7r:
965         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
966         break;
967       case X86Local::MRM0m:
968       case X86Local::MRM1m:
969       case X86Local::MRM2m:
970       case X86Local::MRM3m:
971       case X86Local::MRM4m:
972       case X86Local::MRM5m:
973       case X86Local::MRM6m:
974       case X86Local::MRM7m:
975         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
976         break;
977       MRM_MAPPING
978       } // switch (Form)
979       break;
980     } // switch (Opcode)
981     opcodeToSet = Opcode;
982     break;
983   case X86Local::P_TA:
984   case X86Local::TAXD:
985     opcodeType = THREEBYTE_3A;
986     if (needsModRMForDecode(Form))
987       filter = new ModFilter(isRegFormat(Form));
988     else
989       filter = new DumbFilter();
990     opcodeToSet = Opcode;
991     break;
992   case X86Local::A6:
993     opcodeType = THREEBYTE_A6;
994     if (needsModRMForDecode(Form))
995       filter = new ModFilter(isRegFormat(Form));
996     else
997       filter = new DumbFilter();
998     opcodeToSet = Opcode;
999     break;
1000   case X86Local::A7:
1001     opcodeType = THREEBYTE_A7;
1002     if (needsModRMForDecode(Form))
1003       filter = new ModFilter(isRegFormat(Form));
1004     else
1005       filter = new DumbFilter();
1006     opcodeToSet = Opcode;
1007     break;
1008   case X86Local::XOP8:
1009     opcodeType = XOP8_MAP;
1010     if (needsModRMForDecode(Form))
1011       filter = new ModFilter(isRegFormat(Form));
1012     else
1013       filter = new DumbFilter();
1014     opcodeToSet = Opcode;
1015     break;
1016   case X86Local::XOP9:
1017     opcodeType = XOP9_MAP;
1018     switch (Opcode) {
1019     default:
1020       if (needsModRMForDecode(Form))
1021         filter = new ModFilter(isRegFormat(Form));
1022       else
1023         filter = new DumbFilter();
1024       break;
1025 #define EXTENSION_TABLE(n) case 0x##n:
1026     XOP9_MAP_EXTENSION_TABLES
1027 #undef EXTENSION_TABLE
1028       switch (Form) {
1029       default:
1030         llvm_unreachable("Unhandled XOP9 extended opcode");
1031       case X86Local::MRM0r:
1032       case X86Local::MRM1r:
1033       case X86Local::MRM2r:
1034       case X86Local::MRM3r:
1035       case X86Local::MRM4r:
1036       case X86Local::MRM5r:
1037       case X86Local::MRM6r:
1038       case X86Local::MRM7r:
1039         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1040         break;
1041       case X86Local::MRM0m:
1042       case X86Local::MRM1m:
1043       case X86Local::MRM2m:
1044       case X86Local::MRM3m:
1045       case X86Local::MRM4m:
1046       case X86Local::MRM5m:
1047       case X86Local::MRM6m:
1048       case X86Local::MRM7m:
1049         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1050         break;
1051       MRM_MAPPING
1052       } // switch (Form)
1053       break;
1054     } // switch (Opcode)
1055     opcodeToSet = Opcode;
1056     break;
1057   case X86Local::XOPA:
1058     opcodeType = XOPA_MAP;
1059     if (needsModRMForDecode(Form))
1060       filter = new ModFilter(isRegFormat(Form));
1061     else
1062       filter = new DumbFilter();
1063     opcodeToSet = Opcode;
1064     break;
1065   case X86Local::D8:
1066   case X86Local::D9:
1067   case X86Local::DA:
1068   case X86Local::DB:
1069   case X86Local::DC:
1070   case X86Local::DD:
1071   case X86Local::DE:
1072   case X86Local::DF:
1073     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1074     opcodeType = ONEBYTE;
1075     if (Form == X86Local::AddRegFrm) {
1076       Spec->modifierType = MODIFIER_MODRM;
1077       Spec->modifierBase = Opcode;
1078       filter = new AddRegEscapeFilter(Opcode);
1079     } else {
1080       filter = new EscapeFilter(true, Opcode);
1081     }
1082     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1083     break;
1084   case X86Local::REP:
1085   case 0:
1086     opcodeType = ONEBYTE;
1087     switch (Opcode) {
1088 #define EXTENSION_TABLE(n) case 0x##n:
1089     ONE_BYTE_EXTENSION_TABLES
1090 #undef EXTENSION_TABLE
1091       switch (Form) {
1092       default:
1093         llvm_unreachable("Fell through the cracks of a single-byte "
1094                          "extended opcode");
1095       case X86Local::MRM0r:
1096       case X86Local::MRM1r:
1097       case X86Local::MRM2r:
1098       case X86Local::MRM3r:
1099       case X86Local::MRM4r:
1100       case X86Local::MRM5r:
1101       case X86Local::MRM6r:
1102       case X86Local::MRM7r:
1103         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1104         break;
1105       case X86Local::MRM0m:
1106       case X86Local::MRM1m:
1107       case X86Local::MRM2m:
1108       case X86Local::MRM3m:
1109       case X86Local::MRM4m:
1110       case X86Local::MRM5m:
1111       case X86Local::MRM6m:
1112       case X86Local::MRM7m:
1113         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1114         break;
1115       MRM_MAPPING
1116       } // switch (Form)
1117       break;
1118     case 0xd8:
1119     case 0xd9:
1120     case 0xda:
1121     case 0xdb:
1122     case 0xdc:
1123     case 0xdd:
1124     case 0xde:
1125     case 0xdf:
1126       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1127       break;
1128     default:
1129       if (needsModRMForDecode(Form))
1130         filter = new ModFilter(isRegFormat(Form));
1131       else
1132         filter = new DumbFilter();
1133       break;
1134     } // switch (Opcode)
1135     opcodeToSet = Opcode;
1136   } // switch (Prefix)
1137 
1138   assert(opcodeType != (OpcodeType)-1 &&
1139          "Opcode type not set");
1140   assert(filter && "Filter not set");
1141 
1142   if (Form == X86Local::AddRegFrm) {
1143     if(Spec->modifierType != MODIFIER_MODRM) {
1144       assert(opcodeToSet < 0xf9 &&
1145              "Not enough room for all ADDREG_FRM operands");
1146 
1147       uint8_t currentOpcode;
1148 
1149       for (currentOpcode = opcodeToSet;
1150            currentOpcode < opcodeToSet + 8;
1151            ++currentOpcode)
1152         tables.setTableFields(opcodeType,
1153                               insnContext(),
1154                               currentOpcode,
1155                               *filter,
1156                               UID, Is32Bit, IgnoresVEX_L);
1157 
1158       Spec->modifierType = MODIFIER_OPCODE;
1159       Spec->modifierBase = opcodeToSet;
1160     } else {
1161       // modifierBase was set where MODIFIER_MODRM was set
1162       tables.setTableFields(opcodeType,
1163                             insnContext(),
1164                             opcodeToSet,
1165                             *filter,
1166                             UID, Is32Bit, IgnoresVEX_L);
1167     }
1168   } else {
1169     tables.setTableFields(opcodeType,
1170                           insnContext(),
1171                           opcodeToSet,
1172                           *filter,
1173                           UID, Is32Bit, IgnoresVEX_L);
1174 
1175     Spec->modifierType = MODIFIER_NONE;
1176     Spec->modifierBase = opcodeToSet;
1177   }
1178 
1179   delete filter;
1180 
1181 #undef MAP
1182 }
1183 
1184 #define TYPE(str, type) if (s == str) return type;
1185 OperandType RecognizableInstr::typeFromString(const std::string &s,
1186                                               bool isSSE,
1187                                               bool hasREX_WPrefix,
1188                                               bool hasOpSizePrefix) {
1189   if (isSSE) {
1190     // For SSE instructions, we ignore the OpSize prefix and force operand
1191     // sizes.
1192     TYPE("GR16",              TYPE_R16)
1193     TYPE("GR32",              TYPE_R32)
1194     TYPE("GR64",              TYPE_R64)
1195   }
1196   if(hasREX_WPrefix) {
1197     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1198     // is special.
1199     TYPE("GR32",              TYPE_R32)
1200   }
1201   if(!hasOpSizePrefix) {
1202     // For instructions without an OpSize prefix, a declared 16-bit register or
1203     // immediate encoding is special.
1204     TYPE("GR16",              TYPE_R16)
1205     TYPE("i16imm",            TYPE_IMM16)
1206   }
1207   TYPE("i16mem",              TYPE_Mv)
1208   TYPE("i16imm",              TYPE_IMMv)
1209   TYPE("i16i8imm",            TYPE_IMMv)
1210   TYPE("GR16",                TYPE_Rv)
1211   TYPE("i32mem",              TYPE_Mv)
1212   TYPE("i32imm",              TYPE_IMMv)
1213   TYPE("i32i8imm",            TYPE_IMM32)
1214   TYPE("u32u8imm",            TYPE_IMM32)
1215   TYPE("GR32",                TYPE_Rv)
1216   TYPE("GR32orGR64",          TYPE_R32)
1217   TYPE("i64mem",              TYPE_Mv)
1218   TYPE("i64i32imm",           TYPE_IMM64)
1219   TYPE("i64i8imm",            TYPE_IMM64)
1220   TYPE("GR64",                TYPE_R64)
1221   TYPE("i8mem",               TYPE_M8)
1222   TYPE("i8imm",               TYPE_IMM8)
1223   TYPE("GR8",                 TYPE_R8)
1224   TYPE("VR128",               TYPE_XMM128)
1225   TYPE("VR128X",              TYPE_XMM128)
1226   TYPE("f128mem",             TYPE_M128)
1227   TYPE("f256mem",             TYPE_M256)
1228   TYPE("f512mem",             TYPE_M512)
1229   TYPE("FR64",                TYPE_XMM64)
1230   TYPE("FR64X",               TYPE_XMM64)
1231   TYPE("f64mem",              TYPE_M64FP)
1232   TYPE("sdmem",               TYPE_M64FP)
1233   TYPE("FR32",                TYPE_XMM32)
1234   TYPE("FR32X",               TYPE_XMM32)
1235   TYPE("f32mem",              TYPE_M32FP)
1236   TYPE("ssmem",               TYPE_M32FP)
1237   TYPE("RST",                 TYPE_ST)
1238   TYPE("i128mem",             TYPE_M128)
1239   TYPE("i256mem",             TYPE_M256)
1240   TYPE("i512mem",             TYPE_M512)
1241   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1242   TYPE("i16imm_pcrel",        TYPE_REL16)
1243   TYPE("i32imm_pcrel",        TYPE_REL32)
1244   TYPE("SSECC",               TYPE_IMM3)
1245   TYPE("AVXCC",               TYPE_IMM5)
1246   TYPE("brtarget",            TYPE_RELv)
1247   TYPE("uncondbrtarget",      TYPE_RELv)
1248   TYPE("brtarget8",           TYPE_REL8)
1249   TYPE("f80mem",              TYPE_M80FP)
1250   TYPE("lea32mem",            TYPE_LEA)
1251   TYPE("lea64_32mem",         TYPE_LEA)
1252   TYPE("lea64mem",            TYPE_LEA)
1253   TYPE("VR64",                TYPE_MM64)
1254   TYPE("i64imm",              TYPE_IMMv)
1255   TYPE("opaque32mem",         TYPE_M1616)
1256   TYPE("opaque48mem",         TYPE_M1632)
1257   TYPE("opaque80mem",         TYPE_M1664)
1258   TYPE("opaque512mem",        TYPE_M512)
1259   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1260   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1261   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1262   TYPE("offset8",             TYPE_MOFFS8)
1263   TYPE("offset16",            TYPE_MOFFS16)
1264   TYPE("offset32",            TYPE_MOFFS32)
1265   TYPE("offset64",            TYPE_MOFFS64)
1266   TYPE("VR256",               TYPE_XMM256)
1267   TYPE("VR256X",              TYPE_XMM256)
1268   TYPE("VR512",               TYPE_XMM512)
1269   TYPE("VK8",                 TYPE_VK8)
1270   TYPE("VK8WM",               TYPE_VK8)
1271   TYPE("VK16",                TYPE_VK16)
1272   TYPE("VK16WM",              TYPE_VK16)
1273   TYPE("GR16_NOAX",           TYPE_Rv)
1274   TYPE("GR32_NOAX",           TYPE_Rv)
1275   TYPE("GR64_NOAX",           TYPE_R64)
1276   TYPE("vx32mem",             TYPE_M32)
1277   TYPE("vy32mem",             TYPE_M32)
1278   TYPE("vz32mem",             TYPE_M32)
1279   TYPE("vx64mem",             TYPE_M64)
1280   TYPE("vy64mem",             TYPE_M64)
1281   TYPE("vy64xmem",            TYPE_M64)
1282   TYPE("vz64mem",             TYPE_M64)
1283   errs() << "Unhandled type string " << s << "\n";
1284   llvm_unreachable("Unhandled type string");
1285 }
1286 #undef TYPE
1287 
1288 #define ENCODING(str, encoding) if (s == str) return encoding;
1289 OperandEncoding RecognizableInstr::immediateEncodingFromString
1290   (const std::string &s,
1291    bool hasOpSizePrefix) {
1292   if(!hasOpSizePrefix) {
1293     // For instructions without an OpSize prefix, a declared 16-bit register or
1294     // immediate encoding is special.
1295     ENCODING("i16imm",        ENCODING_IW)
1296   }
1297   ENCODING("i32i8imm",        ENCODING_IB)
1298   ENCODING("u32u8imm",        ENCODING_IB)
1299   ENCODING("SSECC",           ENCODING_IB)
1300   ENCODING("AVXCC",           ENCODING_IB)
1301   ENCODING("i16imm",          ENCODING_Iv)
1302   ENCODING("i16i8imm",        ENCODING_IB)
1303   ENCODING("i32imm",          ENCODING_Iv)
1304   ENCODING("i64i32imm",       ENCODING_ID)
1305   ENCODING("i64i8imm",        ENCODING_IB)
1306   ENCODING("i8imm",           ENCODING_IB)
1307   // This is not a typo.  Instructions like BLENDVPD put
1308   // register IDs in 8-bit immediates nowadays.
1309   ENCODING("FR32",            ENCODING_IB)
1310   ENCODING("FR64",            ENCODING_IB)
1311   ENCODING("VR128",           ENCODING_IB)
1312   ENCODING("VR256",           ENCODING_IB)
1313   ENCODING("FR32X",           ENCODING_IB)
1314   ENCODING("FR64X",           ENCODING_IB)
1315   ENCODING("VR128X",          ENCODING_IB)
1316   ENCODING("VR256X",          ENCODING_IB)
1317   ENCODING("VR512",           ENCODING_IB)
1318   errs() << "Unhandled immediate encoding " << s << "\n";
1319   llvm_unreachable("Unhandled immediate encoding");
1320 }
1321 
1322 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1323   (const std::string &s,
1324    bool hasOpSizePrefix) {
1325   ENCODING("GR16",            ENCODING_RM)
1326   ENCODING("GR32",            ENCODING_RM)
1327   ENCODING("GR32orGR64",      ENCODING_RM)
1328   ENCODING("GR64",            ENCODING_RM)
1329   ENCODING("GR8",             ENCODING_RM)
1330   ENCODING("VR128",           ENCODING_RM)
1331   ENCODING("VR128X",          ENCODING_RM)
1332   ENCODING("FR64",            ENCODING_RM)
1333   ENCODING("FR32",            ENCODING_RM)
1334   ENCODING("FR64X",           ENCODING_RM)
1335   ENCODING("FR32X",           ENCODING_RM)
1336   ENCODING("VR64",            ENCODING_RM)
1337   ENCODING("VR256",           ENCODING_RM)
1338   ENCODING("VR256X",          ENCODING_RM)
1339   ENCODING("VR512",           ENCODING_RM)
1340   ENCODING("VK8",             ENCODING_RM)
1341   ENCODING("VK16",            ENCODING_RM)
1342   errs() << "Unhandled R/M register encoding " << s << "\n";
1343   llvm_unreachable("Unhandled R/M register encoding");
1344 }
1345 
1346 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1347   (const std::string &s,
1348    bool hasOpSizePrefix) {
1349   ENCODING("GR16",            ENCODING_REG)
1350   ENCODING("GR32",            ENCODING_REG)
1351   ENCODING("GR32orGR64",      ENCODING_REG)
1352   ENCODING("GR64",            ENCODING_REG)
1353   ENCODING("GR8",             ENCODING_REG)
1354   ENCODING("VR128",           ENCODING_REG)
1355   ENCODING("FR64",            ENCODING_REG)
1356   ENCODING("FR32",            ENCODING_REG)
1357   ENCODING("VR64",            ENCODING_REG)
1358   ENCODING("SEGMENT_REG",     ENCODING_REG)
1359   ENCODING("DEBUG_REG",       ENCODING_REG)
1360   ENCODING("CONTROL_REG",     ENCODING_REG)
1361   ENCODING("VR256",           ENCODING_REG)
1362   ENCODING("VR256X",          ENCODING_REG)
1363   ENCODING("VR128X",          ENCODING_REG)
1364   ENCODING("FR64X",           ENCODING_REG)
1365   ENCODING("FR32X",           ENCODING_REG)
1366   ENCODING("VR512",           ENCODING_REG)
1367   ENCODING("VK8",             ENCODING_REG)
1368   ENCODING("VK16",            ENCODING_REG)
1369   ENCODING("VK8WM",           ENCODING_REG)
1370   ENCODING("VK16WM",          ENCODING_REG)
1371   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1372   llvm_unreachable("Unhandled reg/opcode register encoding");
1373 }
1374 
1375 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1376   (const std::string &s,
1377    bool hasOpSizePrefix) {
1378   ENCODING("GR32",            ENCODING_VVVV)
1379   ENCODING("GR64",            ENCODING_VVVV)
1380   ENCODING("FR32",            ENCODING_VVVV)
1381   ENCODING("FR64",            ENCODING_VVVV)
1382   ENCODING("VR128",           ENCODING_VVVV)
1383   ENCODING("VR256",           ENCODING_VVVV)
1384   ENCODING("FR32X",           ENCODING_VVVV)
1385   ENCODING("FR64X",           ENCODING_VVVV)
1386   ENCODING("VR128X",          ENCODING_VVVV)
1387   ENCODING("VR256X",          ENCODING_VVVV)
1388   ENCODING("VR512",           ENCODING_VVVV)
1389   ENCODING("VK8",             ENCODING_VVVV)
1390   ENCODING("VK16",            ENCODING_VVVV)
1391   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1392   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1393 }
1394 
1395 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1396   (const std::string &s,
1397    bool hasOpSizePrefix) {
1398   ENCODING("VK8WM",           ENCODING_WRITEMASK)
1399   ENCODING("VK16WM",          ENCODING_WRITEMASK)
1400   errs() << "Unhandled mask register encoding " << s << "\n";
1401   llvm_unreachable("Unhandled mask register encoding");
1402 }
1403 
1404 OperandEncoding RecognizableInstr::memoryEncodingFromString
1405   (const std::string &s,
1406    bool hasOpSizePrefix) {
1407   ENCODING("i16mem",          ENCODING_RM)
1408   ENCODING("i32mem",          ENCODING_RM)
1409   ENCODING("i64mem",          ENCODING_RM)
1410   ENCODING("i8mem",           ENCODING_RM)
1411   ENCODING("ssmem",           ENCODING_RM)
1412   ENCODING("sdmem",           ENCODING_RM)
1413   ENCODING("f128mem",         ENCODING_RM)
1414   ENCODING("f256mem",         ENCODING_RM)
1415   ENCODING("f512mem",         ENCODING_RM)
1416   ENCODING("f64mem",          ENCODING_RM)
1417   ENCODING("f32mem",          ENCODING_RM)
1418   ENCODING("i128mem",         ENCODING_RM)
1419   ENCODING("i256mem",         ENCODING_RM)
1420   ENCODING("i512mem",         ENCODING_RM)
1421   ENCODING("f80mem",          ENCODING_RM)
1422   ENCODING("lea32mem",        ENCODING_RM)
1423   ENCODING("lea64_32mem",     ENCODING_RM)
1424   ENCODING("lea64mem",        ENCODING_RM)
1425   ENCODING("opaque32mem",     ENCODING_RM)
1426   ENCODING("opaque48mem",     ENCODING_RM)
1427   ENCODING("opaque80mem",     ENCODING_RM)
1428   ENCODING("opaque512mem",    ENCODING_RM)
1429   ENCODING("vx32mem",         ENCODING_RM)
1430   ENCODING("vy32mem",         ENCODING_RM)
1431   ENCODING("vz32mem",         ENCODING_RM)
1432   ENCODING("vx64mem",         ENCODING_RM)
1433   ENCODING("vy64mem",         ENCODING_RM)
1434   ENCODING("vy64xmem",        ENCODING_RM)
1435   ENCODING("vz64mem",         ENCODING_RM)
1436   errs() << "Unhandled memory encoding " << s << "\n";
1437   llvm_unreachable("Unhandled memory encoding");
1438 }
1439 
1440 OperandEncoding RecognizableInstr::relocationEncodingFromString
1441   (const std::string &s,
1442    bool hasOpSizePrefix) {
1443   if(!hasOpSizePrefix) {
1444     // For instructions without an OpSize prefix, a declared 16-bit register or
1445     // immediate encoding is special.
1446     ENCODING("i16imm",        ENCODING_IW)
1447   }
1448   ENCODING("i16imm",          ENCODING_Iv)
1449   ENCODING("i16i8imm",        ENCODING_IB)
1450   ENCODING("i32imm",          ENCODING_Iv)
1451   ENCODING("i32i8imm",        ENCODING_IB)
1452   ENCODING("i64i32imm",       ENCODING_ID)
1453   ENCODING("i64i8imm",        ENCODING_IB)
1454   ENCODING("i8imm",           ENCODING_IB)
1455   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1456   ENCODING("i16imm_pcrel",    ENCODING_IW)
1457   ENCODING("i32imm_pcrel",    ENCODING_ID)
1458   ENCODING("brtarget",        ENCODING_Iv)
1459   ENCODING("brtarget8",       ENCODING_IB)
1460   ENCODING("i64imm",          ENCODING_IO)
1461   ENCODING("offset8",         ENCODING_Ia)
1462   ENCODING("offset16",        ENCODING_Ia)
1463   ENCODING("offset32",        ENCODING_Ia)
1464   ENCODING("offset64",        ENCODING_Ia)
1465   errs() << "Unhandled relocation encoding " << s << "\n";
1466   llvm_unreachable("Unhandled relocation encoding");
1467 }
1468 
1469 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1470   (const std::string &s,
1471    bool hasOpSizePrefix) {
1472   ENCODING("RST",             ENCODING_I)
1473   ENCODING("GR32",            ENCODING_Rv)
1474   ENCODING("GR64",            ENCODING_RO)
1475   ENCODING("GR16",            ENCODING_Rv)
1476   ENCODING("GR8",             ENCODING_RB)
1477   ENCODING("GR16_NOAX",       ENCODING_Rv)
1478   ENCODING("GR32_NOAX",       ENCODING_Rv)
1479   ENCODING("GR64_NOAX",       ENCODING_RO)
1480   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1481   llvm_unreachable("Unhandled opcode modifier encoding");
1482 }
1483 #undef ENCODING
1484