1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 #define THREE_BYTE_38_EXTENSION_TABLES \
123   EXTENSION_TABLE(F3)
124 
125 using namespace X86Disassembler;
126 
127 /// needsModRMForDecode - Indicates whether a particular instruction requires a
128 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
129 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
130 ///   0b11.
131 ///
132 /// @param form - The form of the instruction.
133 /// @return     - true if the form implies that a ModR/M byte is required, false
134 ///               otherwise.
135 static bool needsModRMForDecode(uint8_t form) {
136   if (form == X86Local::MRMDestReg    ||
137      form == X86Local::MRMDestMem    ||
138      form == X86Local::MRMSrcReg     ||
139      form == X86Local::MRMSrcMem     ||
140      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
141      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142     return true;
143   else
144     return false;
145 }
146 
147 /// isRegFormat - Indicates whether a particular form requires the Mod field of
148 ///   the ModR/M byte to be 0b11.
149 ///
150 /// @param form - The form of the instruction.
151 /// @return     - true if the form implies that Mod must be 0b11, false
152 ///               otherwise.
153 static bool isRegFormat(uint8_t form) {
154   if (form == X86Local::MRMDestReg ||
155      form == X86Local::MRMSrcReg  ||
156      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157     return true;
158   else
159     return false;
160 }
161 
162 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
163 ///   Useful for switch statements and the like.
164 ///
165 /// @param init - A reference to the BitsInit to be decoded.
166 /// @return     - The field, with the first bit in the BitsInit as the lowest
167 ///               order bit.
168 static uint8_t byteFromBitsInit(BitsInit &init) {
169   int width = init.getNumBits();
170 
171   assert(width <= 8 && "Field is too large for uint8_t!");
172 
173   int     index;
174   uint8_t mask = 0x01;
175 
176   uint8_t ret = 0;
177 
178   for (index = 0; index < width; index++) {
179     if (static_cast<BitInit*>(init.getBit(index))->getValue())
180       ret |= mask;
181 
182     mask <<= 1;
183   }
184 
185   return ret;
186 }
187 
188 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
189 ///   name of the field.
190 ///
191 /// @param rec  - The record from which to extract the value.
192 /// @param name - The name of the field in the record.
193 /// @return     - The field, as translated by byteFromBitsInit().
194 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
195   BitsInit* bits = rec->getValueAsBitsInit(name);
196   return byteFromBitsInit(*bits);
197 }
198 
199 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
200                                      const CodeGenInstruction &insn,
201                                      InstrUID uid) {
202   UID = uid;
203 
204   Rec = insn.TheDef;
205   Name = Rec->getName();
206   Spec = &tables.specForUID(UID);
207 
208   if (!Rec->isSubClassOf("X86Inst")) {
209     ShouldBeEmitted = false;
210     return;
211   }
212 
213   Prefix   = byteFromRec(Rec, "Prefix");
214   Opcode   = byteFromRec(Rec, "Opcode");
215   Form     = byteFromRec(Rec, "FormBits");
216   SegOvr   = byteFromRec(Rec, "SegOvrBits");
217 
218   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
219   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
220   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
221   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
222   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
223   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
224   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
225   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
226   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
227 
228   Name      = Rec->getName();
229   AsmString = Rec->getValueAsString("AsmString");
230 
231   Operands = &insn.Operands.OperandList;
232 
233   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
234                      (Name.find("CRC32") != Name.npos);
235   HasFROperands    = hasFROperands();
236   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
237 
238   // Check for 64-bit inst which does not require REX
239   Is32Bit = false;
240   Is64Bit = false;
241   // FIXME: Is there some better way to check for In64BitMode?
242   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
243   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
244     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
245       Is32Bit = true;
246       break;
247     }
248     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
249       Is64Bit = true;
250       break;
251     }
252   }
253   // FIXME: These instructions aren't marked as 64-bit in any way
254   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
255              Rec->getName() == "MASKMOVDQU64" ||
256              Rec->getName() == "POPFS64" ||
257              Rec->getName() == "POPGS64" ||
258              Rec->getName() == "PUSHFS64" ||
259              Rec->getName() == "PUSHGS64" ||
260              Rec->getName() == "REX64_PREFIX" ||
261              Rec->getName().find("MOV64") != Name.npos ||
262              Rec->getName().find("PUSH64") != Name.npos ||
263              Rec->getName().find("POP64") != Name.npos;
264 
265   ShouldBeEmitted  = true;
266 }
267 
268 void RecognizableInstr::processInstr(DisassemblerTables &tables,
269 	const CodeGenInstruction &insn,
270                                    InstrUID uid)
271 {
272   // Ignore "asm parser only" instructions.
273   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
274     return;
275 
276   RecognizableInstr recogInstr(tables, insn, uid);
277 
278   recogInstr.emitInstructionSpecifier(tables);
279 
280   if (recogInstr.shouldBeEmitted())
281     recogInstr.emitDecodePath(tables);
282 }
283 
284 InstructionContext RecognizableInstr::insnContext() const {
285   InstructionContext insnContext;
286 
287   if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
288     if (HasVEX_LPrefix && HasVEX_WPrefix) {
289       if (HasOpSizePrefix)
290         insnContext = IC_VEX_L_W_OPSIZE;
291       else
292         llvm_unreachable("Don't support VEX.L and VEX.W together");
293     } else if (HasOpSizePrefix && HasVEX_LPrefix)
294       insnContext = IC_VEX_L_OPSIZE;
295     else if (HasOpSizePrefix && HasVEX_WPrefix)
296       insnContext = IC_VEX_W_OPSIZE;
297     else if (HasOpSizePrefix)
298       insnContext = IC_VEX_OPSIZE;
299     else if (HasVEX_LPrefix &&
300              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
301       insnContext = IC_VEX_L_XS;
302     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
303                                 Prefix == X86Local::T8XD ||
304                                 Prefix == X86Local::TAXD))
305       insnContext = IC_VEX_L_XD;
306     else if (HasVEX_WPrefix &&
307              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
308       insnContext = IC_VEX_W_XS;
309     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
310                                 Prefix == X86Local::T8XD ||
311                                 Prefix == X86Local::TAXD))
312       insnContext = IC_VEX_W_XD;
313     else if (HasVEX_WPrefix)
314       insnContext = IC_VEX_W;
315     else if (HasVEX_LPrefix)
316       insnContext = IC_VEX_L;
317     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
318              Prefix == X86Local::TAXD)
319       insnContext = IC_VEX_XD;
320     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
321       insnContext = IC_VEX_XS;
322     else
323       insnContext = IC_VEX;
324   } else if (Is64Bit || HasREX_WPrefix) {
325     if (HasREX_WPrefix && HasOpSizePrefix)
326       insnContext = IC_64BIT_REXW_OPSIZE;
327     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
328                                  Prefix == X86Local::T8XD ||
329                                  Prefix == X86Local::TAXD))
330       insnContext = IC_64BIT_XD_OPSIZE;
331     else if (HasOpSizePrefix &&
332              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
333       insnContext = IC_64BIT_XS_OPSIZE;
334     else if (HasOpSizePrefix)
335       insnContext = IC_64BIT_OPSIZE;
336     else if (HasREX_WPrefix &&
337              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
338       insnContext = IC_64BIT_REXW_XS;
339     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
340                                 Prefix == X86Local::T8XD ||
341                                 Prefix == X86Local::TAXD))
342       insnContext = IC_64BIT_REXW_XD;
343     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
344              Prefix == X86Local::TAXD)
345       insnContext = IC_64BIT_XD;
346     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
347       insnContext = IC_64BIT_XS;
348     else if (HasREX_WPrefix)
349       insnContext = IC_64BIT_REXW;
350     else
351       insnContext = IC_64BIT;
352   } else {
353     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
354                             Prefix == X86Local::T8XD ||
355                             Prefix == X86Local::TAXD))
356       insnContext = IC_XD_OPSIZE;
357     else if (HasOpSizePrefix &&
358              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
359       insnContext = IC_XS_OPSIZE;
360     else if (HasOpSizePrefix)
361       insnContext = IC_OPSIZE;
362     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
363              Prefix == X86Local::TAXD)
364       insnContext = IC_XD;
365     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
366              Prefix == X86Local::REP)
367       insnContext = IC_XS;
368     else
369       insnContext = IC;
370   }
371 
372   return insnContext;
373 }
374 
375 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
376   ///////////////////
377   // FILTER_STRONG
378   //
379 
380   // Filter out intrinsics
381 
382   if (!Rec->isSubClassOf("X86Inst"))
383     return FILTER_STRONG;
384 
385   if (Form == X86Local::Pseudo ||
386       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
387     return FILTER_STRONG;
388 
389   if (Form == X86Local::MRMInitReg)
390     return FILTER_STRONG;
391 
392 
393   // Filter out artificial instructions
394 
395   if (Name.find("_Int") != Name.npos       ||
396       Name.find("Int_") != Name.npos       ||
397       Name.find("_NOREX") != Name.npos     ||
398       Name.find("2SDL") != Name.npos       ||
399       Name == "LOCK_PREFIX")
400     return FILTER_STRONG;
401 
402   // Filter out instructions with segment override prefixes.
403   // They're too messy to handle now and we'll special case them if needed.
404 
405   if (SegOvr)
406     return FILTER_STRONG;
407 
408   // Filter out instructions that can't be printed.
409 
410   if (AsmString.size() == 0)
411     return FILTER_STRONG;
412 
413   // Filter out instructions with subreg operands.
414 
415   if (AsmString.find("subreg") != AsmString.npos)
416     return FILTER_STRONG;
417 
418   /////////////////
419   // FILTER_WEAK
420   //
421 
422 
423   // Filter out instructions with a LOCK prefix;
424   //   prefer forms that do not have the prefix
425   if (HasLockPrefix)
426     return FILTER_WEAK;
427 
428   // Filter out alternate forms of AVX instructions
429   if (Name.find("_alt") != Name.npos ||
430       Name.find("XrYr") != Name.npos ||
431       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
432       Name.find("_64mr") != Name.npos ||
433       Name.find("Xrr") != Name.npos ||
434       Name.find("rr64") != Name.npos)
435     return FILTER_WEAK;
436 
437   // Special cases.
438 
439   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
440     return FILTER_WEAK;
441   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
442     return FILTER_WEAK;
443 
444   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
445     return FILTER_WEAK;
446   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
447     return FILTER_WEAK;
448   if (Name.find("Fs") != Name.npos)
449     return FILTER_WEAK;
450   if (Name == "PUSH64i16"         ||
451       Name == "MOVPQI2QImr"       ||
452       Name == "VMOVPQI2QImr"      ||
453       Name == "MMX_MOVD64rrv164"  ||
454       Name == "MOV64ri64i32"      ||
455       Name == "VMASKMOVDQU64"     ||
456       Name == "VEXTRACTPSrr64"    ||
457       Name == "VMOVQd64rr"        ||
458       Name == "VMOVQs64rr")
459     return FILTER_WEAK;
460 
461   if (HasFROperands && Name.find("MOV") != Name.npos &&
462      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
463       (Name.find("to") != Name.npos)))
464     return FILTER_WEAK;
465 
466   return FILTER_NORMAL;
467 }
468 
469 bool RecognizableInstr::hasFROperands() const {
470   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
471   unsigned numOperands = OperandList.size();
472 
473   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
474     const std::string &recName = OperandList[operandIndex].Rec->getName();
475 
476     if (recName.find("FR") != recName.npos)
477       return true;
478   }
479   return false;
480 }
481 
482 bool RecognizableInstr::has256BitOperands() const {
483   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
484   unsigned numOperands = OperandList.size();
485 
486   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
487     const std::string &recName = OperandList[operandIndex].Rec->getName();
488 
489     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
490       return true;
491     }
492   }
493   return false;
494 }
495 
496 void RecognizableInstr::handleOperand(
497   bool optional,
498   unsigned &operandIndex,
499   unsigned &physicalOperandIndex,
500   unsigned &numPhysicalOperands,
501   unsigned *operandMapping,
502   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
503   if (optional) {
504     if (physicalOperandIndex >= numPhysicalOperands)
505       return;
506   } else {
507     assert(physicalOperandIndex < numPhysicalOperands);
508   }
509 
510   while (operandMapping[operandIndex] != operandIndex) {
511     Spec->operands[operandIndex].encoding = ENCODING_DUP;
512     Spec->operands[operandIndex].type =
513       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
514     ++operandIndex;
515   }
516 
517   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
518 
519   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
520                                                               HasOpSizePrefix);
521   Spec->operands[operandIndex].type = typeFromString(typeName,
522                                                      IsSSE,
523                                                      HasREX_WPrefix,
524                                                      HasOpSizePrefix);
525 
526   ++operandIndex;
527   ++physicalOperandIndex;
528 }
529 
530 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
531   Spec->name       = Name;
532 
533   if (!Rec->isSubClassOf("X86Inst"))
534     return;
535 
536   switch (filter()) {
537   case FILTER_WEAK:
538     Spec->filtered = true;
539     break;
540   case FILTER_STRONG:
541     ShouldBeEmitted = false;
542     return;
543   case FILTER_NORMAL:
544     break;
545   }
546 
547   Spec->insnContext = insnContext();
548 
549   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
550 
551   unsigned operandIndex;
552   unsigned numOperands = OperandList.size();
553   unsigned numPhysicalOperands = 0;
554 
555   // operandMapping maps from operands in OperandList to their originals.
556   // If operandMapping[i] != i, then the entry is a duplicate.
557   unsigned operandMapping[X86_MAX_OPERANDS];
558 
559   bool hasFROperands = false;
560 
561   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
562 
563   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
564     if (OperandList[operandIndex].Constraints.size()) {
565       const CGIOperandList::ConstraintInfo &Constraint =
566         OperandList[operandIndex].Constraints[0];
567       if (Constraint.isTied()) {
568         operandMapping[operandIndex] = Constraint.getTiedOperand();
569       } else {
570         ++numPhysicalOperands;
571         operandMapping[operandIndex] = operandIndex;
572       }
573     } else {
574       ++numPhysicalOperands;
575       operandMapping[operandIndex] = operandIndex;
576     }
577 
578     const std::string &recName = OperandList[operandIndex].Rec->getName();
579 
580     if (recName.find("FR") != recName.npos)
581       hasFROperands = true;
582   }
583 
584   if (hasFROperands && Name.find("MOV") != Name.npos &&
585      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
586       (Name.find("to") != Name.npos)))
587     ShouldBeEmitted = false;
588 
589   if (!ShouldBeEmitted)
590     return;
591 
592 #define HANDLE_OPERAND(class)               \
593   handleOperand(false,                      \
594                 operandIndex,               \
595                 physicalOperandIndex,       \
596                 numPhysicalOperands,        \
597                 operandMapping,             \
598                 class##EncodingFromString);
599 
600 #define HANDLE_OPTIONAL(class)              \
601   handleOperand(true,                       \
602                 operandIndex,               \
603                 physicalOperandIndex,       \
604                 numPhysicalOperands,        \
605                 operandMapping,             \
606                 class##EncodingFromString);
607 
608   // operandIndex should always be < numOperands
609   operandIndex = 0;
610   // physicalOperandIndex should always be < numPhysicalOperands
611   unsigned physicalOperandIndex = 0;
612 
613   switch (Form) {
614   case X86Local::RawFrm:
615     // Operand 1 (optional) is an address or immediate.
616     // Operand 2 (optional) is an immediate.
617     assert(numPhysicalOperands <= 2 &&
618            "Unexpected number of operands for RawFrm");
619     HANDLE_OPTIONAL(relocation)
620     HANDLE_OPTIONAL(immediate)
621     break;
622   case X86Local::AddRegFrm:
623     // Operand 1 is added to the opcode.
624     // Operand 2 (optional) is an address.
625     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
626            "Unexpected number of operands for AddRegFrm");
627     HANDLE_OPERAND(opcodeModifier)
628     HANDLE_OPTIONAL(relocation)
629     break;
630   case X86Local::MRMDestReg:
631     // Operand 1 is a register operand in the R/M field.
632     // Operand 2 is a register operand in the Reg/Opcode field.
633     // - In AVX, there is a register operand in the VEX.vvvv field here -
634     // Operand 3 (optional) is an immediate.
635     if (HasVEX_4VPrefix)
636       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
637              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
638     else
639       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
640              "Unexpected number of operands for MRMDestRegFrm");
641 
642     HANDLE_OPERAND(rmRegister)
643 
644     if (HasVEX_4VPrefix)
645       // FIXME: In AVX, the register below becomes the one encoded
646       // in ModRMVEX and the one above the one in the VEX.VVVV field
647       HANDLE_OPERAND(vvvvRegister)
648 
649     HANDLE_OPERAND(roRegister)
650     HANDLE_OPTIONAL(immediate)
651     break;
652   case X86Local::MRMDestMem:
653     // Operand 1 is a memory operand (possibly SIB-extended)
654     // Operand 2 is a register operand in the Reg/Opcode field.
655     // - In AVX, there is a register operand in the VEX.vvvv field here -
656     // Operand 3 (optional) is an immediate.
657     if (HasVEX_4VPrefix)
658       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
659              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
660     else
661       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
662              "Unexpected number of operands for MRMDestMemFrm");
663     HANDLE_OPERAND(memory)
664 
665     if (HasVEX_4VPrefix)
666       // FIXME: In AVX, the register below becomes the one encoded
667       // in ModRMVEX and the one above the one in the VEX.VVVV field
668       HANDLE_OPERAND(vvvvRegister)
669 
670     HANDLE_OPERAND(roRegister)
671     HANDLE_OPTIONAL(immediate)
672     break;
673   case X86Local::MRMSrcReg:
674     // Operand 1 is a register operand in the Reg/Opcode field.
675     // Operand 2 is a register operand in the R/M field.
676     // - In AVX, there is a register operand in the VEX.vvvv field here -
677     // Operand 3 (optional) is an immediate.
678 
679     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
680       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
681              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
682     else
683       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
684              "Unexpected number of operands for MRMSrcRegFrm");
685 
686     HANDLE_OPERAND(roRegister)
687 
688     if (HasVEX_4VPrefix)
689       // FIXME: In AVX, the register below becomes the one encoded
690       // in ModRMVEX and the one above the one in the VEX.VVVV field
691       HANDLE_OPERAND(vvvvRegister)
692 
693     HANDLE_OPERAND(rmRegister)
694 
695     if (HasVEX_4VOp3Prefix)
696       HANDLE_OPERAND(vvvvRegister)
697 
698     HANDLE_OPTIONAL(immediate)
699     break;
700   case X86Local::MRMSrcMem:
701     // Operand 1 is a register operand in the Reg/Opcode field.
702     // Operand 2 is a memory operand (possibly SIB-extended)
703     // - In AVX, there is a register operand in the VEX.vvvv field here -
704     // Operand 3 (optional) is an immediate.
705 
706     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
707       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
708              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
709     else
710       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
711              "Unexpected number of operands for MRMSrcMemFrm");
712 
713     HANDLE_OPERAND(roRegister)
714 
715     if (HasVEX_4VPrefix)
716       // FIXME: In AVX, the register below becomes the one encoded
717       // in ModRMVEX and the one above the one in the VEX.VVVV field
718       HANDLE_OPERAND(vvvvRegister)
719 
720     HANDLE_OPERAND(memory)
721 
722     if (HasVEX_4VOp3Prefix)
723       HANDLE_OPERAND(vvvvRegister)
724 
725     HANDLE_OPTIONAL(immediate)
726     break;
727   case X86Local::MRM0r:
728   case X86Local::MRM1r:
729   case X86Local::MRM2r:
730   case X86Local::MRM3r:
731   case X86Local::MRM4r:
732   case X86Local::MRM5r:
733   case X86Local::MRM6r:
734   case X86Local::MRM7r:
735     // Operand 1 is a register operand in the R/M field.
736     // Operand 2 (optional) is an immediate or relocation.
737     if (HasVEX_4VPrefix)
738       assert(numPhysicalOperands <= 3 &&
739              "Unexpected number of operands for MRMnRFrm with VEX_4V");
740     else
741       assert(numPhysicalOperands <= 2 &&
742              "Unexpected number of operands for MRMnRFrm");
743     if (HasVEX_4VPrefix)
744       HANDLE_OPERAND(vvvvRegister)
745     HANDLE_OPTIONAL(rmRegister)
746     HANDLE_OPTIONAL(relocation)
747     break;
748   case X86Local::MRM0m:
749   case X86Local::MRM1m:
750   case X86Local::MRM2m:
751   case X86Local::MRM3m:
752   case X86Local::MRM4m:
753   case X86Local::MRM5m:
754   case X86Local::MRM6m:
755   case X86Local::MRM7m:
756     // Operand 1 is a memory operand (possibly SIB-extended)
757     // Operand 2 (optional) is an immediate or relocation.
758     if (HasVEX_4VPrefix)
759       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
760              "Unexpected number of operands for MRMnMFrm");
761     else
762       assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
763              "Unexpected number of operands for MRMnMFrm");
764     if (HasVEX_4VPrefix)
765       HANDLE_OPERAND(vvvvRegister)
766     HANDLE_OPERAND(memory)
767     HANDLE_OPTIONAL(relocation)
768     break;
769   case X86Local::RawFrmImm8:
770     // operand 1 is a 16-bit immediate
771     // operand 2 is an 8-bit immediate
772     assert(numPhysicalOperands == 2 &&
773            "Unexpected number of operands for X86Local::RawFrmImm8");
774     HANDLE_OPERAND(immediate)
775     HANDLE_OPERAND(immediate)
776     break;
777   case X86Local::RawFrmImm16:
778     // operand 1 is a 16-bit immediate
779     // operand 2 is a 16-bit immediate
780     HANDLE_OPERAND(immediate)
781     HANDLE_OPERAND(immediate)
782     break;
783   case X86Local::MRMInitReg:
784     // Ignored.
785     break;
786   }
787 
788   #undef HANDLE_OPERAND
789   #undef HANDLE_OPTIONAL
790 }
791 
792 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
793   // Special cases where the LLVM tables are not complete
794 
795 #define MAP(from, to)                     \
796   case X86Local::MRM_##from:              \
797     filter = new ExactFilter(0x##from);   \
798     break;
799 
800   OpcodeType    opcodeType  = (OpcodeType)-1;
801 
802   ModRMFilter*  filter      = NULL;
803   uint8_t       opcodeToSet = 0;
804 
805   switch (Prefix) {
806   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
807   case X86Local::XD:
808   case X86Local::XS:
809   case X86Local::TB:
810     opcodeType = TWOBYTE;
811 
812     switch (Opcode) {
813     default:
814       if (needsModRMForDecode(Form))
815         filter = new ModFilter(isRegFormat(Form));
816       else
817         filter = new DumbFilter();
818       break;
819 #define EXTENSION_TABLE(n) case 0x##n:
820     TWO_BYTE_EXTENSION_TABLES
821 #undef EXTENSION_TABLE
822       switch (Form) {
823       default:
824         llvm_unreachable("Unhandled two-byte extended opcode");
825       case X86Local::MRM0r:
826       case X86Local::MRM1r:
827       case X86Local::MRM2r:
828       case X86Local::MRM3r:
829       case X86Local::MRM4r:
830       case X86Local::MRM5r:
831       case X86Local::MRM6r:
832       case X86Local::MRM7r:
833         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
834         break;
835       case X86Local::MRM0m:
836       case X86Local::MRM1m:
837       case X86Local::MRM2m:
838       case X86Local::MRM3m:
839       case X86Local::MRM4m:
840       case X86Local::MRM5m:
841       case X86Local::MRM6m:
842       case X86Local::MRM7m:
843         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
844         break;
845       MRM_MAPPING
846       } // switch (Form)
847       break;
848     } // switch (Opcode)
849     opcodeToSet = Opcode;
850     break;
851   case X86Local::T8:
852   case X86Local::T8XD:
853   case X86Local::T8XS:
854     opcodeType = THREEBYTE_38;
855     switch (Opcode) {
856     default:
857       if (needsModRMForDecode(Form))
858         filter = new ModFilter(isRegFormat(Form));
859       else
860         filter = new DumbFilter();
861       break;
862 #define EXTENSION_TABLE(n) case 0x##n:
863     THREE_BYTE_38_EXTENSION_TABLES
864 #undef EXTENSION_TABLE
865       switch (Form) {
866       default:
867         llvm_unreachable("Unhandled two-byte extended opcode");
868       case X86Local::MRM0r:
869       case X86Local::MRM1r:
870       case X86Local::MRM2r:
871       case X86Local::MRM3r:
872       case X86Local::MRM4r:
873       case X86Local::MRM5r:
874       case X86Local::MRM6r:
875       case X86Local::MRM7r:
876         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
877         break;
878       case X86Local::MRM0m:
879       case X86Local::MRM1m:
880       case X86Local::MRM2m:
881       case X86Local::MRM3m:
882       case X86Local::MRM4m:
883       case X86Local::MRM5m:
884       case X86Local::MRM6m:
885       case X86Local::MRM7m:
886         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
887         break;
888       MRM_MAPPING
889       } // switch (Form)
890       break;
891     } // switch (Opcode)
892     opcodeToSet = Opcode;
893     break;
894   case X86Local::P_TA:
895   case X86Local::TAXD:
896     opcodeType = THREEBYTE_3A;
897     if (needsModRMForDecode(Form))
898       filter = new ModFilter(isRegFormat(Form));
899     else
900       filter = new DumbFilter();
901     opcodeToSet = Opcode;
902     break;
903   case X86Local::A6:
904     opcodeType = THREEBYTE_A6;
905     if (needsModRMForDecode(Form))
906       filter = new ModFilter(isRegFormat(Form));
907     else
908       filter = new DumbFilter();
909     opcodeToSet = Opcode;
910     break;
911   case X86Local::A7:
912     opcodeType = THREEBYTE_A7;
913     if (needsModRMForDecode(Form))
914       filter = new ModFilter(isRegFormat(Form));
915     else
916       filter = new DumbFilter();
917     opcodeToSet = Opcode;
918     break;
919   case X86Local::D8:
920   case X86Local::D9:
921   case X86Local::DA:
922   case X86Local::DB:
923   case X86Local::DC:
924   case X86Local::DD:
925   case X86Local::DE:
926   case X86Local::DF:
927     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
928     opcodeType = ONEBYTE;
929     if (Form == X86Local::AddRegFrm) {
930       Spec->modifierType = MODIFIER_MODRM;
931       Spec->modifierBase = Opcode;
932       filter = new AddRegEscapeFilter(Opcode);
933     } else {
934       filter = new EscapeFilter(true, Opcode);
935     }
936     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
937     break;
938   case X86Local::REP:
939   default:
940     opcodeType = ONEBYTE;
941     switch (Opcode) {
942 #define EXTENSION_TABLE(n) case 0x##n:
943     ONE_BYTE_EXTENSION_TABLES
944 #undef EXTENSION_TABLE
945       switch (Form) {
946       default:
947         llvm_unreachable("Fell through the cracks of a single-byte "
948                          "extended opcode");
949       case X86Local::MRM0r:
950       case X86Local::MRM1r:
951       case X86Local::MRM2r:
952       case X86Local::MRM3r:
953       case X86Local::MRM4r:
954       case X86Local::MRM5r:
955       case X86Local::MRM6r:
956       case X86Local::MRM7r:
957         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
958         break;
959       case X86Local::MRM0m:
960       case X86Local::MRM1m:
961       case X86Local::MRM2m:
962       case X86Local::MRM3m:
963       case X86Local::MRM4m:
964       case X86Local::MRM5m:
965       case X86Local::MRM6m:
966       case X86Local::MRM7m:
967         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
968         break;
969       MRM_MAPPING
970       } // switch (Form)
971       break;
972     case 0xd8:
973     case 0xd9:
974     case 0xda:
975     case 0xdb:
976     case 0xdc:
977     case 0xdd:
978     case 0xde:
979     case 0xdf:
980       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
981       break;
982     default:
983       if (needsModRMForDecode(Form))
984         filter = new ModFilter(isRegFormat(Form));
985       else
986         filter = new DumbFilter();
987       break;
988     } // switch (Opcode)
989     opcodeToSet = Opcode;
990   } // switch (Prefix)
991 
992   assert(opcodeType != (OpcodeType)-1 &&
993          "Opcode type not set");
994   assert(filter && "Filter not set");
995 
996   if (Form == X86Local::AddRegFrm) {
997     if(Spec->modifierType != MODIFIER_MODRM) {
998       assert(opcodeToSet < 0xf9 &&
999              "Not enough room for all ADDREG_FRM operands");
1000 
1001       uint8_t currentOpcode;
1002 
1003       for (currentOpcode = opcodeToSet;
1004            currentOpcode < opcodeToSet + 8;
1005            ++currentOpcode)
1006         tables.setTableFields(opcodeType,
1007                               insnContext(),
1008                               currentOpcode,
1009                               *filter,
1010                               UID, Is32Bit, IgnoresVEX_L);
1011 
1012       Spec->modifierType = MODIFIER_OPCODE;
1013       Spec->modifierBase = opcodeToSet;
1014     } else {
1015       // modifierBase was set where MODIFIER_MODRM was set
1016       tables.setTableFields(opcodeType,
1017                             insnContext(),
1018                             opcodeToSet,
1019                             *filter,
1020                             UID, Is32Bit, IgnoresVEX_L);
1021     }
1022   } else {
1023     tables.setTableFields(opcodeType,
1024                           insnContext(),
1025                           opcodeToSet,
1026                           *filter,
1027                           UID, Is32Bit, IgnoresVEX_L);
1028 
1029     Spec->modifierType = MODIFIER_NONE;
1030     Spec->modifierBase = opcodeToSet;
1031   }
1032 
1033   delete filter;
1034 
1035 #undef MAP
1036 }
1037 
1038 #define TYPE(str, type) if (s == str) return type;
1039 OperandType RecognizableInstr::typeFromString(const std::string &s,
1040                                               bool isSSE,
1041                                               bool hasREX_WPrefix,
1042                                               bool hasOpSizePrefix) {
1043   if (isSSE) {
1044     // For SSE instructions, we ignore the OpSize prefix and force operand
1045     // sizes.
1046     TYPE("GR16",              TYPE_R16)
1047     TYPE("GR32",              TYPE_R32)
1048     TYPE("GR64",              TYPE_R64)
1049   }
1050   if(hasREX_WPrefix) {
1051     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1052     // is special.
1053     TYPE("GR32",              TYPE_R32)
1054   }
1055   if(!hasOpSizePrefix) {
1056     // For instructions without an OpSize prefix, a declared 16-bit register or
1057     // immediate encoding is special.
1058     TYPE("GR16",              TYPE_R16)
1059     TYPE("i16imm",            TYPE_IMM16)
1060   }
1061   TYPE("i16mem",              TYPE_Mv)
1062   TYPE("i16imm",              TYPE_IMMv)
1063   TYPE("i16i8imm",            TYPE_IMMv)
1064   TYPE("GR16",                TYPE_Rv)
1065   TYPE("i32mem",              TYPE_Mv)
1066   TYPE("i32imm",              TYPE_IMMv)
1067   TYPE("i32i8imm",            TYPE_IMM32)
1068   TYPE("u32u8imm",            TYPE_IMM32)
1069   TYPE("GR32",                TYPE_Rv)
1070   TYPE("i64mem",              TYPE_Mv)
1071   TYPE("i64i32imm",           TYPE_IMM64)
1072   TYPE("i64i8imm",            TYPE_IMM64)
1073   TYPE("GR64",                TYPE_R64)
1074   TYPE("i8mem",               TYPE_M8)
1075   TYPE("i8imm",               TYPE_IMM8)
1076   TYPE("GR8",                 TYPE_R8)
1077   TYPE("VR128",               TYPE_XMM128)
1078   TYPE("f128mem",             TYPE_M128)
1079   TYPE("f256mem",             TYPE_M256)
1080   TYPE("FR64",                TYPE_XMM64)
1081   TYPE("f64mem",              TYPE_M64FP)
1082   TYPE("sdmem",               TYPE_M64FP)
1083   TYPE("FR32",                TYPE_XMM32)
1084   TYPE("f32mem",              TYPE_M32FP)
1085   TYPE("ssmem",               TYPE_M32FP)
1086   TYPE("RST",                 TYPE_ST)
1087   TYPE("i128mem",             TYPE_M128)
1088   TYPE("i256mem",             TYPE_M256)
1089   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1090   TYPE("i16imm_pcrel",        TYPE_REL16)
1091   TYPE("i32imm_pcrel",        TYPE_REL32)
1092   TYPE("SSECC",               TYPE_IMM3)
1093   TYPE("brtarget",            TYPE_RELv)
1094   TYPE("uncondbrtarget",      TYPE_RELv)
1095   TYPE("brtarget8",           TYPE_REL8)
1096   TYPE("f80mem",              TYPE_M80FP)
1097   TYPE("lea32mem",            TYPE_LEA)
1098   TYPE("lea64_32mem",         TYPE_LEA)
1099   TYPE("lea64mem",            TYPE_LEA)
1100   TYPE("VR64",                TYPE_MM64)
1101   TYPE("i64imm",              TYPE_IMMv)
1102   TYPE("opaque32mem",         TYPE_M1616)
1103   TYPE("opaque48mem",         TYPE_M1632)
1104   TYPE("opaque80mem",         TYPE_M1664)
1105   TYPE("opaque512mem",        TYPE_M512)
1106   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1107   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1108   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1109   TYPE("offset8",             TYPE_MOFFS8)
1110   TYPE("offset16",            TYPE_MOFFS16)
1111   TYPE("offset32",            TYPE_MOFFS32)
1112   TYPE("offset64",            TYPE_MOFFS64)
1113   TYPE("VR256",               TYPE_XMM256)
1114   TYPE("GR16_NOAX",           TYPE_Rv)
1115   TYPE("GR32_NOAX",           TYPE_Rv)
1116   TYPE("GR64_NOAX",           TYPE_R64)
1117   errs() << "Unhandled type string " << s << "\n";
1118   llvm_unreachable("Unhandled type string");
1119 }
1120 #undef TYPE
1121 
1122 #define ENCODING(str, encoding) if (s == str) return encoding;
1123 OperandEncoding RecognizableInstr::immediateEncodingFromString
1124   (const std::string &s,
1125    bool hasOpSizePrefix) {
1126   if(!hasOpSizePrefix) {
1127     // For instructions without an OpSize prefix, a declared 16-bit register or
1128     // immediate encoding is special.
1129     ENCODING("i16imm",        ENCODING_IW)
1130   }
1131   ENCODING("i32i8imm",        ENCODING_IB)
1132   ENCODING("u32u8imm",        ENCODING_IB)
1133   ENCODING("SSECC",           ENCODING_IB)
1134   ENCODING("i16imm",          ENCODING_Iv)
1135   ENCODING("i16i8imm",        ENCODING_IB)
1136   ENCODING("i32imm",          ENCODING_Iv)
1137   ENCODING("i64i32imm",       ENCODING_ID)
1138   ENCODING("i64i8imm",        ENCODING_IB)
1139   ENCODING("i8imm",           ENCODING_IB)
1140   // This is not a typo.  Instructions like BLENDVPD put
1141   // register IDs in 8-bit immediates nowadays.
1142   ENCODING("VR256",           ENCODING_IB)
1143   ENCODING("VR128",           ENCODING_IB)
1144   errs() << "Unhandled immediate encoding " << s << "\n";
1145   llvm_unreachable("Unhandled immediate encoding");
1146 }
1147 
1148 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1149   (const std::string &s,
1150    bool hasOpSizePrefix) {
1151   ENCODING("GR16",            ENCODING_RM)
1152   ENCODING("GR32",            ENCODING_RM)
1153   ENCODING("GR64",            ENCODING_RM)
1154   ENCODING("GR8",             ENCODING_RM)
1155   ENCODING("VR128",           ENCODING_RM)
1156   ENCODING("FR64",            ENCODING_RM)
1157   ENCODING("FR32",            ENCODING_RM)
1158   ENCODING("VR64",            ENCODING_RM)
1159   ENCODING("VR256",           ENCODING_RM)
1160   errs() << "Unhandled R/M register encoding " << s << "\n";
1161   llvm_unreachable("Unhandled R/M register encoding");
1162 }
1163 
1164 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1165   (const std::string &s,
1166    bool hasOpSizePrefix) {
1167   ENCODING("GR16",            ENCODING_REG)
1168   ENCODING("GR32",            ENCODING_REG)
1169   ENCODING("GR64",            ENCODING_REG)
1170   ENCODING("GR8",             ENCODING_REG)
1171   ENCODING("VR128",           ENCODING_REG)
1172   ENCODING("FR64",            ENCODING_REG)
1173   ENCODING("FR32",            ENCODING_REG)
1174   ENCODING("VR64",            ENCODING_REG)
1175   ENCODING("SEGMENT_REG",     ENCODING_REG)
1176   ENCODING("DEBUG_REG",       ENCODING_REG)
1177   ENCODING("CONTROL_REG",     ENCODING_REG)
1178   ENCODING("VR256",           ENCODING_REG)
1179   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1180   llvm_unreachable("Unhandled reg/opcode register encoding");
1181 }
1182 
1183 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1184   (const std::string &s,
1185    bool hasOpSizePrefix) {
1186   ENCODING("GR32",            ENCODING_VVVV)
1187   ENCODING("GR64",            ENCODING_VVVV)
1188   ENCODING("FR32",            ENCODING_VVVV)
1189   ENCODING("FR64",            ENCODING_VVVV)
1190   ENCODING("VR128",           ENCODING_VVVV)
1191   ENCODING("VR256",           ENCODING_VVVV)
1192   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1193   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1194 }
1195 
1196 OperandEncoding RecognizableInstr::memoryEncodingFromString
1197   (const std::string &s,
1198    bool hasOpSizePrefix) {
1199   ENCODING("i16mem",          ENCODING_RM)
1200   ENCODING("i32mem",          ENCODING_RM)
1201   ENCODING("i64mem",          ENCODING_RM)
1202   ENCODING("i8mem",           ENCODING_RM)
1203   ENCODING("ssmem",           ENCODING_RM)
1204   ENCODING("sdmem",           ENCODING_RM)
1205   ENCODING("f128mem",         ENCODING_RM)
1206   ENCODING("f256mem",         ENCODING_RM)
1207   ENCODING("f64mem",          ENCODING_RM)
1208   ENCODING("f32mem",          ENCODING_RM)
1209   ENCODING("i128mem",         ENCODING_RM)
1210   ENCODING("i256mem",         ENCODING_RM)
1211   ENCODING("f80mem",          ENCODING_RM)
1212   ENCODING("lea32mem",        ENCODING_RM)
1213   ENCODING("lea64_32mem",     ENCODING_RM)
1214   ENCODING("lea64mem",        ENCODING_RM)
1215   ENCODING("opaque32mem",     ENCODING_RM)
1216   ENCODING("opaque48mem",     ENCODING_RM)
1217   ENCODING("opaque80mem",     ENCODING_RM)
1218   ENCODING("opaque512mem",    ENCODING_RM)
1219   errs() << "Unhandled memory encoding " << s << "\n";
1220   llvm_unreachable("Unhandled memory encoding");
1221 }
1222 
1223 OperandEncoding RecognizableInstr::relocationEncodingFromString
1224   (const std::string &s,
1225    bool hasOpSizePrefix) {
1226   if(!hasOpSizePrefix) {
1227     // For instructions without an OpSize prefix, a declared 16-bit register or
1228     // immediate encoding is special.
1229     ENCODING("i16imm",        ENCODING_IW)
1230   }
1231   ENCODING("i16imm",          ENCODING_Iv)
1232   ENCODING("i16i8imm",        ENCODING_IB)
1233   ENCODING("i32imm",          ENCODING_Iv)
1234   ENCODING("i32i8imm",        ENCODING_IB)
1235   ENCODING("i64i32imm",       ENCODING_ID)
1236   ENCODING("i64i8imm",        ENCODING_IB)
1237   ENCODING("i8imm",           ENCODING_IB)
1238   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1239   ENCODING("i16imm_pcrel",    ENCODING_IW)
1240   ENCODING("i32imm_pcrel",    ENCODING_ID)
1241   ENCODING("brtarget",        ENCODING_Iv)
1242   ENCODING("brtarget8",       ENCODING_IB)
1243   ENCODING("i64imm",          ENCODING_IO)
1244   ENCODING("offset8",         ENCODING_Ia)
1245   ENCODING("offset16",        ENCODING_Ia)
1246   ENCODING("offset32",        ENCODING_Ia)
1247   ENCODING("offset64",        ENCODING_Ia)
1248   errs() << "Unhandled relocation encoding " << s << "\n";
1249   llvm_unreachable("Unhandled relocation encoding");
1250 }
1251 
1252 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1253   (const std::string &s,
1254    bool hasOpSizePrefix) {
1255   ENCODING("RST",             ENCODING_I)
1256   ENCODING("GR32",            ENCODING_Rv)
1257   ENCODING("GR64",            ENCODING_RO)
1258   ENCODING("GR16",            ENCODING_Rv)
1259   ENCODING("GR8",             ENCODING_RB)
1260   ENCODING("GR16_NOAX",       ENCODING_Rv)
1261   ENCODING("GR32_NOAX",       ENCODING_Rv)
1262   ENCODING("GR64_NOAX",       ENCODING_RO)
1263   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1264   llvm_unreachable("Unhandled opcode modifier encoding");
1265 }
1266 #undef ENCODING
1267