1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22 
23 using namespace llvm;
24 
25 #define MRM_MAPPING     \
26   MAP(C1, 33)           \
27   MAP(C2, 34)           \
28   MAP(C3, 35)           \
29   MAP(C4, 36)           \
30   MAP(C8, 37)           \
31   MAP(C9, 38)           \
32   MAP(CA, 39)           \
33   MAP(CB, 40)           \
34   MAP(E8, 41)           \
35   MAP(F0, 42)           \
36   MAP(F8, 45)           \
37   MAP(F9, 46)           \
38   MAP(D0, 47)           \
39   MAP(D1, 48)           \
40   MAP(D4, 49)           \
41   MAP(D5, 50)           \
42   MAP(D6, 51)           \
43   MAP(D8, 52)           \
44   MAP(D9, 53)           \
45   MAP(DA, 54)           \
46   MAP(DB, 55)           \
47   MAP(DC, 56)           \
48   MAP(DD, 57)           \
49   MAP(DE, 58)           \
50   MAP(DF, 59)
51 
52 // A clone of X86 since we can't depend on something that is generated.
53 namespace X86Local {
54   enum {
55     Pseudo      = 0,
56     RawFrm      = 1,
57     AddRegFrm   = 2,
58     MRMDestReg  = 3,
59     MRMDestMem  = 4,
60     MRMSrcReg   = 5,
61     MRMSrcMem   = 6,
62     RawFrmMemOffs = 7,
63     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
64     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
65     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
66     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
67     RawFrmImm8  = 43,
68     RawFrmImm16 = 44,
69 #define MAP(from, to) MRM_##from = to,
70     MRM_MAPPING
71 #undef MAP
72     lastMRM
73   };
74 
75   enum {
76     TB  = 1,
77     REP = 2,
78     D8 = 3, D9 = 4, DA = 5, DB = 6,
79     DC = 7, DD = 8, DE = 9, DF = 10,
80     XD = 11,  XS = 12,
81     T8 = 13,  P_TA = 14,
82     A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83     XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
84   };
85 }
86 
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
89 //
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 //
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 //
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
103 
104 #define ONE_BYTE_EXTENSION_TABLES \
105   EXTENSION_TABLE(80)             \
106   EXTENSION_TABLE(81)             \
107   EXTENSION_TABLE(82)             \
108   EXTENSION_TABLE(83)             \
109   EXTENSION_TABLE(8f)             \
110   EXTENSION_TABLE(c0)             \
111   EXTENSION_TABLE(c1)             \
112   EXTENSION_TABLE(c6)             \
113   EXTENSION_TABLE(c7)             \
114   EXTENSION_TABLE(d0)             \
115   EXTENSION_TABLE(d1)             \
116   EXTENSION_TABLE(d2)             \
117   EXTENSION_TABLE(d3)             \
118   EXTENSION_TABLE(f6)             \
119   EXTENSION_TABLE(f7)             \
120   EXTENSION_TABLE(fe)             \
121   EXTENSION_TABLE(ff)
122 
123 #define TWO_BYTE_EXTENSION_TABLES \
124   EXTENSION_TABLE(00)             \
125   EXTENSION_TABLE(01)             \
126   EXTENSION_TABLE(0d)             \
127   EXTENSION_TABLE(18)             \
128   EXTENSION_TABLE(71)             \
129   EXTENSION_TABLE(72)             \
130   EXTENSION_TABLE(73)             \
131   EXTENSION_TABLE(ae)             \
132   EXTENSION_TABLE(ba)             \
133   EXTENSION_TABLE(c7)
134 
135 #define THREE_BYTE_38_EXTENSION_TABLES \
136   EXTENSION_TABLE(F3)
137 
138 #define XOP9_MAP_EXTENSION_TABLES \
139   EXTENSION_TABLE(01)             \
140   EXTENSION_TABLE(02)
141 
142 using namespace X86Disassembler;
143 
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
146 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
147 ///   0b11.
148 ///
149 /// @param form - The form of the instruction.
150 /// @return     - true if the form implies that a ModR/M byte is required, false
151 ///               otherwise.
152 static bool needsModRMForDecode(uint8_t form) {
153   if (form == X86Local::MRMDestReg    ||
154      form == X86Local::MRMDestMem    ||
155      form == X86Local::MRMSrcReg     ||
156      form == X86Local::MRMSrcMem     ||
157      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159     return true;
160   else
161     return false;
162 }
163 
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 ///   the ModR/M byte to be 0b11.
166 ///
167 /// @param form - The form of the instruction.
168 /// @return     - true if the form implies that Mod must be 0b11, false
169 ///               otherwise.
170 static bool isRegFormat(uint8_t form) {
171   if (form == X86Local::MRMDestReg ||
172      form == X86Local::MRMSrcReg  ||
173      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174     return true;
175   else
176     return false;
177 }
178 
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 ///   Useful for switch statements and the like.
181 ///
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return     - The field, with the first bit in the BitsInit as the lowest
184 ///               order bit.
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186   int width = init.getNumBits();
187 
188   assert(width <= 8 && "Field is too large for uint8_t!");
189 
190   int     index;
191   uint8_t mask = 0x01;
192 
193   uint8_t ret = 0;
194 
195   for (index = 0; index < width; index++) {
196     if (static_cast<BitInit*>(init.getBit(index))->getValue())
197       ret |= mask;
198 
199     mask <<= 1;
200   }
201 
202   return ret;
203 }
204 
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 ///   name of the field.
207 ///
208 /// @param rec  - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return     - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212   BitsInit* bits = rec->getValueAsBitsInit(name);
213   return byteFromBitsInit(*bits);
214 }
215 
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217                                      const CodeGenInstruction &insn,
218                                      InstrUID uid) {
219   UID = uid;
220 
221   Rec = insn.TheDef;
222   Name = Rec->getName();
223   Spec = &tables.specForUID(UID);
224 
225   if (!Rec->isSubClassOf("X86Inst")) {
226     ShouldBeEmitted = false;
227     return;
228   }
229 
230   Prefix   = byteFromRec(Rec, "Prefix");
231   Opcode   = byteFromRec(Rec, "Opcode");
232   Form     = byteFromRec(Rec, "FormBits");
233 
234   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
235   HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
236   HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
237   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
238   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
239   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
240   HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
242   HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
243   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
244   HasEVEXPrefix    = Rec->getValueAsBit("hasEVEXPrefix");
245   HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246   HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
247   HasEVEX_KZ       = Rec->getValueAsBit("hasEVEX_Z");
248   HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
249   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
250   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
251   ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
252 
253   Name      = Rec->getName();
254   AsmString = Rec->getValueAsString("AsmString");
255 
256   Operands = &insn.Operands.OperandList;
257 
258   HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
259 
260   // Check for 64-bit inst which does not require REX
261   Is32Bit = false;
262   Is64Bit = false;
263   // FIXME: Is there some better way to check for In64BitMode?
264   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
265   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
266     if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
267 	Predicates[i]->getName().find("In32Bit") != Name.npos) {
268       Is32Bit = true;
269       break;
270     }
271     if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
272       Is64Bit = true;
273       break;
274     }
275   }
276 
277   ShouldBeEmitted  = true;
278 }
279 
280 void RecognizableInstr::processInstr(DisassemblerTables &tables,
281                                      const CodeGenInstruction &insn,
282                                      InstrUID uid)
283 {
284   // Ignore "asm parser only" instructions.
285   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
286     return;
287 
288   RecognizableInstr recogInstr(tables, insn, uid);
289 
290   recogInstr.emitInstructionSpecifier();
291 
292   if (recogInstr.shouldBeEmitted())
293     recogInstr.emitDecodePath(tables);
294 }
295 
296 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
297                     (HasEVEX_K && HasEVEX_B ? n##_K_B : \
298                     (HasEVEX_KZ ? n##_KZ : \
299                     (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
300 
301 InstructionContext RecognizableInstr::insnContext() const {
302   InstructionContext insnContext;
303 
304   if (HasEVEXPrefix) {
305     if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
306       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
307       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
308     }
309     // VEX_L & VEX_W
310     if (HasVEX_LPrefix && HasVEX_WPrefix) {
311       if (HasOpSizePrefix || Prefix == X86Local::PD)
312         insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
313       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
314         insnContext = EVEX_KB(IC_EVEX_L_W_XS);
315       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
316                Prefix == X86Local::TAXD)
317         insnContext = EVEX_KB(IC_EVEX_L_W_XD);
318       else
319         insnContext = EVEX_KB(IC_EVEX_L_W);
320     } else if (HasVEX_LPrefix) {
321       // VEX_L
322       if (HasOpSizePrefix || Prefix == X86Local::PD ||
323           Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
324         insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
325       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326         insnContext = EVEX_KB(IC_EVEX_L_XS);
327       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328                Prefix == X86Local::TAXD)
329         insnContext = EVEX_KB(IC_EVEX_L_XD);
330       else
331         insnContext = EVEX_KB(IC_EVEX_L);
332     }
333     else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
334       // EVEX_L2 & VEX_W
335       if (HasOpSizePrefix || Prefix == X86Local::PD ||
336           Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
337         insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
338       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
339         insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
340       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341                Prefix == X86Local::TAXD)
342         insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
343       else
344         insnContext = EVEX_KB(IC_EVEX_L2_W);
345     } else if (HasEVEX_L2Prefix) {
346       // EVEX_L2
347       if (HasOpSizePrefix || Prefix == X86Local::PD ||
348           Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
349         insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
350       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
351                Prefix == X86Local::TAXD)
352         insnContext = EVEX_KB(IC_EVEX_L2_XD);
353       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
354         insnContext = EVEX_KB(IC_EVEX_L2_XS);
355       else
356         insnContext = EVEX_KB(IC_EVEX_L2);
357     }
358     else if (HasVEX_WPrefix) {
359       // VEX_W
360       if (HasOpSizePrefix || Prefix == X86Local::PD ||
361           Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
362         insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
363       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364         insnContext = EVEX_KB(IC_EVEX_W_XS);
365       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
366                Prefix == X86Local::TAXD)
367         insnContext = EVEX_KB(IC_EVEX_W_XD);
368       else
369         insnContext = EVEX_KB(IC_EVEX_W);
370     }
371     // No L, no W
372     else if (HasOpSizePrefix || Prefix == X86Local::PD ||
373           Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
374       insnContext = EVEX_KB(IC_EVEX_OPSIZE);
375     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
376              Prefix == X86Local::TAXD)
377       insnContext = EVEX_KB(IC_EVEX_XD);
378     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
379       insnContext = EVEX_KB(IC_EVEX_XS);
380     else
381       insnContext = EVEX_KB(IC_EVEX);
382     /// eof EVEX
383   } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
384     if (HasVEX_LPrefix && HasVEX_WPrefix) {
385       if (HasOpSizePrefix || Prefix == X86Local::PD ||
386           Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
387         insnContext = IC_VEX_L_W_OPSIZE;
388       else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
389         insnContext = IC_VEX_L_W_XS;
390       else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
391                Prefix == X86Local::TAXD)
392         insnContext = IC_VEX_L_W_XD;
393       else
394         insnContext = IC_VEX_L_W;
395     } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
396                 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
397                HasVEX_LPrefix)
398       insnContext = IC_VEX_L_OPSIZE;
399     else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
400               Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
401              HasVEX_WPrefix)
402       insnContext = IC_VEX_W_OPSIZE;
403     else if (HasOpSizePrefix || Prefix == X86Local::PD ||
404              Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
405       insnContext = IC_VEX_OPSIZE;
406     else if (HasVEX_LPrefix &&
407              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
408       insnContext = IC_VEX_L_XS;
409     else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
410                                 Prefix == X86Local::T8XD ||
411                                 Prefix == X86Local::TAXD))
412       insnContext = IC_VEX_L_XD;
413     else if (HasVEX_WPrefix &&
414              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
415       insnContext = IC_VEX_W_XS;
416     else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
417                                 Prefix == X86Local::T8XD ||
418                                 Prefix == X86Local::TAXD))
419       insnContext = IC_VEX_W_XD;
420     else if (HasVEX_WPrefix)
421       insnContext = IC_VEX_W;
422     else if (HasVEX_LPrefix)
423       insnContext = IC_VEX_L;
424     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
425              Prefix == X86Local::TAXD)
426       insnContext = IC_VEX_XD;
427     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
428       insnContext = IC_VEX_XS;
429     else
430       insnContext = IC_VEX;
431   } else if (Is64Bit || HasREX_WPrefix) {
432     if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
433                            Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
434       insnContext = IC_64BIT_REXW_OPSIZE;
435     else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
436                                  Prefix == X86Local::T8XD ||
437                                  Prefix == X86Local::TAXD))
438       insnContext = IC_64BIT_XD_OPSIZE;
439     else if (HasOpSizePrefix &&
440              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441       insnContext = IC_64BIT_XS_OPSIZE;
442     else if (HasOpSizePrefix || Prefix == X86Local::PD ||
443              Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
444       insnContext = IC_64BIT_OPSIZE;
445     else if (HasAdSizePrefix)
446       insnContext = IC_64BIT_ADSIZE;
447     else if (HasREX_WPrefix &&
448              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
449       insnContext = IC_64BIT_REXW_XS;
450     else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
451                                 Prefix == X86Local::T8XD ||
452                                 Prefix == X86Local::TAXD))
453       insnContext = IC_64BIT_REXW_XD;
454     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
455              Prefix == X86Local::TAXD)
456       insnContext = IC_64BIT_XD;
457     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
458       insnContext = IC_64BIT_XS;
459     else if (HasREX_WPrefix)
460       insnContext = IC_64BIT_REXW;
461     else
462       insnContext = IC_64BIT;
463   } else {
464     if (HasOpSizePrefix && (Prefix == X86Local::XD ||
465                             Prefix == X86Local::T8XD ||
466                             Prefix == X86Local::TAXD))
467       insnContext = IC_XD_OPSIZE;
468     else if (HasOpSizePrefix &&
469              (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
470       insnContext = IC_XS_OPSIZE;
471     else if (HasOpSizePrefix && HasAdSizePrefix)
472       insnContext = IC_OPSIZE_ADSIZE;
473     else if (HasOpSizePrefix || Prefix == X86Local::PD ||
474              Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
475       insnContext = IC_OPSIZE;
476     else if (HasAdSizePrefix)
477       insnContext = IC_ADSIZE;
478     else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
479              Prefix == X86Local::TAXD)
480       insnContext = IC_XD;
481     else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
482              Prefix == X86Local::REP)
483       insnContext = IC_XS;
484     else
485       insnContext = IC;
486   }
487 
488   return insnContext;
489 }
490 
491 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
492   ///////////////////
493   // FILTER_STRONG
494   //
495 
496   // Filter out intrinsics
497 
498   assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
499 
500   if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
501     return FILTER_STRONG;
502 
503 
504   // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
505   // printed as a separate "instruction".
506 
507 
508   /////////////////
509   // FILTER_WEAK
510   //
511 
512 
513   // Filter out instructions with a LOCK prefix;
514   //   prefer forms that do not have the prefix
515   if (HasLockPrefix)
516     return FILTER_WEAK;
517 
518   // Special cases.
519 
520   if (Name == "VMASKMOVDQU64")
521     return FILTER_WEAK;
522 
523   // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
524   // For now, just prefer the REP versions.
525   if (Name == "XACQUIRE_PREFIX" ||
526       Name == "XRELEASE_PREFIX")
527     return FILTER_WEAK;
528 
529   return FILTER_NORMAL;
530 }
531 
532 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
533                                       unsigned &physicalOperandIndex,
534                                       unsigned &numPhysicalOperands,
535                                       const unsigned *operandMapping,
536                                       OperandEncoding (*encodingFromString)
537                                         (const std::string&,
538                                          bool hasOpSizePrefix)) {
539   if (optional) {
540     if (physicalOperandIndex >= numPhysicalOperands)
541       return;
542   } else {
543     assert(physicalOperandIndex < numPhysicalOperands);
544   }
545 
546   while (operandMapping[operandIndex] != operandIndex) {
547     Spec->operands[operandIndex].encoding = ENCODING_DUP;
548     Spec->operands[operandIndex].type =
549       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
550     ++operandIndex;
551   }
552 
553   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
554 
555   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
556                                                               HasOpSizePrefix);
557   Spec->operands[operandIndex].type = typeFromString(typeName,
558                                                      HasREX_WPrefix,
559                                                      HasOpSizePrefix,
560                                                      HasOpSize16Prefix);
561 
562   ++operandIndex;
563   ++physicalOperandIndex;
564 }
565 
566 void RecognizableInstr::emitInstructionSpecifier() {
567   Spec->name       = Name;
568 
569   if (!ShouldBeEmitted)
570     return;
571 
572   switch (filter()) {
573   case FILTER_WEAK:
574     Spec->filtered = true;
575     break;
576   case FILTER_STRONG:
577     ShouldBeEmitted = false;
578     return;
579   case FILTER_NORMAL:
580     break;
581   }
582 
583   Spec->insnContext = insnContext();
584 
585   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
586 
587   unsigned numOperands = OperandList.size();
588   unsigned numPhysicalOperands = 0;
589 
590   // operandMapping maps from operands in OperandList to their originals.
591   // If operandMapping[i] != i, then the entry is a duplicate.
592   unsigned operandMapping[X86_MAX_OPERANDS];
593   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
594 
595   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
596     if (OperandList[operandIndex].Constraints.size()) {
597       const CGIOperandList::ConstraintInfo &Constraint =
598         OperandList[operandIndex].Constraints[0];
599       if (Constraint.isTied()) {
600         operandMapping[operandIndex] = operandIndex;
601         operandMapping[Constraint.getTiedOperand()] = operandIndex;
602       } else {
603         ++numPhysicalOperands;
604         operandMapping[operandIndex] = operandIndex;
605       }
606     } else {
607       ++numPhysicalOperands;
608       operandMapping[operandIndex] = operandIndex;
609     }
610   }
611 
612 #define HANDLE_OPERAND(class)               \
613   handleOperand(false,                      \
614                 operandIndex,               \
615                 physicalOperandIndex,       \
616                 numPhysicalOperands,        \
617                 operandMapping,             \
618                 class##EncodingFromString);
619 
620 #define HANDLE_OPTIONAL(class)              \
621   handleOperand(true,                       \
622                 operandIndex,               \
623                 physicalOperandIndex,       \
624                 numPhysicalOperands,        \
625                 operandMapping,             \
626                 class##EncodingFromString);
627 
628   // operandIndex should always be < numOperands
629   unsigned operandIndex = 0;
630   // physicalOperandIndex should always be < numPhysicalOperands
631   unsigned physicalOperandIndex = 0;
632 
633   switch (Form) {
634   default: llvm_unreachable("Unhandled form");
635   case X86Local::RawFrm:
636     // Operand 1 (optional) is an address or immediate.
637     // Operand 2 (optional) is an immediate.
638     assert(numPhysicalOperands <= 2 &&
639            "Unexpected number of operands for RawFrm");
640     HANDLE_OPTIONAL(relocation)
641     HANDLE_OPTIONAL(immediate)
642     break;
643   case X86Local::RawFrmMemOffs:
644     // Operand 1 is an address.
645     HANDLE_OPERAND(relocation);
646     break;
647   case X86Local::AddRegFrm:
648     // Operand 1 is added to the opcode.
649     // Operand 2 (optional) is an address.
650     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
651            "Unexpected number of operands for AddRegFrm");
652     HANDLE_OPERAND(opcodeModifier)
653     HANDLE_OPTIONAL(relocation)
654     break;
655   case X86Local::MRMDestReg:
656     // Operand 1 is a register operand in the R/M field.
657     // Operand 2 is a register operand in the Reg/Opcode field.
658     // - In AVX, there is a register operand in the VEX.vvvv field here -
659     // Operand 3 (optional) is an immediate.
660     if (HasVEX_4VPrefix)
661       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
662              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
663     else
664       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
665              "Unexpected number of operands for MRMDestRegFrm");
666 
667     HANDLE_OPERAND(rmRegister)
668 
669     if (HasVEX_4VPrefix)
670       // FIXME: In AVX, the register below becomes the one encoded
671       // in ModRMVEX and the one above the one in the VEX.VVVV field
672       HANDLE_OPERAND(vvvvRegister)
673 
674     HANDLE_OPERAND(roRegister)
675     HANDLE_OPTIONAL(immediate)
676     break;
677   case X86Local::MRMDestMem:
678     // Operand 1 is a memory operand (possibly SIB-extended)
679     // Operand 2 is a register operand in the Reg/Opcode field.
680     // - In AVX, there is a register operand in the VEX.vvvv field here -
681     // Operand 3 (optional) is an immediate.
682     if (HasVEX_4VPrefix)
683       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
684              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
685     else
686       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
687              "Unexpected number of operands for MRMDestMemFrm");
688     HANDLE_OPERAND(memory)
689 
690     if (HasEVEX_K)
691       HANDLE_OPERAND(writemaskRegister)
692 
693     if (HasVEX_4VPrefix)
694       // FIXME: In AVX, the register below becomes the one encoded
695       // in ModRMVEX and the one above the one in the VEX.VVVV field
696       HANDLE_OPERAND(vvvvRegister)
697 
698     HANDLE_OPERAND(roRegister)
699     HANDLE_OPTIONAL(immediate)
700     break;
701   case X86Local::MRMSrcReg:
702     // Operand 1 is a register operand in the Reg/Opcode field.
703     // Operand 2 is a register operand in the R/M field.
704     // - In AVX, there is a register operand in the VEX.vvvv field here -
705     // Operand 3 (optional) is an immediate.
706     // Operand 4 (optional) is an immediate.
707 
708     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
709       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
710              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
711     else
712       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
713              "Unexpected number of operands for MRMSrcRegFrm");
714 
715     HANDLE_OPERAND(roRegister)
716 
717     if (HasEVEX_K)
718       HANDLE_OPERAND(writemaskRegister)
719 
720     if (HasVEX_4VPrefix)
721       // FIXME: In AVX, the register below becomes the one encoded
722       // in ModRMVEX and the one above the one in the VEX.VVVV field
723       HANDLE_OPERAND(vvvvRegister)
724 
725     if (HasMemOp4Prefix)
726       HANDLE_OPERAND(immediate)
727 
728     HANDLE_OPERAND(rmRegister)
729 
730     if (HasVEX_4VOp3Prefix)
731       HANDLE_OPERAND(vvvvRegister)
732 
733     if (!HasMemOp4Prefix)
734       HANDLE_OPTIONAL(immediate)
735     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
736     HANDLE_OPTIONAL(immediate)
737     break;
738   case X86Local::MRMSrcMem:
739     // Operand 1 is a register operand in the Reg/Opcode field.
740     // Operand 2 is a memory operand (possibly SIB-extended)
741     // - In AVX, there is a register operand in the VEX.vvvv field here -
742     // Operand 3 (optional) is an immediate.
743 
744     if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
745       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
746              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
747     else
748       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
749              "Unexpected number of operands for MRMSrcMemFrm");
750 
751     HANDLE_OPERAND(roRegister)
752 
753     if (HasEVEX_K)
754       HANDLE_OPERAND(writemaskRegister)
755 
756     if (HasVEX_4VPrefix)
757       // FIXME: In AVX, the register below becomes the one encoded
758       // in ModRMVEX and the one above the one in the VEX.VVVV field
759       HANDLE_OPERAND(vvvvRegister)
760 
761     if (HasMemOp4Prefix)
762       HANDLE_OPERAND(immediate)
763 
764     HANDLE_OPERAND(memory)
765 
766     if (HasVEX_4VOp3Prefix)
767       HANDLE_OPERAND(vvvvRegister)
768 
769     if (!HasMemOp4Prefix)
770       HANDLE_OPTIONAL(immediate)
771     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
772     break;
773   case X86Local::MRM0r:
774   case X86Local::MRM1r:
775   case X86Local::MRM2r:
776   case X86Local::MRM3r:
777   case X86Local::MRM4r:
778   case X86Local::MRM5r:
779   case X86Local::MRM6r:
780   case X86Local::MRM7r:
781     {
782       // Operand 1 is a register operand in the R/M field.
783       // Operand 2 (optional) is an immediate or relocation.
784       // Operand 3 (optional) is an immediate.
785       unsigned kOp = (HasEVEX_K) ? 1:0;
786       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
787       if (numPhysicalOperands > 3 + kOp + Op4v)
788         llvm_unreachable("Unexpected number of operands for MRMnr");
789     }
790     if (HasVEX_4VPrefix)
791       HANDLE_OPERAND(vvvvRegister)
792 
793     if (HasEVEX_K)
794       HANDLE_OPERAND(writemaskRegister)
795     HANDLE_OPTIONAL(rmRegister)
796     HANDLE_OPTIONAL(relocation)
797     HANDLE_OPTIONAL(immediate)
798     break;
799   case X86Local::MRM0m:
800   case X86Local::MRM1m:
801   case X86Local::MRM2m:
802   case X86Local::MRM3m:
803   case X86Local::MRM4m:
804   case X86Local::MRM5m:
805   case X86Local::MRM6m:
806   case X86Local::MRM7m:
807     {
808       // Operand 1 is a memory operand (possibly SIB-extended)
809       // Operand 2 (optional) is an immediate or relocation.
810       unsigned kOp = (HasEVEX_K) ? 1:0;
811       unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
812       if (numPhysicalOperands < 1 + kOp + Op4v ||
813           numPhysicalOperands > 2 + kOp + Op4v)
814         llvm_unreachable("Unexpected number of operands for MRMnm");
815     }
816     if (HasVEX_4VPrefix)
817       HANDLE_OPERAND(vvvvRegister)
818     if (HasEVEX_K)
819       HANDLE_OPERAND(writemaskRegister)
820     HANDLE_OPERAND(memory)
821     HANDLE_OPTIONAL(relocation)
822     break;
823   case X86Local::RawFrmImm8:
824     // operand 1 is a 16-bit immediate
825     // operand 2 is an 8-bit immediate
826     assert(numPhysicalOperands == 2 &&
827            "Unexpected number of operands for X86Local::RawFrmImm8");
828     HANDLE_OPERAND(immediate)
829     HANDLE_OPERAND(immediate)
830     break;
831   case X86Local::RawFrmImm16:
832     // operand 1 is a 16-bit immediate
833     // operand 2 is a 16-bit immediate
834     HANDLE_OPERAND(immediate)
835     HANDLE_OPERAND(immediate)
836     break;
837   case X86Local::MRM_F8:
838     if (Opcode == 0xc6) {
839       assert(numPhysicalOperands == 1 &&
840              "Unexpected number of operands for X86Local::MRM_F8");
841       HANDLE_OPERAND(immediate)
842     } else if (Opcode == 0xc7) {
843       assert(numPhysicalOperands == 1 &&
844              "Unexpected number of operands for X86Local::MRM_F8");
845       HANDLE_OPERAND(relocation)
846     }
847     break;
848   case X86Local::MRM_C1:
849   case X86Local::MRM_C2:
850   case X86Local::MRM_C3:
851   case X86Local::MRM_C4:
852   case X86Local::MRM_C8:
853   case X86Local::MRM_C9:
854   case X86Local::MRM_CA:
855   case X86Local::MRM_CB:
856   case X86Local::MRM_E8:
857   case X86Local::MRM_F0:
858   case X86Local::MRM_F9:
859   case X86Local::MRM_D0:
860   case X86Local::MRM_D1:
861   case X86Local::MRM_D4:
862   case X86Local::MRM_D5:
863   case X86Local::MRM_D6:
864   case X86Local::MRM_D8:
865   case X86Local::MRM_D9:
866   case X86Local::MRM_DA:
867   case X86Local::MRM_DB:
868   case X86Local::MRM_DC:
869   case X86Local::MRM_DD:
870   case X86Local::MRM_DE:
871   case X86Local::MRM_DF:
872     // Ignored.
873     break;
874   }
875 
876   #undef HANDLE_OPERAND
877   #undef HANDLE_OPTIONAL
878 }
879 
880 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
881   // Special cases where the LLVM tables are not complete
882 
883 #define MAP(from, to)                     \
884   case X86Local::MRM_##from:              \
885     filter = new ExactFilter(0x##from);   \
886     break;
887 
888   OpcodeType    opcodeType  = (OpcodeType)-1;
889 
890   ModRMFilter*  filter      = NULL;
891   uint8_t       opcodeToSet = 0;
892 
893   switch (Prefix) {
894   default: llvm_unreachable("Invalid prefix!");
895   // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
896   case X86Local::PD:
897   case X86Local::XD:
898   case X86Local::XS:
899   case X86Local::TB:
900     opcodeType = TWOBYTE;
901 
902     switch (Opcode) {
903     default:
904       if (needsModRMForDecode(Form))
905         filter = new ModFilter(isRegFormat(Form));
906       else
907         filter = new DumbFilter();
908       break;
909 #define EXTENSION_TABLE(n) case 0x##n:
910     TWO_BYTE_EXTENSION_TABLES
911 #undef EXTENSION_TABLE
912       switch (Form) {
913       default:
914         llvm_unreachable("Unhandled two-byte extended opcode");
915       case X86Local::MRM0r:
916       case X86Local::MRM1r:
917       case X86Local::MRM2r:
918       case X86Local::MRM3r:
919       case X86Local::MRM4r:
920       case X86Local::MRM5r:
921       case X86Local::MRM6r:
922       case X86Local::MRM7r:
923         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
924         break;
925       case X86Local::MRM0m:
926       case X86Local::MRM1m:
927       case X86Local::MRM2m:
928       case X86Local::MRM3m:
929       case X86Local::MRM4m:
930       case X86Local::MRM5m:
931       case X86Local::MRM6m:
932       case X86Local::MRM7m:
933         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
934         break;
935       MRM_MAPPING
936       } // switch (Form)
937       break;
938     } // switch (Opcode)
939     opcodeToSet = Opcode;
940     break;
941   case X86Local::T8:
942   case X86Local::T8PD:
943   case X86Local::T8XD:
944   case X86Local::T8XS:
945     opcodeType = THREEBYTE_38;
946     switch (Opcode) {
947     default:
948       if (needsModRMForDecode(Form))
949         filter = new ModFilter(isRegFormat(Form));
950       else
951         filter = new DumbFilter();
952       break;
953 #define EXTENSION_TABLE(n) case 0x##n:
954     THREE_BYTE_38_EXTENSION_TABLES
955 #undef EXTENSION_TABLE
956       switch (Form) {
957       default:
958         llvm_unreachable("Unhandled two-byte extended opcode");
959       case X86Local::MRM0r:
960       case X86Local::MRM1r:
961       case X86Local::MRM2r:
962       case X86Local::MRM3r:
963       case X86Local::MRM4r:
964       case X86Local::MRM5r:
965       case X86Local::MRM6r:
966       case X86Local::MRM7r:
967         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
968         break;
969       case X86Local::MRM0m:
970       case X86Local::MRM1m:
971       case X86Local::MRM2m:
972       case X86Local::MRM3m:
973       case X86Local::MRM4m:
974       case X86Local::MRM5m:
975       case X86Local::MRM6m:
976       case X86Local::MRM7m:
977         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
978         break;
979       MRM_MAPPING
980       } // switch (Form)
981       break;
982     } // switch (Opcode)
983     opcodeToSet = Opcode;
984     break;
985   case X86Local::P_TA:
986   case X86Local::TAPD:
987   case X86Local::TAXD:
988     opcodeType = THREEBYTE_3A;
989     if (needsModRMForDecode(Form))
990       filter = new ModFilter(isRegFormat(Form));
991     else
992       filter = new DumbFilter();
993     opcodeToSet = Opcode;
994     break;
995   case X86Local::A6:
996     opcodeType = THREEBYTE_A6;
997     if (needsModRMForDecode(Form))
998       filter = new ModFilter(isRegFormat(Form));
999     else
1000       filter = new DumbFilter();
1001     opcodeToSet = Opcode;
1002     break;
1003   case X86Local::A7:
1004     opcodeType = THREEBYTE_A7;
1005     if (needsModRMForDecode(Form))
1006       filter = new ModFilter(isRegFormat(Form));
1007     else
1008       filter = new DumbFilter();
1009     opcodeToSet = Opcode;
1010     break;
1011   case X86Local::XOP8:
1012     opcodeType = XOP8_MAP;
1013     if (needsModRMForDecode(Form))
1014       filter = new ModFilter(isRegFormat(Form));
1015     else
1016       filter = new DumbFilter();
1017     opcodeToSet = Opcode;
1018     break;
1019   case X86Local::XOP9:
1020     opcodeType = XOP9_MAP;
1021     switch (Opcode) {
1022     default:
1023       if (needsModRMForDecode(Form))
1024         filter = new ModFilter(isRegFormat(Form));
1025       else
1026         filter = new DumbFilter();
1027       break;
1028 #define EXTENSION_TABLE(n) case 0x##n:
1029     XOP9_MAP_EXTENSION_TABLES
1030 #undef EXTENSION_TABLE
1031       switch (Form) {
1032       default:
1033         llvm_unreachable("Unhandled XOP9 extended opcode");
1034       case X86Local::MRM0r:
1035       case X86Local::MRM1r:
1036       case X86Local::MRM2r:
1037       case X86Local::MRM3r:
1038       case X86Local::MRM4r:
1039       case X86Local::MRM5r:
1040       case X86Local::MRM6r:
1041       case X86Local::MRM7r:
1042         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1043         break;
1044       case X86Local::MRM0m:
1045       case X86Local::MRM1m:
1046       case X86Local::MRM2m:
1047       case X86Local::MRM3m:
1048       case X86Local::MRM4m:
1049       case X86Local::MRM5m:
1050       case X86Local::MRM6m:
1051       case X86Local::MRM7m:
1052         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1053         break;
1054       MRM_MAPPING
1055       } // switch (Form)
1056       break;
1057     } // switch (Opcode)
1058     opcodeToSet = Opcode;
1059     break;
1060   case X86Local::XOPA:
1061     opcodeType = XOPA_MAP;
1062     if (needsModRMForDecode(Form))
1063       filter = new ModFilter(isRegFormat(Form));
1064     else
1065       filter = new DumbFilter();
1066     opcodeToSet = Opcode;
1067     break;
1068   case X86Local::D8:
1069   case X86Local::D9:
1070   case X86Local::DA:
1071   case X86Local::DB:
1072   case X86Local::DC:
1073   case X86Local::DD:
1074   case X86Local::DE:
1075   case X86Local::DF:
1076     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1077     assert(Form == X86Local::RawFrm);
1078     opcodeType = ONEBYTE;
1079     filter = new ExactFilter(Opcode);
1080     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1081     break;
1082   case X86Local::REP:
1083   case 0:
1084     opcodeType = ONEBYTE;
1085     switch (Opcode) {
1086 #define EXTENSION_TABLE(n) case 0x##n:
1087     ONE_BYTE_EXTENSION_TABLES
1088 #undef EXTENSION_TABLE
1089       switch (Form) {
1090       default:
1091         llvm_unreachable("Fell through the cracks of a single-byte "
1092                          "extended opcode");
1093       case X86Local::MRM0r:
1094       case X86Local::MRM1r:
1095       case X86Local::MRM2r:
1096       case X86Local::MRM3r:
1097       case X86Local::MRM4r:
1098       case X86Local::MRM5r:
1099       case X86Local::MRM6r:
1100       case X86Local::MRM7r:
1101         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1102         break;
1103       case X86Local::MRM0m:
1104       case X86Local::MRM1m:
1105       case X86Local::MRM2m:
1106       case X86Local::MRM3m:
1107       case X86Local::MRM4m:
1108       case X86Local::MRM5m:
1109       case X86Local::MRM6m:
1110       case X86Local::MRM7m:
1111         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1112         break;
1113       MRM_MAPPING
1114       } // switch (Form)
1115       break;
1116     case 0xd8:
1117     case 0xd9:
1118     case 0xda:
1119     case 0xdb:
1120     case 0xdc:
1121     case 0xdd:
1122     case 0xde:
1123     case 0xdf:
1124       switch (Form) {
1125       default:
1126         llvm_unreachable("Unhandled escape opcode form");
1127       case X86Local::MRM0r:
1128       case X86Local::MRM1r:
1129       case X86Local::MRM2r:
1130       case X86Local::MRM3r:
1131       case X86Local::MRM4r:
1132       case X86Local::MRM5r:
1133       case X86Local::MRM6r:
1134       case X86Local::MRM7r:
1135         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1136         break;
1137       case X86Local::MRM0m:
1138       case X86Local::MRM1m:
1139       case X86Local::MRM2m:
1140       case X86Local::MRM3m:
1141       case X86Local::MRM4m:
1142       case X86Local::MRM5m:
1143       case X86Local::MRM6m:
1144       case X86Local::MRM7m:
1145         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1146         break;
1147       } // switch (Form)
1148       break;
1149     default:
1150       if (needsModRMForDecode(Form))
1151         filter = new ModFilter(isRegFormat(Form));
1152       else
1153         filter = new DumbFilter();
1154       break;
1155     } // switch (Opcode)
1156     opcodeToSet = Opcode;
1157   } // switch (Prefix)
1158 
1159   assert(opcodeType != (OpcodeType)-1 &&
1160          "Opcode type not set");
1161   assert(filter && "Filter not set");
1162 
1163   if (Form == X86Local::AddRegFrm) {
1164     assert(((opcodeToSet & 7) == 0) &&
1165            "ADDREG_FRM opcode not aligned");
1166 
1167     uint8_t currentOpcode;
1168 
1169     for (currentOpcode = opcodeToSet;
1170          currentOpcode < opcodeToSet + 8;
1171          ++currentOpcode)
1172       tables.setTableFields(opcodeType,
1173                             insnContext(),
1174                             currentOpcode,
1175                             *filter,
1176                             UID, Is32Bit, IgnoresVEX_L);
1177   } else {
1178     tables.setTableFields(opcodeType,
1179                           insnContext(),
1180                           opcodeToSet,
1181                           *filter,
1182                           UID, Is32Bit, IgnoresVEX_L);
1183   }
1184 
1185   delete filter;
1186 
1187 #undef MAP
1188 }
1189 
1190 #define TYPE(str, type) if (s == str) return type;
1191 OperandType RecognizableInstr::typeFromString(const std::string &s,
1192                                               bool hasREX_WPrefix,
1193                                               bool hasOpSizePrefix,
1194                                               bool hasOpSize16Prefix) {
1195   if(hasREX_WPrefix) {
1196     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1197     // is special.
1198     TYPE("GR32",              TYPE_R32)
1199   }
1200   if(hasOpSizePrefix) {
1201     // For instructions with an OpSize prefix, a declared 16-bit register or
1202     // immediate encoding is special.
1203     TYPE("GR16",              TYPE_Rv)
1204     TYPE("i16imm",            TYPE_IMMv)
1205   }
1206   if(hasOpSize16Prefix) {
1207     // For instructions with an OpSize16 prefix, a declared 32-bit register or
1208     // immediate encoding is special.
1209     TYPE("GR32",              TYPE_Rv)
1210   }
1211   TYPE("i16mem",              TYPE_Mv)
1212   TYPE("i16imm",              TYPE_IMM16)
1213   TYPE("i16i8imm",            TYPE_IMMv)
1214   TYPE("GR16",                TYPE_R16)
1215   TYPE("i32mem",              TYPE_Mv)
1216   TYPE("i32imm",              TYPE_IMMv)
1217   TYPE("i32i8imm",            TYPE_IMM32)
1218   TYPE("u32u8imm",            TYPE_IMM32)
1219   TYPE("GR32",                TYPE_R32)
1220   TYPE("GR32orGR64",          TYPE_R32)
1221   TYPE("i64mem",              TYPE_Mv)
1222   TYPE("i64i32imm",           TYPE_IMM64)
1223   TYPE("i64i8imm",            TYPE_IMM64)
1224   TYPE("GR64",                TYPE_R64)
1225   TYPE("i8mem",               TYPE_M8)
1226   TYPE("i8imm",               TYPE_IMM8)
1227   TYPE("GR8",                 TYPE_R8)
1228   TYPE("VR128",               TYPE_XMM128)
1229   TYPE("VR128X",              TYPE_XMM128)
1230   TYPE("f128mem",             TYPE_M128)
1231   TYPE("f256mem",             TYPE_M256)
1232   TYPE("f512mem",             TYPE_M512)
1233   TYPE("FR64",                TYPE_XMM64)
1234   TYPE("FR64X",               TYPE_XMM64)
1235   TYPE("f64mem",              TYPE_M64FP)
1236   TYPE("sdmem",               TYPE_M64FP)
1237   TYPE("FR32",                TYPE_XMM32)
1238   TYPE("FR32X",               TYPE_XMM32)
1239   TYPE("f32mem",              TYPE_M32FP)
1240   TYPE("ssmem",               TYPE_M32FP)
1241   TYPE("RST",                 TYPE_ST)
1242   TYPE("i128mem",             TYPE_M128)
1243   TYPE("i256mem",             TYPE_M256)
1244   TYPE("i512mem",             TYPE_M512)
1245   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1246   TYPE("i16imm_pcrel",        TYPE_REL16)
1247   TYPE("i32imm_pcrel",        TYPE_REL32)
1248   TYPE("SSECC",               TYPE_IMM3)
1249   TYPE("AVXCC",               TYPE_IMM5)
1250   TYPE("AVX512RC",            TYPE_IMM32)
1251   TYPE("brtarget",            TYPE_RELv)
1252   TYPE("uncondbrtarget",      TYPE_RELv)
1253   TYPE("brtarget8",           TYPE_REL8)
1254   TYPE("f80mem",              TYPE_M80FP)
1255   TYPE("lea32mem",            TYPE_LEA)
1256   TYPE("lea64_32mem",         TYPE_LEA)
1257   TYPE("lea64mem",            TYPE_LEA)
1258   TYPE("VR64",                TYPE_MM64)
1259   TYPE("i64imm",              TYPE_IMMv)
1260   TYPE("opaque32mem",         TYPE_M1616)
1261   TYPE("opaque48mem",         TYPE_M1632)
1262   TYPE("opaque80mem",         TYPE_M1664)
1263   TYPE("opaque512mem",        TYPE_M512)
1264   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1265   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1266   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1267   TYPE("offset8",             TYPE_MOFFS8)
1268   TYPE("offset16",            TYPE_MOFFS16)
1269   TYPE("offset32",            TYPE_MOFFS32)
1270   TYPE("offset64",            TYPE_MOFFS64)
1271   TYPE("VR256",               TYPE_XMM256)
1272   TYPE("VR256X",              TYPE_XMM256)
1273   TYPE("VR512",               TYPE_XMM512)
1274   TYPE("VK1",                 TYPE_VK1)
1275   TYPE("VK1WM",               TYPE_VK1)
1276   TYPE("VK8",                 TYPE_VK8)
1277   TYPE("VK8WM",               TYPE_VK8)
1278   TYPE("VK16",                TYPE_VK16)
1279   TYPE("VK16WM",              TYPE_VK16)
1280   TYPE("GR16_NOAX",           TYPE_Rv)
1281   TYPE("GR32_NOAX",           TYPE_Rv)
1282   TYPE("GR64_NOAX",           TYPE_R64)
1283   TYPE("vx32mem",             TYPE_M32)
1284   TYPE("vy32mem",             TYPE_M32)
1285   TYPE("vz32mem",             TYPE_M32)
1286   TYPE("vx64mem",             TYPE_M64)
1287   TYPE("vy64mem",             TYPE_M64)
1288   TYPE("vy64xmem",            TYPE_M64)
1289   TYPE("vz64mem",             TYPE_M64)
1290   errs() << "Unhandled type string " << s << "\n";
1291   llvm_unreachable("Unhandled type string");
1292 }
1293 #undef TYPE
1294 
1295 #define ENCODING(str, encoding) if (s == str) return encoding;
1296 OperandEncoding RecognizableInstr::immediateEncodingFromString
1297   (const std::string &s,
1298    bool hasOpSizePrefix) {
1299   if(!hasOpSizePrefix) {
1300     // For instructions without an OpSize prefix, a declared 16-bit register or
1301     // immediate encoding is special.
1302     ENCODING("i16imm",        ENCODING_IW)
1303   }
1304   ENCODING("i32i8imm",        ENCODING_IB)
1305   ENCODING("u32u8imm",        ENCODING_IB)
1306   ENCODING("SSECC",           ENCODING_IB)
1307   ENCODING("AVXCC",           ENCODING_IB)
1308   ENCODING("AVX512RC",        ENCODING_IB)
1309   ENCODING("i16imm",          ENCODING_Iv)
1310   ENCODING("i16i8imm",        ENCODING_IB)
1311   ENCODING("i32imm",          ENCODING_Iv)
1312   ENCODING("i64i32imm",       ENCODING_ID)
1313   ENCODING("i64i8imm",        ENCODING_IB)
1314   ENCODING("i8imm",           ENCODING_IB)
1315   // This is not a typo.  Instructions like BLENDVPD put
1316   // register IDs in 8-bit immediates nowadays.
1317   ENCODING("FR32",            ENCODING_IB)
1318   ENCODING("FR64",            ENCODING_IB)
1319   ENCODING("VR128",           ENCODING_IB)
1320   ENCODING("VR256",           ENCODING_IB)
1321   ENCODING("FR32X",           ENCODING_IB)
1322   ENCODING("FR64X",           ENCODING_IB)
1323   ENCODING("VR128X",          ENCODING_IB)
1324   ENCODING("VR256X",          ENCODING_IB)
1325   ENCODING("VR512",           ENCODING_IB)
1326   errs() << "Unhandled immediate encoding " << s << "\n";
1327   llvm_unreachable("Unhandled immediate encoding");
1328 }
1329 
1330 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1331   (const std::string &s,
1332    bool hasOpSizePrefix) {
1333   ENCODING("RST",             ENCODING_FP)
1334   ENCODING("GR16",            ENCODING_RM)
1335   ENCODING("GR32",            ENCODING_RM)
1336   ENCODING("GR32orGR64",      ENCODING_RM)
1337   ENCODING("GR64",            ENCODING_RM)
1338   ENCODING("GR8",             ENCODING_RM)
1339   ENCODING("VR128",           ENCODING_RM)
1340   ENCODING("VR128X",          ENCODING_RM)
1341   ENCODING("FR64",            ENCODING_RM)
1342   ENCODING("FR32",            ENCODING_RM)
1343   ENCODING("FR64X",           ENCODING_RM)
1344   ENCODING("FR32X",           ENCODING_RM)
1345   ENCODING("VR64",            ENCODING_RM)
1346   ENCODING("VR256",           ENCODING_RM)
1347   ENCODING("VR256X",          ENCODING_RM)
1348   ENCODING("VR512",           ENCODING_RM)
1349   ENCODING("VK1",             ENCODING_RM)
1350   ENCODING("VK8",             ENCODING_RM)
1351   ENCODING("VK16",            ENCODING_RM)
1352   errs() << "Unhandled R/M register encoding " << s << "\n";
1353   llvm_unreachable("Unhandled R/M register encoding");
1354 }
1355 
1356 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1357   (const std::string &s,
1358    bool hasOpSizePrefix) {
1359   ENCODING("GR16",            ENCODING_REG)
1360   ENCODING("GR32",            ENCODING_REG)
1361   ENCODING("GR32orGR64",      ENCODING_REG)
1362   ENCODING("GR64",            ENCODING_REG)
1363   ENCODING("GR8",             ENCODING_REG)
1364   ENCODING("VR128",           ENCODING_REG)
1365   ENCODING("FR64",            ENCODING_REG)
1366   ENCODING("FR32",            ENCODING_REG)
1367   ENCODING("VR64",            ENCODING_REG)
1368   ENCODING("SEGMENT_REG",     ENCODING_REG)
1369   ENCODING("DEBUG_REG",       ENCODING_REG)
1370   ENCODING("CONTROL_REG",     ENCODING_REG)
1371   ENCODING("VR256",           ENCODING_REG)
1372   ENCODING("VR256X",          ENCODING_REG)
1373   ENCODING("VR128X",          ENCODING_REG)
1374   ENCODING("FR64X",           ENCODING_REG)
1375   ENCODING("FR32X",           ENCODING_REG)
1376   ENCODING("VR512",           ENCODING_REG)
1377   ENCODING("VK1",             ENCODING_REG)
1378   ENCODING("VK8",             ENCODING_REG)
1379   ENCODING("VK16",            ENCODING_REG)
1380   ENCODING("VK1WM",           ENCODING_REG)
1381   ENCODING("VK8WM",           ENCODING_REG)
1382   ENCODING("VK16WM",          ENCODING_REG)
1383   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1384   llvm_unreachable("Unhandled reg/opcode register encoding");
1385 }
1386 
1387 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1388   (const std::string &s,
1389    bool hasOpSizePrefix) {
1390   ENCODING("GR32",            ENCODING_VVVV)
1391   ENCODING("GR64",            ENCODING_VVVV)
1392   ENCODING("FR32",            ENCODING_VVVV)
1393   ENCODING("FR64",            ENCODING_VVVV)
1394   ENCODING("VR128",           ENCODING_VVVV)
1395   ENCODING("VR256",           ENCODING_VVVV)
1396   ENCODING("FR32X",           ENCODING_VVVV)
1397   ENCODING("FR64X",           ENCODING_VVVV)
1398   ENCODING("VR128X",          ENCODING_VVVV)
1399   ENCODING("VR256X",          ENCODING_VVVV)
1400   ENCODING("VR512",           ENCODING_VVVV)
1401   ENCODING("VK1",             ENCODING_VVVV)
1402   ENCODING("VK8",             ENCODING_VVVV)
1403   ENCODING("VK16",            ENCODING_VVVV)
1404   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1405   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1406 }
1407 
1408 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1409   (const std::string &s,
1410    bool hasOpSizePrefix) {
1411   ENCODING("VK1WM",           ENCODING_WRITEMASK)
1412   ENCODING("VK8WM",           ENCODING_WRITEMASK)
1413   ENCODING("VK16WM",          ENCODING_WRITEMASK)
1414   errs() << "Unhandled mask register encoding " << s << "\n";
1415   llvm_unreachable("Unhandled mask register encoding");
1416 }
1417 
1418 OperandEncoding RecognizableInstr::memoryEncodingFromString
1419   (const std::string &s,
1420    bool hasOpSizePrefix) {
1421   ENCODING("i16mem",          ENCODING_RM)
1422   ENCODING("i32mem",          ENCODING_RM)
1423   ENCODING("i64mem",          ENCODING_RM)
1424   ENCODING("i8mem",           ENCODING_RM)
1425   ENCODING("ssmem",           ENCODING_RM)
1426   ENCODING("sdmem",           ENCODING_RM)
1427   ENCODING("f128mem",         ENCODING_RM)
1428   ENCODING("f256mem",         ENCODING_RM)
1429   ENCODING("f512mem",         ENCODING_RM)
1430   ENCODING("f64mem",          ENCODING_RM)
1431   ENCODING("f32mem",          ENCODING_RM)
1432   ENCODING("i128mem",         ENCODING_RM)
1433   ENCODING("i256mem",         ENCODING_RM)
1434   ENCODING("i512mem",         ENCODING_RM)
1435   ENCODING("f80mem",          ENCODING_RM)
1436   ENCODING("lea32mem",        ENCODING_RM)
1437   ENCODING("lea64_32mem",     ENCODING_RM)
1438   ENCODING("lea64mem",        ENCODING_RM)
1439   ENCODING("opaque32mem",     ENCODING_RM)
1440   ENCODING("opaque48mem",     ENCODING_RM)
1441   ENCODING("opaque80mem",     ENCODING_RM)
1442   ENCODING("opaque512mem",    ENCODING_RM)
1443   ENCODING("vx32mem",         ENCODING_RM)
1444   ENCODING("vy32mem",         ENCODING_RM)
1445   ENCODING("vz32mem",         ENCODING_RM)
1446   ENCODING("vx64mem",         ENCODING_RM)
1447   ENCODING("vy64mem",         ENCODING_RM)
1448   ENCODING("vy64xmem",        ENCODING_RM)
1449   ENCODING("vz64mem",         ENCODING_RM)
1450   errs() << "Unhandled memory encoding " << s << "\n";
1451   llvm_unreachable("Unhandled memory encoding");
1452 }
1453 
1454 OperandEncoding RecognizableInstr::relocationEncodingFromString
1455   (const std::string &s,
1456    bool hasOpSizePrefix) {
1457   if(!hasOpSizePrefix) {
1458     // For instructions without an OpSize prefix, a declared 16-bit register or
1459     // immediate encoding is special.
1460     ENCODING("i16imm",        ENCODING_IW)
1461   }
1462   ENCODING("i16imm",          ENCODING_Iv)
1463   ENCODING("i16i8imm",        ENCODING_IB)
1464   ENCODING("i32imm",          ENCODING_Iv)
1465   ENCODING("i32i8imm",        ENCODING_IB)
1466   ENCODING("i64i32imm",       ENCODING_ID)
1467   ENCODING("i64i8imm",        ENCODING_IB)
1468   ENCODING("i8imm",           ENCODING_IB)
1469   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1470   ENCODING("i16imm_pcrel",    ENCODING_IW)
1471   ENCODING("i32imm_pcrel",    ENCODING_ID)
1472   ENCODING("brtarget",        ENCODING_Iv)
1473   ENCODING("brtarget8",       ENCODING_IB)
1474   ENCODING("i64imm",          ENCODING_IO)
1475   ENCODING("offset8",         ENCODING_Ia)
1476   ENCODING("offset16",        ENCODING_Ia)
1477   ENCODING("offset32",        ENCODING_Ia)
1478   ENCODING("offset64",        ENCODING_Ia)
1479   errs() << "Unhandled relocation encoding " << s << "\n";
1480   llvm_unreachable("Unhandled relocation encoding");
1481 }
1482 
1483 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1484   (const std::string &s,
1485    bool hasOpSizePrefix) {
1486   ENCODING("GR32",            ENCODING_Rv)
1487   ENCODING("GR64",            ENCODING_RO)
1488   ENCODING("GR16",            ENCODING_Rv)
1489   ENCODING("GR8",             ENCODING_RB)
1490   ENCODING("GR16_NOAX",       ENCODING_Rv)
1491   ENCODING("GR32_NOAX",       ENCODING_Rv)
1492   ENCODING("GR64_NOAX",       ENCODING_RO)
1493   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1494   llvm_unreachable("Unhandled opcode modifier encoding");
1495 }
1496 #undef ENCODING
1497