1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 25 #define MRM_MAPPING \ 26 MAP(C0, 32) \ 27 MAP(C1, 33) \ 28 MAP(C2, 34) \ 29 MAP(C3, 35) \ 30 MAP(C4, 36) \ 31 MAP(C8, 37) \ 32 MAP(C9, 38) \ 33 MAP(CA, 39) \ 34 MAP(CB, 40) \ 35 MAP(CF, 41) \ 36 MAP(D0, 42) \ 37 MAP(D1, 43) \ 38 MAP(D4, 44) \ 39 MAP(D5, 45) \ 40 MAP(D6, 46) \ 41 MAP(D7, 47) \ 42 MAP(D8, 48) \ 43 MAP(D9, 49) \ 44 MAP(DA, 50) \ 45 MAP(DB, 51) \ 46 MAP(DC, 52) \ 47 MAP(DD, 53) \ 48 MAP(DE, 54) \ 49 MAP(DF, 55) \ 50 MAP(E0, 56) \ 51 MAP(E1, 57) \ 52 MAP(E2, 58) \ 53 MAP(E3, 59) \ 54 MAP(E4, 60) \ 55 MAP(E5, 61) \ 56 MAP(E8, 62) \ 57 MAP(E9, 63) \ 58 MAP(EA, 64) \ 59 MAP(EB, 65) \ 60 MAP(EC, 66) \ 61 MAP(ED, 67) \ 62 MAP(EE, 68) \ 63 MAP(F0, 69) \ 64 MAP(F1, 70) \ 65 MAP(F2, 71) \ 66 MAP(F3, 72) \ 67 MAP(F4, 73) \ 68 MAP(F5, 74) \ 69 MAP(F6, 75) \ 70 MAP(F7, 76) \ 71 MAP(F8, 77) \ 72 MAP(F9, 78) \ 73 MAP(FA, 79) \ 74 MAP(FB, 80) \ 75 MAP(FC, 81) \ 76 MAP(FD, 82) \ 77 MAP(FE, 83) \ 78 MAP(FF, 84) 79 80 // A clone of X86 since we can't depend on something that is generated. 81 namespace X86Local { 82 enum { 83 Pseudo = 0, 84 RawFrm = 1, 85 AddRegFrm = 2, 86 MRMDestReg = 3, 87 MRMDestMem = 4, 88 MRMSrcReg = 5, 89 MRMSrcMem = 6, 90 RawFrmMemOffs = 7, 91 RawFrmSrc = 8, 92 RawFrmDst = 9, 93 RawFrmDstSrc = 10, 94 RawFrmImm8 = 11, 95 RawFrmImm16 = 12, 96 MRMXr = 14, MRMXm = 15, 97 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, 98 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, 99 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, 100 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, 101 #define MAP(from, to) MRM_##from = to, 102 MRM_MAPPING 103 #undef MAP 104 lastMRM 105 }; 106 107 enum { 108 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 109 }; 110 111 enum { 112 PS = 1, PD = 2, XS = 3, XD = 4 113 }; 114 115 enum { 116 VEX = 1, XOP = 2, EVEX = 3 117 }; 118 119 enum { 120 OpSize16 = 1, OpSize32 = 2 121 }; 122 } 123 124 using namespace X86Disassembler; 125 126 /// isRegFormat - Indicates whether a particular form requires the Mod field of 127 /// the ModR/M byte to be 0b11. 128 /// 129 /// @param form - The form of the instruction. 130 /// @return - true if the form implies that Mod must be 0b11, false 131 /// otherwise. 132 static bool isRegFormat(uint8_t form) { 133 return (form == X86Local::MRMDestReg || 134 form == X86Local::MRMSrcReg || 135 form == X86Local::MRMXr || 136 (form >= X86Local::MRM0r && form <= X86Local::MRM7r)); 137 } 138 139 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 140 /// Useful for switch statements and the like. 141 /// 142 /// @param init - A reference to the BitsInit to be decoded. 143 /// @return - The field, with the first bit in the BitsInit as the lowest 144 /// order bit. 145 static uint8_t byteFromBitsInit(BitsInit &init) { 146 int width = init.getNumBits(); 147 148 assert(width <= 8 && "Field is too large for uint8_t!"); 149 150 int index; 151 uint8_t mask = 0x01; 152 153 uint8_t ret = 0; 154 155 for (index = 0; index < width; index++) { 156 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 157 ret |= mask; 158 159 mask <<= 1; 160 } 161 162 return ret; 163 } 164 165 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 166 /// name of the field. 167 /// 168 /// @param rec - The record from which to extract the value. 169 /// @param name - The name of the field in the record. 170 /// @return - The field, as translated by byteFromBitsInit(). 171 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 172 BitsInit* bits = rec->getValueAsBitsInit(name); 173 return byteFromBitsInit(*bits); 174 } 175 176 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 177 const CodeGenInstruction &insn, 178 InstrUID uid) { 179 UID = uid; 180 181 Rec = insn.TheDef; 182 Name = Rec->getName(); 183 Spec = &tables.specForUID(UID); 184 185 if (!Rec->isSubClassOf("X86Inst")) { 186 ShouldBeEmitted = false; 187 return; 188 } 189 190 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 191 OpMap = byteFromRec(Rec, "OpMapBits"); 192 Opcode = byteFromRec(Rec, "Opcode"); 193 Form = byteFromRec(Rec, "FormBits"); 194 Encoding = byteFromRec(Rec, "OpEncBits"); 195 196 OpSize = byteFromRec(Rec, "OpSizeBits"); 197 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); 198 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 199 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 200 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3"); 201 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); 202 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); 203 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 204 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 205 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 206 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 207 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 208 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 209 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 210 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 211 212 Name = Rec->getName(); 213 AsmString = Rec->getValueAsString("AsmString"); 214 215 Operands = &insn.Operands.OperandList; 216 217 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 218 219 // Check for 64-bit inst which does not require REX 220 Is32Bit = false; 221 Is64Bit = false; 222 // FIXME: Is there some better way to check for In64BitMode? 223 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 224 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 225 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 226 Predicates[i]->getName().find("In32Bit") != Name.npos) { 227 Is32Bit = true; 228 break; 229 } 230 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 231 Is64Bit = true; 232 break; 233 } 234 } 235 236 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 237 ShouldBeEmitted = false; 238 return; 239 } 240 241 // Special case since there is no attribute class for 64-bit and VEX 242 if (Name == "VMASKMOVDQU64") { 243 ShouldBeEmitted = false; 244 return; 245 } 246 247 ShouldBeEmitted = true; 248 } 249 250 void RecognizableInstr::processInstr(DisassemblerTables &tables, 251 const CodeGenInstruction &insn, 252 InstrUID uid) 253 { 254 // Ignore "asm parser only" instructions. 255 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 256 return; 257 258 RecognizableInstr recogInstr(tables, insn, uid); 259 260 if (recogInstr.shouldBeEmitted()) { 261 recogInstr.emitInstructionSpecifier(); 262 recogInstr.emitDecodePath(tables); 263 } 264 } 265 266 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 267 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 268 (HasEVEX_KZ ? n##_KZ : \ 269 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 270 271 InstructionContext RecognizableInstr::insnContext() const { 272 InstructionContext insnContext; 273 274 if (Encoding == X86Local::EVEX) { 275 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 276 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 277 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 278 } 279 // VEX_L & VEX_W 280 if (HasVEX_LPrefix && HasVEX_WPrefix) { 281 if (OpPrefix == X86Local::PD) 282 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 283 else if (OpPrefix == X86Local::XS) 284 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 285 else if (OpPrefix == X86Local::XD) 286 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 287 else if (OpPrefix == X86Local::PS) 288 insnContext = EVEX_KB(IC_EVEX_L_W); 289 else { 290 errs() << "Instruction does not use a prefix: " << Name << "\n"; 291 llvm_unreachable("Invalid prefix"); 292 } 293 } else if (HasVEX_LPrefix) { 294 // VEX_L 295 if (OpPrefix == X86Local::PD) 296 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 297 else if (OpPrefix == X86Local::XS) 298 insnContext = EVEX_KB(IC_EVEX_L_XS); 299 else if (OpPrefix == X86Local::XD) 300 insnContext = EVEX_KB(IC_EVEX_L_XD); 301 else if (OpPrefix == X86Local::PS) 302 insnContext = EVEX_KB(IC_EVEX_L); 303 else { 304 errs() << "Instruction does not use a prefix: " << Name << "\n"; 305 llvm_unreachable("Invalid prefix"); 306 } 307 } 308 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { 309 // EVEX_L2 & VEX_W 310 if (OpPrefix == X86Local::PD) 311 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 312 else if (OpPrefix == X86Local::XS) 313 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 314 else if (OpPrefix == X86Local::XD) 315 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 316 else if (OpPrefix == X86Local::PS) 317 insnContext = EVEX_KB(IC_EVEX_L2_W); 318 else { 319 errs() << "Instruction does not use a prefix: " << Name << "\n"; 320 llvm_unreachable("Invalid prefix"); 321 } 322 } else if (HasEVEX_L2Prefix) { 323 // EVEX_L2 324 if (OpPrefix == X86Local::PD) 325 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 326 else if (OpPrefix == X86Local::XD) 327 insnContext = EVEX_KB(IC_EVEX_L2_XD); 328 else if (OpPrefix == X86Local::XS) 329 insnContext = EVEX_KB(IC_EVEX_L2_XS); 330 else if (OpPrefix == X86Local::PS) 331 insnContext = EVEX_KB(IC_EVEX_L2); 332 else { 333 errs() << "Instruction does not use a prefix: " << Name << "\n"; 334 llvm_unreachable("Invalid prefix"); 335 } 336 } 337 else if (HasVEX_WPrefix) { 338 // VEX_W 339 if (OpPrefix == X86Local::PD) 340 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 341 else if (OpPrefix == X86Local::XS) 342 insnContext = EVEX_KB(IC_EVEX_W_XS); 343 else if (OpPrefix == X86Local::XD) 344 insnContext = EVEX_KB(IC_EVEX_W_XD); 345 else if (OpPrefix == X86Local::PS) 346 insnContext = EVEX_KB(IC_EVEX_W); 347 else { 348 errs() << "Instruction does not use a prefix: " << Name << "\n"; 349 llvm_unreachable("Invalid prefix"); 350 } 351 } 352 // No L, no W 353 else if (OpPrefix == X86Local::PD) 354 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 355 else if (OpPrefix == X86Local::XD) 356 insnContext = EVEX_KB(IC_EVEX_XD); 357 else if (OpPrefix == X86Local::XS) 358 insnContext = EVEX_KB(IC_EVEX_XS); 359 else 360 insnContext = EVEX_KB(IC_EVEX); 361 /// eof EVEX 362 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 363 if (HasVEX_LPrefix && HasVEX_WPrefix) { 364 if (OpPrefix == X86Local::PD) 365 insnContext = IC_VEX_L_W_OPSIZE; 366 else if (OpPrefix == X86Local::XS) 367 insnContext = IC_VEX_L_W_XS; 368 else if (OpPrefix == X86Local::XD) 369 insnContext = IC_VEX_L_W_XD; 370 else if (OpPrefix == X86Local::PS) 371 insnContext = IC_VEX_L_W; 372 else { 373 errs() << "Instruction does not use a prefix: " << Name << "\n"; 374 llvm_unreachable("Invalid prefix"); 375 } 376 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 377 insnContext = IC_VEX_L_OPSIZE; 378 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix) 379 insnContext = IC_VEX_W_OPSIZE; 380 else if (OpPrefix == X86Local::PD) 381 insnContext = IC_VEX_OPSIZE; 382 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 383 insnContext = IC_VEX_L_XS; 384 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 385 insnContext = IC_VEX_L_XD; 386 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS) 387 insnContext = IC_VEX_W_XS; 388 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD) 389 insnContext = IC_VEX_W_XD; 390 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS) 391 insnContext = IC_VEX_W; 392 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 393 insnContext = IC_VEX_L; 394 else if (OpPrefix == X86Local::XD) 395 insnContext = IC_VEX_XD; 396 else if (OpPrefix == X86Local::XS) 397 insnContext = IC_VEX_XS; 398 else if (OpPrefix == X86Local::PS) 399 insnContext = IC_VEX; 400 else { 401 errs() << "Instruction does not use a prefix: " << Name << "\n"; 402 llvm_unreachable("Invalid prefix"); 403 } 404 } else if (Is64Bit || HasREX_WPrefix) { 405 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 406 insnContext = IC_64BIT_REXW_OPSIZE; 407 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 408 insnContext = IC_64BIT_XD_OPSIZE; 409 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 410 insnContext = IC_64BIT_XS_OPSIZE; 411 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 412 insnContext = IC_64BIT_OPSIZE; 413 else if (HasAdSizePrefix) 414 insnContext = IC_64BIT_ADSIZE; 415 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 416 insnContext = IC_64BIT_REXW_XS; 417 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 418 insnContext = IC_64BIT_REXW_XD; 419 else if (OpPrefix == X86Local::XD) 420 insnContext = IC_64BIT_XD; 421 else if (OpPrefix == X86Local::XS) 422 insnContext = IC_64BIT_XS; 423 else if (HasREX_WPrefix) 424 insnContext = IC_64BIT_REXW; 425 else 426 insnContext = IC_64BIT; 427 } else { 428 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 429 insnContext = IC_XD_OPSIZE; 430 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 431 insnContext = IC_XS_OPSIZE; 432 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 433 insnContext = IC_OPSIZE; 434 else if (HasAdSizePrefix) 435 insnContext = IC_ADSIZE; 436 else if (OpPrefix == X86Local::XD) 437 insnContext = IC_XD; 438 else if (OpPrefix == X86Local::XS) 439 insnContext = IC_XS; 440 else 441 insnContext = IC; 442 } 443 444 return insnContext; 445 } 446 447 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 448 // The scaling factor for AVX512 compressed displacement encoding is an 449 // instruction attribute. Adjust the ModRM encoding type to include the 450 // scale for compressed displacement. 451 if (encoding != ENCODING_RM || CD8_Scale == 0) 452 return; 453 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 454 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling"); 455 } 456 457 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 458 unsigned &physicalOperandIndex, 459 unsigned &numPhysicalOperands, 460 const unsigned *operandMapping, 461 OperandEncoding (*encodingFromString) 462 (const std::string&, 463 uint8_t OpSize)) { 464 if (optional) { 465 if (physicalOperandIndex >= numPhysicalOperands) 466 return; 467 } else { 468 assert(physicalOperandIndex < numPhysicalOperands); 469 } 470 471 while (operandMapping[operandIndex] != operandIndex) { 472 Spec->operands[operandIndex].encoding = ENCODING_DUP; 473 Spec->operands[operandIndex].type = 474 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 475 ++operandIndex; 476 } 477 478 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 479 480 OperandEncoding encoding = encodingFromString(typeName, OpSize); 481 // Adjust the encoding type for an operand based on the instruction. 482 adjustOperandEncoding(encoding); 483 Spec->operands[operandIndex].encoding = encoding; 484 Spec->operands[operandIndex].type = typeFromString(typeName, 485 HasREX_WPrefix, OpSize); 486 487 ++operandIndex; 488 ++physicalOperandIndex; 489 } 490 491 void RecognizableInstr::emitInstructionSpecifier() { 492 Spec->name = Name; 493 494 Spec->insnContext = insnContext(); 495 496 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 497 498 unsigned numOperands = OperandList.size(); 499 unsigned numPhysicalOperands = 0; 500 501 // operandMapping maps from operands in OperandList to their originals. 502 // If operandMapping[i] != i, then the entry is a duplicate. 503 unsigned operandMapping[X86_MAX_OPERANDS]; 504 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 505 506 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 507 if (OperandList[operandIndex].Constraints.size()) { 508 const CGIOperandList::ConstraintInfo &Constraint = 509 OperandList[operandIndex].Constraints[0]; 510 if (Constraint.isTied()) { 511 operandMapping[operandIndex] = operandIndex; 512 operandMapping[Constraint.getTiedOperand()] = operandIndex; 513 } else { 514 ++numPhysicalOperands; 515 operandMapping[operandIndex] = operandIndex; 516 } 517 } else { 518 ++numPhysicalOperands; 519 operandMapping[operandIndex] = operandIndex; 520 } 521 } 522 523 #define HANDLE_OPERAND(class) \ 524 handleOperand(false, \ 525 operandIndex, \ 526 physicalOperandIndex, \ 527 numPhysicalOperands, \ 528 operandMapping, \ 529 class##EncodingFromString); 530 531 #define HANDLE_OPTIONAL(class) \ 532 handleOperand(true, \ 533 operandIndex, \ 534 physicalOperandIndex, \ 535 numPhysicalOperands, \ 536 operandMapping, \ 537 class##EncodingFromString); 538 539 // operandIndex should always be < numOperands 540 unsigned operandIndex = 0; 541 // physicalOperandIndex should always be < numPhysicalOperands 542 unsigned physicalOperandIndex = 0; 543 544 switch (Form) { 545 default: llvm_unreachable("Unhandled form"); 546 case X86Local::RawFrmSrc: 547 HANDLE_OPERAND(relocation); 548 return; 549 case X86Local::RawFrmDst: 550 HANDLE_OPERAND(relocation); 551 return; 552 case X86Local::RawFrmDstSrc: 553 HANDLE_OPERAND(relocation); 554 HANDLE_OPERAND(relocation); 555 return; 556 case X86Local::RawFrm: 557 // Operand 1 (optional) is an address or immediate. 558 // Operand 2 (optional) is an immediate. 559 assert(numPhysicalOperands <= 2 && 560 "Unexpected number of operands for RawFrm"); 561 HANDLE_OPTIONAL(relocation) 562 HANDLE_OPTIONAL(immediate) 563 break; 564 case X86Local::RawFrmMemOffs: 565 // Operand 1 is an address. 566 HANDLE_OPERAND(relocation); 567 break; 568 case X86Local::AddRegFrm: 569 // Operand 1 is added to the opcode. 570 // Operand 2 (optional) is an address. 571 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 572 "Unexpected number of operands for AddRegFrm"); 573 HANDLE_OPERAND(opcodeModifier) 574 HANDLE_OPTIONAL(relocation) 575 break; 576 case X86Local::MRMDestReg: 577 // Operand 1 is a register operand in the R/M field. 578 // Operand 2 is a register operand in the Reg/Opcode field. 579 // - In AVX, there is a register operand in the VEX.vvvv field here - 580 // Operand 3 (optional) is an immediate. 581 if (HasVEX_4V) 582 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 583 "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); 584 else 585 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 586 "Unexpected number of operands for MRMDestRegFrm"); 587 588 HANDLE_OPERAND(rmRegister) 589 590 if (HasVEX_4V) 591 // FIXME: In AVX, the register below becomes the one encoded 592 // in ModRMVEX and the one above the one in the VEX.VVVV field 593 HANDLE_OPERAND(vvvvRegister) 594 595 HANDLE_OPERAND(roRegister) 596 HANDLE_OPTIONAL(immediate) 597 break; 598 case X86Local::MRMDestMem: 599 // Operand 1 is a memory operand (possibly SIB-extended) 600 // Operand 2 is a register operand in the Reg/Opcode field. 601 // - In AVX, there is a register operand in the VEX.vvvv field here - 602 // Operand 3 (optional) is an immediate. 603 if (HasVEX_4V) 604 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && 605 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 606 else 607 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 608 "Unexpected number of operands for MRMDestMemFrm"); 609 HANDLE_OPERAND(memory) 610 611 if (HasEVEX_K) 612 HANDLE_OPERAND(writemaskRegister) 613 614 if (HasVEX_4V) 615 // FIXME: In AVX, the register below becomes the one encoded 616 // in ModRMVEX and the one above the one in the VEX.VVVV field 617 HANDLE_OPERAND(vvvvRegister) 618 619 HANDLE_OPERAND(roRegister) 620 HANDLE_OPTIONAL(immediate) 621 break; 622 case X86Local::MRMSrcReg: 623 // Operand 1 is a register operand in the Reg/Opcode field. 624 // Operand 2 is a register operand in the R/M field. 625 // - In AVX, there is a register operand in the VEX.vvvv field here - 626 // Operand 3 (optional) is an immediate. 627 // Operand 4 (optional) is an immediate. 628 629 if (HasVEX_4V || HasVEX_4VOp3) 630 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 631 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); 632 else 633 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 && 634 "Unexpected number of operands for MRMSrcRegFrm"); 635 636 HANDLE_OPERAND(roRegister) 637 638 if (HasEVEX_K) 639 HANDLE_OPERAND(writemaskRegister) 640 641 if (HasVEX_4V) 642 // FIXME: In AVX, the register below becomes the one encoded 643 // in ModRMVEX and the one above the one in the VEX.VVVV field 644 HANDLE_OPERAND(vvvvRegister) 645 646 if (HasMemOp4Prefix) 647 HANDLE_OPERAND(immediate) 648 649 HANDLE_OPERAND(rmRegister) 650 651 if (HasVEX_4VOp3) 652 HANDLE_OPERAND(vvvvRegister) 653 654 if (!HasMemOp4Prefix) 655 HANDLE_OPTIONAL(immediate) 656 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 657 HANDLE_OPTIONAL(immediate) 658 break; 659 case X86Local::MRMSrcMem: 660 // Operand 1 is a register operand in the Reg/Opcode field. 661 // Operand 2 is a memory operand (possibly SIB-extended) 662 // - In AVX, there is a register operand in the VEX.vvvv field here - 663 // Operand 3 (optional) is an immediate. 664 665 if (HasVEX_4V || HasVEX_4VOp3) 666 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && 667 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); 668 else 669 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && 670 "Unexpected number of operands for MRMSrcMemFrm"); 671 672 HANDLE_OPERAND(roRegister) 673 674 if (HasEVEX_K) 675 HANDLE_OPERAND(writemaskRegister) 676 677 if (HasVEX_4V) 678 // FIXME: In AVX, the register below becomes the one encoded 679 // in ModRMVEX and the one above the one in the VEX.VVVV field 680 HANDLE_OPERAND(vvvvRegister) 681 682 if (HasMemOp4Prefix) 683 HANDLE_OPERAND(immediate) 684 685 HANDLE_OPERAND(memory) 686 687 if (HasVEX_4VOp3) 688 HANDLE_OPERAND(vvvvRegister) 689 690 if (!HasMemOp4Prefix) 691 HANDLE_OPTIONAL(immediate) 692 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 693 break; 694 case X86Local::MRMXr: 695 case X86Local::MRM0r: 696 case X86Local::MRM1r: 697 case X86Local::MRM2r: 698 case X86Local::MRM3r: 699 case X86Local::MRM4r: 700 case X86Local::MRM5r: 701 case X86Local::MRM6r: 702 case X86Local::MRM7r: 703 { 704 // Operand 1 is a register operand in the R/M field. 705 // Operand 2 (optional) is an immediate or relocation. 706 // Operand 3 (optional) is an immediate. 707 unsigned kOp = (HasEVEX_K) ? 1:0; 708 unsigned Op4v = (HasVEX_4V) ? 1:0; 709 if (numPhysicalOperands > 3 + kOp + Op4v) 710 llvm_unreachable("Unexpected number of operands for MRMnr"); 711 } 712 if (HasVEX_4V) 713 HANDLE_OPERAND(vvvvRegister) 714 715 if (HasEVEX_K) 716 HANDLE_OPERAND(writemaskRegister) 717 HANDLE_OPTIONAL(rmRegister) 718 HANDLE_OPTIONAL(relocation) 719 HANDLE_OPTIONAL(immediate) 720 break; 721 case X86Local::MRMXm: 722 case X86Local::MRM0m: 723 case X86Local::MRM1m: 724 case X86Local::MRM2m: 725 case X86Local::MRM3m: 726 case X86Local::MRM4m: 727 case X86Local::MRM5m: 728 case X86Local::MRM6m: 729 case X86Local::MRM7m: 730 { 731 // Operand 1 is a memory operand (possibly SIB-extended) 732 // Operand 2 (optional) is an immediate or relocation. 733 unsigned kOp = (HasEVEX_K) ? 1:0; 734 unsigned Op4v = (HasVEX_4V) ? 1:0; 735 if (numPhysicalOperands < 1 + kOp + Op4v || 736 numPhysicalOperands > 2 + kOp + Op4v) 737 llvm_unreachable("Unexpected number of operands for MRMnm"); 738 } 739 if (HasVEX_4V) 740 HANDLE_OPERAND(vvvvRegister) 741 if (HasEVEX_K) 742 HANDLE_OPERAND(writemaskRegister) 743 HANDLE_OPERAND(memory) 744 HANDLE_OPTIONAL(relocation) 745 break; 746 case X86Local::RawFrmImm8: 747 // operand 1 is a 16-bit immediate 748 // operand 2 is an 8-bit immediate 749 assert(numPhysicalOperands == 2 && 750 "Unexpected number of operands for X86Local::RawFrmImm8"); 751 HANDLE_OPERAND(immediate) 752 HANDLE_OPERAND(immediate) 753 break; 754 case X86Local::RawFrmImm16: 755 // operand 1 is a 16-bit immediate 756 // operand 2 is a 16-bit immediate 757 HANDLE_OPERAND(immediate) 758 HANDLE_OPERAND(immediate) 759 break; 760 case X86Local::MRM_F8: 761 if (Opcode == 0xc6) { 762 assert(numPhysicalOperands == 1 && 763 "Unexpected number of operands for X86Local::MRM_F8"); 764 HANDLE_OPERAND(immediate) 765 } else if (Opcode == 0xc7) { 766 assert(numPhysicalOperands == 1 && 767 "Unexpected number of operands for X86Local::MRM_F8"); 768 HANDLE_OPERAND(relocation) 769 } 770 break; 771 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 772 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 773 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 774 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1: 775 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6: 776 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9: 777 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC: 778 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF: 779 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2: 780 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5: 781 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA: 782 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED: 783 case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1: 784 case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4: 785 case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7: 786 case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB: 787 case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE: 788 case X86Local::MRM_FF: 789 // Ignored. 790 break; 791 } 792 793 #undef HANDLE_OPERAND 794 #undef HANDLE_OPTIONAL 795 } 796 797 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 798 // Special cases where the LLVM tables are not complete 799 800 #define MAP(from, to) \ 801 case X86Local::MRM_##from: \ 802 filter = new ExactFilter(0x##from); \ 803 break; 804 805 OpcodeType opcodeType = (OpcodeType)-1; 806 807 ModRMFilter* filter = nullptr; 808 uint8_t opcodeToSet = 0; 809 810 switch (OpMap) { 811 default: llvm_unreachable("Invalid map!"); 812 case X86Local::OB: 813 case X86Local::TB: 814 case X86Local::T8: 815 case X86Local::TA: 816 case X86Local::XOP8: 817 case X86Local::XOP9: 818 case X86Local::XOPA: 819 switch (OpMap) { 820 default: llvm_unreachable("Unexpected map!"); 821 case X86Local::OB: opcodeType = ONEBYTE; break; 822 case X86Local::TB: opcodeType = TWOBYTE; break; 823 case X86Local::T8: opcodeType = THREEBYTE_38; break; 824 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 825 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 826 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 827 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 828 } 829 830 switch (Form) { 831 default: 832 filter = new DumbFilter(); 833 break; 834 case X86Local::MRMDestReg: case X86Local::MRMDestMem: 835 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem: 836 case X86Local::MRMXr: case X86Local::MRMXm: 837 filter = new ModFilter(isRegFormat(Form)); 838 break; 839 case X86Local::MRM0r: case X86Local::MRM1r: 840 case X86Local::MRM2r: case X86Local::MRM3r: 841 case X86Local::MRM4r: case X86Local::MRM5r: 842 case X86Local::MRM6r: case X86Local::MRM7r: 843 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 844 break; 845 case X86Local::MRM0m: case X86Local::MRM1m: 846 case X86Local::MRM2m: case X86Local::MRM3m: 847 case X86Local::MRM4m: case X86Local::MRM5m: 848 case X86Local::MRM6m: case X86Local::MRM7m: 849 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 850 break; 851 MRM_MAPPING 852 } // switch (Form) 853 854 opcodeToSet = Opcode; 855 break; 856 } // switch (OpMap) 857 858 assert(opcodeType != (OpcodeType)-1 && 859 "Opcode type not set"); 860 assert(filter && "Filter not set"); 861 862 if (Form == X86Local::AddRegFrm) { 863 assert(((opcodeToSet & 7) == 0) && 864 "ADDREG_FRM opcode not aligned"); 865 866 uint8_t currentOpcode; 867 868 for (currentOpcode = opcodeToSet; 869 currentOpcode < opcodeToSet + 8; 870 ++currentOpcode) 871 tables.setTableFields(opcodeType, 872 insnContext(), 873 currentOpcode, 874 *filter, 875 UID, Is32Bit, IgnoresVEX_L); 876 } else { 877 tables.setTableFields(opcodeType, 878 insnContext(), 879 opcodeToSet, 880 *filter, 881 UID, Is32Bit, IgnoresVEX_L); 882 } 883 884 delete filter; 885 886 #undef MAP 887 } 888 889 #define TYPE(str, type) if (s == str) return type; 890 OperandType RecognizableInstr::typeFromString(const std::string &s, 891 bool hasREX_WPrefix, 892 uint8_t OpSize) { 893 if(hasREX_WPrefix) { 894 // For instructions with a REX_W prefix, a declared 32-bit register encoding 895 // is special. 896 TYPE("GR32", TYPE_R32) 897 } 898 if(OpSize == X86Local::OpSize16) { 899 // For OpSize16 instructions, a declared 16-bit register or 900 // immediate encoding is special. 901 TYPE("GR16", TYPE_Rv) 902 TYPE("i16imm", TYPE_IMMv) 903 } else if(OpSize == X86Local::OpSize32) { 904 // For OpSize32 instructions, a declared 32-bit register or 905 // immediate encoding is special. 906 TYPE("GR32", TYPE_Rv) 907 } 908 TYPE("i16mem", TYPE_Mv) 909 TYPE("i16imm", TYPE_IMM16) 910 TYPE("i16i8imm", TYPE_IMMv) 911 TYPE("GR16", TYPE_R16) 912 TYPE("i32mem", TYPE_Mv) 913 TYPE("i32imm", TYPE_IMMv) 914 TYPE("i32i8imm", TYPE_IMM32) 915 TYPE("u32u8imm", TYPE_IMM32) 916 TYPE("GR32", TYPE_R32) 917 TYPE("GR32orGR64", TYPE_R32) 918 TYPE("i64mem", TYPE_Mv) 919 TYPE("i64i32imm", TYPE_IMM64) 920 TYPE("i64i8imm", TYPE_IMM64) 921 TYPE("GR64", TYPE_R64) 922 TYPE("i8mem", TYPE_M8) 923 TYPE("i8imm", TYPE_IMM8) 924 TYPE("GR8", TYPE_R8) 925 TYPE("VR128", TYPE_XMM128) 926 TYPE("VR128X", TYPE_XMM128) 927 TYPE("f128mem", TYPE_M128) 928 TYPE("f256mem", TYPE_M256) 929 TYPE("f512mem", TYPE_M512) 930 TYPE("FR64", TYPE_XMM64) 931 TYPE("FR64X", TYPE_XMM64) 932 TYPE("f64mem", TYPE_M64FP) 933 TYPE("sdmem", TYPE_M64FP) 934 TYPE("FR32", TYPE_XMM32) 935 TYPE("FR32X", TYPE_XMM32) 936 TYPE("f32mem", TYPE_M32FP) 937 TYPE("ssmem", TYPE_M32FP) 938 TYPE("RST", TYPE_ST) 939 TYPE("i128mem", TYPE_M128) 940 TYPE("i256mem", TYPE_M256) 941 TYPE("i512mem", TYPE_M512) 942 TYPE("i64i32imm_pcrel", TYPE_REL64) 943 TYPE("i16imm_pcrel", TYPE_REL16) 944 TYPE("i32imm_pcrel", TYPE_REL32) 945 TYPE("SSECC", TYPE_IMM3) 946 TYPE("AVXCC", TYPE_IMM5) 947 TYPE("AVX512RC", TYPE_IMM32) 948 TYPE("brtarget", TYPE_RELv) 949 TYPE("uncondbrtarget", TYPE_RELv) 950 TYPE("brtarget8", TYPE_REL8) 951 TYPE("f80mem", TYPE_M80FP) 952 TYPE("lea32mem", TYPE_LEA) 953 TYPE("lea64_32mem", TYPE_LEA) 954 TYPE("lea64mem", TYPE_LEA) 955 TYPE("VR64", TYPE_MM64) 956 TYPE("i64imm", TYPE_IMMv) 957 TYPE("opaque32mem", TYPE_M1616) 958 TYPE("opaque48mem", TYPE_M1632) 959 TYPE("opaque80mem", TYPE_M1664) 960 TYPE("opaque512mem", TYPE_M512) 961 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 962 TYPE("DEBUG_REG", TYPE_DEBUGREG) 963 TYPE("CONTROL_REG", TYPE_CONTROLREG) 964 TYPE("srcidx8", TYPE_SRCIDX8) 965 TYPE("srcidx16", TYPE_SRCIDX16) 966 TYPE("srcidx32", TYPE_SRCIDX32) 967 TYPE("srcidx64", TYPE_SRCIDX64) 968 TYPE("dstidx8", TYPE_DSTIDX8) 969 TYPE("dstidx16", TYPE_DSTIDX16) 970 TYPE("dstidx32", TYPE_DSTIDX32) 971 TYPE("dstidx64", TYPE_DSTIDX64) 972 TYPE("offset8", TYPE_MOFFS8) 973 TYPE("offset16", TYPE_MOFFS16) 974 TYPE("offset32", TYPE_MOFFS32) 975 TYPE("offset64", TYPE_MOFFS64) 976 TYPE("VR256", TYPE_XMM256) 977 TYPE("VR256X", TYPE_XMM256) 978 TYPE("VR512", TYPE_XMM512) 979 TYPE("VK1", TYPE_VK1) 980 TYPE("VK1WM", TYPE_VK1) 981 TYPE("VK2", TYPE_VK2) 982 TYPE("VK2WM", TYPE_VK2) 983 TYPE("VK4", TYPE_VK4) 984 TYPE("VK4WM", TYPE_VK4) 985 TYPE("VK8", TYPE_VK8) 986 TYPE("VK8WM", TYPE_VK8) 987 TYPE("VK16", TYPE_VK16) 988 TYPE("VK16WM", TYPE_VK16) 989 TYPE("VK32", TYPE_VK32) 990 TYPE("VK32WM", TYPE_VK32) 991 TYPE("VK64", TYPE_VK64) 992 TYPE("VK64WM", TYPE_VK64) 993 TYPE("GR16_NOAX", TYPE_Rv) 994 TYPE("GR32_NOAX", TYPE_Rv) 995 TYPE("GR64_NOAX", TYPE_R64) 996 TYPE("vx32mem", TYPE_M32) 997 TYPE("vy32mem", TYPE_M32) 998 TYPE("vz32mem", TYPE_M32) 999 TYPE("vx64mem", TYPE_M64) 1000 TYPE("vy64mem", TYPE_M64) 1001 TYPE("vy64xmem", TYPE_M64) 1002 TYPE("vz64mem", TYPE_M64) 1003 errs() << "Unhandled type string " << s << "\n"; 1004 llvm_unreachable("Unhandled type string"); 1005 } 1006 #undef TYPE 1007 1008 #define ENCODING(str, encoding) if (s == str) return encoding; 1009 OperandEncoding 1010 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1011 uint8_t OpSize) { 1012 if(OpSize != X86Local::OpSize16) { 1013 // For instructions without an OpSize prefix, a declared 16-bit register or 1014 // immediate encoding is special. 1015 ENCODING("i16imm", ENCODING_IW) 1016 } 1017 ENCODING("i32i8imm", ENCODING_IB) 1018 ENCODING("u32u8imm", ENCODING_IB) 1019 ENCODING("SSECC", ENCODING_IB) 1020 ENCODING("AVXCC", ENCODING_IB) 1021 ENCODING("AVX512RC", ENCODING_IB) 1022 ENCODING("i16imm", ENCODING_Iv) 1023 ENCODING("i16i8imm", ENCODING_IB) 1024 ENCODING("i32imm", ENCODING_Iv) 1025 ENCODING("i64i32imm", ENCODING_ID) 1026 ENCODING("i64i8imm", ENCODING_IB) 1027 ENCODING("i8imm", ENCODING_IB) 1028 // This is not a typo. Instructions like BLENDVPD put 1029 // register IDs in 8-bit immediates nowadays. 1030 ENCODING("FR32", ENCODING_IB) 1031 ENCODING("FR64", ENCODING_IB) 1032 ENCODING("VR128", ENCODING_IB) 1033 ENCODING("VR256", ENCODING_IB) 1034 ENCODING("FR32X", ENCODING_IB) 1035 ENCODING("FR64X", ENCODING_IB) 1036 ENCODING("VR128X", ENCODING_IB) 1037 ENCODING("VR256X", ENCODING_IB) 1038 ENCODING("VR512", ENCODING_IB) 1039 errs() << "Unhandled immediate encoding " << s << "\n"; 1040 llvm_unreachable("Unhandled immediate encoding"); 1041 } 1042 1043 OperandEncoding 1044 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1045 uint8_t OpSize) { 1046 ENCODING("RST", ENCODING_FP) 1047 ENCODING("GR16", ENCODING_RM) 1048 ENCODING("GR32", ENCODING_RM) 1049 ENCODING("GR32orGR64", ENCODING_RM) 1050 ENCODING("GR64", ENCODING_RM) 1051 ENCODING("GR8", ENCODING_RM) 1052 ENCODING("VR128", ENCODING_RM) 1053 ENCODING("VR128X", ENCODING_RM) 1054 ENCODING("FR64", ENCODING_RM) 1055 ENCODING("FR32", ENCODING_RM) 1056 ENCODING("FR64X", ENCODING_RM) 1057 ENCODING("FR32X", ENCODING_RM) 1058 ENCODING("VR64", ENCODING_RM) 1059 ENCODING("VR256", ENCODING_RM) 1060 ENCODING("VR256X", ENCODING_RM) 1061 ENCODING("VR512", ENCODING_RM) 1062 ENCODING("VK1", ENCODING_RM) 1063 ENCODING("VK8", ENCODING_RM) 1064 ENCODING("VK16", ENCODING_RM) 1065 ENCODING("VK32", ENCODING_RM) 1066 ENCODING("VK64", ENCODING_RM) 1067 errs() << "Unhandled R/M register encoding " << s << "\n"; 1068 llvm_unreachable("Unhandled R/M register encoding"); 1069 } 1070 1071 OperandEncoding 1072 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1073 uint8_t OpSize) { 1074 ENCODING("GR16", ENCODING_REG) 1075 ENCODING("GR32", ENCODING_REG) 1076 ENCODING("GR32orGR64", ENCODING_REG) 1077 ENCODING("GR64", ENCODING_REG) 1078 ENCODING("GR8", ENCODING_REG) 1079 ENCODING("VR128", ENCODING_REG) 1080 ENCODING("FR64", ENCODING_REG) 1081 ENCODING("FR32", ENCODING_REG) 1082 ENCODING("VR64", ENCODING_REG) 1083 ENCODING("SEGMENT_REG", ENCODING_REG) 1084 ENCODING("DEBUG_REG", ENCODING_REG) 1085 ENCODING("CONTROL_REG", ENCODING_REG) 1086 ENCODING("VR256", ENCODING_REG) 1087 ENCODING("VR256X", ENCODING_REG) 1088 ENCODING("VR128X", ENCODING_REG) 1089 ENCODING("FR64X", ENCODING_REG) 1090 ENCODING("FR32X", ENCODING_REG) 1091 ENCODING("VR512", ENCODING_REG) 1092 ENCODING("VK1", ENCODING_REG) 1093 ENCODING("VK8", ENCODING_REG) 1094 ENCODING("VK16", ENCODING_REG) 1095 ENCODING("VK32", ENCODING_REG) 1096 ENCODING("VK64", ENCODING_REG) 1097 ENCODING("VK1WM", ENCODING_REG) 1098 ENCODING("VK8WM", ENCODING_REG) 1099 ENCODING("VK16WM", ENCODING_REG) 1100 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1101 llvm_unreachable("Unhandled reg/opcode register encoding"); 1102 } 1103 1104 OperandEncoding 1105 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1106 uint8_t OpSize) { 1107 ENCODING("GR32", ENCODING_VVVV) 1108 ENCODING("GR64", ENCODING_VVVV) 1109 ENCODING("FR32", ENCODING_VVVV) 1110 ENCODING("FR64", ENCODING_VVVV) 1111 ENCODING("VR128", ENCODING_VVVV) 1112 ENCODING("VR256", ENCODING_VVVV) 1113 ENCODING("FR32X", ENCODING_VVVV) 1114 ENCODING("FR64X", ENCODING_VVVV) 1115 ENCODING("VR128X", ENCODING_VVVV) 1116 ENCODING("VR256X", ENCODING_VVVV) 1117 ENCODING("VR512", ENCODING_VVVV) 1118 ENCODING("VK1", ENCODING_VVVV) 1119 ENCODING("VK2", ENCODING_VVVV) 1120 ENCODING("VK4", ENCODING_VVVV) 1121 ENCODING("VK8", ENCODING_VVVV) 1122 ENCODING("VK16", ENCODING_VVVV) 1123 ENCODING("VK32", ENCODING_VVVV) 1124 ENCODING("VK64", ENCODING_VVVV) 1125 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1126 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1127 } 1128 1129 OperandEncoding 1130 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1131 uint8_t OpSize) { 1132 ENCODING("VK1WM", ENCODING_WRITEMASK) 1133 ENCODING("VK2WM", ENCODING_WRITEMASK) 1134 ENCODING("VK4WM", ENCODING_WRITEMASK) 1135 ENCODING("VK8WM", ENCODING_WRITEMASK) 1136 ENCODING("VK16WM", ENCODING_WRITEMASK) 1137 ENCODING("VK32WM", ENCODING_WRITEMASK) 1138 ENCODING("VK64WM", ENCODING_WRITEMASK) 1139 errs() << "Unhandled mask register encoding " << s << "\n"; 1140 llvm_unreachable("Unhandled mask register encoding"); 1141 } 1142 1143 OperandEncoding 1144 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1145 uint8_t OpSize) { 1146 ENCODING("i16mem", ENCODING_RM) 1147 ENCODING("i32mem", ENCODING_RM) 1148 ENCODING("i64mem", ENCODING_RM) 1149 ENCODING("i8mem", ENCODING_RM) 1150 ENCODING("ssmem", ENCODING_RM) 1151 ENCODING("sdmem", ENCODING_RM) 1152 ENCODING("f128mem", ENCODING_RM) 1153 ENCODING("f256mem", ENCODING_RM) 1154 ENCODING("f512mem", ENCODING_RM) 1155 ENCODING("f64mem", ENCODING_RM) 1156 ENCODING("f32mem", ENCODING_RM) 1157 ENCODING("i128mem", ENCODING_RM) 1158 ENCODING("i256mem", ENCODING_RM) 1159 ENCODING("i512mem", ENCODING_RM) 1160 ENCODING("f80mem", ENCODING_RM) 1161 ENCODING("lea32mem", ENCODING_RM) 1162 ENCODING("lea64_32mem", ENCODING_RM) 1163 ENCODING("lea64mem", ENCODING_RM) 1164 ENCODING("opaque32mem", ENCODING_RM) 1165 ENCODING("opaque48mem", ENCODING_RM) 1166 ENCODING("opaque80mem", ENCODING_RM) 1167 ENCODING("opaque512mem", ENCODING_RM) 1168 ENCODING("vx32mem", ENCODING_RM) 1169 ENCODING("vy32mem", ENCODING_RM) 1170 ENCODING("vz32mem", ENCODING_RM) 1171 ENCODING("vx64mem", ENCODING_RM) 1172 ENCODING("vy64mem", ENCODING_RM) 1173 ENCODING("vy64xmem", ENCODING_RM) 1174 ENCODING("vz64mem", ENCODING_RM) 1175 errs() << "Unhandled memory encoding " << s << "\n"; 1176 llvm_unreachable("Unhandled memory encoding"); 1177 } 1178 1179 OperandEncoding 1180 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1181 uint8_t OpSize) { 1182 if(OpSize != X86Local::OpSize16) { 1183 // For instructions without an OpSize prefix, a declared 16-bit register or 1184 // immediate encoding is special. 1185 ENCODING("i16imm", ENCODING_IW) 1186 } 1187 ENCODING("i16imm", ENCODING_Iv) 1188 ENCODING("i16i8imm", ENCODING_IB) 1189 ENCODING("i32imm", ENCODING_Iv) 1190 ENCODING("i32i8imm", ENCODING_IB) 1191 ENCODING("i64i32imm", ENCODING_ID) 1192 ENCODING("i64i8imm", ENCODING_IB) 1193 ENCODING("i8imm", ENCODING_IB) 1194 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1195 ENCODING("i16imm_pcrel", ENCODING_IW) 1196 ENCODING("i32imm_pcrel", ENCODING_ID) 1197 ENCODING("brtarget", ENCODING_Iv) 1198 ENCODING("brtarget8", ENCODING_IB) 1199 ENCODING("i64imm", ENCODING_IO) 1200 ENCODING("offset8", ENCODING_Ia) 1201 ENCODING("offset16", ENCODING_Ia) 1202 ENCODING("offset32", ENCODING_Ia) 1203 ENCODING("offset64", ENCODING_Ia) 1204 ENCODING("srcidx8", ENCODING_SI) 1205 ENCODING("srcidx16", ENCODING_SI) 1206 ENCODING("srcidx32", ENCODING_SI) 1207 ENCODING("srcidx64", ENCODING_SI) 1208 ENCODING("dstidx8", ENCODING_DI) 1209 ENCODING("dstidx16", ENCODING_DI) 1210 ENCODING("dstidx32", ENCODING_DI) 1211 ENCODING("dstidx64", ENCODING_DI) 1212 errs() << "Unhandled relocation encoding " << s << "\n"; 1213 llvm_unreachable("Unhandled relocation encoding"); 1214 } 1215 1216 OperandEncoding 1217 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1218 uint8_t OpSize) { 1219 ENCODING("GR32", ENCODING_Rv) 1220 ENCODING("GR64", ENCODING_RO) 1221 ENCODING("GR16", ENCODING_Rv) 1222 ENCODING("GR8", ENCODING_RB) 1223 ENCODING("GR16_NOAX", ENCODING_Rv) 1224 ENCODING("GR32_NOAX", ENCODING_Rv) 1225 ENCODING("GR64_NOAX", ENCODING_RO) 1226 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1227 llvm_unreachable("Unhandled opcode modifier encoding"); 1228 } 1229 #undef ENCODING 1230