1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86ModRMFilters.h" 19 #include "llvm/Support/ErrorHandling.h" 20 #include <string> 21 22 using namespace llvm; 23 using namespace X86Disassembler; 24 25 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 26 /// Useful for switch statements and the like. 27 /// 28 /// @param init - A reference to the BitsInit to be decoded. 29 /// @return - The field, with the first bit in the BitsInit as the lowest 30 /// order bit. 31 static uint8_t byteFromBitsInit(BitsInit &init) { 32 int width = init.getNumBits(); 33 34 assert(width <= 8 && "Field is too large for uint8_t!"); 35 36 int index; 37 uint8_t mask = 0x01; 38 39 uint8_t ret = 0; 40 41 for (index = 0; index < width; index++) { 42 if (cast<BitInit>(init.getBit(index))->getValue()) 43 ret |= mask; 44 45 mask <<= 1; 46 } 47 48 return ret; 49 } 50 51 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 52 /// name of the field. 53 /// 54 /// @param rec - The record from which to extract the value. 55 /// @param name - The name of the field in the record. 56 /// @return - The field, as translated by byteFromBitsInit(). 57 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 58 BitsInit* bits = rec->getValueAsBitsInit(name); 59 return byteFromBitsInit(*bits); 60 } 61 62 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 63 const CodeGenInstruction &insn, 64 InstrUID uid) { 65 UID = uid; 66 67 Rec = insn.TheDef; 68 Name = Rec->getName(); 69 Spec = &tables.specForUID(UID); 70 71 if (!Rec->isSubClassOf("X86Inst")) { 72 ShouldBeEmitted = false; 73 return; 74 } 75 76 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 77 OpMap = byteFromRec(Rec, "OpMapBits"); 78 Opcode = byteFromRec(Rec, "Opcode"); 79 Form = byteFromRec(Rec, "FormBits"); 80 Encoding = byteFromRec(Rec, "OpEncBits"); 81 82 OpSize = byteFromRec(Rec, "OpSizeBits"); 83 AdSize = byteFromRec(Rec, "AdSizeBits"); 84 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 85 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 86 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 87 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 88 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 89 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 90 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 91 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 92 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 93 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 94 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 95 96 Name = Rec->getName(); 97 98 Operands = &insn.Operands.OperandList; 99 100 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 101 102 EncodeRC = HasEVEX_B && 103 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 104 105 // Check for 64-bit inst which does not require REX 106 Is32Bit = false; 107 Is64Bit = false; 108 // FIXME: Is there some better way to check for In64BitMode? 109 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 110 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 111 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 112 Predicates[i]->getName().find("In32Bit") != Name.npos) { 113 Is32Bit = true; 114 break; 115 } 116 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 117 Is64Bit = true; 118 break; 119 } 120 } 121 122 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 123 ShouldBeEmitted = false; 124 return; 125 } 126 127 // Special case since there is no attribute class for 64-bit and VEX 128 if (Name == "VMASKMOVDQU64") { 129 ShouldBeEmitted = false; 130 return; 131 } 132 133 ShouldBeEmitted = true; 134 } 135 136 void RecognizableInstr::processInstr(DisassemblerTables &tables, 137 const CodeGenInstruction &insn, 138 InstrUID uid) 139 { 140 // Ignore "asm parser only" instructions. 141 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 142 return; 143 144 RecognizableInstr recogInstr(tables, insn, uid); 145 146 if (recogInstr.shouldBeEmitted()) { 147 recogInstr.emitInstructionSpecifier(); 148 recogInstr.emitDecodePath(tables); 149 } 150 } 151 152 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 153 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 154 (HasEVEX_KZ ? n##_KZ : \ 155 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 156 157 InstructionContext RecognizableInstr::insnContext() const { 158 InstructionContext insnContext; 159 160 if (Encoding == X86Local::EVEX) { 161 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 162 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 163 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 164 } 165 // VEX_L & VEX_W 166 if (!EncodeRC && HasVEX_LPrefix && (VEX_WPrefix == X86Local::VEX_W1 || 167 VEX_WPrefix == X86Local::VEX_W1X)) { 168 if (OpPrefix == X86Local::PD) 169 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 170 else if (OpPrefix == X86Local::XS) 171 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 172 else if (OpPrefix == X86Local::XD) 173 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 174 else if (OpPrefix == X86Local::PS) 175 insnContext = EVEX_KB(IC_EVEX_L_W); 176 else { 177 errs() << "Instruction does not use a prefix: " << Name << "\n"; 178 llvm_unreachable("Invalid prefix"); 179 } 180 } else if (!EncodeRC && HasVEX_LPrefix) { 181 // VEX_L 182 if (OpPrefix == X86Local::PD) 183 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 184 else if (OpPrefix == X86Local::XS) 185 insnContext = EVEX_KB(IC_EVEX_L_XS); 186 else if (OpPrefix == X86Local::XD) 187 insnContext = EVEX_KB(IC_EVEX_L_XD); 188 else if (OpPrefix == X86Local::PS) 189 insnContext = EVEX_KB(IC_EVEX_L); 190 else { 191 errs() << "Instruction does not use a prefix: " << Name << "\n"; 192 llvm_unreachable("Invalid prefix"); 193 } 194 } else if (!EncodeRC && HasEVEX_L2Prefix && 195 (VEX_WPrefix == X86Local::VEX_W1 || 196 VEX_WPrefix == X86Local::VEX_W1X)) { 197 // EVEX_L2 & VEX_W 198 if (OpPrefix == X86Local::PD) 199 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 200 else if (OpPrefix == X86Local::XS) 201 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 202 else if (OpPrefix == X86Local::XD) 203 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 204 else if (OpPrefix == X86Local::PS) 205 insnContext = EVEX_KB(IC_EVEX_L2_W); 206 else { 207 errs() << "Instruction does not use a prefix: " << Name << "\n"; 208 llvm_unreachable("Invalid prefix"); 209 } 210 } else if (!EncodeRC && HasEVEX_L2Prefix) { 211 // EVEX_L2 212 if (OpPrefix == X86Local::PD) 213 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 214 else if (OpPrefix == X86Local::XD) 215 insnContext = EVEX_KB(IC_EVEX_L2_XD); 216 else if (OpPrefix == X86Local::XS) 217 insnContext = EVEX_KB(IC_EVEX_L2_XS); 218 else if (OpPrefix == X86Local::PS) 219 insnContext = EVEX_KB(IC_EVEX_L2); 220 else { 221 errs() << "Instruction does not use a prefix: " << Name << "\n"; 222 llvm_unreachable("Invalid prefix"); 223 } 224 } 225 else if (VEX_WPrefix == X86Local::VEX_W1 || 226 VEX_WPrefix == X86Local::VEX_W1X) { 227 // VEX_W 228 if (OpPrefix == X86Local::PD) 229 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 230 else if (OpPrefix == X86Local::XS) 231 insnContext = EVEX_KB(IC_EVEX_W_XS); 232 else if (OpPrefix == X86Local::XD) 233 insnContext = EVEX_KB(IC_EVEX_W_XD); 234 else if (OpPrefix == X86Local::PS) 235 insnContext = EVEX_KB(IC_EVEX_W); 236 else { 237 errs() << "Instruction does not use a prefix: " << Name << "\n"; 238 llvm_unreachable("Invalid prefix"); 239 } 240 } 241 // No L, no W 242 else if (OpPrefix == X86Local::PD) 243 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 244 else if (OpPrefix == X86Local::XD) 245 insnContext = EVEX_KB(IC_EVEX_XD); 246 else if (OpPrefix == X86Local::XS) 247 insnContext = EVEX_KB(IC_EVEX_XS); 248 else if (OpPrefix == X86Local::PS) 249 insnContext = EVEX_KB(IC_EVEX); 250 else { 251 errs() << "Instruction does not use a prefix: " << Name << "\n"; 252 llvm_unreachable("Invalid prefix"); 253 } 254 /// eof EVEX 255 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 256 if (HasVEX_LPrefix && (VEX_WPrefix == X86Local::VEX_W1 || 257 VEX_WPrefix == X86Local::VEX_W1X)) { 258 if (OpPrefix == X86Local::PD) 259 insnContext = IC_VEX_L_W_OPSIZE; 260 else if (OpPrefix == X86Local::XS) 261 insnContext = IC_VEX_L_W_XS; 262 else if (OpPrefix == X86Local::XD) 263 insnContext = IC_VEX_L_W_XD; 264 else if (OpPrefix == X86Local::PS) 265 insnContext = IC_VEX_L_W; 266 else { 267 errs() << "Instruction does not use a prefix: " << Name << "\n"; 268 llvm_unreachable("Invalid prefix"); 269 } 270 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 271 insnContext = IC_VEX_L_OPSIZE; 272 else if (OpPrefix == X86Local::PD && (VEX_WPrefix == X86Local::VEX_W1 || 273 VEX_WPrefix == X86Local::VEX_W1X)) 274 insnContext = IC_VEX_W_OPSIZE; 275 else if (OpPrefix == X86Local::PD) 276 insnContext = IC_VEX_OPSIZE; 277 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 278 insnContext = IC_VEX_L_XS; 279 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 280 insnContext = IC_VEX_L_XD; 281 else if ((VEX_WPrefix == X86Local::VEX_W1 || 282 VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::XS) 283 insnContext = IC_VEX_W_XS; 284 else if ((VEX_WPrefix == X86Local::VEX_W1 || 285 VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::XD) 286 insnContext = IC_VEX_W_XD; 287 else if ((VEX_WPrefix == X86Local::VEX_W1 || 288 VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::PS) 289 insnContext = IC_VEX_W; 290 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 291 insnContext = IC_VEX_L; 292 else if (OpPrefix == X86Local::XD) 293 insnContext = IC_VEX_XD; 294 else if (OpPrefix == X86Local::XS) 295 insnContext = IC_VEX_XS; 296 else if (OpPrefix == X86Local::PS) 297 insnContext = IC_VEX; 298 else { 299 errs() << "Instruction does not use a prefix: " << Name << "\n"; 300 llvm_unreachable("Invalid prefix"); 301 } 302 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 303 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 304 insnContext = IC_64BIT_REXW_OPSIZE; 305 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 306 insnContext = IC_64BIT_REXW_ADSIZE; 307 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 308 insnContext = IC_64BIT_XD_OPSIZE; 309 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 310 insnContext = IC_64BIT_XS_OPSIZE; 311 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 312 insnContext = IC_64BIT_OPSIZE_ADSIZE; 313 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 314 insnContext = IC_64BIT_OPSIZE_ADSIZE; 315 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 316 insnContext = IC_64BIT_OPSIZE; 317 else if (AdSize == X86Local::AdSize32) 318 insnContext = IC_64BIT_ADSIZE; 319 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 320 insnContext = IC_64BIT_REXW_XS; 321 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 322 insnContext = IC_64BIT_REXW_XD; 323 else if (OpPrefix == X86Local::XD) 324 insnContext = IC_64BIT_XD; 325 else if (OpPrefix == X86Local::XS) 326 insnContext = IC_64BIT_XS; 327 else if (HasREX_WPrefix) 328 insnContext = IC_64BIT_REXW; 329 else 330 insnContext = IC_64BIT; 331 } else { 332 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 333 insnContext = IC_XD_OPSIZE; 334 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 335 insnContext = IC_XS_OPSIZE; 336 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 337 insnContext = IC_XD_ADSIZE; 338 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 339 insnContext = IC_XS_ADSIZE; 340 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 341 insnContext = IC_OPSIZE_ADSIZE; 342 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 343 insnContext = IC_OPSIZE_ADSIZE; 344 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 345 insnContext = IC_OPSIZE; 346 else if (AdSize == X86Local::AdSize16) 347 insnContext = IC_ADSIZE; 348 else if (OpPrefix == X86Local::XD) 349 insnContext = IC_XD; 350 else if (OpPrefix == X86Local::XS) 351 insnContext = IC_XS; 352 else 353 insnContext = IC; 354 } 355 356 return insnContext; 357 } 358 359 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 360 // The scaling factor for AVX512 compressed displacement encoding is an 361 // instruction attribute. Adjust the ModRM encoding type to include the 362 // scale for compressed displacement. 363 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 364 return; 365 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 366 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 367 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 368 "Invalid CDisp scaling"); 369 } 370 371 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 372 unsigned &physicalOperandIndex, 373 unsigned numPhysicalOperands, 374 const unsigned *operandMapping, 375 OperandEncoding (*encodingFromString) 376 (const std::string&, 377 uint8_t OpSize)) { 378 if (optional) { 379 if (physicalOperandIndex >= numPhysicalOperands) 380 return; 381 } else { 382 assert(physicalOperandIndex < numPhysicalOperands); 383 } 384 385 while (operandMapping[operandIndex] != operandIndex) { 386 Spec->operands[operandIndex].encoding = ENCODING_DUP; 387 Spec->operands[operandIndex].type = 388 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 389 ++operandIndex; 390 } 391 392 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 393 394 OperandEncoding encoding = encodingFromString(typeName, OpSize); 395 // Adjust the encoding type for an operand based on the instruction. 396 adjustOperandEncoding(encoding); 397 Spec->operands[operandIndex].encoding = encoding; 398 Spec->operands[operandIndex].type = typeFromString(typeName, 399 HasREX_WPrefix, OpSize); 400 401 ++operandIndex; 402 ++physicalOperandIndex; 403 } 404 405 void RecognizableInstr::emitInstructionSpecifier() { 406 Spec->name = Name; 407 408 Spec->insnContext = insnContext(); 409 410 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 411 412 unsigned numOperands = OperandList.size(); 413 unsigned numPhysicalOperands = 0; 414 415 // operandMapping maps from operands in OperandList to their originals. 416 // If operandMapping[i] != i, then the entry is a duplicate. 417 unsigned operandMapping[X86_MAX_OPERANDS]; 418 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 419 420 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 421 if (!OperandList[operandIndex].Constraints.empty()) { 422 const CGIOperandList::ConstraintInfo &Constraint = 423 OperandList[operandIndex].Constraints[0]; 424 if (Constraint.isTied()) { 425 operandMapping[operandIndex] = operandIndex; 426 operandMapping[Constraint.getTiedOperand()] = operandIndex; 427 } else { 428 ++numPhysicalOperands; 429 operandMapping[operandIndex] = operandIndex; 430 } 431 } else { 432 ++numPhysicalOperands; 433 operandMapping[operandIndex] = operandIndex; 434 } 435 } 436 437 #define HANDLE_OPERAND(class) \ 438 handleOperand(false, \ 439 operandIndex, \ 440 physicalOperandIndex, \ 441 numPhysicalOperands, \ 442 operandMapping, \ 443 class##EncodingFromString); 444 445 #define HANDLE_OPTIONAL(class) \ 446 handleOperand(true, \ 447 operandIndex, \ 448 physicalOperandIndex, \ 449 numPhysicalOperands, \ 450 operandMapping, \ 451 class##EncodingFromString); 452 453 // operandIndex should always be < numOperands 454 unsigned operandIndex = 0; 455 // physicalOperandIndex should always be < numPhysicalOperands 456 unsigned physicalOperandIndex = 0; 457 458 #ifndef NDEBUG 459 // Given the set of prefix bits, how many additional operands does the 460 // instruction have? 461 unsigned additionalOperands = 0; 462 if (HasVEX_4V) 463 ++additionalOperands; 464 if (HasEVEX_K) 465 ++additionalOperands; 466 #endif 467 468 switch (Form) { 469 default: llvm_unreachable("Unhandled form"); 470 case X86Local::RawFrmSrc: 471 HANDLE_OPERAND(relocation); 472 return; 473 case X86Local::RawFrmDst: 474 HANDLE_OPERAND(relocation); 475 return; 476 case X86Local::RawFrmDstSrc: 477 HANDLE_OPERAND(relocation); 478 HANDLE_OPERAND(relocation); 479 return; 480 case X86Local::RawFrm: 481 // Operand 1 (optional) is an address or immediate. 482 assert(numPhysicalOperands <= 1 && 483 "Unexpected number of operands for RawFrm"); 484 HANDLE_OPTIONAL(relocation) 485 break; 486 case X86Local::RawFrmMemOffs: 487 // Operand 1 is an address. 488 HANDLE_OPERAND(relocation); 489 break; 490 case X86Local::AddRegFrm: 491 // Operand 1 is added to the opcode. 492 // Operand 2 (optional) is an address. 493 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 494 "Unexpected number of operands for AddRegFrm"); 495 HANDLE_OPERAND(opcodeModifier) 496 HANDLE_OPTIONAL(relocation) 497 break; 498 case X86Local::MRMDestReg: 499 // Operand 1 is a register operand in the R/M field. 500 // - In AVX512 there may be a mask operand here - 501 // Operand 2 is a register operand in the Reg/Opcode field. 502 // - In AVX, there is a register operand in the VEX.vvvv field here - 503 // Operand 3 (optional) is an immediate. 504 assert(numPhysicalOperands >= 2 + additionalOperands && 505 numPhysicalOperands <= 3 + additionalOperands && 506 "Unexpected number of operands for MRMDestRegFrm"); 507 508 HANDLE_OPERAND(rmRegister) 509 if (HasEVEX_K) 510 HANDLE_OPERAND(writemaskRegister) 511 512 if (HasVEX_4V) 513 // FIXME: In AVX, the register below becomes the one encoded 514 // in ModRMVEX and the one above the one in the VEX.VVVV field 515 HANDLE_OPERAND(vvvvRegister) 516 517 HANDLE_OPERAND(roRegister) 518 HANDLE_OPTIONAL(immediate) 519 break; 520 case X86Local::MRMDestMem: 521 // Operand 1 is a memory operand (possibly SIB-extended) 522 // Operand 2 is a register operand in the Reg/Opcode field. 523 // - In AVX, there is a register operand in the VEX.vvvv field here - 524 // Operand 3 (optional) is an immediate. 525 assert(numPhysicalOperands >= 2 + additionalOperands && 526 numPhysicalOperands <= 3 + additionalOperands && 527 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 528 529 HANDLE_OPERAND(memory) 530 531 if (HasEVEX_K) 532 HANDLE_OPERAND(writemaskRegister) 533 534 if (HasVEX_4V) 535 // FIXME: In AVX, the register below becomes the one encoded 536 // in ModRMVEX and the one above the one in the VEX.VVVV field 537 HANDLE_OPERAND(vvvvRegister) 538 539 HANDLE_OPERAND(roRegister) 540 HANDLE_OPTIONAL(immediate) 541 break; 542 case X86Local::MRMSrcReg: 543 // Operand 1 is a register operand in the Reg/Opcode field. 544 // Operand 2 is a register operand in the R/M field. 545 // - In AVX, there is a register operand in the VEX.vvvv field here - 546 // Operand 3 (optional) is an immediate. 547 // Operand 4 (optional) is an immediate. 548 549 assert(numPhysicalOperands >= 2 + additionalOperands && 550 numPhysicalOperands <= 4 + additionalOperands && 551 "Unexpected number of operands for MRMSrcRegFrm"); 552 553 HANDLE_OPERAND(roRegister) 554 555 if (HasEVEX_K) 556 HANDLE_OPERAND(writemaskRegister) 557 558 if (HasVEX_4V) 559 // FIXME: In AVX, the register below becomes the one encoded 560 // in ModRMVEX and the one above the one in the VEX.VVVV field 561 HANDLE_OPERAND(vvvvRegister) 562 563 HANDLE_OPERAND(rmRegister) 564 HANDLE_OPTIONAL(immediate) 565 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 566 break; 567 case X86Local::MRMSrcReg4VOp3: 568 assert(numPhysicalOperands == 3 && 569 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 570 HANDLE_OPERAND(roRegister) 571 HANDLE_OPERAND(rmRegister) 572 HANDLE_OPERAND(vvvvRegister) 573 break; 574 case X86Local::MRMSrcRegOp4: 575 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 576 "Unexpected number of operands for MRMSrcRegOp4Frm"); 577 HANDLE_OPERAND(roRegister) 578 HANDLE_OPERAND(vvvvRegister) 579 HANDLE_OPERAND(immediate) // Register in imm[7:4] 580 HANDLE_OPERAND(rmRegister) 581 HANDLE_OPTIONAL(immediate) 582 break; 583 case X86Local::MRMSrcMem: 584 // Operand 1 is a register operand in the Reg/Opcode field. 585 // Operand 2 is a memory operand (possibly SIB-extended) 586 // - In AVX, there is a register operand in the VEX.vvvv field here - 587 // Operand 3 (optional) is an immediate. 588 589 assert(numPhysicalOperands >= 2 + additionalOperands && 590 numPhysicalOperands <= 4 + additionalOperands && 591 "Unexpected number of operands for MRMSrcMemFrm"); 592 593 HANDLE_OPERAND(roRegister) 594 595 if (HasEVEX_K) 596 HANDLE_OPERAND(writemaskRegister) 597 598 if (HasVEX_4V) 599 // FIXME: In AVX, the register below becomes the one encoded 600 // in ModRMVEX and the one above the one in the VEX.VVVV field 601 HANDLE_OPERAND(vvvvRegister) 602 603 HANDLE_OPERAND(memory) 604 HANDLE_OPTIONAL(immediate) 605 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 606 break; 607 case X86Local::MRMSrcMem4VOp3: 608 assert(numPhysicalOperands == 3 && 609 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 610 HANDLE_OPERAND(roRegister) 611 HANDLE_OPERAND(memory) 612 HANDLE_OPERAND(vvvvRegister) 613 break; 614 case X86Local::MRMSrcMemOp4: 615 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 616 "Unexpected number of operands for MRMSrcMemOp4Frm"); 617 HANDLE_OPERAND(roRegister) 618 HANDLE_OPERAND(vvvvRegister) 619 HANDLE_OPERAND(immediate) // Register in imm[7:4] 620 HANDLE_OPERAND(memory) 621 HANDLE_OPTIONAL(immediate) 622 break; 623 case X86Local::MRMXr: 624 case X86Local::MRM0r: 625 case X86Local::MRM1r: 626 case X86Local::MRM2r: 627 case X86Local::MRM3r: 628 case X86Local::MRM4r: 629 case X86Local::MRM5r: 630 case X86Local::MRM6r: 631 case X86Local::MRM7r: 632 // Operand 1 is a register operand in the R/M field. 633 // Operand 2 (optional) is an immediate or relocation. 634 // Operand 3 (optional) is an immediate. 635 assert(numPhysicalOperands >= 0 + additionalOperands && 636 numPhysicalOperands <= 3 + additionalOperands && 637 "Unexpected number of operands for MRMnr"); 638 639 if (HasVEX_4V) 640 HANDLE_OPERAND(vvvvRegister) 641 642 if (HasEVEX_K) 643 HANDLE_OPERAND(writemaskRegister) 644 HANDLE_OPTIONAL(rmRegister) 645 HANDLE_OPTIONAL(relocation) 646 HANDLE_OPTIONAL(immediate) 647 break; 648 case X86Local::MRMXm: 649 case X86Local::MRM0m: 650 case X86Local::MRM1m: 651 case X86Local::MRM2m: 652 case X86Local::MRM3m: 653 case X86Local::MRM4m: 654 case X86Local::MRM5m: 655 case X86Local::MRM6m: 656 case X86Local::MRM7m: 657 // Operand 1 is a memory operand (possibly SIB-extended) 658 // Operand 2 (optional) is an immediate or relocation. 659 assert(numPhysicalOperands >= 1 + additionalOperands && 660 numPhysicalOperands <= 2 + additionalOperands && 661 "Unexpected number of operands for MRMnm"); 662 663 if (HasVEX_4V) 664 HANDLE_OPERAND(vvvvRegister) 665 if (HasEVEX_K) 666 HANDLE_OPERAND(writemaskRegister) 667 HANDLE_OPERAND(memory) 668 HANDLE_OPTIONAL(relocation) 669 break; 670 case X86Local::RawFrmImm8: 671 // operand 1 is a 16-bit immediate 672 // operand 2 is an 8-bit immediate 673 assert(numPhysicalOperands == 2 && 674 "Unexpected number of operands for X86Local::RawFrmImm8"); 675 HANDLE_OPERAND(immediate) 676 HANDLE_OPERAND(immediate) 677 break; 678 case X86Local::RawFrmImm16: 679 // operand 1 is a 16-bit immediate 680 // operand 2 is a 16-bit immediate 681 HANDLE_OPERAND(immediate) 682 HANDLE_OPERAND(immediate) 683 break; 684 #define MAP(from, to) case X86Local::MRM_##from: 685 X86_INSTR_MRM_MAPPING 686 #undef MAP 687 HANDLE_OPTIONAL(relocation) 688 break; 689 } 690 691 #undef HANDLE_OPERAND 692 #undef HANDLE_OPTIONAL 693 } 694 695 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 696 // Special cases where the LLVM tables are not complete 697 698 #define MAP(from, to) \ 699 case X86Local::MRM_##from: 700 701 llvm::Optional<OpcodeType> opcodeType; 702 switch (OpMap) { 703 default: llvm_unreachable("Invalid map!"); 704 case X86Local::OB: opcodeType = ONEBYTE; break; 705 case X86Local::TB: opcodeType = TWOBYTE; break; 706 case X86Local::T8: opcodeType = THREEBYTE_38; break; 707 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 708 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 709 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 710 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 711 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 712 } 713 714 std::unique_ptr<ModRMFilter> filter; 715 switch (Form) { 716 default: llvm_unreachable("Invalid form!"); 717 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 718 case X86Local::RawFrm: 719 case X86Local::AddRegFrm: 720 case X86Local::RawFrmMemOffs: 721 case X86Local::RawFrmSrc: 722 case X86Local::RawFrmDst: 723 case X86Local::RawFrmDstSrc: 724 case X86Local::RawFrmImm8: 725 case X86Local::RawFrmImm16: 726 filter = llvm::make_unique<DumbFilter>(); 727 break; 728 case X86Local::MRMDestReg: 729 case X86Local::MRMSrcReg: 730 case X86Local::MRMSrcReg4VOp3: 731 case X86Local::MRMSrcRegOp4: 732 case X86Local::MRMXr: 733 filter = llvm::make_unique<ModFilter>(true); 734 break; 735 case X86Local::MRMDestMem: 736 case X86Local::MRMSrcMem: 737 case X86Local::MRMSrcMem4VOp3: 738 case X86Local::MRMSrcMemOp4: 739 case X86Local::MRMXm: 740 filter = llvm::make_unique<ModFilter>(false); 741 break; 742 case X86Local::MRM0r: case X86Local::MRM1r: 743 case X86Local::MRM2r: case X86Local::MRM3r: 744 case X86Local::MRM4r: case X86Local::MRM5r: 745 case X86Local::MRM6r: case X86Local::MRM7r: 746 filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 747 break; 748 case X86Local::MRM0m: case X86Local::MRM1m: 749 case X86Local::MRM2m: case X86Local::MRM3m: 750 case X86Local::MRM4m: case X86Local::MRM5m: 751 case X86Local::MRM6m: case X86Local::MRM7m: 752 filter = llvm::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 753 break; 754 X86_INSTR_MRM_MAPPING 755 filter = llvm::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 756 break; 757 } // switch (Form) 758 759 uint8_t opcodeToSet = Opcode; 760 761 unsigned AddressSize = 0; 762 switch (AdSize) { 763 case X86Local::AdSize16: AddressSize = 16; break; 764 case X86Local::AdSize32: AddressSize = 32; break; 765 case X86Local::AdSize64: AddressSize = 64; break; 766 } 767 768 assert(opcodeType && "Opcode type not set"); 769 assert(filter && "Filter not set"); 770 771 if (Form == X86Local::AddRegFrm) { 772 assert(((opcodeToSet & 7) == 0) && 773 "ADDREG_FRM opcode not aligned"); 774 775 uint8_t currentOpcode; 776 777 for (currentOpcode = opcodeToSet; 778 currentOpcode < opcodeToSet + 8; 779 ++currentOpcode) 780 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 781 UID, Is32Bit, OpPrefix == 0, 782 IgnoresVEX_L || EncodeRC, 783 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 784 } else { 785 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 786 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 787 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 788 } 789 790 #undef MAP 791 } 792 793 #define TYPE(str, type) if (s == str) return type; 794 OperandType RecognizableInstr::typeFromString(const std::string &s, 795 bool hasREX_WPrefix, 796 uint8_t OpSize) { 797 if(hasREX_WPrefix) { 798 // For instructions with a REX_W prefix, a declared 32-bit register encoding 799 // is special. 800 TYPE("GR32", TYPE_R32) 801 } 802 if(OpSize == X86Local::OpSize16) { 803 // For OpSize16 instructions, a declared 16-bit register or 804 // immediate encoding is special. 805 TYPE("GR16", TYPE_Rv) 806 } else if(OpSize == X86Local::OpSize32) { 807 // For OpSize32 instructions, a declared 32-bit register or 808 // immediate encoding is special. 809 TYPE("GR32", TYPE_Rv) 810 } 811 TYPE("i16mem", TYPE_M) 812 TYPE("i16imm", TYPE_IMM) 813 TYPE("i16i8imm", TYPE_IMM) 814 TYPE("GR16", TYPE_R16) 815 TYPE("i32mem", TYPE_M) 816 TYPE("i32imm", TYPE_IMM) 817 TYPE("i32i8imm", TYPE_IMM) 818 TYPE("GR32", TYPE_R32) 819 TYPE("GR32orGR64", TYPE_R32) 820 TYPE("i64mem", TYPE_M) 821 TYPE("i64i32imm", TYPE_IMM) 822 TYPE("i64i8imm", TYPE_IMM) 823 TYPE("GR64", TYPE_R64) 824 TYPE("i8mem", TYPE_M) 825 TYPE("i8imm", TYPE_IMM) 826 TYPE("u8imm", TYPE_UIMM8) 827 TYPE("i32u8imm", TYPE_UIMM8) 828 TYPE("GR8", TYPE_R8) 829 TYPE("VR128", TYPE_XMM) 830 TYPE("VR128X", TYPE_XMM) 831 TYPE("f128mem", TYPE_M) 832 TYPE("f256mem", TYPE_M) 833 TYPE("f512mem", TYPE_M) 834 TYPE("FR128", TYPE_XMM) 835 TYPE("FR64", TYPE_XMM) 836 TYPE("FR64X", TYPE_XMM) 837 TYPE("f64mem", TYPE_M) 838 TYPE("sdmem", TYPE_M) 839 TYPE("FR32", TYPE_XMM) 840 TYPE("FR32X", TYPE_XMM) 841 TYPE("f32mem", TYPE_M) 842 TYPE("ssmem", TYPE_M) 843 TYPE("RST", TYPE_ST) 844 TYPE("RSTi", TYPE_ST) 845 TYPE("i128mem", TYPE_M) 846 TYPE("i256mem", TYPE_M) 847 TYPE("i512mem", TYPE_M) 848 TYPE("i64i32imm_pcrel", TYPE_REL) 849 TYPE("i16imm_pcrel", TYPE_REL) 850 TYPE("i32imm_pcrel", TYPE_REL) 851 TYPE("SSECC", TYPE_IMM3) 852 TYPE("XOPCC", TYPE_IMM3) 853 TYPE("AVXCC", TYPE_IMM5) 854 TYPE("AVX512ICC", TYPE_AVX512ICC) 855 TYPE("AVX512RC", TYPE_IMM) 856 TYPE("brtarget32", TYPE_REL) 857 TYPE("brtarget16", TYPE_REL) 858 TYPE("brtarget8", TYPE_REL) 859 TYPE("f80mem", TYPE_M) 860 TYPE("lea64_32mem", TYPE_M) 861 TYPE("lea64mem", TYPE_M) 862 TYPE("VR64", TYPE_MM64) 863 TYPE("i64imm", TYPE_IMM) 864 TYPE("anymem", TYPE_M) 865 TYPE("opaquemem", TYPE_M) 866 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 867 TYPE("DEBUG_REG", TYPE_DEBUGREG) 868 TYPE("CONTROL_REG", TYPE_CONTROLREG) 869 TYPE("srcidx8", TYPE_SRCIDX) 870 TYPE("srcidx16", TYPE_SRCIDX) 871 TYPE("srcidx32", TYPE_SRCIDX) 872 TYPE("srcidx64", TYPE_SRCIDX) 873 TYPE("dstidx8", TYPE_DSTIDX) 874 TYPE("dstidx16", TYPE_DSTIDX) 875 TYPE("dstidx32", TYPE_DSTIDX) 876 TYPE("dstidx64", TYPE_DSTIDX) 877 TYPE("offset16_8", TYPE_MOFFS) 878 TYPE("offset16_16", TYPE_MOFFS) 879 TYPE("offset16_32", TYPE_MOFFS) 880 TYPE("offset32_8", TYPE_MOFFS) 881 TYPE("offset32_16", TYPE_MOFFS) 882 TYPE("offset32_32", TYPE_MOFFS) 883 TYPE("offset32_64", TYPE_MOFFS) 884 TYPE("offset64_8", TYPE_MOFFS) 885 TYPE("offset64_16", TYPE_MOFFS) 886 TYPE("offset64_32", TYPE_MOFFS) 887 TYPE("offset64_64", TYPE_MOFFS) 888 TYPE("VR256", TYPE_YMM) 889 TYPE("VR256X", TYPE_YMM) 890 TYPE("VR512", TYPE_ZMM) 891 TYPE("VK1", TYPE_VK) 892 TYPE("VK1WM", TYPE_VK) 893 TYPE("VK2", TYPE_VK) 894 TYPE("VK2WM", TYPE_VK) 895 TYPE("VK4", TYPE_VK) 896 TYPE("VK4WM", TYPE_VK) 897 TYPE("VK8", TYPE_VK) 898 TYPE("VK8WM", TYPE_VK) 899 TYPE("VK16", TYPE_VK) 900 TYPE("VK16WM", TYPE_VK) 901 TYPE("VK32", TYPE_VK) 902 TYPE("VK32WM", TYPE_VK) 903 TYPE("VK64", TYPE_VK) 904 TYPE("VK64WM", TYPE_VK) 905 TYPE("vx64mem", TYPE_MVSIBX) 906 TYPE("vx128mem", TYPE_MVSIBX) 907 TYPE("vx256mem", TYPE_MVSIBX) 908 TYPE("vy128mem", TYPE_MVSIBY) 909 TYPE("vy256mem", TYPE_MVSIBY) 910 TYPE("vx64xmem", TYPE_MVSIBX) 911 TYPE("vx128xmem", TYPE_MVSIBX) 912 TYPE("vx256xmem", TYPE_MVSIBX) 913 TYPE("vy128xmem", TYPE_MVSIBY) 914 TYPE("vy256xmem", TYPE_MVSIBY) 915 TYPE("vy512xmem", TYPE_MVSIBY) 916 TYPE("vz256mem", TYPE_MVSIBZ) 917 TYPE("vz512mem", TYPE_MVSIBZ) 918 TYPE("BNDR", TYPE_BNDR) 919 errs() << "Unhandled type string " << s << "\n"; 920 llvm_unreachable("Unhandled type string"); 921 } 922 #undef TYPE 923 924 #define ENCODING(str, encoding) if (s == str) return encoding; 925 OperandEncoding 926 RecognizableInstr::immediateEncodingFromString(const std::string &s, 927 uint8_t OpSize) { 928 if(OpSize != X86Local::OpSize16) { 929 // For instructions without an OpSize prefix, a declared 16-bit register or 930 // immediate encoding is special. 931 ENCODING("i16imm", ENCODING_IW) 932 } 933 ENCODING("i32i8imm", ENCODING_IB) 934 ENCODING("SSECC", ENCODING_IB) 935 ENCODING("XOPCC", ENCODING_IB) 936 ENCODING("AVXCC", ENCODING_IB) 937 ENCODING("AVX512ICC", ENCODING_IB) 938 ENCODING("AVX512RC", ENCODING_IRC) 939 ENCODING("i16imm", ENCODING_Iv) 940 ENCODING("i16i8imm", ENCODING_IB) 941 ENCODING("i32imm", ENCODING_Iv) 942 ENCODING("i64i32imm", ENCODING_ID) 943 ENCODING("i64i8imm", ENCODING_IB) 944 ENCODING("i8imm", ENCODING_IB) 945 ENCODING("u8imm", ENCODING_IB) 946 ENCODING("i32u8imm", ENCODING_IB) 947 // This is not a typo. Instructions like BLENDVPD put 948 // register IDs in 8-bit immediates nowadays. 949 ENCODING("FR32", ENCODING_IB) 950 ENCODING("FR64", ENCODING_IB) 951 ENCODING("FR128", ENCODING_IB) 952 ENCODING("VR128", ENCODING_IB) 953 ENCODING("VR256", ENCODING_IB) 954 ENCODING("FR32X", ENCODING_IB) 955 ENCODING("FR64X", ENCODING_IB) 956 ENCODING("VR128X", ENCODING_IB) 957 ENCODING("VR256X", ENCODING_IB) 958 ENCODING("VR512", ENCODING_IB) 959 errs() << "Unhandled immediate encoding " << s << "\n"; 960 llvm_unreachable("Unhandled immediate encoding"); 961 } 962 963 OperandEncoding 964 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 965 uint8_t OpSize) { 966 ENCODING("RST", ENCODING_FP) 967 ENCODING("RSTi", ENCODING_FP) 968 ENCODING("GR16", ENCODING_RM) 969 ENCODING("GR32", ENCODING_RM) 970 ENCODING("GR32orGR64", ENCODING_RM) 971 ENCODING("GR64", ENCODING_RM) 972 ENCODING("GR8", ENCODING_RM) 973 ENCODING("VR128", ENCODING_RM) 974 ENCODING("VR128X", ENCODING_RM) 975 ENCODING("FR128", ENCODING_RM) 976 ENCODING("FR64", ENCODING_RM) 977 ENCODING("FR32", ENCODING_RM) 978 ENCODING("FR64X", ENCODING_RM) 979 ENCODING("FR32X", ENCODING_RM) 980 ENCODING("VR64", ENCODING_RM) 981 ENCODING("VR256", ENCODING_RM) 982 ENCODING("VR256X", ENCODING_RM) 983 ENCODING("VR512", ENCODING_RM) 984 ENCODING("VK1", ENCODING_RM) 985 ENCODING("VK2", ENCODING_RM) 986 ENCODING("VK4", ENCODING_RM) 987 ENCODING("VK8", ENCODING_RM) 988 ENCODING("VK16", ENCODING_RM) 989 ENCODING("VK32", ENCODING_RM) 990 ENCODING("VK64", ENCODING_RM) 991 ENCODING("BNDR", ENCODING_RM) 992 errs() << "Unhandled R/M register encoding " << s << "\n"; 993 llvm_unreachable("Unhandled R/M register encoding"); 994 } 995 996 OperandEncoding 997 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 998 uint8_t OpSize) { 999 ENCODING("GR16", ENCODING_REG) 1000 ENCODING("GR32", ENCODING_REG) 1001 ENCODING("GR32orGR64", ENCODING_REG) 1002 ENCODING("GR64", ENCODING_REG) 1003 ENCODING("GR8", ENCODING_REG) 1004 ENCODING("VR128", ENCODING_REG) 1005 ENCODING("FR128", ENCODING_REG) 1006 ENCODING("FR64", ENCODING_REG) 1007 ENCODING("FR32", ENCODING_REG) 1008 ENCODING("VR64", ENCODING_REG) 1009 ENCODING("SEGMENT_REG", ENCODING_REG) 1010 ENCODING("DEBUG_REG", ENCODING_REG) 1011 ENCODING("CONTROL_REG", ENCODING_REG) 1012 ENCODING("VR256", ENCODING_REG) 1013 ENCODING("VR256X", ENCODING_REG) 1014 ENCODING("VR128X", ENCODING_REG) 1015 ENCODING("FR64X", ENCODING_REG) 1016 ENCODING("FR32X", ENCODING_REG) 1017 ENCODING("VR512", ENCODING_REG) 1018 ENCODING("VK1", ENCODING_REG) 1019 ENCODING("VK2", ENCODING_REG) 1020 ENCODING("VK4", ENCODING_REG) 1021 ENCODING("VK8", ENCODING_REG) 1022 ENCODING("VK16", ENCODING_REG) 1023 ENCODING("VK32", ENCODING_REG) 1024 ENCODING("VK64", ENCODING_REG) 1025 ENCODING("VK1WM", ENCODING_REG) 1026 ENCODING("VK2WM", ENCODING_REG) 1027 ENCODING("VK4WM", ENCODING_REG) 1028 ENCODING("VK8WM", ENCODING_REG) 1029 ENCODING("VK16WM", ENCODING_REG) 1030 ENCODING("VK32WM", ENCODING_REG) 1031 ENCODING("VK64WM", ENCODING_REG) 1032 ENCODING("BNDR", ENCODING_REG) 1033 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1034 llvm_unreachable("Unhandled reg/opcode register encoding"); 1035 } 1036 1037 OperandEncoding 1038 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1039 uint8_t OpSize) { 1040 ENCODING("GR32", ENCODING_VVVV) 1041 ENCODING("GR64", ENCODING_VVVV) 1042 ENCODING("FR32", ENCODING_VVVV) 1043 ENCODING("FR128", ENCODING_VVVV) 1044 ENCODING("FR64", ENCODING_VVVV) 1045 ENCODING("VR128", ENCODING_VVVV) 1046 ENCODING("VR256", ENCODING_VVVV) 1047 ENCODING("FR32X", ENCODING_VVVV) 1048 ENCODING("FR64X", ENCODING_VVVV) 1049 ENCODING("VR128X", ENCODING_VVVV) 1050 ENCODING("VR256X", ENCODING_VVVV) 1051 ENCODING("VR512", ENCODING_VVVV) 1052 ENCODING("VK1", ENCODING_VVVV) 1053 ENCODING("VK2", ENCODING_VVVV) 1054 ENCODING("VK4", ENCODING_VVVV) 1055 ENCODING("VK8", ENCODING_VVVV) 1056 ENCODING("VK16", ENCODING_VVVV) 1057 ENCODING("VK32", ENCODING_VVVV) 1058 ENCODING("VK64", ENCODING_VVVV) 1059 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1060 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1061 } 1062 1063 OperandEncoding 1064 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1065 uint8_t OpSize) { 1066 ENCODING("VK1WM", ENCODING_WRITEMASK) 1067 ENCODING("VK2WM", ENCODING_WRITEMASK) 1068 ENCODING("VK4WM", ENCODING_WRITEMASK) 1069 ENCODING("VK8WM", ENCODING_WRITEMASK) 1070 ENCODING("VK16WM", ENCODING_WRITEMASK) 1071 ENCODING("VK32WM", ENCODING_WRITEMASK) 1072 ENCODING("VK64WM", ENCODING_WRITEMASK) 1073 errs() << "Unhandled mask register encoding " << s << "\n"; 1074 llvm_unreachable("Unhandled mask register encoding"); 1075 } 1076 1077 OperandEncoding 1078 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1079 uint8_t OpSize) { 1080 ENCODING("i16mem", ENCODING_RM) 1081 ENCODING("i32mem", ENCODING_RM) 1082 ENCODING("i64mem", ENCODING_RM) 1083 ENCODING("i8mem", ENCODING_RM) 1084 ENCODING("ssmem", ENCODING_RM) 1085 ENCODING("sdmem", ENCODING_RM) 1086 ENCODING("f128mem", ENCODING_RM) 1087 ENCODING("f256mem", ENCODING_RM) 1088 ENCODING("f512mem", ENCODING_RM) 1089 ENCODING("f64mem", ENCODING_RM) 1090 ENCODING("f32mem", ENCODING_RM) 1091 ENCODING("i128mem", ENCODING_RM) 1092 ENCODING("i256mem", ENCODING_RM) 1093 ENCODING("i512mem", ENCODING_RM) 1094 ENCODING("f80mem", ENCODING_RM) 1095 ENCODING("lea64_32mem", ENCODING_RM) 1096 ENCODING("lea64mem", ENCODING_RM) 1097 ENCODING("anymem", ENCODING_RM) 1098 ENCODING("opaquemem", ENCODING_RM) 1099 ENCODING("vx64mem", ENCODING_VSIB) 1100 ENCODING("vx128mem", ENCODING_VSIB) 1101 ENCODING("vx256mem", ENCODING_VSIB) 1102 ENCODING("vy128mem", ENCODING_VSIB) 1103 ENCODING("vy256mem", ENCODING_VSIB) 1104 ENCODING("vx64xmem", ENCODING_VSIB) 1105 ENCODING("vx128xmem", ENCODING_VSIB) 1106 ENCODING("vx256xmem", ENCODING_VSIB) 1107 ENCODING("vy128xmem", ENCODING_VSIB) 1108 ENCODING("vy256xmem", ENCODING_VSIB) 1109 ENCODING("vy512xmem", ENCODING_VSIB) 1110 ENCODING("vz256mem", ENCODING_VSIB) 1111 ENCODING("vz512mem", ENCODING_VSIB) 1112 errs() << "Unhandled memory encoding " << s << "\n"; 1113 llvm_unreachable("Unhandled memory encoding"); 1114 } 1115 1116 OperandEncoding 1117 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1118 uint8_t OpSize) { 1119 if(OpSize != X86Local::OpSize16) { 1120 // For instructions without an OpSize prefix, a declared 16-bit register or 1121 // immediate encoding is special. 1122 ENCODING("i16imm", ENCODING_IW) 1123 } 1124 ENCODING("i16imm", ENCODING_Iv) 1125 ENCODING("i16i8imm", ENCODING_IB) 1126 ENCODING("i32imm", ENCODING_Iv) 1127 ENCODING("i32i8imm", ENCODING_IB) 1128 ENCODING("i64i32imm", ENCODING_ID) 1129 ENCODING("i64i8imm", ENCODING_IB) 1130 ENCODING("i8imm", ENCODING_IB) 1131 ENCODING("u8imm", ENCODING_IB) 1132 ENCODING("i32u8imm", ENCODING_IB) 1133 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1134 ENCODING("i16imm_pcrel", ENCODING_IW) 1135 ENCODING("i32imm_pcrel", ENCODING_ID) 1136 ENCODING("brtarget32", ENCODING_ID) 1137 ENCODING("brtarget16", ENCODING_IW) 1138 ENCODING("brtarget8", ENCODING_IB) 1139 ENCODING("i64imm", ENCODING_IO) 1140 ENCODING("offset16_8", ENCODING_Ia) 1141 ENCODING("offset16_16", ENCODING_Ia) 1142 ENCODING("offset16_32", ENCODING_Ia) 1143 ENCODING("offset32_8", ENCODING_Ia) 1144 ENCODING("offset32_16", ENCODING_Ia) 1145 ENCODING("offset32_32", ENCODING_Ia) 1146 ENCODING("offset32_64", ENCODING_Ia) 1147 ENCODING("offset64_8", ENCODING_Ia) 1148 ENCODING("offset64_16", ENCODING_Ia) 1149 ENCODING("offset64_32", ENCODING_Ia) 1150 ENCODING("offset64_64", ENCODING_Ia) 1151 ENCODING("srcidx8", ENCODING_SI) 1152 ENCODING("srcidx16", ENCODING_SI) 1153 ENCODING("srcidx32", ENCODING_SI) 1154 ENCODING("srcidx64", ENCODING_SI) 1155 ENCODING("dstidx8", ENCODING_DI) 1156 ENCODING("dstidx16", ENCODING_DI) 1157 ENCODING("dstidx32", ENCODING_DI) 1158 ENCODING("dstidx64", ENCODING_DI) 1159 errs() << "Unhandled relocation encoding " << s << "\n"; 1160 llvm_unreachable("Unhandled relocation encoding"); 1161 } 1162 1163 OperandEncoding 1164 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1165 uint8_t OpSize) { 1166 ENCODING("GR32", ENCODING_Rv) 1167 ENCODING("GR64", ENCODING_RO) 1168 ENCODING("GR16", ENCODING_Rv) 1169 ENCODING("GR8", ENCODING_RB) 1170 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1171 llvm_unreachable("Unhandled opcode modifier encoding"); 1172 } 1173 #undef ENCODING 1174