1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 //  X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
20 
21 #include "llvm/Support/ErrorHandling.h"
22 
23 #include <string>
24 
25 using namespace llvm;
26 
27 #define MRM_MAPPING     \
28   MAP(C1, 33)           \
29   MAP(C2, 34)           \
30   MAP(C3, 35)           \
31   MAP(C4, 36)           \
32   MAP(C8, 37)           \
33   MAP(C9, 38)           \
34   MAP(E8, 39)           \
35   MAP(F0, 40)           \
36   MAP(F8, 41)           \
37   MAP(F9, 42)           \
38   MAP(D0, 45)           \
39   MAP(D1, 46)
40 
41 // A clone of X86 since we can't depend on something that is generated.
42 namespace X86Local {
43   enum {
44     Pseudo      = 0,
45     RawFrm      = 1,
46     AddRegFrm   = 2,
47     MRMDestReg  = 3,
48     MRMDestMem  = 4,
49     MRMSrcReg   = 5,
50     MRMSrcMem   = 6,
51     MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52     MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53     MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54     MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55     MRMInitReg  = 32,
56 #define MAP(from, to) MRM_##from = to,
57     MRM_MAPPING
58 #undef MAP
59     RawFrmImm8  = 43,
60     RawFrmImm16 = 44,
61     lastMRM
62   };
63 
64   enum {
65     TB  = 1,
66     REP = 2,
67     D8 = 3, D9 = 4, DA = 5, DB = 6,
68     DC = 7, DD = 8, DE = 9, DF = 10,
69     XD = 11,  XS = 12,
70     T8 = 13,  P_TA = 14,
71     A6 = 15,  A7 = 16, TF = 17
72   };
73 }
74 
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
77 //
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
80 //
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
83 //
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
91 
92 #define ONE_BYTE_EXTENSION_TABLES \
93   EXTENSION_TABLE(80)             \
94   EXTENSION_TABLE(81)             \
95   EXTENSION_TABLE(82)             \
96   EXTENSION_TABLE(83)             \
97   EXTENSION_TABLE(8f)             \
98   EXTENSION_TABLE(c0)             \
99   EXTENSION_TABLE(c1)             \
100   EXTENSION_TABLE(c6)             \
101   EXTENSION_TABLE(c7)             \
102   EXTENSION_TABLE(d0)             \
103   EXTENSION_TABLE(d1)             \
104   EXTENSION_TABLE(d2)             \
105   EXTENSION_TABLE(d3)             \
106   EXTENSION_TABLE(f6)             \
107   EXTENSION_TABLE(f7)             \
108   EXTENSION_TABLE(fe)             \
109   EXTENSION_TABLE(ff)
110 
111 #define TWO_BYTE_EXTENSION_TABLES \
112   EXTENSION_TABLE(00)             \
113   EXTENSION_TABLE(01)             \
114   EXTENSION_TABLE(18)             \
115   EXTENSION_TABLE(71)             \
116   EXTENSION_TABLE(72)             \
117   EXTENSION_TABLE(73)             \
118   EXTENSION_TABLE(ae)             \
119   EXTENSION_TABLE(ba)             \
120   EXTENSION_TABLE(c7)
121 
122 using namespace X86Disassembler;
123 
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 ///   ModR/M byte for the instruction to be properly decoded.  For example, a
126 ///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 ///   0b11.
128 ///
129 /// @param form - The form of the instruction.
130 /// @return     - true if the form implies that a ModR/M byte is required, false
131 ///               otherwise.
132 static bool needsModRMForDecode(uint8_t form) {
133   if (form == X86Local::MRMDestReg    ||
134      form == X86Local::MRMDestMem    ||
135      form == X86Local::MRMSrcReg     ||
136      form == X86Local::MRMSrcMem     ||
137      (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138      (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
139     return true;
140   else
141     return false;
142 }
143 
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 ///   the ModR/M byte to be 0b11.
146 ///
147 /// @param form - The form of the instruction.
148 /// @return     - true if the form implies that Mod must be 0b11, false
149 ///               otherwise.
150 static bool isRegFormat(uint8_t form) {
151   if (form == X86Local::MRMDestReg ||
152      form == X86Local::MRMSrcReg  ||
153      (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
154     return true;
155   else
156     return false;
157 }
158 
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 ///   Useful for switch statements and the like.
161 ///
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return     - The field, with the first bit in the BitsInit as the lowest
164 ///               order bit.
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166   int width = init.getNumBits();
167 
168   assert(width <= 8 && "Field is too large for uint8_t!");
169 
170   int     index;
171   uint8_t mask = 0x01;
172 
173   uint8_t ret = 0;
174 
175   for (index = 0; index < width; index++) {
176     if (static_cast<BitInit*>(init.getBit(index))->getValue())
177       ret |= mask;
178 
179     mask <<= 1;
180   }
181 
182   return ret;
183 }
184 
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 ///   name of the field.
187 ///
188 /// @param rec  - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return     - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192   BitsInit* bits = rec->getValueAsBitsInit(name);
193   return byteFromBitsInit(*bits);
194 }
195 
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197                                      const CodeGenInstruction &insn,
198                                      InstrUID uid) {
199   UID = uid;
200 
201   Rec = insn.TheDef;
202   Name = Rec->getName();
203   Spec = &tables.specForUID(UID);
204 
205   if (!Rec->isSubClassOf("X86Inst")) {
206     ShouldBeEmitted = false;
207     return;
208   }
209 
210   Prefix   = byteFromRec(Rec, "Prefix");
211   Opcode   = byteFromRec(Rec, "Opcode");
212   Form     = byteFromRec(Rec, "FormBits");
213   SegOvr   = byteFromRec(Rec, "SegOvrBits");
214 
215   HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
216   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
217   HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
218   HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
219   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
220   HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
221   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
222 
223   Name      = Rec->getName();
224   AsmString = Rec->getValueAsString("AsmString");
225 
226   Operands = &insn.Operands.OperandList;
227 
228   IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
229                      (Name.find("CRC32") != Name.npos);
230   HasFROperands    = hasFROperands();
231   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
232 
233   // Check for 64-bit inst which does not require REX
234   Is32Bit = false;
235   Is64Bit = false;
236   // FIXME: Is there some better way to check for In64BitMode?
237   std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
238   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
239     if (Predicates[i]->getName().find("32Bit") != Name.npos) {
240       Is32Bit = true;
241       break;
242     }
243     if (Predicates[i]->getName().find("64Bit") != Name.npos) {
244       Is64Bit = true;
245       break;
246     }
247   }
248   // FIXME: These instructions aren't marked as 64-bit in any way
249   Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
250              Rec->getName() == "MASKMOVDQU64" ||
251              Rec->getName() == "POPFS64" ||
252              Rec->getName() == "POPGS64" ||
253              Rec->getName() == "PUSHFS64" ||
254              Rec->getName() == "PUSHGS64" ||
255              Rec->getName() == "REX64_PREFIX" ||
256              Rec->getName().find("VMREAD64") != Name.npos ||
257              Rec->getName().find("VMWRITE64") != Name.npos ||
258              Rec->getName().find("INVEPT64") != Name.npos ||
259              Rec->getName().find("INVVPID64") != Name.npos ||
260              Rec->getName().find("MOV64") != Name.npos ||
261              Rec->getName().find("PUSH64") != Name.npos ||
262              Rec->getName().find("POP64") != Name.npos;
263 
264   ShouldBeEmitted  = true;
265 }
266 
267 void RecognizableInstr::processInstr(DisassemblerTables &tables,
268 	const CodeGenInstruction &insn,
269                                    InstrUID uid)
270 {
271   // Ignore "asm parser only" instructions.
272   if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
273     return;
274 
275   RecognizableInstr recogInstr(tables, insn, uid);
276 
277   recogInstr.emitInstructionSpecifier(tables);
278 
279   if (recogInstr.shouldBeEmitted())
280     recogInstr.emitDecodePath(tables);
281 }
282 
283 InstructionContext RecognizableInstr::insnContext() const {
284   InstructionContext insnContext;
285 
286   if (HasVEX_4VPrefix || HasVEXPrefix) {
287     if (HasOpSizePrefix && HasVEX_LPrefix)
288       insnContext = IC_VEX_L_OPSIZE;
289     else if (HasOpSizePrefix && HasVEX_WPrefix)
290       insnContext = IC_VEX_W_OPSIZE;
291     else if (HasOpSizePrefix)
292       insnContext = IC_VEX_OPSIZE;
293     else if (HasVEX_LPrefix && Prefix == X86Local::XS)
294       insnContext = IC_VEX_L_XS;
295     else if (HasVEX_LPrefix && Prefix == X86Local::XD)
296       insnContext = IC_VEX_L_XD;
297     else if (HasVEX_WPrefix && Prefix == X86Local::XS)
298       insnContext = IC_VEX_W_XS;
299     else if (HasVEX_WPrefix && Prefix == X86Local::XD)
300       insnContext = IC_VEX_W_XD;
301     else if (HasVEX_WPrefix)
302       insnContext = IC_VEX_W;
303     else if (HasVEX_LPrefix)
304       insnContext = IC_VEX_L;
305     else if (Prefix == X86Local::XD)
306       insnContext = IC_VEX_XD;
307     else if (Prefix == X86Local::XS)
308       insnContext = IC_VEX_XS;
309     else
310       insnContext = IC_VEX;
311   } else if (Is64Bit || HasREX_WPrefix) {
312     if (HasREX_WPrefix && HasOpSizePrefix)
313       insnContext = IC_64BIT_REXW_OPSIZE;
314     else if (HasOpSizePrefix && (Prefix == X86Local::XD || Prefix == X86Local::TF))
315       insnContext = IC_64BIT_XD_OPSIZE;
316     else if (HasOpSizePrefix)
317       insnContext = IC_64BIT_OPSIZE;
318     else if (HasREX_WPrefix && Prefix == X86Local::XS)
319       insnContext = IC_64BIT_REXW_XS;
320     else if (HasREX_WPrefix && (Prefix == X86Local::XD || Prefix == X86Local::TF))
321       insnContext = IC_64BIT_REXW_XD;
322     else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
323       insnContext = IC_64BIT_XD;
324     else if (Prefix == X86Local::XS)
325       insnContext = IC_64BIT_XS;
326     else if (HasREX_WPrefix)
327       insnContext = IC_64BIT_REXW;
328     else
329       insnContext = IC_64BIT;
330   } else {
331     if (HasOpSizePrefix &&
332         (Prefix == X86Local::XD || Prefix == X86Local::TF))
333       insnContext = IC_XD_OPSIZE;
334     else if (HasOpSizePrefix)
335       insnContext = IC_OPSIZE;
336     else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
337       insnContext = IC_XD;
338     else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
339       insnContext = IC_XS;
340     else
341       insnContext = IC;
342   }
343 
344   return insnContext;
345 }
346 
347 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
348   ///////////////////
349   // FILTER_STRONG
350   //
351 
352   // Filter out intrinsics
353 
354   if (!Rec->isSubClassOf("X86Inst"))
355     return FILTER_STRONG;
356 
357   if (Form == X86Local::Pseudo ||
358       (IsCodeGenOnly && Name.find("_REV") == Name.npos))
359     return FILTER_STRONG;
360 
361   if (Form == X86Local::MRMInitReg)
362     return FILTER_STRONG;
363 
364 
365   // Filter out artificial instructions
366 
367   if (Name.find("TAILJMP") != Name.npos    ||
368       Name.find("_Int") != Name.npos       ||
369       Name.find("_int") != Name.npos       ||
370       Name.find("Int_") != Name.npos       ||
371       Name.find("_NOREX") != Name.npos     ||
372       Name.find("_TC") != Name.npos        ||
373       Name.find("EH_RETURN") != Name.npos  ||
374       Name.find("V_SET") != Name.npos      ||
375       Name.find("LOCK_") != Name.npos      ||
376       Name.find("WIN") != Name.npos        ||
377       Name.find("_AVX") != Name.npos       ||
378       Name.find("2SDL") != Name.npos)
379     return FILTER_STRONG;
380 
381   // Filter out instructions with segment override prefixes.
382   // They're too messy to handle now and we'll special case them if needed.
383 
384   if (SegOvr)
385     return FILTER_STRONG;
386 
387   // Filter out instructions that can't be printed.
388 
389   if (AsmString.size() == 0)
390     return FILTER_STRONG;
391 
392   // Filter out instructions with subreg operands.
393 
394   if (AsmString.find("subreg") != AsmString.npos)
395     return FILTER_STRONG;
396 
397   /////////////////
398   // FILTER_WEAK
399   //
400 
401 
402   // Filter out instructions with a LOCK prefix;
403   //   prefer forms that do not have the prefix
404   if (HasLockPrefix)
405     return FILTER_WEAK;
406 
407   // Filter out alternate forms of AVX instructions
408   if (Name.find("_alt") != Name.npos ||
409       Name.find("XrYr") != Name.npos ||
410       (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
411       Name.find("_64mr") != Name.npos ||
412       Name.find("Xrr") != Name.npos ||
413       Name.find("rr64") != Name.npos)
414     return FILTER_WEAK;
415 
416   if (Name == "VMASKMOVDQU64"  ||
417       Name == "VEXTRACTPSrr64" ||
418       Name == "VMOVQd64rr"     ||
419       Name == "VMOVQs64rr")
420     return FILTER_WEAK;
421 
422   // Special cases.
423 
424   if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
425     return FILTER_WEAK;
426   if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
427     return FILTER_WEAK;
428 
429   if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
430     return FILTER_WEAK;
431   if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
432     return FILTER_WEAK;
433   if (Name.find("Fs") != Name.npos)
434     return FILTER_WEAK;
435   if (Name == "MOVLPDrr"          ||
436       Name == "MOVLPSrr"          ||
437       Name == "PUSHFQ"            ||
438       Name == "BSF16rr"           ||
439       Name == "BSF16rm"           ||
440       Name == "BSR16rr"           ||
441       Name == "BSR16rm"           ||
442       Name == "MOVSX16rm8"        ||
443       Name == "MOVSX16rr8"        ||
444       Name == "MOVZX16rm8"        ||
445       Name == "MOVZX16rr8"        ||
446       Name == "PUSH32i16"         ||
447       Name == "PUSH64i16"         ||
448       Name == "MOVPQI2QImr"       ||
449       Name == "VMOVPQI2QImr"      ||
450       Name == "MOVSDmr"           ||
451       Name == "MOVSDrm"           ||
452       Name == "MOVSSmr"           ||
453       Name == "MOVSSrm"           ||
454       Name == "MMX_MOVD64rrv164"  ||
455       Name == "CRC32m16"          ||
456       Name == "MOV64ri64i32"      ||
457       Name == "CRC32r16")
458     return FILTER_WEAK;
459 
460   if (HasFROperands && Name.find("MOV") != Name.npos &&
461      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
462       (Name.find("to") != Name.npos)))
463     return FILTER_WEAK;
464 
465   return FILTER_NORMAL;
466 }
467 
468 bool RecognizableInstr::hasFROperands() const {
469   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
470   unsigned numOperands = OperandList.size();
471 
472   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
473     const std::string &recName = OperandList[operandIndex].Rec->getName();
474 
475     if (recName.find("FR") != recName.npos)
476       return true;
477   }
478   return false;
479 }
480 
481 bool RecognizableInstr::has256BitOperands() const {
482   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
483   unsigned numOperands = OperandList.size();
484 
485   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
486     const std::string &recName = OperandList[operandIndex].Rec->getName();
487 
488     if (!recName.compare("VR256") || !recName.compare("f256mem")) {
489       return true;
490     }
491   }
492   return false;
493 }
494 
495 void RecognizableInstr::handleOperand(
496   bool optional,
497   unsigned &operandIndex,
498   unsigned &physicalOperandIndex,
499   unsigned &numPhysicalOperands,
500   unsigned *operandMapping,
501   OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
502   if (optional) {
503     if (physicalOperandIndex >= numPhysicalOperands)
504       return;
505   } else {
506     assert(physicalOperandIndex < numPhysicalOperands);
507   }
508 
509   while (operandMapping[operandIndex] != operandIndex) {
510     Spec->operands[operandIndex].encoding = ENCODING_DUP;
511     Spec->operands[operandIndex].type =
512       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
513     ++operandIndex;
514   }
515 
516   const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
517 
518   Spec->operands[operandIndex].encoding = encodingFromString(typeName,
519                                                               HasOpSizePrefix);
520   Spec->operands[operandIndex].type = typeFromString(typeName,
521                                                      IsSSE,
522                                                      HasREX_WPrefix,
523                                                      HasOpSizePrefix);
524 
525   ++operandIndex;
526   ++physicalOperandIndex;
527 }
528 
529 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
530   Spec->name       = Name;
531 
532   if (!Rec->isSubClassOf("X86Inst"))
533     return;
534 
535   switch (filter()) {
536   case FILTER_WEAK:
537     Spec->filtered = true;
538     break;
539   case FILTER_STRONG:
540     ShouldBeEmitted = false;
541     return;
542   case FILTER_NORMAL:
543     break;
544   }
545 
546   Spec->insnContext = insnContext();
547 
548   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
549 
550   unsigned operandIndex;
551   unsigned numOperands = OperandList.size();
552   unsigned numPhysicalOperands = 0;
553 
554   // operandMapping maps from operands in OperandList to their originals.
555   // If operandMapping[i] != i, then the entry is a duplicate.
556   unsigned operandMapping[X86_MAX_OPERANDS];
557 
558   bool hasFROperands = false;
559 
560   assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
561 
562   for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
563     if (OperandList[operandIndex].Constraints.size()) {
564       const CGIOperandList::ConstraintInfo &Constraint =
565         OperandList[operandIndex].Constraints[0];
566       if (Constraint.isTied()) {
567         operandMapping[operandIndex] = Constraint.getTiedOperand();
568       } else {
569         ++numPhysicalOperands;
570         operandMapping[operandIndex] = operandIndex;
571       }
572     } else {
573       ++numPhysicalOperands;
574       operandMapping[operandIndex] = operandIndex;
575     }
576 
577     const std::string &recName = OperandList[operandIndex].Rec->getName();
578 
579     if (recName.find("FR") != recName.npos)
580       hasFROperands = true;
581   }
582 
583   if (hasFROperands && Name.find("MOV") != Name.npos &&
584      ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
585       (Name.find("to") != Name.npos)))
586     ShouldBeEmitted = false;
587 
588   if (!ShouldBeEmitted)
589     return;
590 
591 #define HANDLE_OPERAND(class)               \
592   handleOperand(false,                      \
593                 operandIndex,               \
594                 physicalOperandIndex,       \
595                 numPhysicalOperands,        \
596                 operandMapping,             \
597                 class##EncodingFromString);
598 
599 #define HANDLE_OPTIONAL(class)              \
600   handleOperand(true,                       \
601                 operandIndex,               \
602                 physicalOperandIndex,       \
603                 numPhysicalOperands,        \
604                 operandMapping,             \
605                 class##EncodingFromString);
606 
607   // operandIndex should always be < numOperands
608   operandIndex = 0;
609   // physicalOperandIndex should always be < numPhysicalOperands
610   unsigned physicalOperandIndex = 0;
611 
612   switch (Form) {
613   case X86Local::RawFrm:
614     // Operand 1 (optional) is an address or immediate.
615     // Operand 2 (optional) is an immediate.
616     assert(numPhysicalOperands <= 2 &&
617            "Unexpected number of operands for RawFrm");
618     HANDLE_OPTIONAL(relocation)
619     HANDLE_OPTIONAL(immediate)
620     break;
621   case X86Local::AddRegFrm:
622     // Operand 1 is added to the opcode.
623     // Operand 2 (optional) is an address.
624     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
625            "Unexpected number of operands for AddRegFrm");
626     HANDLE_OPERAND(opcodeModifier)
627     HANDLE_OPTIONAL(relocation)
628     break;
629   case X86Local::MRMDestReg:
630     // Operand 1 is a register operand in the R/M field.
631     // Operand 2 is a register operand in the Reg/Opcode field.
632     // - In AVX, there is a register operand in the VEX.vvvv field here -
633     // Operand 3 (optional) is an immediate.
634     if (HasVEX_4VPrefix)
635       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
636              "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
637     else
638       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
639              "Unexpected number of operands for MRMDestRegFrm");
640 
641     HANDLE_OPERAND(rmRegister)
642 
643     if (HasVEX_4VPrefix)
644       // FIXME: In AVX, the register below becomes the one encoded
645       // in ModRMVEX and the one above the one in the VEX.VVVV field
646       HANDLE_OPERAND(vvvvRegister)
647 
648     HANDLE_OPERAND(roRegister)
649     HANDLE_OPTIONAL(immediate)
650     break;
651   case X86Local::MRMDestMem:
652     // Operand 1 is a memory operand (possibly SIB-extended)
653     // Operand 2 is a register operand in the Reg/Opcode field.
654     // - In AVX, there is a register operand in the VEX.vvvv field here -
655     // Operand 3 (optional) is an immediate.
656     if (HasVEX_4VPrefix)
657       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
658              "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
659     else
660       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
661              "Unexpected number of operands for MRMDestMemFrm");
662     HANDLE_OPERAND(memory)
663 
664     if (HasVEX_4VPrefix)
665       // FIXME: In AVX, the register below becomes the one encoded
666       // in ModRMVEX and the one above the one in the VEX.VVVV field
667       HANDLE_OPERAND(vvvvRegister)
668 
669     HANDLE_OPERAND(roRegister)
670     HANDLE_OPTIONAL(immediate)
671     break;
672   case X86Local::MRMSrcReg:
673     // Operand 1 is a register operand in the Reg/Opcode field.
674     // Operand 2 is a register operand in the R/M field.
675     // - In AVX, there is a register operand in the VEX.vvvv field here -
676     // Operand 3 (optional) is an immediate.
677 
678     if (HasVEX_4VPrefix)
679       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
680              "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
681     else
682       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
683              "Unexpected number of operands for MRMSrcRegFrm");
684 
685     HANDLE_OPERAND(roRegister)
686 
687     if (HasVEX_4VPrefix)
688       // FIXME: In AVX, the register below becomes the one encoded
689       // in ModRMVEX and the one above the one in the VEX.VVVV field
690       HANDLE_OPERAND(vvvvRegister)
691 
692     HANDLE_OPERAND(rmRegister)
693     HANDLE_OPTIONAL(immediate)
694     break;
695   case X86Local::MRMSrcMem:
696     // Operand 1 is a register operand in the Reg/Opcode field.
697     // Operand 2 is a memory operand (possibly SIB-extended)
698     // - In AVX, there is a register operand in the VEX.vvvv field here -
699     // Operand 3 (optional) is an immediate.
700 
701     if (HasVEX_4VPrefix)
702       assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
703              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
704     else
705       assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
706              "Unexpected number of operands for MRMSrcMemFrm");
707 
708     HANDLE_OPERAND(roRegister)
709 
710     if (HasVEX_4VPrefix)
711       // FIXME: In AVX, the register below becomes the one encoded
712       // in ModRMVEX and the one above the one in the VEX.VVVV field
713       HANDLE_OPERAND(vvvvRegister)
714 
715     HANDLE_OPERAND(memory)
716     HANDLE_OPTIONAL(immediate)
717     break;
718   case X86Local::MRM0r:
719   case X86Local::MRM1r:
720   case X86Local::MRM2r:
721   case X86Local::MRM3r:
722   case X86Local::MRM4r:
723   case X86Local::MRM5r:
724   case X86Local::MRM6r:
725   case X86Local::MRM7r:
726     // Operand 1 is a register operand in the R/M field.
727     // Operand 2 (optional) is an immediate or relocation.
728     if (HasVEX_4VPrefix)
729       assert(numPhysicalOperands <= 3 &&
730              "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
731     else
732       assert(numPhysicalOperands <= 2 &&
733              "Unexpected number of operands for MRMnRFrm");
734     if (HasVEX_4VPrefix)
735       HANDLE_OPERAND(vvvvRegister);
736     HANDLE_OPTIONAL(rmRegister)
737     HANDLE_OPTIONAL(relocation)
738     break;
739   case X86Local::MRM0m:
740   case X86Local::MRM1m:
741   case X86Local::MRM2m:
742   case X86Local::MRM3m:
743   case X86Local::MRM4m:
744   case X86Local::MRM5m:
745   case X86Local::MRM6m:
746   case X86Local::MRM7m:
747     // Operand 1 is a memory operand (possibly SIB-extended)
748     // Operand 2 (optional) is an immediate or relocation.
749     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
750            "Unexpected number of operands for MRMnMFrm");
751     HANDLE_OPERAND(memory)
752     HANDLE_OPTIONAL(relocation)
753     break;
754   case X86Local::RawFrmImm8:
755     // operand 1 is a 16-bit immediate
756     // operand 2 is an 8-bit immediate
757     assert(numPhysicalOperands == 2 &&
758            "Unexpected number of operands for X86Local::RawFrmImm8");
759     HANDLE_OPERAND(immediate)
760     HANDLE_OPERAND(immediate)
761     break;
762   case X86Local::RawFrmImm16:
763     // operand 1 is a 16-bit immediate
764     // operand 2 is a 16-bit immediate
765     HANDLE_OPERAND(immediate)
766     HANDLE_OPERAND(immediate)
767     break;
768   case X86Local::MRMInitReg:
769     // Ignored.
770     break;
771   }
772 
773   #undef HANDLE_OPERAND
774   #undef HANDLE_OPTIONAL
775 }
776 
777 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
778   // Special cases where the LLVM tables are not complete
779 
780 #define MAP(from, to)                     \
781   case X86Local::MRM_##from:              \
782     filter = new ExactFilter(0x##from);   \
783     break;
784 
785   OpcodeType    opcodeType  = (OpcodeType)-1;
786 
787   ModRMFilter*  filter      = NULL;
788   uint8_t       opcodeToSet = 0;
789 
790   switch (Prefix) {
791   // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
792   case X86Local::XD:
793   case X86Local::XS:
794   case X86Local::TB:
795     opcodeType = TWOBYTE;
796 
797     switch (Opcode) {
798     default:
799       if (needsModRMForDecode(Form))
800         filter = new ModFilter(isRegFormat(Form));
801       else
802         filter = new DumbFilter();
803       break;
804 #define EXTENSION_TABLE(n) case 0x##n:
805     TWO_BYTE_EXTENSION_TABLES
806 #undef EXTENSION_TABLE
807       switch (Form) {
808       default:
809         llvm_unreachable("Unhandled two-byte extended opcode");
810       case X86Local::MRM0r:
811       case X86Local::MRM1r:
812       case X86Local::MRM2r:
813       case X86Local::MRM3r:
814       case X86Local::MRM4r:
815       case X86Local::MRM5r:
816       case X86Local::MRM6r:
817       case X86Local::MRM7r:
818         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
819         break;
820       case X86Local::MRM0m:
821       case X86Local::MRM1m:
822       case X86Local::MRM2m:
823       case X86Local::MRM3m:
824       case X86Local::MRM4m:
825       case X86Local::MRM5m:
826       case X86Local::MRM6m:
827       case X86Local::MRM7m:
828         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
829         break;
830       MRM_MAPPING
831       } // switch (Form)
832       break;
833     } // switch (Opcode)
834     opcodeToSet = Opcode;
835     break;
836   case X86Local::T8:
837   case X86Local::TF:
838     opcodeType = THREEBYTE_38;
839     if (needsModRMForDecode(Form))
840       filter = new ModFilter(isRegFormat(Form));
841     else
842       filter = new DumbFilter();
843     opcodeToSet = Opcode;
844     break;
845   case X86Local::P_TA:
846     opcodeType = THREEBYTE_3A;
847     if (needsModRMForDecode(Form))
848       filter = new ModFilter(isRegFormat(Form));
849     else
850       filter = new DumbFilter();
851     opcodeToSet = Opcode;
852     break;
853   case X86Local::A6:
854     opcodeType = THREEBYTE_A6;
855     if (needsModRMForDecode(Form))
856       filter = new ModFilter(isRegFormat(Form));
857     else
858       filter = new DumbFilter();
859     opcodeToSet = Opcode;
860     break;
861   case X86Local::A7:
862     opcodeType = THREEBYTE_A7;
863     if (needsModRMForDecode(Form))
864       filter = new ModFilter(isRegFormat(Form));
865     else
866       filter = new DumbFilter();
867     opcodeToSet = Opcode;
868     break;
869   case X86Local::D8:
870   case X86Local::D9:
871   case X86Local::DA:
872   case X86Local::DB:
873   case X86Local::DC:
874   case X86Local::DD:
875   case X86Local::DE:
876   case X86Local::DF:
877     assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
878     opcodeType = ONEBYTE;
879     if (Form == X86Local::AddRegFrm) {
880       Spec->modifierType = MODIFIER_MODRM;
881       Spec->modifierBase = Opcode;
882       filter = new AddRegEscapeFilter(Opcode);
883     } else {
884       filter = new EscapeFilter(true, Opcode);
885     }
886     opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
887     break;
888   case X86Local::REP:
889   default:
890     opcodeType = ONEBYTE;
891     switch (Opcode) {
892 #define EXTENSION_TABLE(n) case 0x##n:
893     ONE_BYTE_EXTENSION_TABLES
894 #undef EXTENSION_TABLE
895       switch (Form) {
896       default:
897         llvm_unreachable("Fell through the cracks of a single-byte "
898                          "extended opcode");
899       case X86Local::MRM0r:
900       case X86Local::MRM1r:
901       case X86Local::MRM2r:
902       case X86Local::MRM3r:
903       case X86Local::MRM4r:
904       case X86Local::MRM5r:
905       case X86Local::MRM6r:
906       case X86Local::MRM7r:
907         filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
908         break;
909       case X86Local::MRM0m:
910       case X86Local::MRM1m:
911       case X86Local::MRM2m:
912       case X86Local::MRM3m:
913       case X86Local::MRM4m:
914       case X86Local::MRM5m:
915       case X86Local::MRM6m:
916       case X86Local::MRM7m:
917         filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
918         break;
919       MRM_MAPPING
920       } // switch (Form)
921       break;
922     case 0xd8:
923     case 0xd9:
924     case 0xda:
925     case 0xdb:
926     case 0xdc:
927     case 0xdd:
928     case 0xde:
929     case 0xdf:
930       filter = new EscapeFilter(false, Form - X86Local::MRM0m);
931       break;
932     default:
933       if (needsModRMForDecode(Form))
934         filter = new ModFilter(isRegFormat(Form));
935       else
936         filter = new DumbFilter();
937       break;
938     } // switch (Opcode)
939     opcodeToSet = Opcode;
940   } // switch (Prefix)
941 
942   assert(opcodeType != (OpcodeType)-1 &&
943          "Opcode type not set");
944   assert(filter && "Filter not set");
945 
946   if (Form == X86Local::AddRegFrm) {
947     if(Spec->modifierType != MODIFIER_MODRM) {
948       assert(opcodeToSet < 0xf9 &&
949              "Not enough room for all ADDREG_FRM operands");
950 
951       uint8_t currentOpcode;
952 
953       for (currentOpcode = opcodeToSet;
954            currentOpcode < opcodeToSet + 8;
955            ++currentOpcode)
956         tables.setTableFields(opcodeType,
957                               insnContext(),
958                               currentOpcode,
959                               *filter,
960                               UID, Is32Bit);
961 
962       Spec->modifierType = MODIFIER_OPCODE;
963       Spec->modifierBase = opcodeToSet;
964     } else {
965       // modifierBase was set where MODIFIER_MODRM was set
966       tables.setTableFields(opcodeType,
967                             insnContext(),
968                             opcodeToSet,
969                             *filter,
970                             UID, Is32Bit);
971     }
972   } else {
973     tables.setTableFields(opcodeType,
974                           insnContext(),
975                           opcodeToSet,
976                           *filter,
977                           UID, Is32Bit);
978 
979     Spec->modifierType = MODIFIER_NONE;
980     Spec->modifierBase = opcodeToSet;
981   }
982 
983   delete filter;
984 
985 #undef MAP
986 }
987 
988 #define TYPE(str, type) if (s == str) return type;
989 OperandType RecognizableInstr::typeFromString(const std::string &s,
990                                               bool isSSE,
991                                               bool hasREX_WPrefix,
992                                               bool hasOpSizePrefix) {
993   if (isSSE) {
994     // For SSE instructions, we ignore the OpSize prefix and force operand
995     // sizes.
996     TYPE("GR16",              TYPE_R16)
997     TYPE("GR32",              TYPE_R32)
998     TYPE("GR64",              TYPE_R64)
999   }
1000   if(hasREX_WPrefix) {
1001     // For instructions with a REX_W prefix, a declared 32-bit register encoding
1002     // is special.
1003     TYPE("GR32",              TYPE_R32)
1004   }
1005   if(!hasOpSizePrefix) {
1006     // For instructions without an OpSize prefix, a declared 16-bit register or
1007     // immediate encoding is special.
1008     TYPE("GR16",              TYPE_R16)
1009     TYPE("i16imm",            TYPE_IMM16)
1010   }
1011   TYPE("i16mem",              TYPE_Mv)
1012   TYPE("i16imm",              TYPE_IMMv)
1013   TYPE("i16i8imm",            TYPE_IMMv)
1014   TYPE("GR16",                TYPE_Rv)
1015   TYPE("i32mem",              TYPE_Mv)
1016   TYPE("i32imm",              TYPE_IMMv)
1017   TYPE("i32i8imm",            TYPE_IMM32)
1018   TYPE("u32u8imm",            TYPE_IMM32)
1019   TYPE("GR32",                TYPE_Rv)
1020   TYPE("i64mem",              TYPE_Mv)
1021   TYPE("i64i32imm",           TYPE_IMM64)
1022   TYPE("i64i8imm",            TYPE_IMM64)
1023   TYPE("GR64",                TYPE_R64)
1024   TYPE("i8mem",               TYPE_M8)
1025   TYPE("i8imm",               TYPE_IMM8)
1026   TYPE("GR8",                 TYPE_R8)
1027   TYPE("VR128",               TYPE_XMM128)
1028   TYPE("f128mem",             TYPE_M128)
1029   TYPE("f256mem",             TYPE_M256)
1030   TYPE("FR64",                TYPE_XMM64)
1031   TYPE("f64mem",              TYPE_M64FP)
1032   TYPE("sdmem",               TYPE_M64FP)
1033   TYPE("FR32",                TYPE_XMM32)
1034   TYPE("f32mem",              TYPE_M32FP)
1035   TYPE("ssmem",               TYPE_M32FP)
1036   TYPE("RST",                 TYPE_ST)
1037   TYPE("i128mem",             TYPE_M128)
1038   TYPE("i256mem",             TYPE_M256)
1039   TYPE("i64i32imm_pcrel",     TYPE_REL64)
1040   TYPE("i16imm_pcrel",        TYPE_REL16)
1041   TYPE("i32imm_pcrel",        TYPE_REL32)
1042   TYPE("SSECC",               TYPE_IMM3)
1043   TYPE("brtarget",            TYPE_RELv)
1044   TYPE("uncondbrtarget",      TYPE_RELv)
1045   TYPE("brtarget8",           TYPE_REL8)
1046   TYPE("f80mem",              TYPE_M80FP)
1047   TYPE("lea32mem",            TYPE_LEA)
1048   TYPE("lea64_32mem",         TYPE_LEA)
1049   TYPE("lea64mem",            TYPE_LEA)
1050   TYPE("VR64",                TYPE_MM64)
1051   TYPE("i64imm",              TYPE_IMMv)
1052   TYPE("opaque32mem",         TYPE_M1616)
1053   TYPE("opaque48mem",         TYPE_M1632)
1054   TYPE("opaque80mem",         TYPE_M1664)
1055   TYPE("opaque512mem",        TYPE_M512)
1056   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1057   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1058   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1059   TYPE("offset8",             TYPE_MOFFS8)
1060   TYPE("offset16",            TYPE_MOFFS16)
1061   TYPE("offset32",            TYPE_MOFFS32)
1062   TYPE("offset64",            TYPE_MOFFS64)
1063   TYPE("VR256",               TYPE_XMM256)
1064   errs() << "Unhandled type string " << s << "\n";
1065   llvm_unreachable("Unhandled type string");
1066 }
1067 #undef TYPE
1068 
1069 #define ENCODING(str, encoding) if (s == str) return encoding;
1070 OperandEncoding RecognizableInstr::immediateEncodingFromString
1071   (const std::string &s,
1072    bool hasOpSizePrefix) {
1073   if(!hasOpSizePrefix) {
1074     // For instructions without an OpSize prefix, a declared 16-bit register or
1075     // immediate encoding is special.
1076     ENCODING("i16imm",        ENCODING_IW)
1077   }
1078   ENCODING("i32i8imm",        ENCODING_IB)
1079   ENCODING("u32u8imm",        ENCODING_IB)
1080   ENCODING("SSECC",           ENCODING_IB)
1081   ENCODING("i16imm",          ENCODING_Iv)
1082   ENCODING("i16i8imm",        ENCODING_IB)
1083   ENCODING("i32imm",          ENCODING_Iv)
1084   ENCODING("i64i32imm",       ENCODING_ID)
1085   ENCODING("i64i8imm",        ENCODING_IB)
1086   ENCODING("i8imm",           ENCODING_IB)
1087   // This is not a typo.  Instructions like BLENDVPD put
1088   // register IDs in 8-bit immediates nowadays.
1089   ENCODING("VR256",           ENCODING_IB)
1090   ENCODING("VR128",           ENCODING_IB)
1091   errs() << "Unhandled immediate encoding " << s << "\n";
1092   llvm_unreachable("Unhandled immediate encoding");
1093 }
1094 
1095 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1096   (const std::string &s,
1097    bool hasOpSizePrefix) {
1098   ENCODING("GR16",            ENCODING_RM)
1099   ENCODING("GR32",            ENCODING_RM)
1100   ENCODING("GR64",            ENCODING_RM)
1101   ENCODING("GR8",             ENCODING_RM)
1102   ENCODING("VR128",           ENCODING_RM)
1103   ENCODING("FR64",            ENCODING_RM)
1104   ENCODING("FR32",            ENCODING_RM)
1105   ENCODING("VR64",            ENCODING_RM)
1106   ENCODING("VR256",           ENCODING_RM)
1107   errs() << "Unhandled R/M register encoding " << s << "\n";
1108   llvm_unreachable("Unhandled R/M register encoding");
1109 }
1110 
1111 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1112   (const std::string &s,
1113    bool hasOpSizePrefix) {
1114   ENCODING("GR16",            ENCODING_REG)
1115   ENCODING("GR32",            ENCODING_REG)
1116   ENCODING("GR64",            ENCODING_REG)
1117   ENCODING("GR8",             ENCODING_REG)
1118   ENCODING("VR128",           ENCODING_REG)
1119   ENCODING("FR64",            ENCODING_REG)
1120   ENCODING("FR32",            ENCODING_REG)
1121   ENCODING("VR64",            ENCODING_REG)
1122   ENCODING("SEGMENT_REG",     ENCODING_REG)
1123   ENCODING("DEBUG_REG",       ENCODING_REG)
1124   ENCODING("CONTROL_REG",     ENCODING_REG)
1125   ENCODING("VR256",           ENCODING_REG)
1126   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1127   llvm_unreachable("Unhandled reg/opcode register encoding");
1128 }
1129 
1130 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1131   (const std::string &s,
1132    bool hasOpSizePrefix) {
1133   ENCODING("FR32",            ENCODING_VVVV)
1134   ENCODING("FR64",            ENCODING_VVVV)
1135   ENCODING("VR128",           ENCODING_VVVV)
1136   ENCODING("VR256",           ENCODING_VVVV)
1137   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1138   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1139 }
1140 
1141 OperandEncoding RecognizableInstr::memoryEncodingFromString
1142   (const std::string &s,
1143    bool hasOpSizePrefix) {
1144   ENCODING("i16mem",          ENCODING_RM)
1145   ENCODING("i32mem",          ENCODING_RM)
1146   ENCODING("i64mem",          ENCODING_RM)
1147   ENCODING("i8mem",           ENCODING_RM)
1148   ENCODING("ssmem",           ENCODING_RM)
1149   ENCODING("sdmem",           ENCODING_RM)
1150   ENCODING("f128mem",         ENCODING_RM)
1151   ENCODING("f256mem",         ENCODING_RM)
1152   ENCODING("f64mem",          ENCODING_RM)
1153   ENCODING("f32mem",          ENCODING_RM)
1154   ENCODING("i128mem",         ENCODING_RM)
1155   ENCODING("i256mem",         ENCODING_RM)
1156   ENCODING("f80mem",          ENCODING_RM)
1157   ENCODING("lea32mem",        ENCODING_RM)
1158   ENCODING("lea64_32mem",     ENCODING_RM)
1159   ENCODING("lea64mem",        ENCODING_RM)
1160   ENCODING("opaque32mem",     ENCODING_RM)
1161   ENCODING("opaque48mem",     ENCODING_RM)
1162   ENCODING("opaque80mem",     ENCODING_RM)
1163   ENCODING("opaque512mem",    ENCODING_RM)
1164   errs() << "Unhandled memory encoding " << s << "\n";
1165   llvm_unreachable("Unhandled memory encoding");
1166 }
1167 
1168 OperandEncoding RecognizableInstr::relocationEncodingFromString
1169   (const std::string &s,
1170    bool hasOpSizePrefix) {
1171   if(!hasOpSizePrefix) {
1172     // For instructions without an OpSize prefix, a declared 16-bit register or
1173     // immediate encoding is special.
1174     ENCODING("i16imm",        ENCODING_IW)
1175   }
1176   ENCODING("i16imm",          ENCODING_Iv)
1177   ENCODING("i16i8imm",        ENCODING_IB)
1178   ENCODING("i32imm",          ENCODING_Iv)
1179   ENCODING("i32i8imm",        ENCODING_IB)
1180   ENCODING("i64i32imm",       ENCODING_ID)
1181   ENCODING("i64i8imm",        ENCODING_IB)
1182   ENCODING("i8imm",           ENCODING_IB)
1183   ENCODING("i64i32imm_pcrel", ENCODING_ID)
1184   ENCODING("i16imm_pcrel",    ENCODING_IW)
1185   ENCODING("i32imm_pcrel",    ENCODING_ID)
1186   ENCODING("brtarget",        ENCODING_Iv)
1187   ENCODING("brtarget8",       ENCODING_IB)
1188   ENCODING("i64imm",          ENCODING_IO)
1189   ENCODING("offset8",         ENCODING_Ia)
1190   ENCODING("offset16",        ENCODING_Ia)
1191   ENCODING("offset32",        ENCODING_Ia)
1192   ENCODING("offset64",        ENCODING_Ia)
1193   errs() << "Unhandled relocation encoding " << s << "\n";
1194   llvm_unreachable("Unhandled relocation encoding");
1195 }
1196 
1197 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1198   (const std::string &s,
1199    bool hasOpSizePrefix) {
1200   ENCODING("RST",             ENCODING_I)
1201   ENCODING("GR32",            ENCODING_Rv)
1202   ENCODING("GR64",            ENCODING_RO)
1203   ENCODING("GR16",            ENCODING_Rv)
1204   ENCODING("GR8",             ENCODING_RB)
1205   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1206   llvm_unreachable("Unhandled opcode modifier encoding");
1207 }
1208 #undef ENCODING
1209