1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 using namespace X86Disassembler; 25 26 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 27 /// Useful for switch statements and the like. 28 /// 29 /// @param init - A reference to the BitsInit to be decoded. 30 /// @return - The field, with the first bit in the BitsInit as the lowest 31 /// order bit. 32 static uint8_t byteFromBitsInit(BitsInit &init) { 33 int width = init.getNumBits(); 34 35 assert(width <= 8 && "Field is too large for uint8_t!"); 36 37 int index; 38 uint8_t mask = 0x01; 39 40 uint8_t ret = 0; 41 42 for (index = 0; index < width; index++) { 43 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 44 ret |= mask; 45 46 mask <<= 1; 47 } 48 49 return ret; 50 } 51 52 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 53 /// name of the field. 54 /// 55 /// @param rec - The record from which to extract the value. 56 /// @param name - The name of the field in the record. 57 /// @return - The field, as translated by byteFromBitsInit(). 58 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 59 BitsInit* bits = rec->getValueAsBitsInit(name); 60 return byteFromBitsInit(*bits); 61 } 62 63 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 64 const CodeGenInstruction &insn, 65 InstrUID uid) { 66 UID = uid; 67 68 Rec = insn.TheDef; 69 Name = Rec->getName(); 70 Spec = &tables.specForUID(UID); 71 72 if (!Rec->isSubClassOf("X86Inst")) { 73 ShouldBeEmitted = false; 74 return; 75 } 76 77 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 78 OpMap = byteFromRec(Rec, "OpMapBits"); 79 Opcode = byteFromRec(Rec, "Opcode"); 80 Form = byteFromRec(Rec, "FormBits"); 81 Encoding = byteFromRec(Rec, "OpEncBits"); 82 83 OpSize = byteFromRec(Rec, "OpSizeBits"); 84 AdSize = byteFromRec(Rec, "AdSizeBits"); 85 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 86 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 87 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 95 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 96 97 Name = Rec->getName(); 98 99 Operands = &insn.Operands.OperandList; 100 101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 102 103 // Check for 64-bit inst which does not require REX 104 Is32Bit = false; 105 Is64Bit = false; 106 // FIXME: Is there some better way to check for In64BitMode? 107 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 108 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 109 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 110 Predicates[i]->getName().find("In32Bit") != Name.npos) { 111 Is32Bit = true; 112 break; 113 } 114 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 115 Is64Bit = true; 116 break; 117 } 118 } 119 120 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 121 ShouldBeEmitted = false; 122 return; 123 } 124 125 // Special case since there is no attribute class for 64-bit and VEX 126 if (Name == "VMASKMOVDQU64") { 127 ShouldBeEmitted = false; 128 return; 129 } 130 131 ShouldBeEmitted = true; 132 } 133 134 void RecognizableInstr::processInstr(DisassemblerTables &tables, 135 const CodeGenInstruction &insn, 136 InstrUID uid) 137 { 138 // Ignore "asm parser only" instructions. 139 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 140 return; 141 142 RecognizableInstr recogInstr(tables, insn, uid); 143 144 if (recogInstr.shouldBeEmitted()) { 145 recogInstr.emitInstructionSpecifier(); 146 recogInstr.emitDecodePath(tables); 147 } 148 } 149 150 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 151 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 152 (HasEVEX_KZ ? n##_KZ : \ 153 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 154 155 InstructionContext RecognizableInstr::insnContext() const { 156 InstructionContext insnContext; 157 158 if (Encoding == X86Local::EVEX) { 159 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 160 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 161 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 162 } 163 // VEX_L & VEX_W 164 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 165 if (OpPrefix == X86Local::PD) 166 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 167 else if (OpPrefix == X86Local::XS) 168 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 169 else if (OpPrefix == X86Local::XD) 170 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 171 else if (OpPrefix == X86Local::PS) 172 insnContext = EVEX_KB(IC_EVEX_L_W); 173 else { 174 errs() << "Instruction does not use a prefix: " << Name << "\n"; 175 llvm_unreachable("Invalid prefix"); 176 } 177 } else if (HasVEX_LPrefix) { 178 // VEX_L 179 if (OpPrefix == X86Local::PD) 180 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 181 else if (OpPrefix == X86Local::XS) 182 insnContext = EVEX_KB(IC_EVEX_L_XS); 183 else if (OpPrefix == X86Local::XD) 184 insnContext = EVEX_KB(IC_EVEX_L_XD); 185 else if (OpPrefix == X86Local::PS) 186 insnContext = EVEX_KB(IC_EVEX_L); 187 else { 188 errs() << "Instruction does not use a prefix: " << Name << "\n"; 189 llvm_unreachable("Invalid prefix"); 190 } 191 } 192 else if (HasEVEX_L2Prefix && VEX_WPrefix == X86Local::VEX_W1) { 193 // EVEX_L2 & VEX_W 194 if (OpPrefix == X86Local::PD) 195 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 196 else if (OpPrefix == X86Local::XS) 197 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 198 else if (OpPrefix == X86Local::XD) 199 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 200 else if (OpPrefix == X86Local::PS) 201 insnContext = EVEX_KB(IC_EVEX_L2_W); 202 else { 203 errs() << "Instruction does not use a prefix: " << Name << "\n"; 204 llvm_unreachable("Invalid prefix"); 205 } 206 } else if (HasEVEX_L2Prefix) { 207 // EVEX_L2 208 if (OpPrefix == X86Local::PD) 209 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 210 else if (OpPrefix == X86Local::XD) 211 insnContext = EVEX_KB(IC_EVEX_L2_XD); 212 else if (OpPrefix == X86Local::XS) 213 insnContext = EVEX_KB(IC_EVEX_L2_XS); 214 else if (OpPrefix == X86Local::PS) 215 insnContext = EVEX_KB(IC_EVEX_L2); 216 else { 217 errs() << "Instruction does not use a prefix: " << Name << "\n"; 218 llvm_unreachable("Invalid prefix"); 219 } 220 } 221 else if (VEX_WPrefix == X86Local::VEX_W1) { 222 // VEX_W 223 if (OpPrefix == X86Local::PD) 224 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 225 else if (OpPrefix == X86Local::XS) 226 insnContext = EVEX_KB(IC_EVEX_W_XS); 227 else if (OpPrefix == X86Local::XD) 228 insnContext = EVEX_KB(IC_EVEX_W_XD); 229 else if (OpPrefix == X86Local::PS) 230 insnContext = EVEX_KB(IC_EVEX_W); 231 else { 232 errs() << "Instruction does not use a prefix: " << Name << "\n"; 233 llvm_unreachable("Invalid prefix"); 234 } 235 } 236 // No L, no W 237 else if (OpPrefix == X86Local::PD) 238 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 239 else if (OpPrefix == X86Local::XD) 240 insnContext = EVEX_KB(IC_EVEX_XD); 241 else if (OpPrefix == X86Local::XS) 242 insnContext = EVEX_KB(IC_EVEX_XS); 243 else 244 insnContext = EVEX_KB(IC_EVEX); 245 /// eof EVEX 246 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 247 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 248 if (OpPrefix == X86Local::PD) 249 insnContext = IC_VEX_L_W_OPSIZE; 250 else if (OpPrefix == X86Local::XS) 251 insnContext = IC_VEX_L_W_XS; 252 else if (OpPrefix == X86Local::XD) 253 insnContext = IC_VEX_L_W_XD; 254 else if (OpPrefix == X86Local::PS) 255 insnContext = IC_VEX_L_W; 256 else { 257 errs() << "Instruction does not use a prefix: " << Name << "\n"; 258 llvm_unreachable("Invalid prefix"); 259 } 260 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 261 insnContext = IC_VEX_L_OPSIZE; 262 else if (OpPrefix == X86Local::PD && VEX_WPrefix == X86Local::VEX_W1) 263 insnContext = IC_VEX_W_OPSIZE; 264 else if (OpPrefix == X86Local::PD) 265 insnContext = IC_VEX_OPSIZE; 266 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 267 insnContext = IC_VEX_L_XS; 268 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 269 insnContext = IC_VEX_L_XD; 270 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XS) 271 insnContext = IC_VEX_W_XS; 272 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XD) 273 insnContext = IC_VEX_W_XD; 274 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::PS) 275 insnContext = IC_VEX_W; 276 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 277 insnContext = IC_VEX_L; 278 else if (OpPrefix == X86Local::XD) 279 insnContext = IC_VEX_XD; 280 else if (OpPrefix == X86Local::XS) 281 insnContext = IC_VEX_XS; 282 else if (OpPrefix == X86Local::PS) 283 insnContext = IC_VEX; 284 else { 285 errs() << "Instruction does not use a prefix: " << Name << "\n"; 286 llvm_unreachable("Invalid prefix"); 287 } 288 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 289 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 290 insnContext = IC_64BIT_REXW_OPSIZE; 291 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 292 insnContext = IC_64BIT_REXW_ADSIZE; 293 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 294 insnContext = IC_64BIT_XD_OPSIZE; 295 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 296 insnContext = IC_64BIT_XS_OPSIZE; 297 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 298 insnContext = IC_64BIT_OPSIZE_ADSIZE; 299 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 300 insnContext = IC_64BIT_OPSIZE; 301 else if (AdSize == X86Local::AdSize32) 302 insnContext = IC_64BIT_ADSIZE; 303 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 304 insnContext = IC_64BIT_REXW_XS; 305 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 306 insnContext = IC_64BIT_REXW_XD; 307 else if (OpPrefix == X86Local::XD) 308 insnContext = IC_64BIT_XD; 309 else if (OpPrefix == X86Local::XS) 310 insnContext = IC_64BIT_XS; 311 else if (HasREX_WPrefix) 312 insnContext = IC_64BIT_REXW; 313 else 314 insnContext = IC_64BIT; 315 } else { 316 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 317 insnContext = IC_XD_OPSIZE; 318 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 319 insnContext = IC_XS_OPSIZE; 320 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 321 insnContext = IC_OPSIZE_ADSIZE; 322 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 323 insnContext = IC_OPSIZE; 324 else if (AdSize == X86Local::AdSize16) 325 insnContext = IC_ADSIZE; 326 else if (OpPrefix == X86Local::XD) 327 insnContext = IC_XD; 328 else if (OpPrefix == X86Local::XS) 329 insnContext = IC_XS; 330 else 331 insnContext = IC; 332 } 333 334 return insnContext; 335 } 336 337 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 338 // The scaling factor for AVX512 compressed displacement encoding is an 339 // instruction attribute. Adjust the ModRM encoding type to include the 340 // scale for compressed displacement. 341 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 342 return; 343 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 344 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 345 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 346 "Invalid CDisp scaling"); 347 } 348 349 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 350 unsigned &physicalOperandIndex, 351 unsigned numPhysicalOperands, 352 const unsigned *operandMapping, 353 OperandEncoding (*encodingFromString) 354 (const std::string&, 355 uint8_t OpSize)) { 356 if (optional) { 357 if (physicalOperandIndex >= numPhysicalOperands) 358 return; 359 } else { 360 assert(physicalOperandIndex < numPhysicalOperands); 361 } 362 363 while (operandMapping[operandIndex] != operandIndex) { 364 Spec->operands[operandIndex].encoding = ENCODING_DUP; 365 Spec->operands[operandIndex].type = 366 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 367 ++operandIndex; 368 } 369 370 const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); 371 372 OperandEncoding encoding = encodingFromString(typeName, OpSize); 373 // Adjust the encoding type for an operand based on the instruction. 374 adjustOperandEncoding(encoding); 375 Spec->operands[operandIndex].encoding = encoding; 376 Spec->operands[operandIndex].type = typeFromString(typeName, 377 HasREX_WPrefix, OpSize); 378 379 ++operandIndex; 380 ++physicalOperandIndex; 381 } 382 383 void RecognizableInstr::emitInstructionSpecifier() { 384 Spec->name = Name; 385 386 Spec->insnContext = insnContext(); 387 388 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 389 390 unsigned numOperands = OperandList.size(); 391 unsigned numPhysicalOperands = 0; 392 393 // operandMapping maps from operands in OperandList to their originals. 394 // If operandMapping[i] != i, then the entry is a duplicate. 395 unsigned operandMapping[X86_MAX_OPERANDS]; 396 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 397 398 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 399 if (!OperandList[operandIndex].Constraints.empty()) { 400 const CGIOperandList::ConstraintInfo &Constraint = 401 OperandList[operandIndex].Constraints[0]; 402 if (Constraint.isTied()) { 403 operandMapping[operandIndex] = operandIndex; 404 operandMapping[Constraint.getTiedOperand()] = operandIndex; 405 } else { 406 ++numPhysicalOperands; 407 operandMapping[operandIndex] = operandIndex; 408 } 409 } else { 410 ++numPhysicalOperands; 411 operandMapping[operandIndex] = operandIndex; 412 } 413 } 414 415 #define HANDLE_OPERAND(class) \ 416 handleOperand(false, \ 417 operandIndex, \ 418 physicalOperandIndex, \ 419 numPhysicalOperands, \ 420 operandMapping, \ 421 class##EncodingFromString); 422 423 #define HANDLE_OPTIONAL(class) \ 424 handleOperand(true, \ 425 operandIndex, \ 426 physicalOperandIndex, \ 427 numPhysicalOperands, \ 428 operandMapping, \ 429 class##EncodingFromString); 430 431 // operandIndex should always be < numOperands 432 unsigned operandIndex = 0; 433 // physicalOperandIndex should always be < numPhysicalOperands 434 unsigned physicalOperandIndex = 0; 435 436 #ifndef NDEBUG 437 // Given the set of prefix bits, how many additional operands does the 438 // instruction have? 439 unsigned additionalOperands = 0; 440 if (HasVEX_4V) 441 ++additionalOperands; 442 if (HasEVEX_K) 443 ++additionalOperands; 444 #endif 445 446 switch (Form) { 447 default: llvm_unreachable("Unhandled form"); 448 case X86Local::RawFrmSrc: 449 HANDLE_OPERAND(relocation); 450 return; 451 case X86Local::RawFrmDst: 452 HANDLE_OPERAND(relocation); 453 return; 454 case X86Local::RawFrmDstSrc: 455 HANDLE_OPERAND(relocation); 456 HANDLE_OPERAND(relocation); 457 return; 458 case X86Local::RawFrm: 459 // Operand 1 (optional) is an address or immediate. 460 assert(numPhysicalOperands <= 1 && 461 "Unexpected number of operands for RawFrm"); 462 HANDLE_OPTIONAL(relocation) 463 break; 464 case X86Local::RawFrmMemOffs: 465 // Operand 1 is an address. 466 HANDLE_OPERAND(relocation); 467 break; 468 case X86Local::AddRegFrm: 469 // Operand 1 is added to the opcode. 470 // Operand 2 (optional) is an address. 471 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 472 "Unexpected number of operands for AddRegFrm"); 473 HANDLE_OPERAND(opcodeModifier) 474 HANDLE_OPTIONAL(relocation) 475 break; 476 case X86Local::MRMDestReg: 477 // Operand 1 is a register operand in the R/M field. 478 // - In AVX512 there may be a mask operand here - 479 // Operand 2 is a register operand in the Reg/Opcode field. 480 // - In AVX, there is a register operand in the VEX.vvvv field here - 481 // Operand 3 (optional) is an immediate. 482 assert(numPhysicalOperands >= 2 + additionalOperands && 483 numPhysicalOperands <= 3 + additionalOperands && 484 "Unexpected number of operands for MRMDestRegFrm"); 485 486 HANDLE_OPERAND(rmRegister) 487 if (HasEVEX_K) 488 HANDLE_OPERAND(writemaskRegister) 489 490 if (HasVEX_4V) 491 // FIXME: In AVX, the register below becomes the one encoded 492 // in ModRMVEX and the one above the one in the VEX.VVVV field 493 HANDLE_OPERAND(vvvvRegister) 494 495 HANDLE_OPERAND(roRegister) 496 HANDLE_OPTIONAL(immediate) 497 break; 498 case X86Local::MRMDestMem: 499 // Operand 1 is a memory operand (possibly SIB-extended) 500 // Operand 2 is a register operand in the Reg/Opcode field. 501 // - In AVX, there is a register operand in the VEX.vvvv field here - 502 // Operand 3 (optional) is an immediate. 503 assert(numPhysicalOperands >= 2 + additionalOperands && 504 numPhysicalOperands <= 3 + additionalOperands && 505 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 506 507 HANDLE_OPERAND(memory) 508 509 if (HasEVEX_K) 510 HANDLE_OPERAND(writemaskRegister) 511 512 if (HasVEX_4V) 513 // FIXME: In AVX, the register below becomes the one encoded 514 // in ModRMVEX and the one above the one in the VEX.VVVV field 515 HANDLE_OPERAND(vvvvRegister) 516 517 HANDLE_OPERAND(roRegister) 518 HANDLE_OPTIONAL(immediate) 519 break; 520 case X86Local::MRMSrcReg: 521 // Operand 1 is a register operand in the Reg/Opcode field. 522 // Operand 2 is a register operand in the R/M field. 523 // - In AVX, there is a register operand in the VEX.vvvv field here - 524 // Operand 3 (optional) is an immediate. 525 // Operand 4 (optional) is an immediate. 526 527 assert(numPhysicalOperands >= 2 + additionalOperands && 528 numPhysicalOperands <= 4 + additionalOperands && 529 "Unexpected number of operands for MRMSrcRegFrm"); 530 531 HANDLE_OPERAND(roRegister) 532 533 if (HasEVEX_K) 534 HANDLE_OPERAND(writemaskRegister) 535 536 if (HasVEX_4V) 537 // FIXME: In AVX, the register below becomes the one encoded 538 // in ModRMVEX and the one above the one in the VEX.VVVV field 539 HANDLE_OPERAND(vvvvRegister) 540 541 HANDLE_OPERAND(rmRegister) 542 HANDLE_OPTIONAL(immediate) 543 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 544 HANDLE_OPTIONAL(immediate) 545 break; 546 case X86Local::MRMSrcReg4VOp3: 547 assert(numPhysicalOperands == 3 && 548 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 549 HANDLE_OPERAND(roRegister) 550 HANDLE_OPERAND(rmRegister) 551 HANDLE_OPERAND(vvvvRegister) 552 break; 553 case X86Local::MRMSrcRegOp4: 554 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 555 "Unexpected number of operands for MRMSrcRegOp4Frm"); 556 HANDLE_OPERAND(roRegister) 557 HANDLE_OPERAND(vvvvRegister) 558 HANDLE_OPERAND(immediate) // Register in imm[7:4] 559 HANDLE_OPERAND(rmRegister) 560 HANDLE_OPTIONAL(immediate) 561 break; 562 case X86Local::MRMSrcMem: 563 // Operand 1 is a register operand in the Reg/Opcode field. 564 // Operand 2 is a memory operand (possibly SIB-extended) 565 // - In AVX, there is a register operand in the VEX.vvvv field here - 566 // Operand 3 (optional) is an immediate. 567 568 assert(numPhysicalOperands >= 2 + additionalOperands && 569 numPhysicalOperands <= 4 + additionalOperands && 570 "Unexpected number of operands for MRMSrcMemFrm"); 571 572 HANDLE_OPERAND(roRegister) 573 574 if (HasEVEX_K) 575 HANDLE_OPERAND(writemaskRegister) 576 577 if (HasVEX_4V) 578 // FIXME: In AVX, the register below becomes the one encoded 579 // in ModRMVEX and the one above the one in the VEX.VVVV field 580 HANDLE_OPERAND(vvvvRegister) 581 582 HANDLE_OPERAND(memory) 583 HANDLE_OPTIONAL(immediate) 584 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 585 break; 586 case X86Local::MRMSrcMem4VOp3: 587 assert(numPhysicalOperands == 3 && 588 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 589 HANDLE_OPERAND(roRegister) 590 HANDLE_OPERAND(memory) 591 HANDLE_OPERAND(vvvvRegister) 592 break; 593 case X86Local::MRMSrcMemOp4: 594 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 595 "Unexpected number of operands for MRMSrcMemOp4Frm"); 596 HANDLE_OPERAND(roRegister) 597 HANDLE_OPERAND(vvvvRegister) 598 HANDLE_OPERAND(immediate) // Register in imm[7:4] 599 HANDLE_OPERAND(memory) 600 HANDLE_OPTIONAL(immediate) 601 break; 602 case X86Local::MRMXr: 603 case X86Local::MRM0r: 604 case X86Local::MRM1r: 605 case X86Local::MRM2r: 606 case X86Local::MRM3r: 607 case X86Local::MRM4r: 608 case X86Local::MRM5r: 609 case X86Local::MRM6r: 610 case X86Local::MRM7r: 611 // Operand 1 is a register operand in the R/M field. 612 // Operand 2 (optional) is an immediate or relocation. 613 // Operand 3 (optional) is an immediate. 614 assert(numPhysicalOperands >= 0 + additionalOperands && 615 numPhysicalOperands <= 3 + additionalOperands && 616 "Unexpected number of operands for MRMnr"); 617 618 if (HasVEX_4V) 619 HANDLE_OPERAND(vvvvRegister) 620 621 if (HasEVEX_K) 622 HANDLE_OPERAND(writemaskRegister) 623 HANDLE_OPTIONAL(rmRegister) 624 HANDLE_OPTIONAL(relocation) 625 HANDLE_OPTIONAL(immediate) 626 break; 627 case X86Local::MRMXm: 628 case X86Local::MRM0m: 629 case X86Local::MRM1m: 630 case X86Local::MRM2m: 631 case X86Local::MRM3m: 632 case X86Local::MRM4m: 633 case X86Local::MRM5m: 634 case X86Local::MRM6m: 635 case X86Local::MRM7m: 636 // Operand 1 is a memory operand (possibly SIB-extended) 637 // Operand 2 (optional) is an immediate or relocation. 638 assert(numPhysicalOperands >= 1 + additionalOperands && 639 numPhysicalOperands <= 2 + additionalOperands && 640 "Unexpected number of operands for MRMnm"); 641 642 if (HasVEX_4V) 643 HANDLE_OPERAND(vvvvRegister) 644 if (HasEVEX_K) 645 HANDLE_OPERAND(writemaskRegister) 646 HANDLE_OPERAND(memory) 647 HANDLE_OPTIONAL(relocation) 648 break; 649 case X86Local::RawFrmImm8: 650 // operand 1 is a 16-bit immediate 651 // operand 2 is an 8-bit immediate 652 assert(numPhysicalOperands == 2 && 653 "Unexpected number of operands for X86Local::RawFrmImm8"); 654 HANDLE_OPERAND(immediate) 655 HANDLE_OPERAND(immediate) 656 break; 657 case X86Local::RawFrmImm16: 658 // operand 1 is a 16-bit immediate 659 // operand 2 is a 16-bit immediate 660 HANDLE_OPERAND(immediate) 661 HANDLE_OPERAND(immediate) 662 break; 663 case X86Local::MRM_F8: 664 if (Opcode == 0xc6) { 665 assert(numPhysicalOperands == 1 && 666 "Unexpected number of operands for X86Local::MRM_F8"); 667 HANDLE_OPERAND(immediate) 668 } else if (Opcode == 0xc7) { 669 assert(numPhysicalOperands == 1 && 670 "Unexpected number of operands for X86Local::MRM_F8"); 671 HANDLE_OPERAND(relocation) 672 } 673 break; 674 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 675 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 676 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 677 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1: 678 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6: 679 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9: 680 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC: 681 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF: 682 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2: 683 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5: 684 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA: 685 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED: 686 case X86Local::MRM_EE: case X86Local::MRM_EF: case X86Local::MRM_F0: 687 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: 688 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: 689 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: 690 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: 691 case X86Local::MRM_FE: case X86Local::MRM_FF: 692 // Ignored. 693 break; 694 } 695 696 #undef HANDLE_OPERAND 697 #undef HANDLE_OPTIONAL 698 } 699 700 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 701 // Special cases where the LLVM tables are not complete 702 703 #define MAP(from, to) \ 704 case X86Local::MRM_##from: 705 706 OpcodeType opcodeType = (OpcodeType)-1; 707 708 ModRMFilter* filter = nullptr; 709 uint8_t opcodeToSet = 0; 710 711 switch (OpMap) { 712 default: llvm_unreachable("Invalid map!"); 713 case X86Local::OB: 714 case X86Local::TB: 715 case X86Local::T8: 716 case X86Local::TA: 717 case X86Local::XOP8: 718 case X86Local::XOP9: 719 case X86Local::XOPA: 720 switch (OpMap) { 721 default: llvm_unreachable("Unexpected map!"); 722 case X86Local::OB: opcodeType = ONEBYTE; break; 723 case X86Local::TB: opcodeType = TWOBYTE; break; 724 case X86Local::T8: opcodeType = THREEBYTE_38; break; 725 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 726 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 727 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 728 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 729 } 730 731 switch (Form) { 732 default: llvm_unreachable("Invalid form!"); 733 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 734 case X86Local::RawFrm: 735 case X86Local::AddRegFrm: 736 case X86Local::RawFrmMemOffs: 737 case X86Local::RawFrmSrc: 738 case X86Local::RawFrmDst: 739 case X86Local::RawFrmDstSrc: 740 case X86Local::RawFrmImm8: 741 case X86Local::RawFrmImm16: 742 filter = new DumbFilter(); 743 break; 744 case X86Local::MRMDestReg: 745 case X86Local::MRMSrcReg: 746 case X86Local::MRMSrcReg4VOp3: 747 case X86Local::MRMSrcRegOp4: 748 case X86Local::MRMXr: 749 filter = new ModFilter(true); 750 break; 751 case X86Local::MRMDestMem: 752 case X86Local::MRMSrcMem: 753 case X86Local::MRMSrcMem4VOp3: 754 case X86Local::MRMSrcMemOp4: 755 case X86Local::MRMXm: 756 filter = new ModFilter(false); 757 break; 758 case X86Local::MRM0r: case X86Local::MRM1r: 759 case X86Local::MRM2r: case X86Local::MRM3r: 760 case X86Local::MRM4r: case X86Local::MRM5r: 761 case X86Local::MRM6r: case X86Local::MRM7r: 762 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 763 break; 764 case X86Local::MRM0m: case X86Local::MRM1m: 765 case X86Local::MRM2m: case X86Local::MRM3m: 766 case X86Local::MRM4m: case X86Local::MRM5m: 767 case X86Local::MRM6m: case X86Local::MRM7m: 768 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 769 break; 770 X86_INSTR_MRM_MAPPING 771 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \ 772 break; 773 } // switch (Form) 774 775 opcodeToSet = Opcode; 776 break; 777 } // switch (OpMap) 778 779 unsigned AddressSize = 0; 780 switch (AdSize) { 781 case X86Local::AdSize16: AddressSize = 16; break; 782 case X86Local::AdSize32: AddressSize = 32; break; 783 case X86Local::AdSize64: AddressSize = 64; break; 784 } 785 786 assert(opcodeType != (OpcodeType)-1 && 787 "Opcode type not set"); 788 assert(filter && "Filter not set"); 789 790 if (Form == X86Local::AddRegFrm) { 791 assert(((opcodeToSet & 7) == 0) && 792 "ADDREG_FRM opcode not aligned"); 793 794 uint8_t currentOpcode; 795 796 for (currentOpcode = opcodeToSet; 797 currentOpcode < opcodeToSet + 8; 798 ++currentOpcode) 799 tables.setTableFields(opcodeType, 800 insnContext(), 801 currentOpcode, 802 *filter, 803 UID, Is32Bit, IgnoresVEX_L, AddressSize); 804 } else { 805 tables.setTableFields(opcodeType, 806 insnContext(), 807 opcodeToSet, 808 *filter, 809 UID, Is32Bit, IgnoresVEX_L, AddressSize); 810 } 811 812 delete filter; 813 814 #undef MAP 815 } 816 817 #define TYPE(str, type) if (s == str) return type; 818 OperandType RecognizableInstr::typeFromString(const std::string &s, 819 bool hasREX_WPrefix, 820 uint8_t OpSize) { 821 if(hasREX_WPrefix) { 822 // For instructions with a REX_W prefix, a declared 32-bit register encoding 823 // is special. 824 TYPE("GR32", TYPE_R32) 825 } 826 if(OpSize == X86Local::OpSize16) { 827 // For OpSize16 instructions, a declared 16-bit register or 828 // immediate encoding is special. 829 TYPE("GR16", TYPE_Rv) 830 } else if(OpSize == X86Local::OpSize32) { 831 // For OpSize32 instructions, a declared 32-bit register or 832 // immediate encoding is special. 833 TYPE("GR32", TYPE_Rv) 834 } 835 TYPE("i16mem", TYPE_M) 836 TYPE("i16imm", TYPE_IMM) 837 TYPE("i16i8imm", TYPE_IMM) 838 TYPE("GR16", TYPE_R16) 839 TYPE("i32mem", TYPE_M) 840 TYPE("i32imm", TYPE_IMM) 841 TYPE("i32i8imm", TYPE_IMM) 842 TYPE("GR32", TYPE_R32) 843 TYPE("GR32orGR64", TYPE_R32) 844 TYPE("i64mem", TYPE_M) 845 TYPE("i64i32imm", TYPE_IMM) 846 TYPE("i64i8imm", TYPE_IMM) 847 TYPE("GR64", TYPE_R64) 848 TYPE("i8mem", TYPE_M) 849 TYPE("i8imm", TYPE_IMM) 850 TYPE("u8imm", TYPE_UIMM8) 851 TYPE("i32u8imm", TYPE_UIMM8) 852 TYPE("GR8", TYPE_R8) 853 TYPE("VR128", TYPE_XMM) 854 TYPE("VR128X", TYPE_XMM) 855 TYPE("f128mem", TYPE_M) 856 TYPE("f256mem", TYPE_M) 857 TYPE("f512mem", TYPE_M) 858 TYPE("FR128", TYPE_XMM) 859 TYPE("FR64", TYPE_XMM) 860 TYPE("FR64X", TYPE_XMM) 861 TYPE("f64mem", TYPE_M) 862 TYPE("sdmem", TYPE_M) 863 TYPE("FR32", TYPE_XMM) 864 TYPE("FR32X", TYPE_XMM) 865 TYPE("f32mem", TYPE_M) 866 TYPE("ssmem", TYPE_M) 867 TYPE("RST", TYPE_ST) 868 TYPE("i128mem", TYPE_M) 869 TYPE("i256mem", TYPE_M) 870 TYPE("i512mem", TYPE_M) 871 TYPE("i64i32imm_pcrel", TYPE_REL) 872 TYPE("i16imm_pcrel", TYPE_REL) 873 TYPE("i32imm_pcrel", TYPE_REL) 874 TYPE("SSECC", TYPE_IMM3) 875 TYPE("XOPCC", TYPE_IMM3) 876 TYPE("AVXCC", TYPE_IMM5) 877 TYPE("AVX512ICC", TYPE_AVX512ICC) 878 TYPE("AVX512RC", TYPE_IMM) 879 TYPE("brtarget32", TYPE_REL) 880 TYPE("brtarget16", TYPE_REL) 881 TYPE("brtarget8", TYPE_REL) 882 TYPE("f80mem", TYPE_M) 883 TYPE("lea64_32mem", TYPE_M) 884 TYPE("lea64mem", TYPE_M) 885 TYPE("VR64", TYPE_MM64) 886 TYPE("i64imm", TYPE_IMM) 887 TYPE("anymem", TYPE_M) 888 TYPE("opaque32mem", TYPE_M) 889 TYPE("opaque48mem", TYPE_M) 890 TYPE("opaque80mem", TYPE_M) 891 TYPE("opaque512mem", TYPE_M) 892 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 893 TYPE("DEBUG_REG", TYPE_DEBUGREG) 894 TYPE("CONTROL_REG", TYPE_CONTROLREG) 895 TYPE("srcidx8", TYPE_SRCIDX) 896 TYPE("srcidx16", TYPE_SRCIDX) 897 TYPE("srcidx32", TYPE_SRCIDX) 898 TYPE("srcidx64", TYPE_SRCIDX) 899 TYPE("dstidx8", TYPE_DSTIDX) 900 TYPE("dstidx16", TYPE_DSTIDX) 901 TYPE("dstidx32", TYPE_DSTIDX) 902 TYPE("dstidx64", TYPE_DSTIDX) 903 TYPE("offset16_8", TYPE_MOFFS) 904 TYPE("offset16_16", TYPE_MOFFS) 905 TYPE("offset16_32", TYPE_MOFFS) 906 TYPE("offset32_8", TYPE_MOFFS) 907 TYPE("offset32_16", TYPE_MOFFS) 908 TYPE("offset32_32", TYPE_MOFFS) 909 TYPE("offset32_64", TYPE_MOFFS) 910 TYPE("offset64_8", TYPE_MOFFS) 911 TYPE("offset64_16", TYPE_MOFFS) 912 TYPE("offset64_32", TYPE_MOFFS) 913 TYPE("offset64_64", TYPE_MOFFS) 914 TYPE("VR256", TYPE_YMM) 915 TYPE("VR256X", TYPE_YMM) 916 TYPE("VR512", TYPE_ZMM) 917 TYPE("VK1", TYPE_VK) 918 TYPE("VK1WM", TYPE_VK) 919 TYPE("VK2", TYPE_VK) 920 TYPE("VK2WM", TYPE_VK) 921 TYPE("VK4", TYPE_VK) 922 TYPE("VK4WM", TYPE_VK) 923 TYPE("VK8", TYPE_VK) 924 TYPE("VK8WM", TYPE_VK) 925 TYPE("VK16", TYPE_VK) 926 TYPE("VK16WM", TYPE_VK) 927 TYPE("VK32", TYPE_VK) 928 TYPE("VK32WM", TYPE_VK) 929 TYPE("VK64", TYPE_VK) 930 TYPE("VK64WM", TYPE_VK) 931 TYPE("GR32_NOAX", TYPE_Rv) 932 TYPE("vx64mem", TYPE_M) 933 TYPE("vx128mem", TYPE_M) 934 TYPE("vx256mem", TYPE_M) 935 TYPE("vy128mem", TYPE_M) 936 TYPE("vy256mem", TYPE_M) 937 TYPE("vx64xmem", TYPE_M) 938 TYPE("vx128xmem", TYPE_M) 939 TYPE("vx256xmem", TYPE_M) 940 TYPE("vy128xmem", TYPE_M) 941 TYPE("vy256xmem", TYPE_M) 942 TYPE("vy512mem", TYPE_M) 943 TYPE("vz256xmem", TYPE_M) 944 TYPE("vz512mem", TYPE_M) 945 TYPE("BNDR", TYPE_BNDR) 946 errs() << "Unhandled type string " << s << "\n"; 947 llvm_unreachable("Unhandled type string"); 948 } 949 #undef TYPE 950 951 #define ENCODING(str, encoding) if (s == str) return encoding; 952 OperandEncoding 953 RecognizableInstr::immediateEncodingFromString(const std::string &s, 954 uint8_t OpSize) { 955 if(OpSize != X86Local::OpSize16) { 956 // For instructions without an OpSize prefix, a declared 16-bit register or 957 // immediate encoding is special. 958 ENCODING("i16imm", ENCODING_IW) 959 } 960 ENCODING("i32i8imm", ENCODING_IB) 961 ENCODING("SSECC", ENCODING_IB) 962 ENCODING("XOPCC", ENCODING_IB) 963 ENCODING("AVXCC", ENCODING_IB) 964 ENCODING("AVX512ICC", ENCODING_IB) 965 ENCODING("AVX512RC", ENCODING_IB) 966 ENCODING("i16imm", ENCODING_Iv) 967 ENCODING("i16i8imm", ENCODING_IB) 968 ENCODING("i32imm", ENCODING_Iv) 969 ENCODING("i64i32imm", ENCODING_ID) 970 ENCODING("i64i8imm", ENCODING_IB) 971 ENCODING("i8imm", ENCODING_IB) 972 ENCODING("u8imm", ENCODING_IB) 973 ENCODING("i32u8imm", ENCODING_IB) 974 // This is not a typo. Instructions like BLENDVPD put 975 // register IDs in 8-bit immediates nowadays. 976 ENCODING("FR32", ENCODING_IB) 977 ENCODING("FR64", ENCODING_IB) 978 ENCODING("FR128", ENCODING_IB) 979 ENCODING("VR128", ENCODING_IB) 980 ENCODING("VR256", ENCODING_IB) 981 ENCODING("FR32X", ENCODING_IB) 982 ENCODING("FR64X", ENCODING_IB) 983 ENCODING("VR128X", ENCODING_IB) 984 ENCODING("VR256X", ENCODING_IB) 985 ENCODING("VR512", ENCODING_IB) 986 errs() << "Unhandled immediate encoding " << s << "\n"; 987 llvm_unreachable("Unhandled immediate encoding"); 988 } 989 990 OperandEncoding 991 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 992 uint8_t OpSize) { 993 ENCODING("RST", ENCODING_FP) 994 ENCODING("GR16", ENCODING_RM) 995 ENCODING("GR32", ENCODING_RM) 996 ENCODING("GR32orGR64", ENCODING_RM) 997 ENCODING("GR64", ENCODING_RM) 998 ENCODING("GR8", ENCODING_RM) 999 ENCODING("VR128", ENCODING_RM) 1000 ENCODING("VR128X", ENCODING_RM) 1001 ENCODING("FR128", ENCODING_RM) 1002 ENCODING("FR64", ENCODING_RM) 1003 ENCODING("FR32", ENCODING_RM) 1004 ENCODING("FR64X", ENCODING_RM) 1005 ENCODING("FR32X", ENCODING_RM) 1006 ENCODING("VR64", ENCODING_RM) 1007 ENCODING("VR256", ENCODING_RM) 1008 ENCODING("VR256X", ENCODING_RM) 1009 ENCODING("VR512", ENCODING_RM) 1010 ENCODING("VK1", ENCODING_RM) 1011 ENCODING("VK2", ENCODING_RM) 1012 ENCODING("VK4", ENCODING_RM) 1013 ENCODING("VK8", ENCODING_RM) 1014 ENCODING("VK16", ENCODING_RM) 1015 ENCODING("VK32", ENCODING_RM) 1016 ENCODING("VK64", ENCODING_RM) 1017 ENCODING("BNDR", ENCODING_RM) 1018 errs() << "Unhandled R/M register encoding " << s << "\n"; 1019 llvm_unreachable("Unhandled R/M register encoding"); 1020 } 1021 1022 OperandEncoding 1023 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1024 uint8_t OpSize) { 1025 ENCODING("GR16", ENCODING_REG) 1026 ENCODING("GR32", ENCODING_REG) 1027 ENCODING("GR32orGR64", ENCODING_REG) 1028 ENCODING("GR64", ENCODING_REG) 1029 ENCODING("GR8", ENCODING_REG) 1030 ENCODING("VR128", ENCODING_REG) 1031 ENCODING("FR128", ENCODING_REG) 1032 ENCODING("FR64", ENCODING_REG) 1033 ENCODING("FR32", ENCODING_REG) 1034 ENCODING("VR64", ENCODING_REG) 1035 ENCODING("SEGMENT_REG", ENCODING_REG) 1036 ENCODING("DEBUG_REG", ENCODING_REG) 1037 ENCODING("CONTROL_REG", ENCODING_REG) 1038 ENCODING("VR256", ENCODING_REG) 1039 ENCODING("VR256X", ENCODING_REG) 1040 ENCODING("VR128X", ENCODING_REG) 1041 ENCODING("FR64X", ENCODING_REG) 1042 ENCODING("FR32X", ENCODING_REG) 1043 ENCODING("VR512", ENCODING_REG) 1044 ENCODING("VK1", ENCODING_REG) 1045 ENCODING("VK2", ENCODING_REG) 1046 ENCODING("VK4", ENCODING_REG) 1047 ENCODING("VK8", ENCODING_REG) 1048 ENCODING("VK16", ENCODING_REG) 1049 ENCODING("VK32", ENCODING_REG) 1050 ENCODING("VK64", ENCODING_REG) 1051 ENCODING("VK1WM", ENCODING_REG) 1052 ENCODING("VK2WM", ENCODING_REG) 1053 ENCODING("VK4WM", ENCODING_REG) 1054 ENCODING("VK8WM", ENCODING_REG) 1055 ENCODING("VK16WM", ENCODING_REG) 1056 ENCODING("VK32WM", ENCODING_REG) 1057 ENCODING("VK64WM", ENCODING_REG) 1058 ENCODING("BNDR", ENCODING_REG) 1059 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1060 llvm_unreachable("Unhandled reg/opcode register encoding"); 1061 } 1062 1063 OperandEncoding 1064 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1065 uint8_t OpSize) { 1066 ENCODING("GR32", ENCODING_VVVV) 1067 ENCODING("GR64", ENCODING_VVVV) 1068 ENCODING("FR32", ENCODING_VVVV) 1069 ENCODING("FR128", ENCODING_VVVV) 1070 ENCODING("FR64", ENCODING_VVVV) 1071 ENCODING("VR128", ENCODING_VVVV) 1072 ENCODING("VR256", ENCODING_VVVV) 1073 ENCODING("FR32X", ENCODING_VVVV) 1074 ENCODING("FR64X", ENCODING_VVVV) 1075 ENCODING("VR128X", ENCODING_VVVV) 1076 ENCODING("VR256X", ENCODING_VVVV) 1077 ENCODING("VR512", ENCODING_VVVV) 1078 ENCODING("VK1", ENCODING_VVVV) 1079 ENCODING("VK2", ENCODING_VVVV) 1080 ENCODING("VK4", ENCODING_VVVV) 1081 ENCODING("VK8", ENCODING_VVVV) 1082 ENCODING("VK16", ENCODING_VVVV) 1083 ENCODING("VK32", ENCODING_VVVV) 1084 ENCODING("VK64", ENCODING_VVVV) 1085 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1086 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1087 } 1088 1089 OperandEncoding 1090 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1091 uint8_t OpSize) { 1092 ENCODING("VK1WM", ENCODING_WRITEMASK) 1093 ENCODING("VK2WM", ENCODING_WRITEMASK) 1094 ENCODING("VK4WM", ENCODING_WRITEMASK) 1095 ENCODING("VK8WM", ENCODING_WRITEMASK) 1096 ENCODING("VK16WM", ENCODING_WRITEMASK) 1097 ENCODING("VK32WM", ENCODING_WRITEMASK) 1098 ENCODING("VK64WM", ENCODING_WRITEMASK) 1099 errs() << "Unhandled mask register encoding " << s << "\n"; 1100 llvm_unreachable("Unhandled mask register encoding"); 1101 } 1102 1103 OperandEncoding 1104 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1105 uint8_t OpSize) { 1106 ENCODING("i16mem", ENCODING_RM) 1107 ENCODING("i32mem", ENCODING_RM) 1108 ENCODING("i64mem", ENCODING_RM) 1109 ENCODING("i8mem", ENCODING_RM) 1110 ENCODING("ssmem", ENCODING_RM) 1111 ENCODING("sdmem", ENCODING_RM) 1112 ENCODING("f128mem", ENCODING_RM) 1113 ENCODING("f256mem", ENCODING_RM) 1114 ENCODING("f512mem", ENCODING_RM) 1115 ENCODING("f64mem", ENCODING_RM) 1116 ENCODING("f32mem", ENCODING_RM) 1117 ENCODING("i128mem", ENCODING_RM) 1118 ENCODING("i256mem", ENCODING_RM) 1119 ENCODING("i512mem", ENCODING_RM) 1120 ENCODING("f80mem", ENCODING_RM) 1121 ENCODING("lea64_32mem", ENCODING_RM) 1122 ENCODING("lea64mem", ENCODING_RM) 1123 ENCODING("anymem", ENCODING_RM) 1124 ENCODING("opaque32mem", ENCODING_RM) 1125 ENCODING("opaque48mem", ENCODING_RM) 1126 ENCODING("opaque80mem", ENCODING_RM) 1127 ENCODING("opaque512mem", ENCODING_RM) 1128 ENCODING("vx64mem", ENCODING_VSIB) 1129 ENCODING("vx128mem", ENCODING_VSIB) 1130 ENCODING("vx256mem", ENCODING_VSIB) 1131 ENCODING("vy128mem", ENCODING_VSIB) 1132 ENCODING("vy256mem", ENCODING_VSIB) 1133 ENCODING("vx64xmem", ENCODING_VSIB) 1134 ENCODING("vx128xmem", ENCODING_VSIB) 1135 ENCODING("vx256xmem", ENCODING_VSIB) 1136 ENCODING("vy128xmem", ENCODING_VSIB) 1137 ENCODING("vy256xmem", ENCODING_VSIB) 1138 ENCODING("vy512mem", ENCODING_VSIB) 1139 ENCODING("vz256xmem", ENCODING_VSIB) 1140 ENCODING("vz512mem", ENCODING_VSIB) 1141 errs() << "Unhandled memory encoding " << s << "\n"; 1142 llvm_unreachable("Unhandled memory encoding"); 1143 } 1144 1145 OperandEncoding 1146 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1147 uint8_t OpSize) { 1148 if(OpSize != X86Local::OpSize16) { 1149 // For instructions without an OpSize prefix, a declared 16-bit register or 1150 // immediate encoding is special. 1151 ENCODING("i16imm", ENCODING_IW) 1152 } 1153 ENCODING("i16imm", ENCODING_Iv) 1154 ENCODING("i16i8imm", ENCODING_IB) 1155 ENCODING("i32imm", ENCODING_Iv) 1156 ENCODING("i32i8imm", ENCODING_IB) 1157 ENCODING("i64i32imm", ENCODING_ID) 1158 ENCODING("i64i8imm", ENCODING_IB) 1159 ENCODING("i8imm", ENCODING_IB) 1160 ENCODING("u8imm", ENCODING_IB) 1161 ENCODING("i32u8imm", ENCODING_IB) 1162 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1163 ENCODING("i16imm_pcrel", ENCODING_IW) 1164 ENCODING("i32imm_pcrel", ENCODING_ID) 1165 ENCODING("brtarget32", ENCODING_Iv) 1166 ENCODING("brtarget16", ENCODING_Iv) 1167 ENCODING("brtarget8", ENCODING_IB) 1168 ENCODING("i64imm", ENCODING_IO) 1169 ENCODING("offset16_8", ENCODING_Ia) 1170 ENCODING("offset16_16", ENCODING_Ia) 1171 ENCODING("offset16_32", ENCODING_Ia) 1172 ENCODING("offset32_8", ENCODING_Ia) 1173 ENCODING("offset32_16", ENCODING_Ia) 1174 ENCODING("offset32_32", ENCODING_Ia) 1175 ENCODING("offset32_64", ENCODING_Ia) 1176 ENCODING("offset64_8", ENCODING_Ia) 1177 ENCODING("offset64_16", ENCODING_Ia) 1178 ENCODING("offset64_32", ENCODING_Ia) 1179 ENCODING("offset64_64", ENCODING_Ia) 1180 ENCODING("srcidx8", ENCODING_SI) 1181 ENCODING("srcidx16", ENCODING_SI) 1182 ENCODING("srcidx32", ENCODING_SI) 1183 ENCODING("srcidx64", ENCODING_SI) 1184 ENCODING("dstidx8", ENCODING_DI) 1185 ENCODING("dstidx16", ENCODING_DI) 1186 ENCODING("dstidx32", ENCODING_DI) 1187 ENCODING("dstidx64", ENCODING_DI) 1188 errs() << "Unhandled relocation encoding " << s << "\n"; 1189 llvm_unreachable("Unhandled relocation encoding"); 1190 } 1191 1192 OperandEncoding 1193 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1194 uint8_t OpSize) { 1195 ENCODING("GR32", ENCODING_Rv) 1196 ENCODING("GR64", ENCODING_RO) 1197 ENCODING("GR16", ENCODING_Rv) 1198 ENCODING("GR8", ENCODING_RB) 1199 ENCODING("GR32_NOAX", ENCODING_Rv) 1200 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1201 llvm_unreachable("Unhandled opcode modifier encoding"); 1202 } 1203 #undef ENCODING 1204