1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisassemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 using namespace X86Disassembler; 25 26 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 27 /// Useful for switch statements and the like. 28 /// 29 /// @param init - A reference to the BitsInit to be decoded. 30 /// @return - The field, with the first bit in the BitsInit as the lowest 31 /// order bit. 32 static uint8_t byteFromBitsInit(BitsInit &init) { 33 int width = init.getNumBits(); 34 35 assert(width <= 8 && "Field is too large for uint8_t!"); 36 37 int index; 38 uint8_t mask = 0x01; 39 40 uint8_t ret = 0; 41 42 for (index = 0; index < width; index++) { 43 if (cast<BitInit>(init.getBit(index))->getValue()) 44 ret |= mask; 45 46 mask <<= 1; 47 } 48 49 return ret; 50 } 51 52 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 53 /// name of the field. 54 /// 55 /// @param rec - The record from which to extract the value. 56 /// @param name - The name of the field in the record. 57 /// @return - The field, as translated by byteFromBitsInit(). 58 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 59 BitsInit* bits = rec->getValueAsBitsInit(name); 60 return byteFromBitsInit(*bits); 61 } 62 63 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 64 const CodeGenInstruction &insn, 65 InstrUID uid) { 66 UID = uid; 67 68 Rec = insn.TheDef; 69 Name = Rec->getName(); 70 Spec = &tables.specForUID(UID); 71 72 if (!Rec->isSubClassOf("X86Inst")) { 73 ShouldBeEmitted = false; 74 return; 75 } 76 77 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 78 OpMap = byteFromRec(Rec, "OpMapBits"); 79 Opcode = byteFromRec(Rec, "Opcode"); 80 Form = byteFromRec(Rec, "FormBits"); 81 Encoding = byteFromRec(Rec, "OpEncBits"); 82 83 OpSize = byteFromRec(Rec, "OpSizeBits"); 84 AdSize = byteFromRec(Rec, "AdSizeBits"); 85 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 86 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 87 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 95 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 96 97 Name = Rec->getName(); 98 99 Operands = &insn.Operands.OperandList; 100 101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 102 103 EncodeRC = HasEVEX_B && 104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 105 106 // Check for 64-bit inst which does not require REX 107 Is32Bit = false; 108 Is64Bit = false; 109 // FIXME: Is there some better way to check for In64BitMode? 110 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 111 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 112 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 113 Predicates[i]->getName().find("In32Bit") != Name.npos) { 114 Is32Bit = true; 115 break; 116 } 117 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 118 Is64Bit = true; 119 break; 120 } 121 } 122 123 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 124 ShouldBeEmitted = false; 125 return; 126 } 127 128 // Special case since there is no attribute class for 64-bit and VEX 129 if (Name == "VMASKMOVDQU64") { 130 ShouldBeEmitted = false; 131 return; 132 } 133 134 ShouldBeEmitted = true; 135 } 136 137 void RecognizableInstr::processInstr(DisassemblerTables &tables, 138 const CodeGenInstruction &insn, 139 InstrUID uid) 140 { 141 // Ignore "asm parser only" instructions. 142 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 143 return; 144 145 RecognizableInstr recogInstr(tables, insn, uid); 146 147 if (recogInstr.shouldBeEmitted()) { 148 recogInstr.emitInstructionSpecifier(); 149 recogInstr.emitDecodePath(tables); 150 } 151 } 152 153 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 154 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 155 (HasEVEX_KZ ? n##_KZ : \ 156 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 157 158 InstructionContext RecognizableInstr::insnContext() const { 159 InstructionContext insnContext; 160 161 if (Encoding == X86Local::EVEX) { 162 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 165 } 166 // VEX_L & VEX_W 167 if (!EncodeRC && HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 168 if (OpPrefix == X86Local::PD) 169 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 170 else if (OpPrefix == X86Local::XS) 171 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 172 else if (OpPrefix == X86Local::XD) 173 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 174 else if (OpPrefix == X86Local::PS) 175 insnContext = EVEX_KB(IC_EVEX_L_W); 176 else { 177 errs() << "Instruction does not use a prefix: " << Name << "\n"; 178 llvm_unreachable("Invalid prefix"); 179 } 180 } else if (!EncodeRC && HasVEX_LPrefix) { 181 // VEX_L 182 if (OpPrefix == X86Local::PD) 183 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 184 else if (OpPrefix == X86Local::XS) 185 insnContext = EVEX_KB(IC_EVEX_L_XS); 186 else if (OpPrefix == X86Local::XD) 187 insnContext = EVEX_KB(IC_EVEX_L_XD); 188 else if (OpPrefix == X86Local::PS) 189 insnContext = EVEX_KB(IC_EVEX_L); 190 else { 191 errs() << "Instruction does not use a prefix: " << Name << "\n"; 192 llvm_unreachable("Invalid prefix"); 193 } 194 } else if (!EncodeRC && HasEVEX_L2Prefix && 195 VEX_WPrefix == X86Local::VEX_W1) { 196 // EVEX_L2 & VEX_W 197 if (OpPrefix == X86Local::PD) 198 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 199 else if (OpPrefix == X86Local::XS) 200 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 201 else if (OpPrefix == X86Local::XD) 202 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 203 else if (OpPrefix == X86Local::PS) 204 insnContext = EVEX_KB(IC_EVEX_L2_W); 205 else { 206 errs() << "Instruction does not use a prefix: " << Name << "\n"; 207 llvm_unreachable("Invalid prefix"); 208 } 209 } else if (!EncodeRC && HasEVEX_L2Prefix) { 210 // EVEX_L2 211 if (OpPrefix == X86Local::PD) 212 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 213 else if (OpPrefix == X86Local::XD) 214 insnContext = EVEX_KB(IC_EVEX_L2_XD); 215 else if (OpPrefix == X86Local::XS) 216 insnContext = EVEX_KB(IC_EVEX_L2_XS); 217 else if (OpPrefix == X86Local::PS) 218 insnContext = EVEX_KB(IC_EVEX_L2); 219 else { 220 errs() << "Instruction does not use a prefix: " << Name << "\n"; 221 llvm_unreachable("Invalid prefix"); 222 } 223 } 224 else if (VEX_WPrefix == X86Local::VEX_W1) { 225 // VEX_W 226 if (OpPrefix == X86Local::PD) 227 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 228 else if (OpPrefix == X86Local::XS) 229 insnContext = EVEX_KB(IC_EVEX_W_XS); 230 else if (OpPrefix == X86Local::XD) 231 insnContext = EVEX_KB(IC_EVEX_W_XD); 232 else if (OpPrefix == X86Local::PS) 233 insnContext = EVEX_KB(IC_EVEX_W); 234 else { 235 errs() << "Instruction does not use a prefix: " << Name << "\n"; 236 llvm_unreachable("Invalid prefix"); 237 } 238 } 239 // No L, no W 240 else if (OpPrefix == X86Local::PD) 241 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 242 else if (OpPrefix == X86Local::XD) 243 insnContext = EVEX_KB(IC_EVEX_XD); 244 else if (OpPrefix == X86Local::XS) 245 insnContext = EVEX_KB(IC_EVEX_XS); 246 else if (OpPrefix == X86Local::PS) 247 insnContext = EVEX_KB(IC_EVEX); 248 else { 249 errs() << "Instruction does not use a prefix: " << Name << "\n"; 250 llvm_unreachable("Invalid prefix"); 251 } 252 /// eof EVEX 253 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 254 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 255 if (OpPrefix == X86Local::PD) 256 insnContext = IC_VEX_L_W_OPSIZE; 257 else if (OpPrefix == X86Local::XS) 258 insnContext = IC_VEX_L_W_XS; 259 else if (OpPrefix == X86Local::XD) 260 insnContext = IC_VEX_L_W_XD; 261 else if (OpPrefix == X86Local::PS) 262 insnContext = IC_VEX_L_W; 263 else { 264 errs() << "Instruction does not use a prefix: " << Name << "\n"; 265 llvm_unreachable("Invalid prefix"); 266 } 267 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 268 insnContext = IC_VEX_L_OPSIZE; 269 else if (OpPrefix == X86Local::PD && VEX_WPrefix == X86Local::VEX_W1) 270 insnContext = IC_VEX_W_OPSIZE; 271 else if (OpPrefix == X86Local::PD) 272 insnContext = IC_VEX_OPSIZE; 273 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 274 insnContext = IC_VEX_L_XS; 275 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 276 insnContext = IC_VEX_L_XD; 277 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XS) 278 insnContext = IC_VEX_W_XS; 279 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XD) 280 insnContext = IC_VEX_W_XD; 281 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::PS) 282 insnContext = IC_VEX_W; 283 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 284 insnContext = IC_VEX_L; 285 else if (OpPrefix == X86Local::XD) 286 insnContext = IC_VEX_XD; 287 else if (OpPrefix == X86Local::XS) 288 insnContext = IC_VEX_XS; 289 else if (OpPrefix == X86Local::PS) 290 insnContext = IC_VEX; 291 else { 292 errs() << "Instruction does not use a prefix: " << Name << "\n"; 293 llvm_unreachable("Invalid prefix"); 294 } 295 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 296 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 297 insnContext = IC_64BIT_REXW_OPSIZE; 298 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 299 insnContext = IC_64BIT_REXW_ADSIZE; 300 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 301 insnContext = IC_64BIT_XD_OPSIZE; 302 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 303 insnContext = IC_64BIT_XS_OPSIZE; 304 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 305 insnContext = IC_64BIT_OPSIZE_ADSIZE; 306 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 307 insnContext = IC_64BIT_OPSIZE; 308 else if (AdSize == X86Local::AdSize32) 309 insnContext = IC_64BIT_ADSIZE; 310 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 311 insnContext = IC_64BIT_REXW_XS; 312 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 313 insnContext = IC_64BIT_REXW_XD; 314 else if (OpPrefix == X86Local::XD) 315 insnContext = IC_64BIT_XD; 316 else if (OpPrefix == X86Local::XS) 317 insnContext = IC_64BIT_XS; 318 else if (HasREX_WPrefix) 319 insnContext = IC_64BIT_REXW; 320 else 321 insnContext = IC_64BIT; 322 } else { 323 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 324 insnContext = IC_XD_OPSIZE; 325 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 326 insnContext = IC_XS_OPSIZE; 327 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 328 insnContext = IC_XD_ADSIZE; 329 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 330 insnContext = IC_XS_ADSIZE; 331 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 332 insnContext = IC_OPSIZE_ADSIZE; 333 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 334 insnContext = IC_OPSIZE; 335 else if (AdSize == X86Local::AdSize16) 336 insnContext = IC_ADSIZE; 337 else if (OpPrefix == X86Local::XD) 338 insnContext = IC_XD; 339 else if (OpPrefix == X86Local::XS) 340 insnContext = IC_XS; 341 else 342 insnContext = IC; 343 } 344 345 return insnContext; 346 } 347 348 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 349 // The scaling factor for AVX512 compressed displacement encoding is an 350 // instruction attribute. Adjust the ModRM encoding type to include the 351 // scale for compressed displacement. 352 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 353 return; 354 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 355 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 356 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 357 "Invalid CDisp scaling"); 358 } 359 360 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 361 unsigned &physicalOperandIndex, 362 unsigned numPhysicalOperands, 363 const unsigned *operandMapping, 364 OperandEncoding (*encodingFromString) 365 (const std::string&, 366 uint8_t OpSize)) { 367 if (optional) { 368 if (physicalOperandIndex >= numPhysicalOperands) 369 return; 370 } else { 371 assert(physicalOperandIndex < numPhysicalOperands); 372 } 373 374 while (operandMapping[operandIndex] != operandIndex) { 375 Spec->operands[operandIndex].encoding = ENCODING_DUP; 376 Spec->operands[operandIndex].type = 377 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 378 ++operandIndex; 379 } 380 381 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 382 383 OperandEncoding encoding = encodingFromString(typeName, OpSize); 384 // Adjust the encoding type for an operand based on the instruction. 385 adjustOperandEncoding(encoding); 386 Spec->operands[operandIndex].encoding = encoding; 387 Spec->operands[operandIndex].type = typeFromString(typeName, 388 HasREX_WPrefix, OpSize); 389 390 ++operandIndex; 391 ++physicalOperandIndex; 392 } 393 394 void RecognizableInstr::emitInstructionSpecifier() { 395 Spec->name = Name; 396 397 Spec->insnContext = insnContext(); 398 399 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 400 401 unsigned numOperands = OperandList.size(); 402 unsigned numPhysicalOperands = 0; 403 404 // operandMapping maps from operands in OperandList to their originals. 405 // If operandMapping[i] != i, then the entry is a duplicate. 406 unsigned operandMapping[X86_MAX_OPERANDS]; 407 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 408 409 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 410 if (!OperandList[operandIndex].Constraints.empty()) { 411 const CGIOperandList::ConstraintInfo &Constraint = 412 OperandList[operandIndex].Constraints[0]; 413 if (Constraint.isTied()) { 414 operandMapping[operandIndex] = operandIndex; 415 operandMapping[Constraint.getTiedOperand()] = operandIndex; 416 } else { 417 ++numPhysicalOperands; 418 operandMapping[operandIndex] = operandIndex; 419 } 420 } else { 421 ++numPhysicalOperands; 422 operandMapping[operandIndex] = operandIndex; 423 } 424 } 425 426 #define HANDLE_OPERAND(class) \ 427 handleOperand(false, \ 428 operandIndex, \ 429 physicalOperandIndex, \ 430 numPhysicalOperands, \ 431 operandMapping, \ 432 class##EncodingFromString); 433 434 #define HANDLE_OPTIONAL(class) \ 435 handleOperand(true, \ 436 operandIndex, \ 437 physicalOperandIndex, \ 438 numPhysicalOperands, \ 439 operandMapping, \ 440 class##EncodingFromString); 441 442 // operandIndex should always be < numOperands 443 unsigned operandIndex = 0; 444 // physicalOperandIndex should always be < numPhysicalOperands 445 unsigned physicalOperandIndex = 0; 446 447 #ifndef NDEBUG 448 // Given the set of prefix bits, how many additional operands does the 449 // instruction have? 450 unsigned additionalOperands = 0; 451 if (HasVEX_4V) 452 ++additionalOperands; 453 if (HasEVEX_K) 454 ++additionalOperands; 455 #endif 456 457 switch (Form) { 458 default: llvm_unreachable("Unhandled form"); 459 case X86Local::RawFrmSrc: 460 HANDLE_OPERAND(relocation); 461 return; 462 case X86Local::RawFrmDst: 463 HANDLE_OPERAND(relocation); 464 return; 465 case X86Local::RawFrmDstSrc: 466 HANDLE_OPERAND(relocation); 467 HANDLE_OPERAND(relocation); 468 return; 469 case X86Local::RawFrm: 470 // Operand 1 (optional) is an address or immediate. 471 assert(numPhysicalOperands <= 1 && 472 "Unexpected number of operands for RawFrm"); 473 HANDLE_OPTIONAL(relocation) 474 break; 475 case X86Local::RawFrmMemOffs: 476 // Operand 1 is an address. 477 HANDLE_OPERAND(relocation); 478 break; 479 case X86Local::AddRegFrm: 480 // Operand 1 is added to the opcode. 481 // Operand 2 (optional) is an address. 482 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 483 "Unexpected number of operands for AddRegFrm"); 484 HANDLE_OPERAND(opcodeModifier) 485 HANDLE_OPTIONAL(relocation) 486 break; 487 case X86Local::MRMDestReg: 488 // Operand 1 is a register operand in the R/M field. 489 // - In AVX512 there may be a mask operand here - 490 // Operand 2 is a register operand in the Reg/Opcode field. 491 // - In AVX, there is a register operand in the VEX.vvvv field here - 492 // Operand 3 (optional) is an immediate. 493 assert(numPhysicalOperands >= 2 + additionalOperands && 494 numPhysicalOperands <= 3 + additionalOperands && 495 "Unexpected number of operands for MRMDestRegFrm"); 496 497 HANDLE_OPERAND(rmRegister) 498 if (HasEVEX_K) 499 HANDLE_OPERAND(writemaskRegister) 500 501 if (HasVEX_4V) 502 // FIXME: In AVX, the register below becomes the one encoded 503 // in ModRMVEX and the one above the one in the VEX.VVVV field 504 HANDLE_OPERAND(vvvvRegister) 505 506 HANDLE_OPERAND(roRegister) 507 HANDLE_OPTIONAL(immediate) 508 break; 509 case X86Local::MRMDestMem: 510 // Operand 1 is a memory operand (possibly SIB-extended) 511 // Operand 2 is a register operand in the Reg/Opcode field. 512 // - In AVX, there is a register operand in the VEX.vvvv field here - 513 // Operand 3 (optional) is an immediate. 514 assert(numPhysicalOperands >= 2 + additionalOperands && 515 numPhysicalOperands <= 3 + additionalOperands && 516 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 517 518 HANDLE_OPERAND(memory) 519 520 if (HasEVEX_K) 521 HANDLE_OPERAND(writemaskRegister) 522 523 if (HasVEX_4V) 524 // FIXME: In AVX, the register below becomes the one encoded 525 // in ModRMVEX and the one above the one in the VEX.VVVV field 526 HANDLE_OPERAND(vvvvRegister) 527 528 HANDLE_OPERAND(roRegister) 529 HANDLE_OPTIONAL(immediate) 530 break; 531 case X86Local::MRMSrcReg: 532 // Operand 1 is a register operand in the Reg/Opcode field. 533 // Operand 2 is a register operand in the R/M field. 534 // - In AVX, there is a register operand in the VEX.vvvv field here - 535 // Operand 3 (optional) is an immediate. 536 // Operand 4 (optional) is an immediate. 537 538 assert(numPhysicalOperands >= 2 + additionalOperands && 539 numPhysicalOperands <= 4 + additionalOperands && 540 "Unexpected number of operands for MRMSrcRegFrm"); 541 542 HANDLE_OPERAND(roRegister) 543 544 if (HasEVEX_K) 545 HANDLE_OPERAND(writemaskRegister) 546 547 if (HasVEX_4V) 548 // FIXME: In AVX, the register below becomes the one encoded 549 // in ModRMVEX and the one above the one in the VEX.VVVV field 550 HANDLE_OPERAND(vvvvRegister) 551 552 HANDLE_OPERAND(rmRegister) 553 HANDLE_OPTIONAL(immediate) 554 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 555 break; 556 case X86Local::MRMSrcReg4VOp3: 557 assert(numPhysicalOperands == 3 && 558 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 559 HANDLE_OPERAND(roRegister) 560 HANDLE_OPERAND(rmRegister) 561 HANDLE_OPERAND(vvvvRegister) 562 break; 563 case X86Local::MRMSrcRegOp4: 564 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 565 "Unexpected number of operands for MRMSrcRegOp4Frm"); 566 HANDLE_OPERAND(roRegister) 567 HANDLE_OPERAND(vvvvRegister) 568 HANDLE_OPERAND(immediate) // Register in imm[7:4] 569 HANDLE_OPERAND(rmRegister) 570 HANDLE_OPTIONAL(immediate) 571 break; 572 case X86Local::MRMSrcMem: 573 // Operand 1 is a register operand in the Reg/Opcode field. 574 // Operand 2 is a memory operand (possibly SIB-extended) 575 // - In AVX, there is a register operand in the VEX.vvvv field here - 576 // Operand 3 (optional) is an immediate. 577 578 assert(numPhysicalOperands >= 2 + additionalOperands && 579 numPhysicalOperands <= 4 + additionalOperands && 580 "Unexpected number of operands for MRMSrcMemFrm"); 581 582 HANDLE_OPERAND(roRegister) 583 584 if (HasEVEX_K) 585 HANDLE_OPERAND(writemaskRegister) 586 587 if (HasVEX_4V) 588 // FIXME: In AVX, the register below becomes the one encoded 589 // in ModRMVEX and the one above the one in the VEX.VVVV field 590 HANDLE_OPERAND(vvvvRegister) 591 592 HANDLE_OPERAND(memory) 593 HANDLE_OPTIONAL(immediate) 594 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 595 break; 596 case X86Local::MRMSrcMem4VOp3: 597 assert(numPhysicalOperands == 3 && 598 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 599 HANDLE_OPERAND(roRegister) 600 HANDLE_OPERAND(memory) 601 HANDLE_OPERAND(vvvvRegister) 602 break; 603 case X86Local::MRMSrcMemOp4: 604 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 605 "Unexpected number of operands for MRMSrcMemOp4Frm"); 606 HANDLE_OPERAND(roRegister) 607 HANDLE_OPERAND(vvvvRegister) 608 HANDLE_OPERAND(immediate) // Register in imm[7:4] 609 HANDLE_OPERAND(memory) 610 HANDLE_OPTIONAL(immediate) 611 break; 612 case X86Local::MRMXr: 613 case X86Local::MRM0r: 614 case X86Local::MRM1r: 615 case X86Local::MRM2r: 616 case X86Local::MRM3r: 617 case X86Local::MRM4r: 618 case X86Local::MRM5r: 619 case X86Local::MRM6r: 620 case X86Local::MRM7r: 621 // Operand 1 is a register operand in the R/M field. 622 // Operand 2 (optional) is an immediate or relocation. 623 // Operand 3 (optional) is an immediate. 624 assert(numPhysicalOperands >= 0 + additionalOperands && 625 numPhysicalOperands <= 3 + additionalOperands && 626 "Unexpected number of operands for MRMnr"); 627 628 if (HasVEX_4V) 629 HANDLE_OPERAND(vvvvRegister) 630 631 if (HasEVEX_K) 632 HANDLE_OPERAND(writemaskRegister) 633 HANDLE_OPTIONAL(rmRegister) 634 HANDLE_OPTIONAL(relocation) 635 HANDLE_OPTIONAL(immediate) 636 break; 637 case X86Local::MRMXm: 638 case X86Local::MRM0m: 639 case X86Local::MRM1m: 640 case X86Local::MRM2m: 641 case X86Local::MRM3m: 642 case X86Local::MRM4m: 643 case X86Local::MRM5m: 644 case X86Local::MRM6m: 645 case X86Local::MRM7m: 646 // Operand 1 is a memory operand (possibly SIB-extended) 647 // Operand 2 (optional) is an immediate or relocation. 648 assert(numPhysicalOperands >= 1 + additionalOperands && 649 numPhysicalOperands <= 2 + additionalOperands && 650 "Unexpected number of operands for MRMnm"); 651 652 if (HasVEX_4V) 653 HANDLE_OPERAND(vvvvRegister) 654 if (HasEVEX_K) 655 HANDLE_OPERAND(writemaskRegister) 656 HANDLE_OPERAND(memory) 657 HANDLE_OPTIONAL(relocation) 658 break; 659 case X86Local::RawFrmImm8: 660 // operand 1 is a 16-bit immediate 661 // operand 2 is an 8-bit immediate 662 assert(numPhysicalOperands == 2 && 663 "Unexpected number of operands for X86Local::RawFrmImm8"); 664 HANDLE_OPERAND(immediate) 665 HANDLE_OPERAND(immediate) 666 break; 667 case X86Local::RawFrmImm16: 668 // operand 1 is a 16-bit immediate 669 // operand 2 is a 16-bit immediate 670 HANDLE_OPERAND(immediate) 671 HANDLE_OPERAND(immediate) 672 break; 673 #define MAP(from, to) case X86Local::MRM_##from: 674 X86_INSTR_MRM_MAPPING 675 #undef MAP 676 HANDLE_OPTIONAL(relocation) 677 break; 678 } 679 680 #undef HANDLE_OPERAND 681 #undef HANDLE_OPTIONAL 682 } 683 684 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 685 // Special cases where the LLVM tables are not complete 686 687 #define MAP(from, to) \ 688 case X86Local::MRM_##from: 689 690 llvm::Optional<OpcodeType> opcodeType; 691 switch (OpMap) { 692 default: llvm_unreachable("Invalid map!"); 693 case X86Local::OB: opcodeType = ONEBYTE; break; 694 case X86Local::TB: opcodeType = TWOBYTE; break; 695 case X86Local::T8: opcodeType = THREEBYTE_38; break; 696 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 697 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 698 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 699 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 700 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 701 } 702 703 std::unique_ptr<ModRMFilter> filter; 704 switch (Form) { 705 default: llvm_unreachable("Invalid form!"); 706 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 707 case X86Local::RawFrm: 708 case X86Local::AddRegFrm: 709 case X86Local::RawFrmMemOffs: 710 case X86Local::RawFrmSrc: 711 case X86Local::RawFrmDst: 712 case X86Local::RawFrmDstSrc: 713 case X86Local::RawFrmImm8: 714 case X86Local::RawFrmImm16: 715 filter = llvm::make_unique<DumbFilter>(); 716 break; 717 case X86Local::MRMDestReg: 718 case X86Local::MRMSrcReg: 719 case X86Local::MRMSrcReg4VOp3: 720 case X86Local::MRMSrcRegOp4: 721 case X86Local::MRMXr: 722 filter = llvm::make_unique<ModFilter>(true); 723 break; 724 case X86Local::MRMDestMem: 725 case X86Local::MRMSrcMem: 726 case X86Local::MRMSrcMem4VOp3: 727 case X86Local::MRMSrcMemOp4: 728 case X86Local::MRMXm: 729 filter = llvm::make_unique<ModFilter>(false); 730 break; 731 case X86Local::MRM0r: case X86Local::MRM1r: 732 case X86Local::MRM2r: case X86Local::MRM3r: 733 case X86Local::MRM4r: case X86Local::MRM5r: 734 case X86Local::MRM6r: case X86Local::MRM7r: 735 filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 736 break; 737 case X86Local::MRM0m: case X86Local::MRM1m: 738 case X86Local::MRM2m: case X86Local::MRM3m: 739 case X86Local::MRM4m: case X86Local::MRM5m: 740 case X86Local::MRM6m: case X86Local::MRM7m: 741 filter = llvm::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 742 break; 743 X86_INSTR_MRM_MAPPING 744 filter = llvm::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 745 break; 746 } // switch (Form) 747 748 uint8_t opcodeToSet = Opcode; 749 750 unsigned AddressSize = 0; 751 switch (AdSize) { 752 case X86Local::AdSize16: AddressSize = 16; break; 753 case X86Local::AdSize32: AddressSize = 32; break; 754 case X86Local::AdSize64: AddressSize = 64; break; 755 } 756 757 assert(opcodeType && "Opcode type not set"); 758 assert(filter && "Filter not set"); 759 760 if (Form == X86Local::AddRegFrm) { 761 assert(((opcodeToSet & 7) == 0) && 762 "ADDREG_FRM opcode not aligned"); 763 764 uint8_t currentOpcode; 765 766 for (currentOpcode = opcodeToSet; 767 currentOpcode < opcodeToSet + 8; 768 ++currentOpcode) 769 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 770 UID, Is32Bit, OpPrefix == 0, 771 IgnoresVEX_L || EncodeRC, 772 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 773 } else { 774 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 775 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 776 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 777 } 778 779 #undef MAP 780 } 781 782 #define TYPE(str, type) if (s == str) return type; 783 OperandType RecognizableInstr::typeFromString(const std::string &s, 784 bool hasREX_WPrefix, 785 uint8_t OpSize) { 786 if(hasREX_WPrefix) { 787 // For instructions with a REX_W prefix, a declared 32-bit register encoding 788 // is special. 789 TYPE("GR32", TYPE_R32) 790 } 791 if(OpSize == X86Local::OpSize16) { 792 // For OpSize16 instructions, a declared 16-bit register or 793 // immediate encoding is special. 794 TYPE("GR16", TYPE_Rv) 795 } else if(OpSize == X86Local::OpSize32) { 796 // For OpSize32 instructions, a declared 32-bit register or 797 // immediate encoding is special. 798 TYPE("GR32", TYPE_Rv) 799 } 800 TYPE("i16mem", TYPE_M) 801 TYPE("i16imm", TYPE_IMM) 802 TYPE("i16i8imm", TYPE_IMM) 803 TYPE("GR16", TYPE_R16) 804 TYPE("i32mem", TYPE_M) 805 TYPE("i32imm", TYPE_IMM) 806 TYPE("i32i8imm", TYPE_IMM) 807 TYPE("GR32", TYPE_R32) 808 TYPE("GR32orGR64", TYPE_R32) 809 TYPE("i64mem", TYPE_M) 810 TYPE("i64i32imm", TYPE_IMM) 811 TYPE("i64i8imm", TYPE_IMM) 812 TYPE("GR64", TYPE_R64) 813 TYPE("i8mem", TYPE_M) 814 TYPE("i8imm", TYPE_IMM) 815 TYPE("u8imm", TYPE_UIMM8) 816 TYPE("i32u8imm", TYPE_UIMM8) 817 TYPE("GR8", TYPE_R8) 818 TYPE("VR128", TYPE_XMM) 819 TYPE("VR128X", TYPE_XMM) 820 TYPE("f128mem", TYPE_M) 821 TYPE("f256mem", TYPE_M) 822 TYPE("f512mem", TYPE_M) 823 TYPE("FR128", TYPE_XMM) 824 TYPE("FR64", TYPE_XMM) 825 TYPE("FR64X", TYPE_XMM) 826 TYPE("f64mem", TYPE_M) 827 TYPE("sdmem", TYPE_M) 828 TYPE("FR32", TYPE_XMM) 829 TYPE("FR32X", TYPE_XMM) 830 TYPE("f32mem", TYPE_M) 831 TYPE("ssmem", TYPE_M) 832 TYPE("RST", TYPE_ST) 833 TYPE("i128mem", TYPE_M) 834 TYPE("i256mem", TYPE_M) 835 TYPE("i512mem", TYPE_M) 836 TYPE("i64i32imm_pcrel", TYPE_REL) 837 TYPE("i16imm_pcrel", TYPE_REL) 838 TYPE("i32imm_pcrel", TYPE_REL) 839 TYPE("SSECC", TYPE_IMM3) 840 TYPE("XOPCC", TYPE_IMM3) 841 TYPE("AVXCC", TYPE_IMM5) 842 TYPE("AVX512ICC", TYPE_AVX512ICC) 843 TYPE("AVX512RC", TYPE_IMM) 844 TYPE("brtarget32", TYPE_REL) 845 TYPE("brtarget16", TYPE_REL) 846 TYPE("brtarget8", TYPE_REL) 847 TYPE("f80mem", TYPE_M) 848 TYPE("lea64_32mem", TYPE_M) 849 TYPE("lea64mem", TYPE_M) 850 TYPE("VR64", TYPE_MM64) 851 TYPE("i64imm", TYPE_IMM) 852 TYPE("anymem", TYPE_M) 853 TYPE("opaque32mem", TYPE_M) 854 TYPE("opaque48mem", TYPE_M) 855 TYPE("opaque80mem", TYPE_M) 856 TYPE("opaque512mem", TYPE_M) 857 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 858 TYPE("DEBUG_REG", TYPE_DEBUGREG) 859 TYPE("CONTROL_REG", TYPE_CONTROLREG) 860 TYPE("srcidx8", TYPE_SRCIDX) 861 TYPE("srcidx16", TYPE_SRCIDX) 862 TYPE("srcidx32", TYPE_SRCIDX) 863 TYPE("srcidx64", TYPE_SRCIDX) 864 TYPE("dstidx8", TYPE_DSTIDX) 865 TYPE("dstidx16", TYPE_DSTIDX) 866 TYPE("dstidx32", TYPE_DSTIDX) 867 TYPE("dstidx64", TYPE_DSTIDX) 868 TYPE("offset16_8", TYPE_MOFFS) 869 TYPE("offset16_16", TYPE_MOFFS) 870 TYPE("offset16_32", TYPE_MOFFS) 871 TYPE("offset32_8", TYPE_MOFFS) 872 TYPE("offset32_16", TYPE_MOFFS) 873 TYPE("offset32_32", TYPE_MOFFS) 874 TYPE("offset32_64", TYPE_MOFFS) 875 TYPE("offset64_8", TYPE_MOFFS) 876 TYPE("offset64_16", TYPE_MOFFS) 877 TYPE("offset64_32", TYPE_MOFFS) 878 TYPE("offset64_64", TYPE_MOFFS) 879 TYPE("VR256", TYPE_YMM) 880 TYPE("VR256X", TYPE_YMM) 881 TYPE("VR512", TYPE_ZMM) 882 TYPE("VK1", TYPE_VK) 883 TYPE("VK1WM", TYPE_VK) 884 TYPE("VK2", TYPE_VK) 885 TYPE("VK2WM", TYPE_VK) 886 TYPE("VK4", TYPE_VK) 887 TYPE("VK4WM", TYPE_VK) 888 TYPE("VK8", TYPE_VK) 889 TYPE("VK8WM", TYPE_VK) 890 TYPE("VK16", TYPE_VK) 891 TYPE("VK16WM", TYPE_VK) 892 TYPE("VK32", TYPE_VK) 893 TYPE("VK32WM", TYPE_VK) 894 TYPE("VK64", TYPE_VK) 895 TYPE("VK64WM", TYPE_VK) 896 TYPE("vx64mem", TYPE_MVSIBX) 897 TYPE("vx128mem", TYPE_MVSIBX) 898 TYPE("vx256mem", TYPE_MVSIBX) 899 TYPE("vy128mem", TYPE_MVSIBY) 900 TYPE("vy256mem", TYPE_MVSIBY) 901 TYPE("vx64xmem", TYPE_MVSIBX) 902 TYPE("vx128xmem", TYPE_MVSIBX) 903 TYPE("vx256xmem", TYPE_MVSIBX) 904 TYPE("vy128xmem", TYPE_MVSIBY) 905 TYPE("vy256xmem", TYPE_MVSIBY) 906 TYPE("vy512mem", TYPE_MVSIBY) 907 TYPE("vz256xmem", TYPE_MVSIBZ) 908 TYPE("vz512mem", TYPE_MVSIBZ) 909 TYPE("BNDR", TYPE_BNDR) 910 errs() << "Unhandled type string " << s << "\n"; 911 llvm_unreachable("Unhandled type string"); 912 } 913 #undef TYPE 914 915 #define ENCODING(str, encoding) if (s == str) return encoding; 916 OperandEncoding 917 RecognizableInstr::immediateEncodingFromString(const std::string &s, 918 uint8_t OpSize) { 919 if(OpSize != X86Local::OpSize16) { 920 // For instructions without an OpSize prefix, a declared 16-bit register or 921 // immediate encoding is special. 922 ENCODING("i16imm", ENCODING_IW) 923 } 924 ENCODING("i32i8imm", ENCODING_IB) 925 ENCODING("SSECC", ENCODING_IB) 926 ENCODING("XOPCC", ENCODING_IB) 927 ENCODING("AVXCC", ENCODING_IB) 928 ENCODING("AVX512ICC", ENCODING_IB) 929 ENCODING("AVX512RC", ENCODING_IRC) 930 ENCODING("i16imm", ENCODING_Iv) 931 ENCODING("i16i8imm", ENCODING_IB) 932 ENCODING("i32imm", ENCODING_Iv) 933 ENCODING("i64i32imm", ENCODING_ID) 934 ENCODING("i64i8imm", ENCODING_IB) 935 ENCODING("i8imm", ENCODING_IB) 936 ENCODING("u8imm", ENCODING_IB) 937 ENCODING("i32u8imm", ENCODING_IB) 938 // This is not a typo. Instructions like BLENDVPD put 939 // register IDs in 8-bit immediates nowadays. 940 ENCODING("FR32", ENCODING_IB) 941 ENCODING("FR64", ENCODING_IB) 942 ENCODING("FR128", ENCODING_IB) 943 ENCODING("VR128", ENCODING_IB) 944 ENCODING("VR256", ENCODING_IB) 945 ENCODING("FR32X", ENCODING_IB) 946 ENCODING("FR64X", ENCODING_IB) 947 ENCODING("VR128X", ENCODING_IB) 948 ENCODING("VR256X", ENCODING_IB) 949 ENCODING("VR512", ENCODING_IB) 950 errs() << "Unhandled immediate encoding " << s << "\n"; 951 llvm_unreachable("Unhandled immediate encoding"); 952 } 953 954 OperandEncoding 955 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 956 uint8_t OpSize) { 957 ENCODING("RST", ENCODING_FP) 958 ENCODING("GR16", ENCODING_RM) 959 ENCODING("GR32", ENCODING_RM) 960 ENCODING("GR32orGR64", ENCODING_RM) 961 ENCODING("GR64", ENCODING_RM) 962 ENCODING("GR8", ENCODING_RM) 963 ENCODING("VR128", ENCODING_RM) 964 ENCODING("VR128X", ENCODING_RM) 965 ENCODING("FR128", ENCODING_RM) 966 ENCODING("FR64", ENCODING_RM) 967 ENCODING("FR32", ENCODING_RM) 968 ENCODING("FR64X", ENCODING_RM) 969 ENCODING("FR32X", ENCODING_RM) 970 ENCODING("VR64", ENCODING_RM) 971 ENCODING("VR256", ENCODING_RM) 972 ENCODING("VR256X", ENCODING_RM) 973 ENCODING("VR512", ENCODING_RM) 974 ENCODING("VK1", ENCODING_RM) 975 ENCODING("VK2", ENCODING_RM) 976 ENCODING("VK4", ENCODING_RM) 977 ENCODING("VK8", ENCODING_RM) 978 ENCODING("VK16", ENCODING_RM) 979 ENCODING("VK32", ENCODING_RM) 980 ENCODING("VK64", ENCODING_RM) 981 ENCODING("BNDR", ENCODING_RM) 982 errs() << "Unhandled R/M register encoding " << s << "\n"; 983 llvm_unreachable("Unhandled R/M register encoding"); 984 } 985 986 OperandEncoding 987 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 988 uint8_t OpSize) { 989 ENCODING("GR16", ENCODING_REG) 990 ENCODING("GR32", ENCODING_REG) 991 ENCODING("GR32orGR64", ENCODING_REG) 992 ENCODING("GR64", ENCODING_REG) 993 ENCODING("GR8", ENCODING_REG) 994 ENCODING("VR128", ENCODING_REG) 995 ENCODING("FR128", ENCODING_REG) 996 ENCODING("FR64", ENCODING_REG) 997 ENCODING("FR32", ENCODING_REG) 998 ENCODING("VR64", ENCODING_REG) 999 ENCODING("SEGMENT_REG", ENCODING_REG) 1000 ENCODING("DEBUG_REG", ENCODING_REG) 1001 ENCODING("CONTROL_REG", ENCODING_REG) 1002 ENCODING("VR256", ENCODING_REG) 1003 ENCODING("VR256X", ENCODING_REG) 1004 ENCODING("VR128X", ENCODING_REG) 1005 ENCODING("FR64X", ENCODING_REG) 1006 ENCODING("FR32X", ENCODING_REG) 1007 ENCODING("VR512", ENCODING_REG) 1008 ENCODING("VK1", ENCODING_REG) 1009 ENCODING("VK2", ENCODING_REG) 1010 ENCODING("VK4", ENCODING_REG) 1011 ENCODING("VK8", ENCODING_REG) 1012 ENCODING("VK16", ENCODING_REG) 1013 ENCODING("VK32", ENCODING_REG) 1014 ENCODING("VK64", ENCODING_REG) 1015 ENCODING("VK1WM", ENCODING_REG) 1016 ENCODING("VK2WM", ENCODING_REG) 1017 ENCODING("VK4WM", ENCODING_REG) 1018 ENCODING("VK8WM", ENCODING_REG) 1019 ENCODING("VK16WM", ENCODING_REG) 1020 ENCODING("VK32WM", ENCODING_REG) 1021 ENCODING("VK64WM", ENCODING_REG) 1022 ENCODING("BNDR", ENCODING_REG) 1023 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1024 llvm_unreachable("Unhandled reg/opcode register encoding"); 1025 } 1026 1027 OperandEncoding 1028 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1029 uint8_t OpSize) { 1030 ENCODING("GR32", ENCODING_VVVV) 1031 ENCODING("GR64", ENCODING_VVVV) 1032 ENCODING("FR32", ENCODING_VVVV) 1033 ENCODING("FR128", ENCODING_VVVV) 1034 ENCODING("FR64", ENCODING_VVVV) 1035 ENCODING("VR128", ENCODING_VVVV) 1036 ENCODING("VR256", ENCODING_VVVV) 1037 ENCODING("FR32X", ENCODING_VVVV) 1038 ENCODING("FR64X", ENCODING_VVVV) 1039 ENCODING("VR128X", ENCODING_VVVV) 1040 ENCODING("VR256X", ENCODING_VVVV) 1041 ENCODING("VR512", ENCODING_VVVV) 1042 ENCODING("VK1", ENCODING_VVVV) 1043 ENCODING("VK2", ENCODING_VVVV) 1044 ENCODING("VK4", ENCODING_VVVV) 1045 ENCODING("VK8", ENCODING_VVVV) 1046 ENCODING("VK16", ENCODING_VVVV) 1047 ENCODING("VK32", ENCODING_VVVV) 1048 ENCODING("VK64", ENCODING_VVVV) 1049 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1050 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1051 } 1052 1053 OperandEncoding 1054 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1055 uint8_t OpSize) { 1056 ENCODING("VK1WM", ENCODING_WRITEMASK) 1057 ENCODING("VK2WM", ENCODING_WRITEMASK) 1058 ENCODING("VK4WM", ENCODING_WRITEMASK) 1059 ENCODING("VK8WM", ENCODING_WRITEMASK) 1060 ENCODING("VK16WM", ENCODING_WRITEMASK) 1061 ENCODING("VK32WM", ENCODING_WRITEMASK) 1062 ENCODING("VK64WM", ENCODING_WRITEMASK) 1063 errs() << "Unhandled mask register encoding " << s << "\n"; 1064 llvm_unreachable("Unhandled mask register encoding"); 1065 } 1066 1067 OperandEncoding 1068 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1069 uint8_t OpSize) { 1070 ENCODING("i16mem", ENCODING_RM) 1071 ENCODING("i32mem", ENCODING_RM) 1072 ENCODING("i64mem", ENCODING_RM) 1073 ENCODING("i8mem", ENCODING_RM) 1074 ENCODING("ssmem", ENCODING_RM) 1075 ENCODING("sdmem", ENCODING_RM) 1076 ENCODING("f128mem", ENCODING_RM) 1077 ENCODING("f256mem", ENCODING_RM) 1078 ENCODING("f512mem", ENCODING_RM) 1079 ENCODING("f64mem", ENCODING_RM) 1080 ENCODING("f32mem", ENCODING_RM) 1081 ENCODING("i128mem", ENCODING_RM) 1082 ENCODING("i256mem", ENCODING_RM) 1083 ENCODING("i512mem", ENCODING_RM) 1084 ENCODING("f80mem", ENCODING_RM) 1085 ENCODING("lea64_32mem", ENCODING_RM) 1086 ENCODING("lea64mem", ENCODING_RM) 1087 ENCODING("anymem", ENCODING_RM) 1088 ENCODING("opaque32mem", ENCODING_RM) 1089 ENCODING("opaque48mem", ENCODING_RM) 1090 ENCODING("opaque80mem", ENCODING_RM) 1091 ENCODING("opaque512mem", ENCODING_RM) 1092 ENCODING("vx64mem", ENCODING_VSIB) 1093 ENCODING("vx128mem", ENCODING_VSIB) 1094 ENCODING("vx256mem", ENCODING_VSIB) 1095 ENCODING("vy128mem", ENCODING_VSIB) 1096 ENCODING("vy256mem", ENCODING_VSIB) 1097 ENCODING("vx64xmem", ENCODING_VSIB) 1098 ENCODING("vx128xmem", ENCODING_VSIB) 1099 ENCODING("vx256xmem", ENCODING_VSIB) 1100 ENCODING("vy128xmem", ENCODING_VSIB) 1101 ENCODING("vy256xmem", ENCODING_VSIB) 1102 ENCODING("vy512mem", ENCODING_VSIB) 1103 ENCODING("vz256xmem", ENCODING_VSIB) 1104 ENCODING("vz512mem", ENCODING_VSIB) 1105 errs() << "Unhandled memory encoding " << s << "\n"; 1106 llvm_unreachable("Unhandled memory encoding"); 1107 } 1108 1109 OperandEncoding 1110 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1111 uint8_t OpSize) { 1112 if(OpSize != X86Local::OpSize16) { 1113 // For instructions without an OpSize prefix, a declared 16-bit register or 1114 // immediate encoding is special. 1115 ENCODING("i16imm", ENCODING_IW) 1116 } 1117 ENCODING("i16imm", ENCODING_Iv) 1118 ENCODING("i16i8imm", ENCODING_IB) 1119 ENCODING("i32imm", ENCODING_Iv) 1120 ENCODING("i32i8imm", ENCODING_IB) 1121 ENCODING("i64i32imm", ENCODING_ID) 1122 ENCODING("i64i8imm", ENCODING_IB) 1123 ENCODING("i8imm", ENCODING_IB) 1124 ENCODING("u8imm", ENCODING_IB) 1125 ENCODING("i32u8imm", ENCODING_IB) 1126 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1127 ENCODING("i16imm_pcrel", ENCODING_IW) 1128 ENCODING("i32imm_pcrel", ENCODING_ID) 1129 ENCODING("brtarget32", ENCODING_Iv) 1130 ENCODING("brtarget16", ENCODING_Iv) 1131 ENCODING("brtarget8", ENCODING_IB) 1132 ENCODING("i64imm", ENCODING_IO) 1133 ENCODING("offset16_8", ENCODING_Ia) 1134 ENCODING("offset16_16", ENCODING_Ia) 1135 ENCODING("offset16_32", ENCODING_Ia) 1136 ENCODING("offset32_8", ENCODING_Ia) 1137 ENCODING("offset32_16", ENCODING_Ia) 1138 ENCODING("offset32_32", ENCODING_Ia) 1139 ENCODING("offset32_64", ENCODING_Ia) 1140 ENCODING("offset64_8", ENCODING_Ia) 1141 ENCODING("offset64_16", ENCODING_Ia) 1142 ENCODING("offset64_32", ENCODING_Ia) 1143 ENCODING("offset64_64", ENCODING_Ia) 1144 ENCODING("srcidx8", ENCODING_SI) 1145 ENCODING("srcidx16", ENCODING_SI) 1146 ENCODING("srcidx32", ENCODING_SI) 1147 ENCODING("srcidx64", ENCODING_SI) 1148 ENCODING("dstidx8", ENCODING_DI) 1149 ENCODING("dstidx16", ENCODING_DI) 1150 ENCODING("dstidx32", ENCODING_DI) 1151 ENCODING("dstidx64", ENCODING_DI) 1152 errs() << "Unhandled relocation encoding " << s << "\n"; 1153 llvm_unreachable("Unhandled relocation encoding"); 1154 } 1155 1156 OperandEncoding 1157 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1158 uint8_t OpSize) { 1159 ENCODING("GR32", ENCODING_Rv) 1160 ENCODING("GR64", ENCODING_RO) 1161 ENCODING("GR16", ENCODING_Rv) 1162 ENCODING("GR8", ENCODING_RB) 1163 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1164 llvm_unreachable("Unhandled opcode modifier encoding"); 1165 } 1166 #undef ENCODING 1167