1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the implementation of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisassemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "X86RecognizableInstr.h" 18 #include "X86DisassemblerShared.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <string> 22 23 using namespace llvm; 24 using namespace X86Disassembler; 25 26 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 27 /// Useful for switch statements and the like. 28 /// 29 /// @param init - A reference to the BitsInit to be decoded. 30 /// @return - The field, with the first bit in the BitsInit as the lowest 31 /// order bit. 32 static uint8_t byteFromBitsInit(BitsInit &init) { 33 int width = init.getNumBits(); 34 35 assert(width <= 8 && "Field is too large for uint8_t!"); 36 37 int index; 38 uint8_t mask = 0x01; 39 40 uint8_t ret = 0; 41 42 for (index = 0; index < width; index++) { 43 if (static_cast<BitInit*>(init.getBit(index))->getValue()) 44 ret |= mask; 45 46 mask <<= 1; 47 } 48 49 return ret; 50 } 51 52 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 53 /// name of the field. 54 /// 55 /// @param rec - The record from which to extract the value. 56 /// @param name - The name of the field in the record. 57 /// @return - The field, as translated by byteFromBitsInit(). 58 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 59 BitsInit* bits = rec->getValueAsBitsInit(name); 60 return byteFromBitsInit(*bits); 61 } 62 63 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 64 const CodeGenInstruction &insn, 65 InstrUID uid) { 66 UID = uid; 67 68 Rec = insn.TheDef; 69 Name = Rec->getName(); 70 Spec = &tables.specForUID(UID); 71 72 if (!Rec->isSubClassOf("X86Inst")) { 73 ShouldBeEmitted = false; 74 return; 75 } 76 77 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 78 OpMap = byteFromRec(Rec, "OpMapBits"); 79 Opcode = byteFromRec(Rec, "Opcode"); 80 Form = byteFromRec(Rec, "FormBits"); 81 Encoding = byteFromRec(Rec, "OpEncBits"); 82 83 OpSize = byteFromRec(Rec, "OpSizeBits"); 84 AdSize = byteFromRec(Rec, "AdSizeBits"); 85 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 86 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 87 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix"); 88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 93 Has3DNow0F0FOpcode = Rec->getValueAsBit("has3DNow0F0FOpcode"); 94 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 95 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 96 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 97 98 Name = Rec->getName(); 99 100 Operands = &insn.Operands.OperandList; 101 102 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 103 104 EncodeRC = HasEVEX_B && 105 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 106 107 // Check for 64-bit inst which does not require REX 108 Is32Bit = false; 109 Is64Bit = false; 110 // FIXME: Is there some better way to check for In64BitMode? 111 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 112 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 113 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 114 Predicates[i]->getName().find("In32Bit") != Name.npos) { 115 Is32Bit = true; 116 break; 117 } 118 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 119 Is64Bit = true; 120 break; 121 } 122 } 123 124 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 125 ShouldBeEmitted = false; 126 return; 127 } 128 129 // Special case since there is no attribute class for 64-bit and VEX 130 if (Name == "VMASKMOVDQU64") { 131 ShouldBeEmitted = false; 132 return; 133 } 134 135 ShouldBeEmitted = true; 136 } 137 138 void RecognizableInstr::processInstr(DisassemblerTables &tables, 139 const CodeGenInstruction &insn, 140 InstrUID uid) 141 { 142 // Ignore "asm parser only" instructions. 143 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 144 return; 145 146 RecognizableInstr recogInstr(tables, insn, uid); 147 148 if (recogInstr.shouldBeEmitted()) { 149 recogInstr.emitInstructionSpecifier(); 150 recogInstr.emitDecodePath(tables); 151 } 152 } 153 154 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 155 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 156 (HasEVEX_KZ ? n##_KZ : \ 157 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 158 159 InstructionContext RecognizableInstr::insnContext() const { 160 InstructionContext insnContext; 161 162 if (Encoding == X86Local::EVEX) { 163 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 164 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 165 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 166 } 167 // VEX_L & VEX_W 168 if (!EncodeRC && HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 169 if (OpPrefix == X86Local::PD) 170 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 171 else if (OpPrefix == X86Local::XS) 172 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 173 else if (OpPrefix == X86Local::XD) 174 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 175 else if (OpPrefix == X86Local::PS) 176 insnContext = EVEX_KB(IC_EVEX_L_W); 177 else { 178 errs() << "Instruction does not use a prefix: " << Name << "\n"; 179 llvm_unreachable("Invalid prefix"); 180 } 181 } else if (!EncodeRC && HasVEX_LPrefix) { 182 // VEX_L 183 if (OpPrefix == X86Local::PD) 184 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 185 else if (OpPrefix == X86Local::XS) 186 insnContext = EVEX_KB(IC_EVEX_L_XS); 187 else if (OpPrefix == X86Local::XD) 188 insnContext = EVEX_KB(IC_EVEX_L_XD); 189 else if (OpPrefix == X86Local::PS) 190 insnContext = EVEX_KB(IC_EVEX_L); 191 else { 192 errs() << "Instruction does not use a prefix: " << Name << "\n"; 193 llvm_unreachable("Invalid prefix"); 194 } 195 } else if (!EncodeRC && HasEVEX_L2Prefix && 196 VEX_WPrefix == X86Local::VEX_W1) { 197 // EVEX_L2 & VEX_W 198 if (OpPrefix == X86Local::PD) 199 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 200 else if (OpPrefix == X86Local::XS) 201 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 202 else if (OpPrefix == X86Local::XD) 203 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 204 else if (OpPrefix == X86Local::PS) 205 insnContext = EVEX_KB(IC_EVEX_L2_W); 206 else { 207 errs() << "Instruction does not use a prefix: " << Name << "\n"; 208 llvm_unreachable("Invalid prefix"); 209 } 210 } else if (!EncodeRC && HasEVEX_L2Prefix) { 211 // EVEX_L2 212 if (OpPrefix == X86Local::PD) 213 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 214 else if (OpPrefix == X86Local::XD) 215 insnContext = EVEX_KB(IC_EVEX_L2_XD); 216 else if (OpPrefix == X86Local::XS) 217 insnContext = EVEX_KB(IC_EVEX_L2_XS); 218 else if (OpPrefix == X86Local::PS) 219 insnContext = EVEX_KB(IC_EVEX_L2); 220 else { 221 errs() << "Instruction does not use a prefix: " << Name << "\n"; 222 llvm_unreachable("Invalid prefix"); 223 } 224 } 225 else if (VEX_WPrefix == X86Local::VEX_W1) { 226 // VEX_W 227 if (OpPrefix == X86Local::PD) 228 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 229 else if (OpPrefix == X86Local::XS) 230 insnContext = EVEX_KB(IC_EVEX_W_XS); 231 else if (OpPrefix == X86Local::XD) 232 insnContext = EVEX_KB(IC_EVEX_W_XD); 233 else if (OpPrefix == X86Local::PS) 234 insnContext = EVEX_KB(IC_EVEX_W); 235 else { 236 errs() << "Instruction does not use a prefix: " << Name << "\n"; 237 llvm_unreachable("Invalid prefix"); 238 } 239 } 240 // No L, no W 241 else if (OpPrefix == X86Local::PD) 242 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 243 else if (OpPrefix == X86Local::XD) 244 insnContext = EVEX_KB(IC_EVEX_XD); 245 else if (OpPrefix == X86Local::XS) 246 insnContext = EVEX_KB(IC_EVEX_XS); 247 else 248 insnContext = EVEX_KB(IC_EVEX); 249 /// eof EVEX 250 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 251 if (HasVEX_LPrefix && VEX_WPrefix == X86Local::VEX_W1) { 252 if (OpPrefix == X86Local::PD) 253 insnContext = IC_VEX_L_W_OPSIZE; 254 else if (OpPrefix == X86Local::XS) 255 insnContext = IC_VEX_L_W_XS; 256 else if (OpPrefix == X86Local::XD) 257 insnContext = IC_VEX_L_W_XD; 258 else if (OpPrefix == X86Local::PS) 259 insnContext = IC_VEX_L_W; 260 else { 261 errs() << "Instruction does not use a prefix: " << Name << "\n"; 262 llvm_unreachable("Invalid prefix"); 263 } 264 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 265 insnContext = IC_VEX_L_OPSIZE; 266 else if (OpPrefix == X86Local::PD && VEX_WPrefix == X86Local::VEX_W1) 267 insnContext = IC_VEX_W_OPSIZE; 268 else if (OpPrefix == X86Local::PD) 269 insnContext = IC_VEX_OPSIZE; 270 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 271 insnContext = IC_VEX_L_XS; 272 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 273 insnContext = IC_VEX_L_XD; 274 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XS) 275 insnContext = IC_VEX_W_XS; 276 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::XD) 277 insnContext = IC_VEX_W_XD; 278 else if (VEX_WPrefix == X86Local::VEX_W1 && OpPrefix == X86Local::PS) 279 insnContext = IC_VEX_W; 280 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 281 insnContext = IC_VEX_L; 282 else if (OpPrefix == X86Local::XD) 283 insnContext = IC_VEX_XD; 284 else if (OpPrefix == X86Local::XS) 285 insnContext = IC_VEX_XS; 286 else if (OpPrefix == X86Local::PS) 287 insnContext = IC_VEX; 288 else { 289 errs() << "Instruction does not use a prefix: " << Name << "\n"; 290 llvm_unreachable("Invalid prefix"); 291 } 292 } else if (Has3DNow0F0FOpcode) { 293 insnContext = IC_3DNOW; 294 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 295 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 296 insnContext = IC_64BIT_REXW_OPSIZE; 297 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 298 insnContext = IC_64BIT_REXW_ADSIZE; 299 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 300 insnContext = IC_64BIT_XD_OPSIZE; 301 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 302 insnContext = IC_64BIT_XS_OPSIZE; 303 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 304 insnContext = IC_64BIT_OPSIZE_ADSIZE; 305 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 306 insnContext = IC_64BIT_OPSIZE; 307 else if (AdSize == X86Local::AdSize32) 308 insnContext = IC_64BIT_ADSIZE; 309 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 310 insnContext = IC_64BIT_REXW_XS; 311 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 312 insnContext = IC_64BIT_REXW_XD; 313 else if (OpPrefix == X86Local::XD) 314 insnContext = IC_64BIT_XD; 315 else if (OpPrefix == X86Local::XS) 316 insnContext = IC_64BIT_XS; 317 else if (HasREX_WPrefix) 318 insnContext = IC_64BIT_REXW; 319 else 320 insnContext = IC_64BIT; 321 } else { 322 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 323 insnContext = IC_XD_OPSIZE; 324 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 325 insnContext = IC_XS_OPSIZE; 326 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 327 insnContext = IC_OPSIZE_ADSIZE; 328 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 329 insnContext = IC_OPSIZE; 330 else if (AdSize == X86Local::AdSize16) 331 insnContext = IC_ADSIZE; 332 else if (OpPrefix == X86Local::XD) 333 insnContext = IC_XD; 334 else if (OpPrefix == X86Local::XS) 335 insnContext = IC_XS; 336 else 337 insnContext = IC; 338 } 339 340 return insnContext; 341 } 342 343 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 344 // The scaling factor for AVX512 compressed displacement encoding is an 345 // instruction attribute. Adjust the ModRM encoding type to include the 346 // scale for compressed displacement. 347 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 348 return; 349 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 350 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 351 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 352 "Invalid CDisp scaling"); 353 } 354 355 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 356 unsigned &physicalOperandIndex, 357 unsigned numPhysicalOperands, 358 const unsigned *operandMapping, 359 OperandEncoding (*encodingFromString) 360 (const std::string&, 361 uint8_t OpSize)) { 362 if (optional) { 363 if (physicalOperandIndex >= numPhysicalOperands) 364 return; 365 } else { 366 assert(physicalOperandIndex < numPhysicalOperands); 367 } 368 369 while (operandMapping[operandIndex] != operandIndex) { 370 Spec->operands[operandIndex].encoding = ENCODING_DUP; 371 Spec->operands[operandIndex].type = 372 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 373 ++operandIndex; 374 } 375 376 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 377 378 OperandEncoding encoding = encodingFromString(typeName, OpSize); 379 // Adjust the encoding type for an operand based on the instruction. 380 adjustOperandEncoding(encoding); 381 Spec->operands[operandIndex].encoding = encoding; 382 Spec->operands[operandIndex].type = typeFromString(typeName, 383 HasREX_WPrefix, OpSize); 384 385 ++operandIndex; 386 ++physicalOperandIndex; 387 } 388 389 void RecognizableInstr::emitInstructionSpecifier() { 390 Spec->name = Name; 391 392 Spec->insnContext = insnContext(); 393 394 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 395 396 unsigned numOperands = OperandList.size(); 397 unsigned numPhysicalOperands = 0; 398 399 // operandMapping maps from operands in OperandList to their originals. 400 // If operandMapping[i] != i, then the entry is a duplicate. 401 unsigned operandMapping[X86_MAX_OPERANDS]; 402 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 403 404 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 405 if (!OperandList[operandIndex].Constraints.empty()) { 406 const CGIOperandList::ConstraintInfo &Constraint = 407 OperandList[operandIndex].Constraints[0]; 408 if (Constraint.isTied()) { 409 operandMapping[operandIndex] = operandIndex; 410 operandMapping[Constraint.getTiedOperand()] = operandIndex; 411 } else { 412 ++numPhysicalOperands; 413 operandMapping[operandIndex] = operandIndex; 414 } 415 } else { 416 ++numPhysicalOperands; 417 operandMapping[operandIndex] = operandIndex; 418 } 419 } 420 421 #define HANDLE_OPERAND(class) \ 422 handleOperand(false, \ 423 operandIndex, \ 424 physicalOperandIndex, \ 425 numPhysicalOperands, \ 426 operandMapping, \ 427 class##EncodingFromString); 428 429 #define HANDLE_OPTIONAL(class) \ 430 handleOperand(true, \ 431 operandIndex, \ 432 physicalOperandIndex, \ 433 numPhysicalOperands, \ 434 operandMapping, \ 435 class##EncodingFromString); 436 437 // operandIndex should always be < numOperands 438 unsigned operandIndex = 0; 439 // physicalOperandIndex should always be < numPhysicalOperands 440 unsigned physicalOperandIndex = 0; 441 442 #ifndef NDEBUG 443 // Given the set of prefix bits, how many additional operands does the 444 // instruction have? 445 unsigned additionalOperands = 0; 446 if (HasVEX_4V) 447 ++additionalOperands; 448 if (HasEVEX_K) 449 ++additionalOperands; 450 #endif 451 452 switch (Form) { 453 default: llvm_unreachable("Unhandled form"); 454 case X86Local::RawFrmSrc: 455 HANDLE_OPERAND(relocation); 456 return; 457 case X86Local::RawFrmDst: 458 HANDLE_OPERAND(relocation); 459 return; 460 case X86Local::RawFrmDstSrc: 461 HANDLE_OPERAND(relocation); 462 HANDLE_OPERAND(relocation); 463 return; 464 case X86Local::RawFrm: 465 // Operand 1 (optional) is an address or immediate. 466 assert(numPhysicalOperands <= 1 && 467 "Unexpected number of operands for RawFrm"); 468 HANDLE_OPTIONAL(relocation) 469 break; 470 case X86Local::RawFrmMemOffs: 471 // Operand 1 is an address. 472 HANDLE_OPERAND(relocation); 473 break; 474 case X86Local::AddRegFrm: 475 // Operand 1 is added to the opcode. 476 // Operand 2 (optional) is an address. 477 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 478 "Unexpected number of operands for AddRegFrm"); 479 HANDLE_OPERAND(opcodeModifier) 480 HANDLE_OPTIONAL(relocation) 481 break; 482 case X86Local::MRMDestReg: 483 // Operand 1 is a register operand in the R/M field. 484 // - In AVX512 there may be a mask operand here - 485 // Operand 2 is a register operand in the Reg/Opcode field. 486 // - In AVX, there is a register operand in the VEX.vvvv field here - 487 // Operand 3 (optional) is an immediate. 488 assert(numPhysicalOperands >= 2 + additionalOperands && 489 numPhysicalOperands <= 3 + additionalOperands && 490 "Unexpected number of operands for MRMDestRegFrm"); 491 492 HANDLE_OPERAND(rmRegister) 493 if (HasEVEX_K) 494 HANDLE_OPERAND(writemaskRegister) 495 496 if (HasVEX_4V) 497 // FIXME: In AVX, the register below becomes the one encoded 498 // in ModRMVEX and the one above the one in the VEX.VVVV field 499 HANDLE_OPERAND(vvvvRegister) 500 501 HANDLE_OPERAND(roRegister) 502 HANDLE_OPTIONAL(immediate) 503 break; 504 case X86Local::MRMDestMem: 505 // Operand 1 is a memory operand (possibly SIB-extended) 506 // Operand 2 is a register operand in the Reg/Opcode field. 507 // - In AVX, there is a register operand in the VEX.vvvv field here - 508 // Operand 3 (optional) is an immediate. 509 assert(numPhysicalOperands >= 2 + additionalOperands && 510 numPhysicalOperands <= 3 + additionalOperands && 511 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 512 513 HANDLE_OPERAND(memory) 514 515 if (HasEVEX_K) 516 HANDLE_OPERAND(writemaskRegister) 517 518 if (HasVEX_4V) 519 // FIXME: In AVX, the register below becomes the one encoded 520 // in ModRMVEX and the one above the one in the VEX.VVVV field 521 HANDLE_OPERAND(vvvvRegister) 522 523 HANDLE_OPERAND(roRegister) 524 HANDLE_OPTIONAL(immediate) 525 break; 526 case X86Local::MRMSrcReg: 527 // Operand 1 is a register operand in the Reg/Opcode field. 528 // Operand 2 is a register operand in the R/M field. 529 // - In AVX, there is a register operand in the VEX.vvvv field here - 530 // Operand 3 (optional) is an immediate. 531 // Operand 4 (optional) is an immediate. 532 533 assert(numPhysicalOperands >= 2 + additionalOperands && 534 numPhysicalOperands <= 4 + additionalOperands && 535 "Unexpected number of operands for MRMSrcRegFrm"); 536 537 HANDLE_OPERAND(roRegister) 538 539 if (HasEVEX_K) 540 HANDLE_OPERAND(writemaskRegister) 541 542 if (HasVEX_4V) 543 // FIXME: In AVX, the register below becomes the one encoded 544 // in ModRMVEX and the one above the one in the VEX.VVVV field 545 HANDLE_OPERAND(vvvvRegister) 546 547 HANDLE_OPERAND(rmRegister) 548 HANDLE_OPTIONAL(immediate) 549 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 550 HANDLE_OPTIONAL(immediate) 551 break; 552 case X86Local::MRMSrcReg4VOp3: 553 assert(numPhysicalOperands == 3 && 554 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 555 HANDLE_OPERAND(roRegister) 556 HANDLE_OPERAND(rmRegister) 557 HANDLE_OPERAND(vvvvRegister) 558 break; 559 case X86Local::MRMSrcRegOp4: 560 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 561 "Unexpected number of operands for MRMSrcRegOp4Frm"); 562 HANDLE_OPERAND(roRegister) 563 HANDLE_OPERAND(vvvvRegister) 564 HANDLE_OPERAND(immediate) // Register in imm[7:4] 565 HANDLE_OPERAND(rmRegister) 566 HANDLE_OPTIONAL(immediate) 567 break; 568 case X86Local::MRMSrcMem: 569 // Operand 1 is a register operand in the Reg/Opcode field. 570 // Operand 2 is a memory operand (possibly SIB-extended) 571 // - In AVX, there is a register operand in the VEX.vvvv field here - 572 // Operand 3 (optional) is an immediate. 573 574 assert(numPhysicalOperands >= 2 + additionalOperands && 575 numPhysicalOperands <= 4 + additionalOperands && 576 "Unexpected number of operands for MRMSrcMemFrm"); 577 578 HANDLE_OPERAND(roRegister) 579 580 if (HasEVEX_K) 581 HANDLE_OPERAND(writemaskRegister) 582 583 if (HasVEX_4V) 584 // FIXME: In AVX, the register below becomes the one encoded 585 // in ModRMVEX and the one above the one in the VEX.VVVV field 586 HANDLE_OPERAND(vvvvRegister) 587 588 HANDLE_OPERAND(memory) 589 HANDLE_OPTIONAL(immediate) 590 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 591 break; 592 case X86Local::MRMSrcMem4VOp3: 593 assert(numPhysicalOperands == 3 && 594 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 595 HANDLE_OPERAND(roRegister) 596 HANDLE_OPERAND(memory) 597 HANDLE_OPERAND(vvvvRegister) 598 break; 599 case X86Local::MRMSrcMemOp4: 600 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 601 "Unexpected number of operands for MRMSrcMemOp4Frm"); 602 HANDLE_OPERAND(roRegister) 603 HANDLE_OPERAND(vvvvRegister) 604 HANDLE_OPERAND(immediate) // Register in imm[7:4] 605 HANDLE_OPERAND(memory) 606 HANDLE_OPTIONAL(immediate) 607 break; 608 case X86Local::MRMXr: 609 case X86Local::MRM0r: 610 case X86Local::MRM1r: 611 case X86Local::MRM2r: 612 case X86Local::MRM3r: 613 case X86Local::MRM4r: 614 case X86Local::MRM5r: 615 case X86Local::MRM6r: 616 case X86Local::MRM7r: 617 // Operand 1 is a register operand in the R/M field. 618 // Operand 2 (optional) is an immediate or relocation. 619 // Operand 3 (optional) is an immediate. 620 assert(numPhysicalOperands >= 0 + additionalOperands && 621 numPhysicalOperands <= 3 + additionalOperands && 622 "Unexpected number of operands for MRMnr"); 623 624 if (HasVEX_4V) 625 HANDLE_OPERAND(vvvvRegister) 626 627 if (HasEVEX_K) 628 HANDLE_OPERAND(writemaskRegister) 629 HANDLE_OPTIONAL(rmRegister) 630 HANDLE_OPTIONAL(relocation) 631 HANDLE_OPTIONAL(immediate) 632 break; 633 case X86Local::MRMXm: 634 case X86Local::MRM0m: 635 case X86Local::MRM1m: 636 case X86Local::MRM2m: 637 case X86Local::MRM3m: 638 case X86Local::MRM4m: 639 case X86Local::MRM5m: 640 case X86Local::MRM6m: 641 case X86Local::MRM7m: 642 // Operand 1 is a memory operand (possibly SIB-extended) 643 // Operand 2 (optional) is an immediate or relocation. 644 assert(numPhysicalOperands >= 1 + additionalOperands && 645 numPhysicalOperands <= 2 + additionalOperands && 646 "Unexpected number of operands for MRMnm"); 647 648 if (HasVEX_4V) 649 HANDLE_OPERAND(vvvvRegister) 650 if (HasEVEX_K) 651 HANDLE_OPERAND(writemaskRegister) 652 HANDLE_OPERAND(memory) 653 HANDLE_OPTIONAL(relocation) 654 break; 655 case X86Local::RawFrmImm8: 656 // operand 1 is a 16-bit immediate 657 // operand 2 is an 8-bit immediate 658 assert(numPhysicalOperands == 2 && 659 "Unexpected number of operands for X86Local::RawFrmImm8"); 660 HANDLE_OPERAND(immediate) 661 HANDLE_OPERAND(immediate) 662 break; 663 case X86Local::RawFrmImm16: 664 // operand 1 is a 16-bit immediate 665 // operand 2 is a 16-bit immediate 666 HANDLE_OPERAND(immediate) 667 HANDLE_OPERAND(immediate) 668 break; 669 case X86Local::MRM_F8: 670 if (Opcode == 0xc6) { 671 assert(numPhysicalOperands == 1 && 672 "Unexpected number of operands for X86Local::MRM_F8"); 673 HANDLE_OPERAND(immediate) 674 } else if (Opcode == 0xc7) { 675 assert(numPhysicalOperands == 1 && 676 "Unexpected number of operands for X86Local::MRM_F8"); 677 HANDLE_OPERAND(relocation) 678 } 679 break; 680 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: 681 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: 682 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: 683 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1: 684 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6: 685 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9: 686 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC: 687 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF: 688 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2: 689 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5: 690 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA: 691 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED: 692 case X86Local::MRM_EE: case X86Local::MRM_EF: case X86Local::MRM_F0: 693 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: 694 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: 695 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: 696 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: 697 case X86Local::MRM_FE: case X86Local::MRM_FF: 698 // Ignored. 699 break; 700 } 701 702 #undef HANDLE_OPERAND 703 #undef HANDLE_OPTIONAL 704 } 705 706 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 707 // Special cases where the LLVM tables are not complete 708 709 #define MAP(from, to) \ 710 case X86Local::MRM_##from: 711 712 llvm::Optional<OpcodeType> opcodeType; 713 714 ModRMFilter* filter = nullptr; 715 uint8_t opcodeToSet = 0; 716 717 switch (OpMap) { 718 default: llvm_unreachable("Invalid map!"); 719 case X86Local::OB: 720 case X86Local::TB: 721 case X86Local::T8: 722 case X86Local::TA: 723 case X86Local::XOP8: 724 case X86Local::XOP9: 725 case X86Local::XOPA: 726 switch (OpMap) { 727 default: llvm_unreachable("Unexpected map!"); 728 case X86Local::OB: opcodeType = ONEBYTE; break; 729 case X86Local::TB: opcodeType = TWOBYTE; break; 730 case X86Local::T8: opcodeType = THREEBYTE_38; break; 731 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 732 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 733 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 734 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 735 } 736 737 switch (Form) { 738 default: llvm_unreachable("Invalid form!"); 739 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 740 case X86Local::RawFrm: 741 case X86Local::AddRegFrm: 742 case X86Local::RawFrmMemOffs: 743 case X86Local::RawFrmSrc: 744 case X86Local::RawFrmDst: 745 case X86Local::RawFrmDstSrc: 746 case X86Local::RawFrmImm8: 747 case X86Local::RawFrmImm16: 748 filter = new DumbFilter(); 749 break; 750 case X86Local::MRMDestReg: 751 case X86Local::MRMSrcReg: 752 case X86Local::MRMSrcReg4VOp3: 753 case X86Local::MRMSrcRegOp4: 754 case X86Local::MRMXr: 755 filter = new ModFilter(true); 756 break; 757 case X86Local::MRMDestMem: 758 case X86Local::MRMSrcMem: 759 case X86Local::MRMSrcMem4VOp3: 760 case X86Local::MRMSrcMemOp4: 761 case X86Local::MRMXm: 762 filter = new ModFilter(false); 763 break; 764 case X86Local::MRM0r: case X86Local::MRM1r: 765 case X86Local::MRM2r: case X86Local::MRM3r: 766 case X86Local::MRM4r: case X86Local::MRM5r: 767 case X86Local::MRM6r: case X86Local::MRM7r: 768 filter = new ExtendedFilter(true, Form - X86Local::MRM0r); 769 break; 770 case X86Local::MRM0m: case X86Local::MRM1m: 771 case X86Local::MRM2m: case X86Local::MRM3m: 772 case X86Local::MRM4m: case X86Local::MRM5m: 773 case X86Local::MRM6m: case X86Local::MRM7m: 774 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); 775 break; 776 X86_INSTR_MRM_MAPPING 777 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \ 778 break; 779 } // switch (Form) 780 781 opcodeToSet = Opcode; 782 break; 783 } // switch (OpMap) 784 785 unsigned AddressSize = 0; 786 switch (AdSize) { 787 case X86Local::AdSize16: AddressSize = 16; break; 788 case X86Local::AdSize32: AddressSize = 32; break; 789 case X86Local::AdSize64: AddressSize = 64; break; 790 } 791 792 assert(opcodeType && "Opcode type not set"); 793 assert(filter && "Filter not set"); 794 795 if (Form == X86Local::AddRegFrm) { 796 assert(((opcodeToSet & 7) == 0) && 797 "ADDREG_FRM opcode not aligned"); 798 799 uint8_t currentOpcode; 800 801 for (currentOpcode = opcodeToSet; 802 currentOpcode < opcodeToSet + 8; 803 ++currentOpcode) 804 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 805 UID, Is32Bit, OpPrefix == 0, 806 IgnoresVEX_L || EncodeRC, 807 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 808 } else { 809 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 810 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 811 VEX_WPrefix == X86Local::VEX_WIG, AddressSize); 812 } 813 814 delete filter; 815 816 #undef MAP 817 } 818 819 #define TYPE(str, type) if (s == str) return type; 820 OperandType RecognizableInstr::typeFromString(const std::string &s, 821 bool hasREX_WPrefix, 822 uint8_t OpSize) { 823 if(hasREX_WPrefix) { 824 // For instructions with a REX_W prefix, a declared 32-bit register encoding 825 // is special. 826 TYPE("GR32", TYPE_R32) 827 } 828 if(OpSize == X86Local::OpSize16) { 829 // For OpSize16 instructions, a declared 16-bit register or 830 // immediate encoding is special. 831 TYPE("GR16", TYPE_Rv) 832 } else if(OpSize == X86Local::OpSize32) { 833 // For OpSize32 instructions, a declared 32-bit register or 834 // immediate encoding is special. 835 TYPE("GR32", TYPE_Rv) 836 } 837 TYPE("i16mem", TYPE_M) 838 TYPE("i16imm", TYPE_IMM) 839 TYPE("i16i8imm", TYPE_IMM) 840 TYPE("GR16", TYPE_R16) 841 TYPE("i32mem", TYPE_M) 842 TYPE("i32imm", TYPE_IMM) 843 TYPE("i32i8imm", TYPE_IMM) 844 TYPE("GR32", TYPE_R32) 845 TYPE("GR32orGR64", TYPE_R32) 846 TYPE("i64mem", TYPE_M) 847 TYPE("i64i32imm", TYPE_IMM) 848 TYPE("i64i8imm", TYPE_IMM) 849 TYPE("GR64", TYPE_R64) 850 TYPE("i8mem", TYPE_M) 851 TYPE("i8imm", TYPE_IMM) 852 TYPE("u8imm", TYPE_UIMM8) 853 TYPE("i32u8imm", TYPE_UIMM8) 854 TYPE("GR8", TYPE_R8) 855 TYPE("VR128", TYPE_XMM) 856 TYPE("VR128X", TYPE_XMM) 857 TYPE("f128mem", TYPE_M) 858 TYPE("f256mem", TYPE_M) 859 TYPE("f512mem", TYPE_M) 860 TYPE("FR128", TYPE_XMM) 861 TYPE("FR64", TYPE_XMM) 862 TYPE("FR64X", TYPE_XMM) 863 TYPE("f64mem", TYPE_M) 864 TYPE("sdmem", TYPE_M) 865 TYPE("FR32", TYPE_XMM) 866 TYPE("FR32X", TYPE_XMM) 867 TYPE("f32mem", TYPE_M) 868 TYPE("ssmem", TYPE_M) 869 TYPE("RST", TYPE_ST) 870 TYPE("i128mem", TYPE_M) 871 TYPE("i256mem", TYPE_M) 872 TYPE("i512mem", TYPE_M) 873 TYPE("i64i32imm_pcrel", TYPE_REL) 874 TYPE("i16imm_pcrel", TYPE_REL) 875 TYPE("i32imm_pcrel", TYPE_REL) 876 TYPE("SSECC", TYPE_IMM3) 877 TYPE("XOPCC", TYPE_IMM3) 878 TYPE("AVXCC", TYPE_IMM5) 879 TYPE("AVX512ICC", TYPE_AVX512ICC) 880 TYPE("AVX512RC", TYPE_IMM) 881 TYPE("brtarget32", TYPE_REL) 882 TYPE("brtarget16", TYPE_REL) 883 TYPE("brtarget8", TYPE_REL) 884 TYPE("f80mem", TYPE_M) 885 TYPE("lea64_32mem", TYPE_M) 886 TYPE("lea64mem", TYPE_M) 887 TYPE("VR64", TYPE_MM64) 888 TYPE("i64imm", TYPE_IMM) 889 TYPE("anymem", TYPE_M) 890 TYPE("opaque32mem", TYPE_M) 891 TYPE("opaque48mem", TYPE_M) 892 TYPE("opaque80mem", TYPE_M) 893 TYPE("opaque512mem", TYPE_M) 894 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 895 TYPE("DEBUG_REG", TYPE_DEBUGREG) 896 TYPE("CONTROL_REG", TYPE_CONTROLREG) 897 TYPE("srcidx8", TYPE_SRCIDX) 898 TYPE("srcidx16", TYPE_SRCIDX) 899 TYPE("srcidx32", TYPE_SRCIDX) 900 TYPE("srcidx64", TYPE_SRCIDX) 901 TYPE("dstidx8", TYPE_DSTIDX) 902 TYPE("dstidx16", TYPE_DSTIDX) 903 TYPE("dstidx32", TYPE_DSTIDX) 904 TYPE("dstidx64", TYPE_DSTIDX) 905 TYPE("offset16_8", TYPE_MOFFS) 906 TYPE("offset16_16", TYPE_MOFFS) 907 TYPE("offset16_32", TYPE_MOFFS) 908 TYPE("offset32_8", TYPE_MOFFS) 909 TYPE("offset32_16", TYPE_MOFFS) 910 TYPE("offset32_32", TYPE_MOFFS) 911 TYPE("offset32_64", TYPE_MOFFS) 912 TYPE("offset64_8", TYPE_MOFFS) 913 TYPE("offset64_16", TYPE_MOFFS) 914 TYPE("offset64_32", TYPE_MOFFS) 915 TYPE("offset64_64", TYPE_MOFFS) 916 TYPE("VR256", TYPE_YMM) 917 TYPE("VR256X", TYPE_YMM) 918 TYPE("VR512", TYPE_ZMM) 919 TYPE("VK1", TYPE_VK) 920 TYPE("VK1WM", TYPE_VK) 921 TYPE("VK2", TYPE_VK) 922 TYPE("VK2WM", TYPE_VK) 923 TYPE("VK4", TYPE_VK) 924 TYPE("VK4WM", TYPE_VK) 925 TYPE("VK8", TYPE_VK) 926 TYPE("VK8WM", TYPE_VK) 927 TYPE("VK16", TYPE_VK) 928 TYPE("VK16WM", TYPE_VK) 929 TYPE("VK32", TYPE_VK) 930 TYPE("VK32WM", TYPE_VK) 931 TYPE("VK64", TYPE_VK) 932 TYPE("VK64WM", TYPE_VK) 933 TYPE("vx64mem", TYPE_MVSIBX) 934 TYPE("vx128mem", TYPE_MVSIBX) 935 TYPE("vx256mem", TYPE_MVSIBX) 936 TYPE("vy128mem", TYPE_MVSIBY) 937 TYPE("vy256mem", TYPE_MVSIBY) 938 TYPE("vx64xmem", TYPE_MVSIBX) 939 TYPE("vx128xmem", TYPE_MVSIBX) 940 TYPE("vx256xmem", TYPE_MVSIBX) 941 TYPE("vy128xmem", TYPE_MVSIBY) 942 TYPE("vy256xmem", TYPE_MVSIBY) 943 TYPE("vy512mem", TYPE_MVSIBY) 944 TYPE("vz256xmem", TYPE_MVSIBZ) 945 TYPE("vz512mem", TYPE_MVSIBZ) 946 TYPE("BNDR", TYPE_BNDR) 947 errs() << "Unhandled type string " << s << "\n"; 948 llvm_unreachable("Unhandled type string"); 949 } 950 #undef TYPE 951 952 #define ENCODING(str, encoding) if (s == str) return encoding; 953 OperandEncoding 954 RecognizableInstr::immediateEncodingFromString(const std::string &s, 955 uint8_t OpSize) { 956 if(OpSize != X86Local::OpSize16) { 957 // For instructions without an OpSize prefix, a declared 16-bit register or 958 // immediate encoding is special. 959 ENCODING("i16imm", ENCODING_IW) 960 } 961 ENCODING("i32i8imm", ENCODING_IB) 962 ENCODING("SSECC", ENCODING_IB) 963 ENCODING("XOPCC", ENCODING_IB) 964 ENCODING("AVXCC", ENCODING_IB) 965 ENCODING("AVX512ICC", ENCODING_IB) 966 ENCODING("AVX512RC", ENCODING_IRC) 967 ENCODING("i16imm", ENCODING_Iv) 968 ENCODING("i16i8imm", ENCODING_IB) 969 ENCODING("i32imm", ENCODING_Iv) 970 ENCODING("i64i32imm", ENCODING_ID) 971 ENCODING("i64i8imm", ENCODING_IB) 972 ENCODING("i8imm", ENCODING_IB) 973 ENCODING("u8imm", ENCODING_IB) 974 ENCODING("i32u8imm", ENCODING_IB) 975 // This is not a typo. Instructions like BLENDVPD put 976 // register IDs in 8-bit immediates nowadays. 977 ENCODING("FR32", ENCODING_IB) 978 ENCODING("FR64", ENCODING_IB) 979 ENCODING("FR128", ENCODING_IB) 980 ENCODING("VR128", ENCODING_IB) 981 ENCODING("VR256", ENCODING_IB) 982 ENCODING("FR32X", ENCODING_IB) 983 ENCODING("FR64X", ENCODING_IB) 984 ENCODING("VR128X", ENCODING_IB) 985 ENCODING("VR256X", ENCODING_IB) 986 ENCODING("VR512", ENCODING_IB) 987 errs() << "Unhandled immediate encoding " << s << "\n"; 988 llvm_unreachable("Unhandled immediate encoding"); 989 } 990 991 OperandEncoding 992 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 993 uint8_t OpSize) { 994 ENCODING("RST", ENCODING_FP) 995 ENCODING("GR16", ENCODING_RM) 996 ENCODING("GR32", ENCODING_RM) 997 ENCODING("GR32orGR64", ENCODING_RM) 998 ENCODING("GR64", ENCODING_RM) 999 ENCODING("GR8", ENCODING_RM) 1000 ENCODING("VR128", ENCODING_RM) 1001 ENCODING("VR128X", ENCODING_RM) 1002 ENCODING("FR128", ENCODING_RM) 1003 ENCODING("FR64", ENCODING_RM) 1004 ENCODING("FR32", ENCODING_RM) 1005 ENCODING("FR64X", ENCODING_RM) 1006 ENCODING("FR32X", ENCODING_RM) 1007 ENCODING("VR64", ENCODING_RM) 1008 ENCODING("VR256", ENCODING_RM) 1009 ENCODING("VR256X", ENCODING_RM) 1010 ENCODING("VR512", ENCODING_RM) 1011 ENCODING("VK1", ENCODING_RM) 1012 ENCODING("VK2", ENCODING_RM) 1013 ENCODING("VK4", ENCODING_RM) 1014 ENCODING("VK8", ENCODING_RM) 1015 ENCODING("VK16", ENCODING_RM) 1016 ENCODING("VK32", ENCODING_RM) 1017 ENCODING("VK64", ENCODING_RM) 1018 ENCODING("BNDR", ENCODING_RM) 1019 errs() << "Unhandled R/M register encoding " << s << "\n"; 1020 llvm_unreachable("Unhandled R/M register encoding"); 1021 } 1022 1023 OperandEncoding 1024 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1025 uint8_t OpSize) { 1026 ENCODING("GR16", ENCODING_REG) 1027 ENCODING("GR32", ENCODING_REG) 1028 ENCODING("GR32orGR64", ENCODING_REG) 1029 ENCODING("GR64", ENCODING_REG) 1030 ENCODING("GR8", ENCODING_REG) 1031 ENCODING("VR128", ENCODING_REG) 1032 ENCODING("FR128", ENCODING_REG) 1033 ENCODING("FR64", ENCODING_REG) 1034 ENCODING("FR32", ENCODING_REG) 1035 ENCODING("VR64", ENCODING_REG) 1036 ENCODING("SEGMENT_REG", ENCODING_REG) 1037 ENCODING("DEBUG_REG", ENCODING_REG) 1038 ENCODING("CONTROL_REG", ENCODING_REG) 1039 ENCODING("VR256", ENCODING_REG) 1040 ENCODING("VR256X", ENCODING_REG) 1041 ENCODING("VR128X", ENCODING_REG) 1042 ENCODING("FR64X", ENCODING_REG) 1043 ENCODING("FR32X", ENCODING_REG) 1044 ENCODING("VR512", ENCODING_REG) 1045 ENCODING("VK1", ENCODING_REG) 1046 ENCODING("VK2", ENCODING_REG) 1047 ENCODING("VK4", ENCODING_REG) 1048 ENCODING("VK8", ENCODING_REG) 1049 ENCODING("VK16", ENCODING_REG) 1050 ENCODING("VK32", ENCODING_REG) 1051 ENCODING("VK64", ENCODING_REG) 1052 ENCODING("VK1WM", ENCODING_REG) 1053 ENCODING("VK2WM", ENCODING_REG) 1054 ENCODING("VK4WM", ENCODING_REG) 1055 ENCODING("VK8WM", ENCODING_REG) 1056 ENCODING("VK16WM", ENCODING_REG) 1057 ENCODING("VK32WM", ENCODING_REG) 1058 ENCODING("VK64WM", ENCODING_REG) 1059 ENCODING("BNDR", ENCODING_REG) 1060 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1061 llvm_unreachable("Unhandled reg/opcode register encoding"); 1062 } 1063 1064 OperandEncoding 1065 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1066 uint8_t OpSize) { 1067 ENCODING("GR32", ENCODING_VVVV) 1068 ENCODING("GR64", ENCODING_VVVV) 1069 ENCODING("FR32", ENCODING_VVVV) 1070 ENCODING("FR128", ENCODING_VVVV) 1071 ENCODING("FR64", ENCODING_VVVV) 1072 ENCODING("VR128", ENCODING_VVVV) 1073 ENCODING("VR256", ENCODING_VVVV) 1074 ENCODING("FR32X", ENCODING_VVVV) 1075 ENCODING("FR64X", ENCODING_VVVV) 1076 ENCODING("VR128X", ENCODING_VVVV) 1077 ENCODING("VR256X", ENCODING_VVVV) 1078 ENCODING("VR512", ENCODING_VVVV) 1079 ENCODING("VK1", ENCODING_VVVV) 1080 ENCODING("VK2", ENCODING_VVVV) 1081 ENCODING("VK4", ENCODING_VVVV) 1082 ENCODING("VK8", ENCODING_VVVV) 1083 ENCODING("VK16", ENCODING_VVVV) 1084 ENCODING("VK32", ENCODING_VVVV) 1085 ENCODING("VK64", ENCODING_VVVV) 1086 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1087 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1088 } 1089 1090 OperandEncoding 1091 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1092 uint8_t OpSize) { 1093 ENCODING("VK1WM", ENCODING_WRITEMASK) 1094 ENCODING("VK2WM", ENCODING_WRITEMASK) 1095 ENCODING("VK4WM", ENCODING_WRITEMASK) 1096 ENCODING("VK8WM", ENCODING_WRITEMASK) 1097 ENCODING("VK16WM", ENCODING_WRITEMASK) 1098 ENCODING("VK32WM", ENCODING_WRITEMASK) 1099 ENCODING("VK64WM", ENCODING_WRITEMASK) 1100 errs() << "Unhandled mask register encoding " << s << "\n"; 1101 llvm_unreachable("Unhandled mask register encoding"); 1102 } 1103 1104 OperandEncoding 1105 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1106 uint8_t OpSize) { 1107 ENCODING("i16mem", ENCODING_RM) 1108 ENCODING("i32mem", ENCODING_RM) 1109 ENCODING("i64mem", ENCODING_RM) 1110 ENCODING("i8mem", ENCODING_RM) 1111 ENCODING("ssmem", ENCODING_RM) 1112 ENCODING("sdmem", ENCODING_RM) 1113 ENCODING("f128mem", ENCODING_RM) 1114 ENCODING("f256mem", ENCODING_RM) 1115 ENCODING("f512mem", ENCODING_RM) 1116 ENCODING("f64mem", ENCODING_RM) 1117 ENCODING("f32mem", ENCODING_RM) 1118 ENCODING("i128mem", ENCODING_RM) 1119 ENCODING("i256mem", ENCODING_RM) 1120 ENCODING("i512mem", ENCODING_RM) 1121 ENCODING("f80mem", ENCODING_RM) 1122 ENCODING("lea64_32mem", ENCODING_RM) 1123 ENCODING("lea64mem", ENCODING_RM) 1124 ENCODING("anymem", ENCODING_RM) 1125 ENCODING("opaque32mem", ENCODING_RM) 1126 ENCODING("opaque48mem", ENCODING_RM) 1127 ENCODING("opaque80mem", ENCODING_RM) 1128 ENCODING("opaque512mem", ENCODING_RM) 1129 ENCODING("vx64mem", ENCODING_VSIB) 1130 ENCODING("vx128mem", ENCODING_VSIB) 1131 ENCODING("vx256mem", ENCODING_VSIB) 1132 ENCODING("vy128mem", ENCODING_VSIB) 1133 ENCODING("vy256mem", ENCODING_VSIB) 1134 ENCODING("vx64xmem", ENCODING_VSIB) 1135 ENCODING("vx128xmem", ENCODING_VSIB) 1136 ENCODING("vx256xmem", ENCODING_VSIB) 1137 ENCODING("vy128xmem", ENCODING_VSIB) 1138 ENCODING("vy256xmem", ENCODING_VSIB) 1139 ENCODING("vy512mem", ENCODING_VSIB) 1140 ENCODING("vz256xmem", ENCODING_VSIB) 1141 ENCODING("vz512mem", ENCODING_VSIB) 1142 errs() << "Unhandled memory encoding " << s << "\n"; 1143 llvm_unreachable("Unhandled memory encoding"); 1144 } 1145 1146 OperandEncoding 1147 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1148 uint8_t OpSize) { 1149 if(OpSize != X86Local::OpSize16) { 1150 // For instructions without an OpSize prefix, a declared 16-bit register or 1151 // immediate encoding is special. 1152 ENCODING("i16imm", ENCODING_IW) 1153 } 1154 ENCODING("i16imm", ENCODING_Iv) 1155 ENCODING("i16i8imm", ENCODING_IB) 1156 ENCODING("i32imm", ENCODING_Iv) 1157 ENCODING("i32i8imm", ENCODING_IB) 1158 ENCODING("i64i32imm", ENCODING_ID) 1159 ENCODING("i64i8imm", ENCODING_IB) 1160 ENCODING("i8imm", ENCODING_IB) 1161 ENCODING("u8imm", ENCODING_IB) 1162 ENCODING("i32u8imm", ENCODING_IB) 1163 ENCODING("i64i32imm_pcrel", ENCODING_ID) 1164 ENCODING("i16imm_pcrel", ENCODING_IW) 1165 ENCODING("i32imm_pcrel", ENCODING_ID) 1166 ENCODING("brtarget32", ENCODING_Iv) 1167 ENCODING("brtarget16", ENCODING_Iv) 1168 ENCODING("brtarget8", ENCODING_IB) 1169 ENCODING("i64imm", ENCODING_IO) 1170 ENCODING("offset16_8", ENCODING_Ia) 1171 ENCODING("offset16_16", ENCODING_Ia) 1172 ENCODING("offset16_32", ENCODING_Ia) 1173 ENCODING("offset32_8", ENCODING_Ia) 1174 ENCODING("offset32_16", ENCODING_Ia) 1175 ENCODING("offset32_32", ENCODING_Ia) 1176 ENCODING("offset32_64", ENCODING_Ia) 1177 ENCODING("offset64_8", ENCODING_Ia) 1178 ENCODING("offset64_16", ENCODING_Ia) 1179 ENCODING("offset64_32", ENCODING_Ia) 1180 ENCODING("offset64_64", ENCODING_Ia) 1181 ENCODING("srcidx8", ENCODING_SI) 1182 ENCODING("srcidx16", ENCODING_SI) 1183 ENCODING("srcidx32", ENCODING_SI) 1184 ENCODING("srcidx64", ENCODING_SI) 1185 ENCODING("dstidx8", ENCODING_DI) 1186 ENCODING("dstidx16", ENCODING_DI) 1187 ENCODING("dstidx32", ENCODING_DI) 1188 ENCODING("dstidx64", ENCODING_DI) 1189 errs() << "Unhandled relocation encoding " << s << "\n"; 1190 llvm_unreachable("Unhandled relocation encoding"); 1191 } 1192 1193 OperandEncoding 1194 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1195 uint8_t OpSize) { 1196 ENCODING("GR32", ENCODING_Rv) 1197 ENCODING("GR64", ENCODING_RO) 1198 ENCODING("GR16", ENCODING_Rv) 1199 ENCODING("GR8", ENCODING_RB) 1200 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1201 llvm_unreachable("Unhandled opcode modifier encoding"); 1202 } 1203 #undef ENCODING 1204