1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler Emitter.
10 // It contains the implementation of a single recognizable instruction.
11 // Documentation for the disassembler emitter in general can be found in
12 //  X86DisassemblerEmitter.h.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RecognizableInstr.h"
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/TableGen/Record.h"
22 #include <string>
23 
24 using namespace llvm;
25 using namespace X86Disassembler;
26 
getMnemonic(const CodeGenInstruction * I,unsigned Variant)27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) {
28     std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant);
29     StringRef Mnemonic(AsmString);
30     // Extract a mnemonic assuming it's separated by \t
31     Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; });
32 
33     // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic.
34     // Replace it with "CC" in-place.
35     size_t CondPos = Mnemonic.find("${cond}");
36     if (CondPos != StringRef::npos)
37       Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC");
38     return Mnemonic.upper();
39 }
40 
isRegisterOperand(const Record * Rec)41 bool X86Disassembler::isRegisterOperand(const Record *Rec) {
42   return Rec->isSubClassOf("RegisterClass") ||
43          Rec->isSubClassOf("RegisterOperand");
44 }
45 
isMemoryOperand(const Record * Rec)46 bool X86Disassembler::isMemoryOperand(const Record *Rec) {
47   return Rec->isSubClassOf("Operand") &&
48          Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
49 }
50 
isImmediateOperand(const Record * Rec)51 bool X86Disassembler::isImmediateOperand(const Record *Rec) {
52   return Rec->isSubClassOf("Operand") &&
53          Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
54 }
55 
getRegOperandSize(const Record * RegRec)56 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) {
57   if (RegRec->isSubClassOf("RegisterClass"))
58     return RegRec->getValueAsInt("Alignment");
59   if (RegRec->isSubClassOf("RegisterOperand"))
60     return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
61 
62   llvm_unreachable("Register operand's size not known!");
63 }
64 
getMemOperandSize(const Record * MemRec)65 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) {
66   if (MemRec->isSubClassOf("X86MemOperand"))
67     return MemRec->getValueAsInt("Size");
68 
69   llvm_unreachable("Memory operand's size not known!");
70 }
71 
72 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
73 ///   Useful for switch statements and the like.
74 ///
75 /// @param init - A reference to the BitsInit to be decoded.
76 /// @return     - The field, with the first bit in the BitsInit as the lowest
77 ///               order bit.
byteFromBitsInit(BitsInit & init)78 static uint8_t byteFromBitsInit(BitsInit &init) {
79   int width = init.getNumBits();
80 
81   assert(width <= 8 && "Field is too large for uint8_t!");
82 
83   int     index;
84   uint8_t mask = 0x01;
85 
86   uint8_t ret = 0;
87 
88   for (index = 0; index < width; index++) {
89     if (cast<BitInit>(init.getBit(index))->getValue())
90       ret |= mask;
91 
92     mask <<= 1;
93   }
94 
95   return ret;
96 }
97 
98 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
99 ///   name of the field.
100 ///
101 /// @param rec  - The record from which to extract the value.
102 /// @param name - The name of the field in the record.
103 /// @return     - The field, as translated by byteFromBitsInit().
byteFromRec(const Record * rec,StringRef name)104 static uint8_t byteFromRec(const Record* rec, StringRef name) {
105   BitsInit* bits = rec->getValueAsBitsInit(name);
106   return byteFromBitsInit(*bits);
107 }
108 
RecognizableInstrBase(const CodeGenInstruction & insn)109 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
110   const Record *Rec = insn.TheDef;
111   assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction");
112   OpPrefix = byteFromRec(Rec, "OpPrefixBits");
113   OpMap = byteFromRec(Rec, "OpMapBits");
114   Opcode = byteFromRec(Rec, "Opcode");
115   Form = byteFromRec(Rec, "FormBits");
116   Encoding = byteFromRec(Rec, "OpEncBits");
117   OpSize = byteFromRec(Rec, "OpSizeBits");
118   AdSize = byteFromRec(Rec, "AdSizeBits");
119   HasREX_W = Rec->getValueAsBit("hasREX_W");
120   HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
121   HasVEX_W = Rec->getValueAsBit("HasVEX_W");
122   IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W");
123   IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
124   HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2");
125   HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
126   HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
127   HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
128   IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
129   IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly");
130   ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
131   CD8_Scale = byteFromRec(Rec, "CD8_Scale");
132   HasVEX_L = Rec->getValueAsBit("hasVEX_L");
133 
134   EncodeRC = HasEVEX_B &&
135              (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
136 }
137 
shouldBeEmitted() const138 bool RecognizableInstrBase::shouldBeEmitted() const {
139   return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) &&
140          !IsAsmParserOnly;
141 }
142 
RecognizableInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)143 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
144                                      const CodeGenInstruction &insn,
145                                      InstrUID uid)
146     : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()),
147       Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList),
148       UID(uid), Spec(&tables.specForUID(uid)) {
149   // Check for 64-bit inst which does not require REX
150   // FIXME: Is there some better way to check for In64BitMode?
151   std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates");
152   for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
153     if (Predicates[i]->getName().contains("Not64Bit") ||
154         Predicates[i]->getName().contains("In32Bit")) {
155       Is32Bit = true;
156       break;
157     }
158     if (Predicates[i]->getName().contains("In64Bit")) {
159       Is64Bit = true;
160       break;
161     }
162   }
163 }
164 
processInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)165 void RecognizableInstr::processInstr(DisassemblerTables &tables,
166                                      const CodeGenInstruction &insn,
167                                      InstrUID uid) {
168   if (!insn.TheDef->isSubClassOf("X86Inst"))
169     return;
170   RecognizableInstr recogInstr(tables, insn, uid);
171 
172   if (!recogInstr.shouldBeEmitted())
173     return;
174   recogInstr.emitInstructionSpecifier();
175   recogInstr.emitDecodePath(tables);
176 }
177 
178 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
179                     (HasEVEX_K && HasEVEX_B ? n##_K_B : \
180                     (HasEVEX_KZ ? n##_KZ : \
181                     (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
182 
insnContext() const183 InstructionContext RecognizableInstr::insnContext() const {
184   InstructionContext insnContext;
185 
186   if (Encoding == X86Local::EVEX) {
187     if (HasVEX_L && HasEVEX_L2) {
188       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
189       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
190     }
191     // VEX_L & VEX_W
192     if (!EncodeRC && HasVEX_L && HasVEX_W) {
193       if (OpPrefix == X86Local::PD)
194         insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
195       else if (OpPrefix == X86Local::XS)
196         insnContext = EVEX_KB(IC_EVEX_L_W_XS);
197       else if (OpPrefix == X86Local::XD)
198         insnContext = EVEX_KB(IC_EVEX_L_W_XD);
199       else if (OpPrefix == X86Local::PS)
200         insnContext = EVEX_KB(IC_EVEX_L_W);
201       else {
202         errs() << "Instruction does not use a prefix: " << Name << "\n";
203         llvm_unreachable("Invalid prefix");
204       }
205     } else if (!EncodeRC && HasVEX_L) {
206       // VEX_L
207       if (OpPrefix == X86Local::PD)
208         insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
209       else if (OpPrefix == X86Local::XS)
210         insnContext = EVEX_KB(IC_EVEX_L_XS);
211       else if (OpPrefix == X86Local::XD)
212         insnContext = EVEX_KB(IC_EVEX_L_XD);
213       else if (OpPrefix == X86Local::PS)
214         insnContext = EVEX_KB(IC_EVEX_L);
215       else {
216         errs() << "Instruction does not use a prefix: " << Name << "\n";
217         llvm_unreachable("Invalid prefix");
218       }
219     } else if (!EncodeRC && HasEVEX_L2 && HasVEX_W) {
220       // EVEX_L2 & VEX_W
221       if (OpPrefix == X86Local::PD)
222         insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
223       else if (OpPrefix == X86Local::XS)
224         insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
225       else if (OpPrefix == X86Local::XD)
226         insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
227       else if (OpPrefix == X86Local::PS)
228         insnContext = EVEX_KB(IC_EVEX_L2_W);
229       else {
230         errs() << "Instruction does not use a prefix: " << Name << "\n";
231         llvm_unreachable("Invalid prefix");
232       }
233     } else if (!EncodeRC && HasEVEX_L2) {
234       // EVEX_L2
235       if (OpPrefix == X86Local::PD)
236         insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
237       else if (OpPrefix == X86Local::XD)
238         insnContext = EVEX_KB(IC_EVEX_L2_XD);
239       else if (OpPrefix == X86Local::XS)
240         insnContext = EVEX_KB(IC_EVEX_L2_XS);
241       else if (OpPrefix == X86Local::PS)
242         insnContext = EVEX_KB(IC_EVEX_L2);
243       else {
244         errs() << "Instruction does not use a prefix: " << Name << "\n";
245         llvm_unreachable("Invalid prefix");
246       }
247     }
248     else if (HasVEX_W) {
249       // VEX_W
250       if (OpPrefix == X86Local::PD)
251         insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
252       else if (OpPrefix == X86Local::XS)
253         insnContext = EVEX_KB(IC_EVEX_W_XS);
254       else if (OpPrefix == X86Local::XD)
255         insnContext = EVEX_KB(IC_EVEX_W_XD);
256       else if (OpPrefix == X86Local::PS)
257         insnContext = EVEX_KB(IC_EVEX_W);
258       else {
259         errs() << "Instruction does not use a prefix: " << Name << "\n";
260         llvm_unreachable("Invalid prefix");
261       }
262     }
263     // No L, no W
264     else if (OpPrefix == X86Local::PD)
265       insnContext = EVEX_KB(IC_EVEX_OPSIZE);
266     else if (OpPrefix == X86Local::XD)
267       insnContext = EVEX_KB(IC_EVEX_XD);
268     else if (OpPrefix == X86Local::XS)
269       insnContext = EVEX_KB(IC_EVEX_XS);
270     else if (OpPrefix == X86Local::PS)
271       insnContext = EVEX_KB(IC_EVEX);
272     else {
273       errs() << "Instruction does not use a prefix: " << Name << "\n";
274       llvm_unreachable("Invalid prefix");
275     }
276     /// eof EVEX
277   } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
278     if (HasVEX_L && HasVEX_W) {
279       if (OpPrefix == X86Local::PD)
280         insnContext = IC_VEX_L_W_OPSIZE;
281       else if (OpPrefix == X86Local::XS)
282         insnContext = IC_VEX_L_W_XS;
283       else if (OpPrefix == X86Local::XD)
284         insnContext = IC_VEX_L_W_XD;
285       else if (OpPrefix == X86Local::PS)
286         insnContext = IC_VEX_L_W;
287       else {
288         errs() << "Instruction does not use a prefix: " << Name << "\n";
289         llvm_unreachable("Invalid prefix");
290       }
291     } else if (OpPrefix == X86Local::PD && HasVEX_L)
292       insnContext = IC_VEX_L_OPSIZE;
293     else if (OpPrefix == X86Local::PD && HasVEX_W)
294       insnContext = IC_VEX_W_OPSIZE;
295     else if (OpPrefix == X86Local::PD)
296       insnContext = IC_VEX_OPSIZE;
297     else if (HasVEX_L && OpPrefix == X86Local::XS)
298       insnContext = IC_VEX_L_XS;
299     else if (HasVEX_L && OpPrefix == X86Local::XD)
300       insnContext = IC_VEX_L_XD;
301     else if (HasVEX_W && OpPrefix == X86Local::XS)
302       insnContext = IC_VEX_W_XS;
303     else if (HasVEX_W && OpPrefix == X86Local::XD)
304       insnContext = IC_VEX_W_XD;
305     else if (HasVEX_W && OpPrefix == X86Local::PS)
306       insnContext = IC_VEX_W;
307     else if (HasVEX_L && OpPrefix == X86Local::PS)
308       insnContext = IC_VEX_L;
309     else if (OpPrefix == X86Local::XD)
310       insnContext = IC_VEX_XD;
311     else if (OpPrefix == X86Local::XS)
312       insnContext = IC_VEX_XS;
313     else if (OpPrefix == X86Local::PS)
314       insnContext = IC_VEX;
315     else {
316       errs() << "Instruction does not use a prefix: " << Name << "\n";
317       llvm_unreachable("Invalid prefix");
318     }
319   } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) {
320     if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
321       insnContext = IC_64BIT_REXW_OPSIZE;
322     else if (HasREX_W && AdSize == X86Local::AdSize32)
323       insnContext = IC_64BIT_REXW_ADSIZE;
324     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
325       insnContext = IC_64BIT_XD_OPSIZE;
326     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
327       insnContext = IC_64BIT_XS_OPSIZE;
328     else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
329       insnContext = IC_64BIT_OPSIZE_ADSIZE;
330     else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
331       insnContext = IC_64BIT_OPSIZE_ADSIZE;
332     else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
333       insnContext = IC_64BIT_OPSIZE;
334     else if (AdSize == X86Local::AdSize32)
335       insnContext = IC_64BIT_ADSIZE;
336     else if (HasREX_W && OpPrefix == X86Local::XS)
337       insnContext = IC_64BIT_REXW_XS;
338     else if (HasREX_W && OpPrefix == X86Local::XD)
339       insnContext = IC_64BIT_REXW_XD;
340     else if (OpPrefix == X86Local::XD)
341       insnContext = IC_64BIT_XD;
342     else if (OpPrefix == X86Local::XS)
343       insnContext = IC_64BIT_XS;
344     else if (HasREX_W)
345       insnContext = IC_64BIT_REXW;
346     else
347       insnContext = IC_64BIT;
348   } else {
349     if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
350       insnContext = IC_XD_OPSIZE;
351     else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
352       insnContext = IC_XS_OPSIZE;
353     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
354       insnContext = IC_XD_ADSIZE;
355     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
356       insnContext = IC_XS_ADSIZE;
357     else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
358       insnContext = IC_OPSIZE_ADSIZE;
359     else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
360       insnContext = IC_OPSIZE_ADSIZE;
361     else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
362       insnContext = IC_OPSIZE;
363     else if (AdSize == X86Local::AdSize16)
364       insnContext = IC_ADSIZE;
365     else if (OpPrefix == X86Local::XD)
366       insnContext = IC_XD;
367     else if (OpPrefix == X86Local::XS)
368       insnContext = IC_XS;
369     else
370       insnContext = IC;
371   }
372 
373   return insnContext;
374 }
375 
adjustOperandEncoding(OperandEncoding & encoding)376 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
377   // The scaling factor for AVX512 compressed displacement encoding is an
378   // instruction attribute.  Adjust the ModRM encoding type to include the
379   // scale for compressed displacement.
380   if ((encoding != ENCODING_RM &&
381        encoding != ENCODING_VSIB &&
382        encoding != ENCODING_SIB) ||CD8_Scale == 0)
383     return;
384   encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
385   assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
386           (encoding == ENCODING_SIB) ||
387           (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
388          "Invalid CDisp scaling");
389 }
390 
handleOperand(bool optional,unsigned & operandIndex,unsigned & physicalOperandIndex,unsigned numPhysicalOperands,const unsigned * operandMapping,OperandEncoding (* encodingFromString)(const std::string &,uint8_t OpSize))391 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
392                                       unsigned &physicalOperandIndex,
393                                       unsigned numPhysicalOperands,
394                                       const unsigned *operandMapping,
395                                       OperandEncoding (*encodingFromString)
396                                         (const std::string&,
397                                          uint8_t OpSize)) {
398   if (optional) {
399     if (physicalOperandIndex >= numPhysicalOperands)
400       return;
401   } else {
402     assert(physicalOperandIndex < numPhysicalOperands);
403   }
404 
405   while (operandMapping[operandIndex] != operandIndex) {
406     Spec->operands[operandIndex].encoding = ENCODING_DUP;
407     Spec->operands[operandIndex].type =
408       (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
409     ++operandIndex;
410   }
411 
412   StringRef typeName = (*Operands)[operandIndex].Rec->getName();
413 
414   OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize);
415   // Adjust the encoding type for an operand based on the instruction.
416   adjustOperandEncoding(encoding);
417   Spec->operands[operandIndex].encoding = encoding;
418   Spec->operands[operandIndex].type =
419       typeFromString(std::string(typeName), HasREX_W, OpSize);
420 
421   ++operandIndex;
422   ++physicalOperandIndex;
423 }
424 
emitInstructionSpecifier()425 void RecognizableInstr::emitInstructionSpecifier() {
426   Spec->name       = Name;
427 
428   Spec->insnContext = insnContext();
429 
430   const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
431 
432   unsigned numOperands = OperandList.size();
433   unsigned numPhysicalOperands = 0;
434 
435   // operandMapping maps from operands in OperandList to their originals.
436   // If operandMapping[i] != i, then the entry is a duplicate.
437   unsigned operandMapping[X86_MAX_OPERANDS];
438   assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
439 
440   for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
441     if (!OperandList[operandIndex].Constraints.empty()) {
442       const CGIOperandList::ConstraintInfo &Constraint =
443         OperandList[operandIndex].Constraints[0];
444       if (Constraint.isTied()) {
445         operandMapping[operandIndex] = operandIndex;
446         operandMapping[Constraint.getTiedOperand()] = operandIndex;
447       } else {
448         ++numPhysicalOperands;
449         operandMapping[operandIndex] = operandIndex;
450       }
451     } else {
452       ++numPhysicalOperands;
453       operandMapping[operandIndex] = operandIndex;
454     }
455   }
456 
457 #define HANDLE_OPERAND(class)               \
458   handleOperand(false,                      \
459                 operandIndex,               \
460                 physicalOperandIndex,       \
461                 numPhysicalOperands,        \
462                 operandMapping,             \
463                 class##EncodingFromString);
464 
465 #define HANDLE_OPTIONAL(class)              \
466   handleOperand(true,                       \
467                 operandIndex,               \
468                 physicalOperandIndex,       \
469                 numPhysicalOperands,        \
470                 operandMapping,             \
471                 class##EncodingFromString);
472 
473   // operandIndex should always be < numOperands
474   unsigned operandIndex = 0;
475   // physicalOperandIndex should always be < numPhysicalOperands
476   unsigned physicalOperandIndex = 0;
477 
478 #ifndef NDEBUG
479   // Given the set of prefix bits, how many additional operands does the
480   // instruction have?
481   unsigned additionalOperands = 0;
482   if (HasVEX_4V)
483     ++additionalOperands;
484   if (HasEVEX_K)
485     ++additionalOperands;
486 #endif
487 
488   switch (Form) {
489   default: llvm_unreachable("Unhandled form");
490   case X86Local::PrefixByte:
491     return;
492   case X86Local::RawFrmSrc:
493     HANDLE_OPERAND(relocation);
494     return;
495   case X86Local::RawFrmDst:
496     HANDLE_OPERAND(relocation);
497     return;
498   case X86Local::RawFrmDstSrc:
499     HANDLE_OPERAND(relocation);
500     HANDLE_OPERAND(relocation);
501     return;
502   case X86Local::RawFrm:
503     // Operand 1 (optional) is an address or immediate.
504     assert(numPhysicalOperands <= 1 &&
505            "Unexpected number of operands for RawFrm");
506     HANDLE_OPTIONAL(relocation)
507     break;
508   case X86Local::RawFrmMemOffs:
509     // Operand 1 is an address.
510     HANDLE_OPERAND(relocation);
511     break;
512   case X86Local::AddRegFrm:
513     // Operand 1 is added to the opcode.
514     // Operand 2 (optional) is an address.
515     assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
516            "Unexpected number of operands for AddRegFrm");
517     HANDLE_OPERAND(opcodeModifier)
518     HANDLE_OPTIONAL(relocation)
519     break;
520   case X86Local::AddCCFrm:
521     // Operand 1 (optional) is an address or immediate.
522     assert(numPhysicalOperands == 2 &&
523            "Unexpected number of operands for AddCCFrm");
524     HANDLE_OPERAND(relocation)
525     HANDLE_OPERAND(opcodeModifier)
526     break;
527   case X86Local::MRMDestReg:
528     // Operand 1 is a register operand in the R/M field.
529     // - In AVX512 there may be a mask operand here -
530     // Operand 2 is a register operand in the Reg/Opcode field.
531     // - In AVX, there is a register operand in the VEX.vvvv field here -
532     // Operand 3 (optional) is an immediate.
533     assert(numPhysicalOperands >= 2 + additionalOperands &&
534            numPhysicalOperands <= 3 + additionalOperands &&
535            "Unexpected number of operands for MRMDestRegFrm");
536 
537     HANDLE_OPERAND(rmRegister)
538     if (HasEVEX_K)
539       HANDLE_OPERAND(writemaskRegister)
540 
541     if (HasVEX_4V)
542       // FIXME: In AVX, the register below becomes the one encoded
543       // in ModRMVEX and the one above the one in the VEX.VVVV field
544       HANDLE_OPERAND(vvvvRegister)
545 
546     HANDLE_OPERAND(roRegister)
547     HANDLE_OPTIONAL(immediate)
548     break;
549   case X86Local::MRMDestMem:
550   case X86Local::MRMDestMemFSIB:
551     // Operand 1 is a memory operand (possibly SIB-extended)
552     // Operand 2 is a register operand in the Reg/Opcode field.
553     // - In AVX, there is a register operand in the VEX.vvvv field here -
554     // Operand 3 (optional) is an immediate.
555     assert(numPhysicalOperands >= 2 + additionalOperands &&
556            numPhysicalOperands <= 3 + additionalOperands &&
557            "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
558 
559     HANDLE_OPERAND(memory)
560 
561     if (HasEVEX_K)
562       HANDLE_OPERAND(writemaskRegister)
563 
564     if (HasVEX_4V)
565       // FIXME: In AVX, the register below becomes the one encoded
566       // in ModRMVEX and the one above the one in the VEX.VVVV field
567       HANDLE_OPERAND(vvvvRegister)
568 
569     HANDLE_OPERAND(roRegister)
570     HANDLE_OPTIONAL(immediate)
571     break;
572   case X86Local::MRMSrcReg:
573     // Operand 1 is a register operand in the Reg/Opcode field.
574     // Operand 2 is a register operand in the R/M field.
575     // - In AVX, there is a register operand in the VEX.vvvv field here -
576     // Operand 3 (optional) is an immediate.
577     // Operand 4 (optional) is an immediate.
578 
579     assert(numPhysicalOperands >= 2 + additionalOperands &&
580            numPhysicalOperands <= 4 + additionalOperands &&
581            "Unexpected number of operands for MRMSrcRegFrm");
582 
583     HANDLE_OPERAND(roRegister)
584 
585     if (HasEVEX_K)
586       HANDLE_OPERAND(writemaskRegister)
587 
588     if (HasVEX_4V)
589       // FIXME: In AVX, the register below becomes the one encoded
590       // in ModRMVEX and the one above the one in the VEX.VVVV field
591       HANDLE_OPERAND(vvvvRegister)
592 
593     HANDLE_OPERAND(rmRegister)
594     HANDLE_OPTIONAL(immediate)
595     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
596     break;
597   case X86Local::MRMSrcReg4VOp3:
598     assert(numPhysicalOperands == 3 &&
599            "Unexpected number of operands for MRMSrcReg4VOp3Frm");
600     HANDLE_OPERAND(roRegister)
601     HANDLE_OPERAND(rmRegister)
602     HANDLE_OPERAND(vvvvRegister)
603     break;
604   case X86Local::MRMSrcRegOp4:
605     assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
606            "Unexpected number of operands for MRMSrcRegOp4Frm");
607     HANDLE_OPERAND(roRegister)
608     HANDLE_OPERAND(vvvvRegister)
609     HANDLE_OPERAND(immediate) // Register in imm[7:4]
610     HANDLE_OPERAND(rmRegister)
611     HANDLE_OPTIONAL(immediate)
612     break;
613   case X86Local::MRMSrcRegCC:
614     assert(numPhysicalOperands == 3 &&
615            "Unexpected number of operands for MRMSrcRegCC");
616     HANDLE_OPERAND(roRegister)
617     HANDLE_OPERAND(rmRegister)
618     HANDLE_OPERAND(opcodeModifier)
619     break;
620   case X86Local::MRMSrcMem:
621   case X86Local::MRMSrcMemFSIB:
622     // Operand 1 is a register operand in the Reg/Opcode field.
623     // Operand 2 is a memory operand (possibly SIB-extended)
624     // - In AVX, there is a register operand in the VEX.vvvv field here -
625     // Operand 3 (optional) is an immediate.
626 
627     assert(numPhysicalOperands >= 2 + additionalOperands &&
628            numPhysicalOperands <= 4 + additionalOperands &&
629            "Unexpected number of operands for MRMSrcMemFrm");
630 
631     HANDLE_OPERAND(roRegister)
632 
633     if (HasEVEX_K)
634       HANDLE_OPERAND(writemaskRegister)
635 
636     if (HasVEX_4V)
637       // FIXME: In AVX, the register below becomes the one encoded
638       // in ModRMVEX and the one above the one in the VEX.VVVV field
639       HANDLE_OPERAND(vvvvRegister)
640 
641     HANDLE_OPERAND(memory)
642     HANDLE_OPTIONAL(immediate)
643     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
644     break;
645   case X86Local::MRMSrcMem4VOp3:
646     assert(numPhysicalOperands == 3 &&
647            "Unexpected number of operands for MRMSrcMem4VOp3Frm");
648     HANDLE_OPERAND(roRegister)
649     HANDLE_OPERAND(memory)
650     HANDLE_OPERAND(vvvvRegister)
651     break;
652   case X86Local::MRMSrcMemOp4:
653     assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
654            "Unexpected number of operands for MRMSrcMemOp4Frm");
655     HANDLE_OPERAND(roRegister)
656     HANDLE_OPERAND(vvvvRegister)
657     HANDLE_OPERAND(immediate) // Register in imm[7:4]
658     HANDLE_OPERAND(memory)
659     HANDLE_OPTIONAL(immediate)
660     break;
661   case X86Local::MRMSrcMemCC:
662     assert(numPhysicalOperands == 3 &&
663            "Unexpected number of operands for MRMSrcMemCC");
664     HANDLE_OPERAND(roRegister)
665     HANDLE_OPERAND(memory)
666     HANDLE_OPERAND(opcodeModifier)
667     break;
668   case X86Local::MRMXrCC:
669     assert(numPhysicalOperands == 2 &&
670            "Unexpected number of operands for MRMXrCC");
671     HANDLE_OPERAND(rmRegister)
672     HANDLE_OPERAND(opcodeModifier)
673     break;
674   case X86Local::MRMr0:
675     // Operand 1 is a register operand in the R/M field.
676     HANDLE_OPERAND(roRegister)
677     break;
678   case X86Local::MRMXr:
679   case X86Local::MRM0r:
680   case X86Local::MRM1r:
681   case X86Local::MRM2r:
682   case X86Local::MRM3r:
683   case X86Local::MRM4r:
684   case X86Local::MRM5r:
685   case X86Local::MRM6r:
686   case X86Local::MRM7r:
687     // Operand 1 is a register operand in the R/M field.
688     // Operand 2 (optional) is an immediate or relocation.
689     // Operand 3 (optional) is an immediate.
690     assert(numPhysicalOperands >= 0 + additionalOperands &&
691            numPhysicalOperands <= 3 + additionalOperands &&
692            "Unexpected number of operands for MRMnr");
693 
694     if (HasVEX_4V)
695       HANDLE_OPERAND(vvvvRegister)
696 
697     if (HasEVEX_K)
698       HANDLE_OPERAND(writemaskRegister)
699     HANDLE_OPTIONAL(rmRegister)
700     HANDLE_OPTIONAL(relocation)
701     HANDLE_OPTIONAL(immediate)
702     break;
703   case X86Local::MRMXmCC:
704     assert(numPhysicalOperands == 2 &&
705            "Unexpected number of operands for MRMXm");
706     HANDLE_OPERAND(memory)
707     HANDLE_OPERAND(opcodeModifier)
708     break;
709   case X86Local::MRMXm:
710   case X86Local::MRM0m:
711   case X86Local::MRM1m:
712   case X86Local::MRM2m:
713   case X86Local::MRM3m:
714   case X86Local::MRM4m:
715   case X86Local::MRM5m:
716   case X86Local::MRM6m:
717   case X86Local::MRM7m:
718     // Operand 1 is a memory operand (possibly SIB-extended)
719     // Operand 2 (optional) is an immediate or relocation.
720     assert(numPhysicalOperands >= 1 + additionalOperands &&
721            numPhysicalOperands <= 2 + additionalOperands &&
722            "Unexpected number of operands for MRMnm");
723 
724     if (HasVEX_4V)
725       HANDLE_OPERAND(vvvvRegister)
726     if (HasEVEX_K)
727       HANDLE_OPERAND(writemaskRegister)
728     HANDLE_OPERAND(memory)
729     HANDLE_OPTIONAL(relocation)
730     break;
731   case X86Local::RawFrmImm8:
732     // operand 1 is a 16-bit immediate
733     // operand 2 is an 8-bit immediate
734     assert(numPhysicalOperands == 2 &&
735            "Unexpected number of operands for X86Local::RawFrmImm8");
736     HANDLE_OPERAND(immediate)
737     HANDLE_OPERAND(immediate)
738     break;
739   case X86Local::RawFrmImm16:
740     // operand 1 is a 16-bit immediate
741     // operand 2 is a 16-bit immediate
742     HANDLE_OPERAND(immediate)
743     HANDLE_OPERAND(immediate)
744     break;
745   case X86Local::MRM0X:
746   case X86Local::MRM1X:
747   case X86Local::MRM2X:
748   case X86Local::MRM3X:
749   case X86Local::MRM4X:
750   case X86Local::MRM5X:
751   case X86Local::MRM6X:
752   case X86Local::MRM7X:
753 #define MAP(from, to) case X86Local::MRM_##from:
754   X86_INSTR_MRM_MAPPING
755 #undef MAP
756     HANDLE_OPTIONAL(relocation)
757     break;
758   }
759 
760 #undef HANDLE_OPERAND
761 #undef HANDLE_OPTIONAL
762 }
763 
emitDecodePath(DisassemblerTables & tables) const764 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
765   // Special cases where the LLVM tables are not complete
766 
767 #define MAP(from, to)                     \
768   case X86Local::MRM_##from:
769 
770   llvm::Optional<OpcodeType> opcodeType;
771   switch (OpMap) {
772   default: llvm_unreachable("Invalid map!");
773   case X86Local::OB:        opcodeType = ONEBYTE;       break;
774   case X86Local::TB:        opcodeType = TWOBYTE;       break;
775   case X86Local::T8:        opcodeType = THREEBYTE_38;  break;
776   case X86Local::TA:        opcodeType = THREEBYTE_3A;  break;
777   case X86Local::XOP8:      opcodeType = XOP8_MAP;      break;
778   case X86Local::XOP9:      opcodeType = XOP9_MAP;      break;
779   case X86Local::XOPA:      opcodeType = XOPA_MAP;      break;
780   case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
781   case X86Local::T_MAP5:    opcodeType = MAP5;          break;
782   case X86Local::T_MAP6:    opcodeType = MAP6;          break;
783   }
784 
785   std::unique_ptr<ModRMFilter> filter;
786   switch (Form) {
787   default: llvm_unreachable("Invalid form!");
788   case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
789   case X86Local::RawFrm:
790   case X86Local::AddRegFrm:
791   case X86Local::RawFrmMemOffs:
792   case X86Local::RawFrmSrc:
793   case X86Local::RawFrmDst:
794   case X86Local::RawFrmDstSrc:
795   case X86Local::RawFrmImm8:
796   case X86Local::RawFrmImm16:
797   case X86Local::AddCCFrm:
798   case X86Local::PrefixByte:
799     filter = std::make_unique<DumbFilter>();
800     break;
801   case X86Local::MRMDestReg:
802   case X86Local::MRMSrcReg:
803   case X86Local::MRMSrcReg4VOp3:
804   case X86Local::MRMSrcRegOp4:
805   case X86Local::MRMSrcRegCC:
806   case X86Local::MRMXrCC:
807   case X86Local::MRMXr:
808     filter = std::make_unique<ModFilter>(true);
809     break;
810   case X86Local::MRMDestMem:
811   case X86Local::MRMDestMemFSIB:
812   case X86Local::MRMSrcMem:
813   case X86Local::MRMSrcMemFSIB:
814   case X86Local::MRMSrcMem4VOp3:
815   case X86Local::MRMSrcMemOp4:
816   case X86Local::MRMSrcMemCC:
817   case X86Local::MRMXmCC:
818   case X86Local::MRMXm:
819     filter = std::make_unique<ModFilter>(false);
820     break;
821   case X86Local::MRM0r: case X86Local::MRM1r:
822   case X86Local::MRM2r: case X86Local::MRM3r:
823   case X86Local::MRM4r: case X86Local::MRM5r:
824   case X86Local::MRM6r: case X86Local::MRM7r:
825     filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
826     break;
827   case X86Local::MRM0X: case X86Local::MRM1X:
828   case X86Local::MRM2X: case X86Local::MRM3X:
829   case X86Local::MRM4X: case X86Local::MRM5X:
830   case X86Local::MRM6X: case X86Local::MRM7X:
831     filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
832     break;
833   case X86Local::MRMr0:
834     filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
835     break;
836   case X86Local::MRM0m: case X86Local::MRM1m:
837   case X86Local::MRM2m: case X86Local::MRM3m:
838   case X86Local::MRM4m: case X86Local::MRM5m:
839   case X86Local::MRM6m: case X86Local::MRM7m:
840     filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
841     break;
842   X86_INSTR_MRM_MAPPING
843     filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
844     break;
845   } // switch (Form)
846 
847   uint8_t opcodeToSet = Opcode;
848 
849   unsigned AddressSize = 0;
850   switch (AdSize) {
851   case X86Local::AdSize16: AddressSize = 16; break;
852   case X86Local::AdSize32: AddressSize = 32; break;
853   case X86Local::AdSize64: AddressSize = 64; break;
854   }
855 
856   assert(opcodeType && "Opcode type not set");
857   assert(filter && "Filter not set");
858 
859   if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
860       Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
861       Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) {
862     uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16;
863     assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
864 
865     uint8_t currentOpcode;
866 
867     for (currentOpcode = opcodeToSet;
868          currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode)
869       tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
870                             UID, Is32Bit, OpPrefix == 0,
871                             IgnoresVEX_L || EncodeRC,
872                             IgnoresVEX_W, AddressSize);
873   } else {
874     tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
875                           Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
876                           IgnoresVEX_W, AddressSize);
877   }
878 
879 #undef MAP
880 }
881 
882 #define TYPE(str, type) if (s == str) return type;
typeFromString(const std::string & s,bool hasREX_W,uint8_t OpSize)883 OperandType RecognizableInstr::typeFromString(const std::string &s,
884                                               bool hasREX_W,
885                                               uint8_t OpSize) {
886   if(hasREX_W) {
887     // For instructions with a REX_W prefix, a declared 32-bit register encoding
888     // is special.
889     TYPE("GR32",              TYPE_R32)
890   }
891   if(OpSize == X86Local::OpSize16) {
892     // For OpSize16 instructions, a declared 16-bit register or
893     // immediate encoding is special.
894     TYPE("GR16",              TYPE_Rv)
895   } else if(OpSize == X86Local::OpSize32) {
896     // For OpSize32 instructions, a declared 32-bit register or
897     // immediate encoding is special.
898     TYPE("GR32",              TYPE_Rv)
899   }
900   TYPE("i16mem",              TYPE_M)
901   TYPE("i16imm",              TYPE_IMM)
902   TYPE("i16i8imm",            TYPE_IMM)
903   TYPE("GR16",                TYPE_R16)
904   TYPE("GR16orGR32orGR64",    TYPE_R16)
905   TYPE("i32mem",              TYPE_M)
906   TYPE("i32imm",              TYPE_IMM)
907   TYPE("i32i8imm",            TYPE_IMM)
908   TYPE("GR32",                TYPE_R32)
909   TYPE("GR32orGR64",          TYPE_R32)
910   TYPE("i64mem",              TYPE_M)
911   TYPE("i64i32imm",           TYPE_IMM)
912   TYPE("i64i8imm",            TYPE_IMM)
913   TYPE("GR64",                TYPE_R64)
914   TYPE("i8mem",               TYPE_M)
915   TYPE("i8imm",               TYPE_IMM)
916   TYPE("u4imm",               TYPE_UIMM8)
917   TYPE("u8imm",               TYPE_UIMM8)
918   TYPE("i16u8imm",            TYPE_UIMM8)
919   TYPE("i32u8imm",            TYPE_UIMM8)
920   TYPE("i64u8imm",            TYPE_UIMM8)
921   TYPE("GR8",                 TYPE_R8)
922   TYPE("VR128",               TYPE_XMM)
923   TYPE("VR128X",              TYPE_XMM)
924   TYPE("f128mem",             TYPE_M)
925   TYPE("f256mem",             TYPE_M)
926   TYPE("f512mem",             TYPE_M)
927   TYPE("FR128",               TYPE_XMM)
928   TYPE("FR64",                TYPE_XMM)
929   TYPE("FR64X",               TYPE_XMM)
930   TYPE("f64mem",              TYPE_M)
931   TYPE("sdmem",               TYPE_M)
932   TYPE("FR16X",               TYPE_XMM)
933   TYPE("FR32",                TYPE_XMM)
934   TYPE("FR32X",               TYPE_XMM)
935   TYPE("f32mem",              TYPE_M)
936   TYPE("f16mem",              TYPE_M)
937   TYPE("ssmem",               TYPE_M)
938   TYPE("shmem",               TYPE_M)
939   TYPE("RST",                 TYPE_ST)
940   TYPE("RSTi",                TYPE_ST)
941   TYPE("i128mem",             TYPE_M)
942   TYPE("i256mem",             TYPE_M)
943   TYPE("i512mem",             TYPE_M)
944   TYPE("i64i32imm_brtarget",  TYPE_REL)
945   TYPE("i16imm_brtarget",     TYPE_REL)
946   TYPE("i32imm_brtarget",     TYPE_REL)
947   TYPE("ccode",               TYPE_IMM)
948   TYPE("AVX512RC",            TYPE_IMM)
949   TYPE("brtarget32",          TYPE_REL)
950   TYPE("brtarget16",          TYPE_REL)
951   TYPE("brtarget8",           TYPE_REL)
952   TYPE("f80mem",              TYPE_M)
953   TYPE("lea64_32mem",         TYPE_M)
954   TYPE("lea64mem",            TYPE_M)
955   TYPE("VR64",                TYPE_MM64)
956   TYPE("i64imm",              TYPE_IMM)
957   TYPE("anymem",              TYPE_M)
958   TYPE("opaquemem",           TYPE_M)
959   TYPE("sibmem",              TYPE_MSIB)
960   TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
961   TYPE("DEBUG_REG",           TYPE_DEBUGREG)
962   TYPE("CONTROL_REG",         TYPE_CONTROLREG)
963   TYPE("srcidx8",             TYPE_SRCIDX)
964   TYPE("srcidx16",            TYPE_SRCIDX)
965   TYPE("srcidx32",            TYPE_SRCIDX)
966   TYPE("srcidx64",            TYPE_SRCIDX)
967   TYPE("dstidx8",             TYPE_DSTIDX)
968   TYPE("dstidx16",            TYPE_DSTIDX)
969   TYPE("dstidx32",            TYPE_DSTIDX)
970   TYPE("dstidx64",            TYPE_DSTIDX)
971   TYPE("offset16_8",          TYPE_MOFFS)
972   TYPE("offset16_16",         TYPE_MOFFS)
973   TYPE("offset16_32",         TYPE_MOFFS)
974   TYPE("offset32_8",          TYPE_MOFFS)
975   TYPE("offset32_16",         TYPE_MOFFS)
976   TYPE("offset32_32",         TYPE_MOFFS)
977   TYPE("offset32_64",         TYPE_MOFFS)
978   TYPE("offset64_8",          TYPE_MOFFS)
979   TYPE("offset64_16",         TYPE_MOFFS)
980   TYPE("offset64_32",         TYPE_MOFFS)
981   TYPE("offset64_64",         TYPE_MOFFS)
982   TYPE("VR256",               TYPE_YMM)
983   TYPE("VR256X",              TYPE_YMM)
984   TYPE("VR512",               TYPE_ZMM)
985   TYPE("VK1",                 TYPE_VK)
986   TYPE("VK1WM",               TYPE_VK)
987   TYPE("VK2",                 TYPE_VK)
988   TYPE("VK2WM",               TYPE_VK)
989   TYPE("VK4",                 TYPE_VK)
990   TYPE("VK4WM",               TYPE_VK)
991   TYPE("VK8",                 TYPE_VK)
992   TYPE("VK8WM",               TYPE_VK)
993   TYPE("VK16",                TYPE_VK)
994   TYPE("VK16WM",              TYPE_VK)
995   TYPE("VK32",                TYPE_VK)
996   TYPE("VK32WM",              TYPE_VK)
997   TYPE("VK64",                TYPE_VK)
998   TYPE("VK64WM",              TYPE_VK)
999   TYPE("VK1Pair",             TYPE_VK_PAIR)
1000   TYPE("VK2Pair",             TYPE_VK_PAIR)
1001   TYPE("VK4Pair",             TYPE_VK_PAIR)
1002   TYPE("VK8Pair",             TYPE_VK_PAIR)
1003   TYPE("VK16Pair",            TYPE_VK_PAIR)
1004   TYPE("vx64mem",             TYPE_MVSIBX)
1005   TYPE("vx128mem",            TYPE_MVSIBX)
1006   TYPE("vx256mem",            TYPE_MVSIBX)
1007   TYPE("vy128mem",            TYPE_MVSIBY)
1008   TYPE("vy256mem",            TYPE_MVSIBY)
1009   TYPE("vx64xmem",            TYPE_MVSIBX)
1010   TYPE("vx128xmem",           TYPE_MVSIBX)
1011   TYPE("vx256xmem",           TYPE_MVSIBX)
1012   TYPE("vy128xmem",           TYPE_MVSIBY)
1013   TYPE("vy256xmem",           TYPE_MVSIBY)
1014   TYPE("vy512xmem",           TYPE_MVSIBY)
1015   TYPE("vz256mem",            TYPE_MVSIBZ)
1016   TYPE("vz512mem",            TYPE_MVSIBZ)
1017   TYPE("BNDR",                TYPE_BNDR)
1018   TYPE("TILE",                TYPE_TMM)
1019   errs() << "Unhandled type string " << s << "\n";
1020   llvm_unreachable("Unhandled type string");
1021 }
1022 #undef TYPE
1023 
1024 #define ENCODING(str, encoding) if (s == str) return encoding;
1025 OperandEncoding
immediateEncodingFromString(const std::string & s,uint8_t OpSize)1026 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1027                                                uint8_t OpSize) {
1028   if(OpSize != X86Local::OpSize16) {
1029     // For instructions without an OpSize prefix, a declared 16-bit register or
1030     // immediate encoding is special.
1031     ENCODING("i16imm",        ENCODING_IW)
1032   }
1033   ENCODING("i32i8imm",        ENCODING_IB)
1034   ENCODING("AVX512RC",        ENCODING_IRC)
1035   ENCODING("i16imm",          ENCODING_Iv)
1036   ENCODING("i16i8imm",        ENCODING_IB)
1037   ENCODING("i32imm",          ENCODING_Iv)
1038   ENCODING("i64i32imm",       ENCODING_ID)
1039   ENCODING("i64i8imm",        ENCODING_IB)
1040   ENCODING("i8imm",           ENCODING_IB)
1041   ENCODING("u4imm",           ENCODING_IB)
1042   ENCODING("u8imm",           ENCODING_IB)
1043   ENCODING("i16u8imm",        ENCODING_IB)
1044   ENCODING("i32u8imm",        ENCODING_IB)
1045   ENCODING("i64u8imm",        ENCODING_IB)
1046   // This is not a typo.  Instructions like BLENDVPD put
1047   // register IDs in 8-bit immediates nowadays.
1048   ENCODING("FR32",            ENCODING_IB)
1049   ENCODING("FR64",            ENCODING_IB)
1050   ENCODING("FR128",           ENCODING_IB)
1051   ENCODING("VR128",           ENCODING_IB)
1052   ENCODING("VR256",           ENCODING_IB)
1053   ENCODING("FR16X",           ENCODING_IB)
1054   ENCODING("FR32X",           ENCODING_IB)
1055   ENCODING("FR64X",           ENCODING_IB)
1056   ENCODING("VR128X",          ENCODING_IB)
1057   ENCODING("VR256X",          ENCODING_IB)
1058   ENCODING("VR512",           ENCODING_IB)
1059   ENCODING("TILE",            ENCODING_IB)
1060   errs() << "Unhandled immediate encoding " << s << "\n";
1061   llvm_unreachable("Unhandled immediate encoding");
1062 }
1063 
1064 OperandEncoding
rmRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1065 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1066                                                 uint8_t OpSize) {
1067   ENCODING("RST",             ENCODING_FP)
1068   ENCODING("RSTi",            ENCODING_FP)
1069   ENCODING("GR16",            ENCODING_RM)
1070   ENCODING("GR16orGR32orGR64",ENCODING_RM)
1071   ENCODING("GR32",            ENCODING_RM)
1072   ENCODING("GR32orGR64",      ENCODING_RM)
1073   ENCODING("GR64",            ENCODING_RM)
1074   ENCODING("GR8",             ENCODING_RM)
1075   ENCODING("VR128",           ENCODING_RM)
1076   ENCODING("VR128X",          ENCODING_RM)
1077   ENCODING("FR128",           ENCODING_RM)
1078   ENCODING("FR64",            ENCODING_RM)
1079   ENCODING("FR32",            ENCODING_RM)
1080   ENCODING("FR64X",           ENCODING_RM)
1081   ENCODING("FR32X",           ENCODING_RM)
1082   ENCODING("FR16X",           ENCODING_RM)
1083   ENCODING("VR64",            ENCODING_RM)
1084   ENCODING("VR256",           ENCODING_RM)
1085   ENCODING("VR256X",          ENCODING_RM)
1086   ENCODING("VR512",           ENCODING_RM)
1087   ENCODING("VK1",             ENCODING_RM)
1088   ENCODING("VK2",             ENCODING_RM)
1089   ENCODING("VK4",             ENCODING_RM)
1090   ENCODING("VK8",             ENCODING_RM)
1091   ENCODING("VK16",            ENCODING_RM)
1092   ENCODING("VK32",            ENCODING_RM)
1093   ENCODING("VK64",            ENCODING_RM)
1094   ENCODING("BNDR",            ENCODING_RM)
1095   ENCODING("TILE",            ENCODING_RM)
1096   errs() << "Unhandled R/M register encoding " << s << "\n";
1097   llvm_unreachable("Unhandled R/M register encoding");
1098 }
1099 
1100 OperandEncoding
roRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1101 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1102                                                 uint8_t OpSize) {
1103   ENCODING("GR16",            ENCODING_REG)
1104   ENCODING("GR16orGR32orGR64",ENCODING_REG)
1105   ENCODING("GR32",            ENCODING_REG)
1106   ENCODING("GR32orGR64",      ENCODING_REG)
1107   ENCODING("GR64",            ENCODING_REG)
1108   ENCODING("GR8",             ENCODING_REG)
1109   ENCODING("VR128",           ENCODING_REG)
1110   ENCODING("FR128",           ENCODING_REG)
1111   ENCODING("FR64",            ENCODING_REG)
1112   ENCODING("FR32",            ENCODING_REG)
1113   ENCODING("VR64",            ENCODING_REG)
1114   ENCODING("SEGMENT_REG",     ENCODING_REG)
1115   ENCODING("DEBUG_REG",       ENCODING_REG)
1116   ENCODING("CONTROL_REG",     ENCODING_REG)
1117   ENCODING("VR256",           ENCODING_REG)
1118   ENCODING("VR256X",          ENCODING_REG)
1119   ENCODING("VR128X",          ENCODING_REG)
1120   ENCODING("FR64X",           ENCODING_REG)
1121   ENCODING("FR32X",           ENCODING_REG)
1122   ENCODING("FR16X",           ENCODING_REG)
1123   ENCODING("VR512",           ENCODING_REG)
1124   ENCODING("VK1",             ENCODING_REG)
1125   ENCODING("VK2",             ENCODING_REG)
1126   ENCODING("VK4",             ENCODING_REG)
1127   ENCODING("VK8",             ENCODING_REG)
1128   ENCODING("VK16",            ENCODING_REG)
1129   ENCODING("VK32",            ENCODING_REG)
1130   ENCODING("VK64",            ENCODING_REG)
1131   ENCODING("VK1Pair",         ENCODING_REG)
1132   ENCODING("VK2Pair",         ENCODING_REG)
1133   ENCODING("VK4Pair",         ENCODING_REG)
1134   ENCODING("VK8Pair",         ENCODING_REG)
1135   ENCODING("VK16Pair",        ENCODING_REG)
1136   ENCODING("VK1WM",           ENCODING_REG)
1137   ENCODING("VK2WM",           ENCODING_REG)
1138   ENCODING("VK4WM",           ENCODING_REG)
1139   ENCODING("VK8WM",           ENCODING_REG)
1140   ENCODING("VK16WM",          ENCODING_REG)
1141   ENCODING("VK32WM",          ENCODING_REG)
1142   ENCODING("VK64WM",          ENCODING_REG)
1143   ENCODING("BNDR",            ENCODING_REG)
1144   ENCODING("TILE",            ENCODING_REG)
1145   errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1146   llvm_unreachable("Unhandled reg/opcode register encoding");
1147 }
1148 
1149 OperandEncoding
vvvvRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1150 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1151                                                   uint8_t OpSize) {
1152   ENCODING("GR32",            ENCODING_VVVV)
1153   ENCODING("GR64",            ENCODING_VVVV)
1154   ENCODING("FR32",            ENCODING_VVVV)
1155   ENCODING("FR128",           ENCODING_VVVV)
1156   ENCODING("FR64",            ENCODING_VVVV)
1157   ENCODING("VR128",           ENCODING_VVVV)
1158   ENCODING("VR256",           ENCODING_VVVV)
1159   ENCODING("FR16X",           ENCODING_VVVV)
1160   ENCODING("FR32X",           ENCODING_VVVV)
1161   ENCODING("FR64X",           ENCODING_VVVV)
1162   ENCODING("VR128X",          ENCODING_VVVV)
1163   ENCODING("VR256X",          ENCODING_VVVV)
1164   ENCODING("VR512",           ENCODING_VVVV)
1165   ENCODING("VK1",             ENCODING_VVVV)
1166   ENCODING("VK2",             ENCODING_VVVV)
1167   ENCODING("VK4",             ENCODING_VVVV)
1168   ENCODING("VK8",             ENCODING_VVVV)
1169   ENCODING("VK16",            ENCODING_VVVV)
1170   ENCODING("VK32",            ENCODING_VVVV)
1171   ENCODING("VK64",            ENCODING_VVVV)
1172   ENCODING("TILE",            ENCODING_VVVV)
1173   errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1174   llvm_unreachable("Unhandled VEX.vvvv register encoding");
1175 }
1176 
1177 OperandEncoding
writemaskRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1178 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1179                                                        uint8_t OpSize) {
1180   ENCODING("VK1WM",           ENCODING_WRITEMASK)
1181   ENCODING("VK2WM",           ENCODING_WRITEMASK)
1182   ENCODING("VK4WM",           ENCODING_WRITEMASK)
1183   ENCODING("VK8WM",           ENCODING_WRITEMASK)
1184   ENCODING("VK16WM",          ENCODING_WRITEMASK)
1185   ENCODING("VK32WM",          ENCODING_WRITEMASK)
1186   ENCODING("VK64WM",          ENCODING_WRITEMASK)
1187   errs() << "Unhandled mask register encoding " << s << "\n";
1188   llvm_unreachable("Unhandled mask register encoding");
1189 }
1190 
1191 OperandEncoding
memoryEncodingFromString(const std::string & s,uint8_t OpSize)1192 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1193                                             uint8_t OpSize) {
1194   ENCODING("i16mem",          ENCODING_RM)
1195   ENCODING("i32mem",          ENCODING_RM)
1196   ENCODING("i64mem",          ENCODING_RM)
1197   ENCODING("i8mem",           ENCODING_RM)
1198   ENCODING("shmem",           ENCODING_RM)
1199   ENCODING("ssmem",           ENCODING_RM)
1200   ENCODING("sdmem",           ENCODING_RM)
1201   ENCODING("f128mem",         ENCODING_RM)
1202   ENCODING("f256mem",         ENCODING_RM)
1203   ENCODING("f512mem",         ENCODING_RM)
1204   ENCODING("f64mem",          ENCODING_RM)
1205   ENCODING("f32mem",          ENCODING_RM)
1206   ENCODING("f16mem",          ENCODING_RM)
1207   ENCODING("i128mem",         ENCODING_RM)
1208   ENCODING("i256mem",         ENCODING_RM)
1209   ENCODING("i512mem",         ENCODING_RM)
1210   ENCODING("f80mem",          ENCODING_RM)
1211   ENCODING("lea64_32mem",     ENCODING_RM)
1212   ENCODING("lea64mem",        ENCODING_RM)
1213   ENCODING("anymem",          ENCODING_RM)
1214   ENCODING("opaquemem",       ENCODING_RM)
1215   ENCODING("sibmem",          ENCODING_SIB)
1216   ENCODING("vx64mem",         ENCODING_VSIB)
1217   ENCODING("vx128mem",        ENCODING_VSIB)
1218   ENCODING("vx256mem",        ENCODING_VSIB)
1219   ENCODING("vy128mem",        ENCODING_VSIB)
1220   ENCODING("vy256mem",        ENCODING_VSIB)
1221   ENCODING("vx64xmem",        ENCODING_VSIB)
1222   ENCODING("vx128xmem",       ENCODING_VSIB)
1223   ENCODING("vx256xmem",       ENCODING_VSIB)
1224   ENCODING("vy128xmem",       ENCODING_VSIB)
1225   ENCODING("vy256xmem",       ENCODING_VSIB)
1226   ENCODING("vy512xmem",       ENCODING_VSIB)
1227   ENCODING("vz256mem",        ENCODING_VSIB)
1228   ENCODING("vz512mem",        ENCODING_VSIB)
1229   errs() << "Unhandled memory encoding " << s << "\n";
1230   llvm_unreachable("Unhandled memory encoding");
1231 }
1232 
1233 OperandEncoding
relocationEncodingFromString(const std::string & s,uint8_t OpSize)1234 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1235                                                 uint8_t OpSize) {
1236   if(OpSize != X86Local::OpSize16) {
1237     // For instructions without an OpSize prefix, a declared 16-bit register or
1238     // immediate encoding is special.
1239     ENCODING("i16imm",           ENCODING_IW)
1240   }
1241   ENCODING("i16imm",             ENCODING_Iv)
1242   ENCODING("i16i8imm",           ENCODING_IB)
1243   ENCODING("i32imm",             ENCODING_Iv)
1244   ENCODING("i32i8imm",           ENCODING_IB)
1245   ENCODING("i64i32imm",          ENCODING_ID)
1246   ENCODING("i64i8imm",           ENCODING_IB)
1247   ENCODING("i8imm",              ENCODING_IB)
1248   ENCODING("u8imm",              ENCODING_IB)
1249   ENCODING("i16u8imm",           ENCODING_IB)
1250   ENCODING("i32u8imm",           ENCODING_IB)
1251   ENCODING("i64u8imm",           ENCODING_IB)
1252   ENCODING("i64i32imm_brtarget", ENCODING_ID)
1253   ENCODING("i16imm_brtarget",    ENCODING_IW)
1254   ENCODING("i32imm_brtarget",    ENCODING_ID)
1255   ENCODING("brtarget32",         ENCODING_ID)
1256   ENCODING("brtarget16",         ENCODING_IW)
1257   ENCODING("brtarget8",          ENCODING_IB)
1258   ENCODING("i64imm",             ENCODING_IO)
1259   ENCODING("offset16_8",         ENCODING_Ia)
1260   ENCODING("offset16_16",        ENCODING_Ia)
1261   ENCODING("offset16_32",        ENCODING_Ia)
1262   ENCODING("offset32_8",         ENCODING_Ia)
1263   ENCODING("offset32_16",        ENCODING_Ia)
1264   ENCODING("offset32_32",        ENCODING_Ia)
1265   ENCODING("offset32_64",        ENCODING_Ia)
1266   ENCODING("offset64_8",         ENCODING_Ia)
1267   ENCODING("offset64_16",        ENCODING_Ia)
1268   ENCODING("offset64_32",        ENCODING_Ia)
1269   ENCODING("offset64_64",        ENCODING_Ia)
1270   ENCODING("srcidx8",            ENCODING_SI)
1271   ENCODING("srcidx16",           ENCODING_SI)
1272   ENCODING("srcidx32",           ENCODING_SI)
1273   ENCODING("srcidx64",           ENCODING_SI)
1274   ENCODING("dstidx8",            ENCODING_DI)
1275   ENCODING("dstidx16",           ENCODING_DI)
1276   ENCODING("dstidx32",           ENCODING_DI)
1277   ENCODING("dstidx64",           ENCODING_DI)
1278   errs() << "Unhandled relocation encoding " << s << "\n";
1279   llvm_unreachable("Unhandled relocation encoding");
1280 }
1281 
1282 OperandEncoding
opcodeModifierEncodingFromString(const std::string & s,uint8_t OpSize)1283 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1284                                                     uint8_t OpSize) {
1285   ENCODING("GR32",            ENCODING_Rv)
1286   ENCODING("GR64",            ENCODING_RO)
1287   ENCODING("GR16",            ENCODING_Rv)
1288   ENCODING("GR8",             ENCODING_RB)
1289   ENCODING("ccode",           ENCODING_CC)
1290   errs() << "Unhandled opcode modifier encoding " << s << "\n";
1291   llvm_unreachable("Unhandled opcode modifier encoding");
1292 }
1293 #undef ENCODING
1294