1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the main function for LLVM's TableGen. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "TableGenBackends.h" // Declares all backends. 15 16 #include "SetTheory.h" 17 #include "llvm/Support/CommandLine.h" 18 #include "llvm/Support/PrettyStackTrace.h" 19 #include "llvm/Support/Signals.h" 20 #include "llvm/TableGen/Error.h" 21 #include "llvm/TableGen/Main.h" 22 #include "llvm/TableGen/Record.h" 23 24 using namespace llvm; 25 26 enum ActionType { 27 PrintRecords, 28 GenEmitter, 29 GenRegisterInfo, 30 GenInstrInfo, 31 GenAsmWriter, 32 GenAsmMatcher, 33 GenDisassembler, 34 GenPseudoLowering, 35 GenCallingConv, 36 GenDAGISel, 37 GenDFAPacketizer, 38 GenFastISel, 39 GenSubtarget, 40 GenIntrinsic, 41 GenTgtIntrinsic, 42 GenEDInfo, 43 PrintEnums, 44 PrintSets 45 }; 46 47 namespace { 48 cl::opt<ActionType> 49 Action(cl::desc("Action to perform:"), 50 cl::values(clEnumValN(PrintRecords, "print-records", 51 "Print all records to stdout (default)"), 52 clEnumValN(GenEmitter, "gen-emitter", 53 "Generate machine code emitter"), 54 clEnumValN(GenRegisterInfo, "gen-register-info", 55 "Generate registers and register classes info"), 56 clEnumValN(GenInstrInfo, "gen-instr-info", 57 "Generate instruction descriptions"), 58 clEnumValN(GenCallingConv, "gen-callingconv", 59 "Generate calling convention descriptions"), 60 clEnumValN(GenAsmWriter, "gen-asm-writer", 61 "Generate assembly writer"), 62 clEnumValN(GenDisassembler, "gen-disassembler", 63 "Generate disassembler"), 64 clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", 65 "Generate pseudo instruction lowering"), 66 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 67 "Generate assembly instruction matcher"), 68 clEnumValN(GenDAGISel, "gen-dag-isel", 69 "Generate a DAG instruction selector"), 70 clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer", 71 "Generate DFA Packetizer for VLIW targets"), 72 clEnumValN(GenFastISel, "gen-fast-isel", 73 "Generate a \"fast\" instruction selector"), 74 clEnumValN(GenSubtarget, "gen-subtarget", 75 "Generate subtarget enumerations"), 76 clEnumValN(GenIntrinsic, "gen-intrinsic", 77 "Generate intrinsic information"), 78 clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", 79 "Generate target intrinsic information"), 80 clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info", 81 "Generate enhanced disassembly info"), 82 clEnumValN(PrintEnums, "print-enums", 83 "Print enum values for a class"), 84 clEnumValN(PrintSets, "print-sets", 85 "Print expanded sets for testing DAG exprs"), 86 clEnumValEnd)); 87 88 cl::opt<std::string> 89 Class("class", cl::desc("Print Enum list for this class"), 90 cl::value_desc("class name")); 91 92 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 93 switch (Action) { 94 case PrintRecords: 95 OS << Records; // No argument, dump all contents 96 break; 97 case GenEmitter: 98 EmitCodeEmitter(Records, OS); 99 break; 100 case GenRegisterInfo: 101 EmitRegisterInfo(Records, OS); 102 break; 103 case GenInstrInfo: 104 EmitInstrInfo(Records, OS); 105 break; 106 case GenCallingConv: 107 EmitCallingConv(Records, OS); 108 break; 109 case GenAsmWriter: 110 EmitAsmWriter(Records, OS); 111 break; 112 case GenAsmMatcher: 113 EmitAsmMatcher(Records, OS); 114 break; 115 case GenDisassembler: 116 EmitDisassembler(Records, OS); 117 break; 118 case GenPseudoLowering: 119 EmitPseudoLowering(Records, OS); 120 break; 121 case GenDAGISel: 122 EmitDAGISel(Records, OS); 123 break; 124 case GenDFAPacketizer: 125 EmitDFAPacketizer(Records, OS); 126 break; 127 case GenFastISel: 128 EmitFastISel(Records, OS); 129 break; 130 case GenSubtarget: 131 EmitSubtarget(Records, OS); 132 break; 133 case GenIntrinsic: 134 EmitIntrinsics(Records, OS); 135 break; 136 case GenTgtIntrinsic: 137 EmitIntrinsics(Records, OS, true); 138 break; 139 case GenEDInfo: 140 EmitEnhancedDisassemblerInfo(Records, OS); 141 break; 142 case PrintEnums: 143 { 144 std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class); 145 for (unsigned i = 0, e = Recs.size(); i != e; ++i) 146 OS << Recs[i]->getName() << ", "; 147 OS << "\n"; 148 break; 149 } 150 case PrintSets: 151 { 152 SetTheory Sets; 153 Sets.addFieldExpander("Set", "Elements"); 154 std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set"); 155 for (unsigned i = 0, e = Recs.size(); i != e; ++i) { 156 OS << Recs[i]->getName() << " = ["; 157 const std::vector<Record*> *Elts = Sets.expand(Recs[i]); 158 assert(Elts && "Couldn't expand Set instance"); 159 for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei) 160 OS << ' ' << (*Elts)[ei]->getName(); 161 OS << " ]\n"; 162 } 163 break; 164 } 165 } 166 167 return false; 168 } 169 } 170 171 int main(int argc, char **argv) { 172 sys::PrintStackTraceOnErrorSignal(); 173 PrettyStackTraceProgram X(argc, argv); 174 cl::ParseCommandLineOptions(argc, argv); 175 176 return TableGenMain(argv[0], &LLVMTableGenMain); 177 } 178