1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the main function for LLVM's TableGen. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "TableGenBackends.h" // Declares all backends. 15 #include "llvm/Support/CommandLine.h" 16 #include "llvm/Support/PrettyStackTrace.h" 17 #include "llvm/Support/Signals.h" 18 #include "llvm/TableGen/Error.h" 19 #include "llvm/TableGen/Main.h" 20 #include "llvm/TableGen/Record.h" 21 #include "llvm/TableGen/SetTheory.h" 22 23 using namespace llvm; 24 25 enum ActionType { 26 PrintRecords, 27 GenEmitter, 28 GenRegisterInfo, 29 GenInstrInfo, 30 GenAsmWriter, 31 GenAsmMatcher, 32 GenDisassembler, 33 GenPseudoLowering, 34 GenCallingConv, 35 GenDAGISel, 36 GenDFAPacketizer, 37 GenFastISel, 38 GenSubtarget, 39 GenIntrinsic, 40 GenTgtIntrinsic, 41 PrintEnums, 42 PrintSets, 43 GenOptParserDefs, 44 GenCTags, 45 GenAttributes 46 }; 47 48 namespace { 49 cl::opt<ActionType> 50 Action(cl::desc("Action to perform:"), 51 cl::values(clEnumValN(PrintRecords, "print-records", 52 "Print all records to stdout (default)"), 53 clEnumValN(GenEmitter, "gen-emitter", 54 "Generate machine code emitter"), 55 clEnumValN(GenRegisterInfo, "gen-register-info", 56 "Generate registers and register classes info"), 57 clEnumValN(GenInstrInfo, "gen-instr-info", 58 "Generate instruction descriptions"), 59 clEnumValN(GenCallingConv, "gen-callingconv", 60 "Generate calling convention descriptions"), 61 clEnumValN(GenAsmWriter, "gen-asm-writer", 62 "Generate assembly writer"), 63 clEnumValN(GenDisassembler, "gen-disassembler", 64 "Generate disassembler"), 65 clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", 66 "Generate pseudo instruction lowering"), 67 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 68 "Generate assembly instruction matcher"), 69 clEnumValN(GenDAGISel, "gen-dag-isel", 70 "Generate a DAG instruction selector"), 71 clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer", 72 "Generate DFA Packetizer for VLIW targets"), 73 clEnumValN(GenFastISel, "gen-fast-isel", 74 "Generate a \"fast\" instruction selector"), 75 clEnumValN(GenSubtarget, "gen-subtarget", 76 "Generate subtarget enumerations"), 77 clEnumValN(GenIntrinsic, "gen-intrinsic", 78 "Generate intrinsic information"), 79 clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", 80 "Generate target intrinsic information"), 81 clEnumValN(PrintEnums, "print-enums", 82 "Print enum values for a class"), 83 clEnumValN(PrintSets, "print-sets", 84 "Print expanded sets for testing DAG exprs"), 85 clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", 86 "Generate option definitions"), 87 clEnumValN(GenCTags, "gen-ctags", 88 "Generate ctags-compatible index"), 89 clEnumValN(GenAttributes, "gen-attrs", 90 "Generate attributes"), 91 clEnumValEnd)); 92 93 cl::opt<std::string> 94 Class("class", cl::desc("Print Enum list for this class"), 95 cl::value_desc("class name")); 96 97 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 98 switch (Action) { 99 case PrintRecords: 100 OS << Records; // No argument, dump all contents 101 break; 102 case GenEmitter: 103 EmitCodeEmitter(Records, OS); 104 break; 105 case GenRegisterInfo: 106 EmitRegisterInfo(Records, OS); 107 break; 108 case GenInstrInfo: 109 EmitInstrInfo(Records, OS); 110 break; 111 case GenCallingConv: 112 EmitCallingConv(Records, OS); 113 break; 114 case GenAsmWriter: 115 EmitAsmWriter(Records, OS); 116 break; 117 case GenAsmMatcher: 118 EmitAsmMatcher(Records, OS); 119 break; 120 case GenDisassembler: 121 EmitDisassembler(Records, OS); 122 break; 123 case GenPseudoLowering: 124 EmitPseudoLowering(Records, OS); 125 break; 126 case GenDAGISel: 127 EmitDAGISel(Records, OS); 128 break; 129 case GenDFAPacketizer: 130 EmitDFAPacketizer(Records, OS); 131 break; 132 case GenFastISel: 133 EmitFastISel(Records, OS); 134 break; 135 case GenSubtarget: 136 EmitSubtarget(Records, OS); 137 break; 138 case GenIntrinsic: 139 EmitIntrinsics(Records, OS); 140 break; 141 case GenTgtIntrinsic: 142 EmitIntrinsics(Records, OS, true); 143 break; 144 case GenOptParserDefs: 145 EmitOptParser(Records, OS); 146 break; 147 case PrintEnums: 148 { 149 for (Record *Rec : Records.getAllDerivedDefinitions(Class)) 150 OS << Rec->getName() << ", "; 151 OS << "\n"; 152 break; 153 } 154 case PrintSets: 155 { 156 SetTheory Sets; 157 Sets.addFieldExpander("Set", "Elements"); 158 for (Record *Rec : Records.getAllDerivedDefinitions("Set")) { 159 OS << Rec->getName() << " = ["; 160 const std::vector<Record*> *Elts = Sets.expand(Rec); 161 assert(Elts && "Couldn't expand Set instance"); 162 for (Record *Elt : *Elts) 163 OS << ' ' << Elt->getName(); 164 OS << " ]\n"; 165 } 166 break; 167 } 168 case GenCTags: 169 EmitCTags(Records, OS); 170 break; 171 case GenAttributes: 172 EmitAttributes(Records, OS); 173 break; 174 } 175 176 return false; 177 } 178 } 179 180 int main(int argc, char **argv) { 181 sys::PrintStackTraceOnErrorSignal(); 182 PrettyStackTraceProgram X(argc, argv); 183 cl::ParseCommandLineOptions(argc, argv); 184 185 return TableGenMain(argv[0], &LLVMTableGenMain); 186 } 187 188 #ifdef __has_feature 189 #if __has_feature(address_sanitizer) 190 #include <sanitizer/lsan_interface.h> 191 // Disable LeakSanitizer for this binary as it has too many leaks that are not 192 // very interesting to fix. See compiler-rt/include/sanitizer/lsan_interface.h . 193 int __lsan_is_turned_off() { return 1; } 194 #endif // __has_feature(address_sanitizer) 195 #endif // defined(__has_feature) 196