1 //===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "AMDGPUSubtarget.h"
10 #include "AMDGPUTargetMachine.h"
11 #include "llvm/CodeGen/TargetSubtargetInfo.h"
12 #include "llvm/MC/MCTargetOptions.h"
13 #include "llvm/MC/TargetRegistry.h"
14 #include "llvm/Support/TargetSelect.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "gtest/gtest.h"
17 #include <thread>
18
19 using namespace llvm;
20
21 std::once_flag flag;
22
InitializeAMDGPUTarget()23 void InitializeAMDGPUTarget() {
24 std::call_once(flag, []() {
25 LLVMInitializeAMDGPUTargetInfo();
26 LLVMInitializeAMDGPUTarget();
27 LLVMInitializeAMDGPUTargetMC();
28 });
29 }
30
31 std::unique_ptr<const GCNTargetMachine>
createTargetMachine(std::string TStr,StringRef CPU,StringRef FS)32 createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
33 InitializeAMDGPUTarget();
34
35 std::string Error;
36 const Target *T = TargetRegistry::lookupTarget(TStr, Error);
37 if (!T)
38 return nullptr;
39
40 TargetOptions Options;
41 return std::unique_ptr<GCNTargetMachine>(static_cast<GCNTargetMachine *>(
42 T->createTargetMachine(TStr, CPU, FS, Options, None, None)));
43 }
44
TEST(AMDGPUDwarfRegMappingTests,TestWave64DwarfRegMapping)45 TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
46 for (auto Triple :
47 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
48 auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
49 if (TM) {
50 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
51 std::string(TM->getTargetFeatureString()), *TM);
52 auto MRI = ST.getRegisterInfo();
53 if (MRI) {
54 // Wave64 Dwarf register mapping test numbers
55 // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
56 // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
57 // A0 => 3072, A255 => 3327
58 for (int llvmReg :
59 {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
60 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
61 EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
62 }
63 }
64 }
65 }
66 }
67
TEST(AMDGPUDwarfRegMappingTests,TestWave32DwarfRegMapping)68 TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
69 for (auto Triple :
70 {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
71 auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
72 if (TM) {
73 GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
74 std::string(TM->getTargetFeatureString()), *TM);
75 auto MRI = ST.getRegisterInfo();
76 if (MRI) {
77 // Wave32 Dwarf register mapping test numbers
78 // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
79 // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
80 // A0 => 2048, A255 => 2303
81 for (int llvmReg :
82 {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
83 MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
84 EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
85 }
86 }
87 }
88 }
89 }
90