1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
3
4define i64 @i64_test(i64 %i) nounwind readnone {
5; CHECK-LABEL: i64_test:
6; CHECK:       ; %bb.0:
7; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; CHECK-NEXT:    v_mov_b32_e32 v1, 0
9; CHECK-NEXT:    s_setpc_b64 s[30:31]
10  %loc = alloca i64
11  %j = load i64, i64 * %loc
12  %r = add i64 %i, %j
13  ret i64 %r
14}
15
16define i64 @i32_test(i32 %i) nounwind readnone {
17; CHECK-LABEL: i32_test:
18; CHECK:       ; %bb.0:
19; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; CHECK-NEXT:    v_mov_b32_e32 v0, 0
21; CHECK-NEXT:    v_mov_b32_e32 v1, 0
22; CHECK-NEXT:    s_setpc_b64 s[30:31]
23  %loc = alloca i32
24  %j = load i32, i32 * %loc
25  %r = add i32 %i, %j
26  %ext = zext i32 %r to i64
27  ret i64 %ext
28}
29
30define i64 @i16_test(i16 %i) nounwind readnone {
31; CHECK-LABEL: i16_test:
32; CHECK:       ; %bb.0:
33; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
34; CHECK-NEXT:    v_mov_b32_e32 v0, 0
35; CHECK-NEXT:    v_mov_b32_e32 v1, 0
36; CHECK-NEXT:    s_setpc_b64 s[30:31]
37  %loc = alloca i16
38  %j = load i16, i16 * %loc
39  %r = add i16 %i, %j
40  %ext = zext i16 %r to i64
41  ret i64 %ext
42}
43
44define i64 @i8_test(i8 %i) nounwind readnone {
45; CHECK-LABEL: i8_test:
46; CHECK:       ; %bb.0:
47; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48; CHECK-NEXT:    v_mov_b32_e32 v0, 0
49; CHECK-NEXT:    v_mov_b32_e32 v1, 0
50; CHECK-NEXT:    s_setpc_b64 s[30:31]
51  %loc = alloca i8
52  %j = load i8, i8 * %loc
53  %r = add i8 %i, %j
54  %ext = zext i8 %r to i64
55  ret i64 %ext
56}
57