1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -slp-vectorizer < %s -S -mtriple="x86_64-grtev3-linux-gnu" -mcpu=corei7-avx | FileCheck %s
3
4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
5
6; We used to crash on this example because we were building a constant
7; expression during vectorization and the vectorizer expects instructions
8; as elements of the vectorized tree.
9; PR19621
10
11define void @test() {
12; CHECK-LABEL: @test(
13; CHECK-NEXT:  bb279:
14; CHECK-NEXT:    br label [[BB283:%.*]]
15; CHECK:       bb283:
16; CHECK-NEXT:    [[TMP0:%.*]] = phi <2 x float> [ undef, [[BB279:%.*]] ], [ [[TMP11:%.*]], [[EXIT:%.*]] ]
17; CHECK-NEXT:    [[TMP1:%.*]] = phi <2 x float> [ undef, [[BB279]] ], [ undef, [[EXIT]] ]
18; CHECK-NEXT:    br label [[BB284:%.*]]
19; CHECK:       bb284:
20; CHECK-NEXT:    [[TMP2:%.*]] = fpext <2 x float> [[TMP0]] to <2 x double>
21; CHECK-NEXT:    [[TMP3:%.*]] = fsub <2 x double> [[TMP2]], undef
22; CHECK-NEXT:    [[TMP4:%.*]] = fsub <2 x double> [[TMP3]], undef
23; CHECK-NEXT:    br label [[BB21_I:%.*]]
24; CHECK:       bb21.i:
25; CHECK-NEXT:    br i1 undef, label [[BB22_I:%.*]], label [[EXIT]]
26; CHECK:       bb22.i:
27; CHECK-NEXT:    [[TMP5:%.*]] = fadd <2 x double> undef, [[TMP4]]
28; CHECK-NEXT:    br label [[BB32_I:%.*]]
29; CHECK:       bb32.i:
30; CHECK-NEXT:    [[TMP6:%.*]] = phi <2 x double> [ [[TMP5]], [[BB22_I]] ], [ zeroinitializer, [[BB32_I]] ]
31; CHECK-NEXT:    br i1 undef, label [[BB32_I]], label [[BB21_I]]
32; CHECK:       exit:
33; CHECK-NEXT:    [[TMP7:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
34; CHECK-NEXT:    [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], <double undef, double 0.000000e+00>
35; CHECK-NEXT:    [[TMP9:%.*]] = fadd <2 x double> undef, [[TMP8]]
36; CHECK-NEXT:    [[TMP10:%.*]] = fadd <2 x double> [[TMP9]], undef
37; CHECK-NEXT:    [[TMP11]] = fptrunc <2 x double> [[TMP10]] to <2 x float>
38; CHECK-NEXT:    br label [[BB283]]
39;
40bb279:
41  br label %bb283
42
43bb283:
44  %Av.sroa.8.0 = phi float [ undef, %bb279 ], [ %tmp315, %exit ]
45  %Av.sroa.5.0 = phi float [ undef, %bb279 ], [ %tmp319, %exit ]
46  %Av.sroa.3.0 = phi float [ undef, %bb279 ], [ %tmp307, %exit ]
47  %Av.sroa.0.0 = phi float [ undef, %bb279 ], [ %tmp317, %exit ]
48  br label %bb284
49
50bb284:
51  %tmp7.i = fpext float %Av.sroa.3.0 to double
52  %tmp8.i = fsub double %tmp7.i, undef
53  %tmp9.i = fsub double %tmp8.i, undef
54  %tmp17.i = fpext float %Av.sroa.8.0 to double
55  %tmp19.i = fsub double %tmp17.i, undef
56  %tmp20.i = fsub double %tmp19.i, undef
57  br label %bb21.i
58
59bb21.i:
60  br i1 undef, label %bb22.i, label %exit
61
62bb22.i:
63  %tmp24.i = fadd double undef, %tmp9.i
64  %tmp26.i = fadd double undef, %tmp20.i
65  br label %bb32.i
66
67bb32.i:
68  %xs.0.i = phi double [ %tmp24.i, %bb22.i ], [ 0.000000e+00, %bb32.i ]
69  %ys.0.i = phi double [ %tmp26.i, %bb22.i ], [ 0.000000e+00, %bb32.i ]
70  br i1 undef, label %bb32.i, label %bb21.i
71
72exit:
73  %tmp303 = fpext float %Av.sroa.0.0 to double
74  %tmp304 = fmul double %tmp303, undef
75  %tmp305 = fadd double undef, %tmp304
76  %tmp306 = fadd double %tmp305, undef
77  %tmp307 = fptrunc double %tmp306 to float
78  %tmp311 = fpext float %Av.sroa.5.0 to double
79  %tmp312 = fmul double %tmp311, 0.000000e+00
80  %tmp313 = fadd double undef, %tmp312
81  %tmp314 = fadd double %tmp313, undef
82  %tmp315 = fptrunc double %tmp314 to float
83  %tmp317 = fptrunc double undef to float
84  %tmp319 = fptrunc double undef to float
85  br label %bb283
86}
87
88; Make sure that we probably handle constant folded vectorized trees. The
89; vectorizer starts at the type (%t2, %t3) and wil constant fold the tree.
90; The code that handles insertelement instructions must handle this.
91define <4 x double> @constant_folding() {
92; CHECK-LABEL: @constant_folding(
93; CHECK-NEXT:  entry:
94; CHECK-NEXT:    ret <4 x double> <double 2.000000e+00, double 1.000000e+00, double undef, double undef>
95;
96entry:
97  %t0 = fadd double 1.000000e+00 , 0.000000e+00
98  %t1 = fadd double 1.000000e+00 , 1.000000e+00
99  %t2 = fmul double %t0, 1.000000e+00
100  %i1 = insertelement <4 x double> undef, double %t2, i32 1
101  %t3 = fmul double %t1, 1.000000e+00
102  %i2 = insertelement <4 x double> %i1, double %t3, i32 0
103  ret <4 x double> %i2
104}
105