1; REQUIRES: asserts 2 3; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -enable-interleaved-mem-accesses=true -enable-masked-interleaved-mem-accesses -disable-output %s 2>&1 | FileCheck %s 4 5target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 6 7; Tests for printing VPlans. 8 9define void @print_call_and_memory(i64 %n, float* noalias %y, float* noalias %x) nounwind uwtable { 10; CHECK-LABEL: Checking a loop in "print_call_and_memory" 11; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 12; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 13; CHECK-EMPTY: 14; CHECK-NEXT: <x1> vector loop: { 15; CHECK-NEXT: for.body: 16; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 17; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, 0 18; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> 19; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> 20; CHECK-NEXT: WIDEN-CALL ir<%call> = call @llvm.sqrt.f32(ir<%lv>) 21; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv> 22; CHECK-NEXT: WIDEN store ir<%arrayidx2>, ir<%call> 23; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 24; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 25; CHECK-NEXT: No successors 26; CHECK-NEXT: } 27; CHECK-NEXT: No successors 28; CHECK-NEXT: } 29; 30entry: 31 %cmp6 = icmp sgt i64 %n, 0 32 br i1 %cmp6, label %for.body, label %for.end 33 34for.body: ; preds = %entry, %for.body 35 %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ] 36 %arrayidx = getelementptr inbounds float, float* %y, i64 %iv 37 %lv = load float, float* %arrayidx, align 4 38 %call = tail call float @llvm.sqrt.f32(float %lv) nounwind readnone 39 %arrayidx2 = getelementptr inbounds float, float* %x, i64 %iv 40 store float %call, float* %arrayidx2, align 4 41 %iv.next = add i64 %iv, 1 42 %exitcond = icmp eq i64 %iv.next, %n 43 br i1 %exitcond, label %for.end, label %for.body 44 45for.end: ; preds = %for.body, %entry 46 ret void 47} 48 49define void @print_widen_gep_and_select(i64 %n, float* noalias %y, float* noalias %x, float* %z) nounwind uwtable { 50; CHECK-LABEL: Checking a loop in "print_widen_gep_and_select" 51; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 52; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 53; CHECK-EMPTY: 54; CHECK-NEXT: <x1> vector loop: { 55; CHECK-NEXT: for.body: 56; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 57; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, 0 58; CHECK-NEXT: WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> 59; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> 60; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z> 61; CHECK-NEXT: WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01> 62; CHECK-NEXT: WIDEN ir<%add> = fadd ir<%lv>, ir<%sel> 63; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%x>, ir<%iv> 64; CHECK-NEXT: WIDEN store ir<%arrayidx2>, ir<%add> 65; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 66; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 67; CHECK-NEXT: No successors 68; CHECK-NEXT: } 69; CHECK-NEXT: No successors 70; CHECK-NEXT: } 71; 72entry: 73 %cmp6 = icmp sgt i64 %n, 0 74 br i1 %cmp6, label %for.body, label %for.end 75 76for.body: ; preds = %entry, %for.body 77 %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ] 78 %arrayidx = getelementptr inbounds float, float* %y, i64 %iv 79 %lv = load float, float* %arrayidx, align 4 80 %cmp = icmp eq float* %arrayidx, %z 81 %sel = select i1 %cmp, float 10.0, float 20.0 82 %add = fadd float %lv, %sel 83 %arrayidx2 = getelementptr inbounds float, float* %x, i64 %iv 84 store float %add, float* %arrayidx2, align 4 85 %iv.next = add i64 %iv, 1 86 %exitcond = icmp eq i64 %iv.next, %n 87 br i1 %exitcond, label %for.end, label %for.body 88 89for.end: ; preds = %for.body, %entry 90 ret void 91} 92 93define float @print_reduction(i64 %n, float* noalias %y) { 94; CHECK-LABEL: Checking a loop in "print_reduction" 95; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 96; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 97; CHECK-EMPTY: 98; CHECK-NEXT: <x1> vector loop: { 99; CHECK-NEXT: for.body: 100; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 101; CHECK-NEXT: WIDEN-INDUCTION %iv = phi %iv.next, 0 102; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi ir<0.000000e+00>, ir<%red.next> 103; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%y>, ir<%iv> 104; CHECK-NEXT: WIDEN ir<%lv> = load ir<%arrayidx> 105; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>) 106; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 107; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 108; CHECK-NEXT: No successors 109; CHECK-NEXT: } 110; CHECK-NEXT: No successors 111; CHECK-NEXT: } 112; 113entry: 114 br label %for.body 115 116for.body: ; preds = %entry, %for.body 117 %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ] 118 %red = phi float [ %red.next, %for.body ], [ 0.0, %entry ] 119 %arrayidx = getelementptr inbounds float, float* %y, i64 %iv 120 %lv = load float, float* %arrayidx, align 4 121 %red.next = fadd fast float %lv, %red 122 %iv.next = add i64 %iv, 1 123 %exitcond = icmp eq i64 %iv.next, %n 124 br i1 %exitcond, label %for.end, label %for.body 125 126for.end: ; preds = %for.body, %entry 127 ret float %red.next 128} 129 130define void @print_replicate_predicated_phi(i64 %n, i64* %x) { 131; CHECK-LABEL: Checking a loop in "print_replicate_predicated_phi" 132; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 133; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 134; CHECK-EMPTY: 135; CHECK-NEXT: <x1> vector loop: { 136; CHECK-NEXT: for.body: 137; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 138; CHECK-NEXT: WIDEN-INDUCTION %i = phi 0, %i.next 139; CHECK-NEXT: WIDEN ir<%cmp> = icmp ir<%i>, ir<5> 140; CHECK-NEXT: Successor(s): if.then 141; CHECK-EMPTY: 142; CHECK-NEXT: if.then: 143; CHECK-NEXT: Successor(s): pred.udiv 144; CHECK-EMPTY: 145; CHECK-NEXT: <xVFxUF> pred.udiv: { 146; CHECK-NEXT: pred.udiv.entry: 147; CHECK-NEXT: BRANCH-ON-MASK ir<%cmp> 148; CHECK-NEXT: Successor(s): pred.udiv.if, pred.udiv.continue 149; CHECK-NEXT: CondBit: ir<%cmp> 150; CHECK-EMPTY: 151; CHECK-NEXT: pred.udiv.if: 152; CHECK-NEXT: REPLICATE ir<%tmp4> = udiv ir<%n>, ir<%i> (S->V) 153; CHECK-NEXT: Successor(s): pred.udiv.continue 154; CHECK-EMPTY: 155; CHECK-NEXT: pred.udiv.continue: 156; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%tmp4> 157; CHECK-NEXT: No successors 158; CHECK-NEXT: } 159; CHECK-NEXT: Successor(s): if.then.0 160; CHECK-EMPTY: 161; CHECK-NEXT: if.then.0: 162; CHECK-NEXT: Successor(s): for.inc 163; CHECK-EMPTY: 164; CHECK-NEXT: for.inc: 165; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%cmp> 166; CHECK-NEXT: BLEND %d = ir<0>/vp<[[NOT]]> vp<[[PRED]]>/ir<%cmp> 167; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%x>, ir<%i> 168; CHECK-NEXT: WIDEN store ir<%idx>, ir<%d> 169; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 170; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 171; CHECK-NEXT: No successors 172; CHECK-NEXT: } 173; CHECK-NEXT: No successors 174; CHECK-NEXT: } 175; 176entry: 177 br label %for.body 178 179for.body: ; preds = %for.inc, %entry 180 %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ] 181 %cmp = icmp ult i64 %i, 5 182 br i1 %cmp, label %if.then, label %for.inc 183 184if.then: ; preds = %for.body 185 %tmp4 = udiv i64 %n, %i 186 br label %for.inc 187 188for.inc: ; preds = %if.then, %for.body 189 %d = phi i64 [ 0, %for.body ], [ %tmp4, %if.then ] 190 %idx = getelementptr i64, i64* %x, i64 %i 191 store i64 %d, i64* %idx 192 %i.next = add nuw nsw i64 %i, 1 193 %cond = icmp slt i64 %i.next, %n 194 br i1 %cond, label %for.body, label %for.end 195 196for.end: ; preds = %for.inc 197 ret void 198} 199 200@AB = common global [1024 x i32] zeroinitializer, align 4 201@CD = common global [1024 x i32] zeroinitializer, align 4 202 203define void @print_interleave_groups(i32 %C, i32 %D) { 204; CHECK-LABEL: Checking a loop in "print_interleave_groups" 205; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 206; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 207; CHECK-EMPTY: 208; CHECK-NEXT: <x1> vector loop: { 209; CHECK-NEXT: for.body: 210; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 211; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 212; CHECK-NEXT: CLONE ir<%gep.AB.0> = getelementptr ir<@AB>, ir<0>, ir<%iv> 213; CHECK-NEXT: INTERLEAVE-GROUP with factor 4 at %AB.0, ir<%gep.AB.0> 214; CHECK-NEXT: ir<%AB.0> = load from index 0 215; CHECK-NEXT: ir<%AB.1> = load from index 1 216; CHECK-NEXT: ir<%AB.3> = load from index 3 217; CHECK-NEXT: CLONE ir<%iv.plus.1> = add ir<%iv>, ir<1> 218; CHECK-NEXT: CLONE ir<%gep.AB.1> = getelementptr ir<@AB>, ir<0>, ir<%iv.plus.1> 219; CHECK-NEXT: CLONE ir<%iv.plus.2> = add ir<%iv>, ir<2> 220; CHECK-NEXT: CLONE ir<%iv.plus.3> = add ir<%iv>, ir<3> 221; CHECK-NEXT: CLONE ir<%gep.AB.3> = getelementptr ir<@AB>, ir<0>, ir<%iv.plus.3> 222; CHECK-NEXT: WIDEN ir<%add> = add ir<%AB.0>, ir<%AB.1> 223; CHECK-NEXT: CLONE ir<%gep.CD.0> = getelementptr ir<@CD>, ir<0>, ir<%iv> 224; CHECK-NEXT: CLONE ir<%gep.CD.1> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.1> 225; CHECK-NEXT: CLONE ir<%gep.CD.2> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.2> 226; CHECK-NEXT: CLONE ir<%gep.CD.3> = getelementptr ir<@CD>, ir<0>, ir<%iv.plus.3> 227; CHECK-NEXT: INTERLEAVE-GROUP with factor 4 at <badref>, ir<%gep.CD.3> 228; CHECK-NEXT: store ir<%add> to index 0 229; CHECK-NEXT: store ir<1> to index 1 230; CHECK-NEXT: store ir<2> to index 2 231; CHECK-NEXT: store ir<%AB.3> to index 3 232; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 233; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 234; CHECK-NEXT: No successors 235; CHECK-NEXT: } 236; CHECK-NEXT: No successors 237; CHECK-NEXT: } 238; 239entry: 240 br label %for.body 241 242for.body: 243 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] 244 %gep.AB.0= getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %iv 245 %AB.0 = load i32, i32* %gep.AB.0, align 4 246 %iv.plus.1 = add i64 %iv, 1 247 %gep.AB.1 = getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %iv.plus.1 248 %AB.1 = load i32, i32* %gep.AB.1, align 4 249 %iv.plus.2 = add i64 %iv, 2 250 %iv.plus.3 = add i64 %iv, 3 251 %gep.AB.3 = getelementptr inbounds [1024 x i32], [1024 x i32]* @AB, i64 0, i64 %iv.plus.3 252 %AB.3 = load i32, i32* %gep.AB.3, align 4 253 %add = add nsw i32 %AB.0, %AB.1 254 %gep.CD.0 = getelementptr inbounds [1024 x i32], [1024 x i32]* @CD, i64 0, i64 %iv 255 store i32 %add, i32* %gep.CD.0, align 4 256 %gep.CD.1 = getelementptr inbounds [1024 x i32], [1024 x i32]* @CD, i64 0, i64 %iv.plus.1 257 store i32 1, i32* %gep.CD.1, align 4 258 %gep.CD.2 = getelementptr inbounds [1024 x i32], [1024 x i32]* @CD, i64 0, i64 %iv.plus.2 259 store i32 2, i32* %gep.CD.2, align 4 260 %gep.CD.3 = getelementptr inbounds [1024 x i32], [1024 x i32]* @CD, i64 0, i64 %iv.plus.3 261 store i32 %AB.3, i32* %gep.CD.3, align 4 262 %iv.next = add nuw nsw i64 %iv, 4 263 %cmp = icmp slt i64 %iv.next, 1024 264 br i1 %cmp, label %for.body, label %for.end 265 266for.end: 267 ret void 268} 269 270define float @print_fmuladd_strict(float* %a, float* %b, i64 %n) { 271; CHECK-LABEL: Checking a loop in "print_fmuladd_strict" 272; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 273; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 274; CHECK-EMPTY: 275; CHECK-NEXT: <x1> vector loop: { 276; CHECK-NEXT: for.body: 277; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 278; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 279; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%sum.07> = phi ir<0.000000e+00>, ir<%muladd> 280; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr ir<%a>, ir<%iv> 281; CHECK-NEXT: WIDEN ir<%l.a> = load ir<%arrayidx> 282; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr ir<%b>, ir<%iv> 283; CHECK-NEXT: WIDEN ir<%l.b> = load ir<%arrayidx2> 284; CHECK-NEXT: EMIT vp<[[FMUL:%.]]> = fmul nnan ninf nsz ir<%l.a> ir<%l.b> 285; CHECK-NEXT: REDUCE ir<[[MULADD:%.+]]> = ir<%sum.07> + nnan ninf nsz reduce.fadd (vp<[[FMUL]]>) 286; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 287; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 288; CHECK-NEXT: No successors 289; CHECK-NEXT: } 290 291entry: 292 br label %for.body 293 294for.body: 295 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] 296 %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %for.body ] 297 %arrayidx = getelementptr inbounds float, float* %a, i64 %iv 298 %l.a = load float, float* %arrayidx, align 4 299 %arrayidx2 = getelementptr inbounds float, float* %b, i64 %iv 300 %l.b = load float, float* %arrayidx2, align 4 301 %muladd = tail call nnan ninf nsz float @llvm.fmuladd.f32(float %l.a, float %l.b, float %sum.07) 302 %iv.next = add nuw nsw i64 %iv, 1 303 %exitcond.not = icmp eq i64 %iv.next, %n 304 br i1 %exitcond.not, label %for.end, label %for.body 305 306for.end: 307 ret float %muladd 308} 309 310define void @debug_loc_vpinstruction(i32* nocapture %asd, i32* nocapture %bsd) !dbg !5 { 311; CHECK-LABEL: Checking a loop in "debug_loc_vpinstruction" 312; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { 313; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count 314; CHECK-EMPTY: 315; CHECK-NEXT: <x1> vector loop: { 316; CHECK-NEXT: loop: 317; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION 318; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next 319; CHECK-NEXT: CLONE ir<%isd> = getelementptr ir<%asd>, ir<%iv> 320; CHECK-NEXT: WIDEN ir<%lsd> = load ir<%isd> 321; CHECK-NEXT: WIDEN ir<%psd> = add ir<%lsd>, ir<23> 322; CHECK-NEXT: WIDEN ir<%cmp1> = icmp ir<%lsd>, ir<100> 323; CHECK-NEXT: Successor(s): check 324; CHECK-EMPTY: 325; CHECK-NEXT: check: 326; CHECK-NEXT: WIDEN ir<%cmp2> = icmp ir<%lsd>, ir<200> 327; CHECK-NEXT: Successor(s): if.then 328; CHECK-EMPTY: 329; CHECK-NEXT: if.then: 330; CHECK-NEXT: EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:5:3 331; CHECK-NEXT: EMIT vp<[[SEL1:%.+]]> = select vp<[[NOT1]]> ir<%cmp2> ir<false>, !dbg /tmp/s.c:5:21 332; CHECK-NEXT: EMIT vp<[[OR1:%.+]]> = or vp<[[SEL1]]> ir<%cmp1> 333; CHECK-NEXT: Successor(s): pred.sdiv 334; CHECK-EMPTY: 335; CHECK-NEXT: <xVFxUF> pred.sdiv: { 336; CHECK-NEXT: pred.sdiv.entry: 337; CHECK-NEXT: BRANCH-ON-MASK vp<[[OR1]]> 338; CHECK-NEXT: Successor(s): pred.sdiv.if, pred.sdiv.continue 339; CHECK-NEXT: CondBit: vp<[[OR1]]> (if.then) 340; CHECK-EMPTY: 341; CHECK-NEXT: pred.sdiv.if: 342; CHECK-NEXT: REPLICATE ir<%sd1> = sdiv ir<%psd>, ir<%lsd> (S->V) 343; CHECK-NEXT: Successor(s): pred.sdiv.continue 344; CHECK-EMPTY: 345; CHECK-NEXT: pred.sdiv.continue: 346; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PHI:%.+]]> = ir<%sd1> 347; CHECK-NEXT: No successors 348; CHECK-NEXT: } 349; CHECK-NEXT: Successor(s): if.then.0 350; CHECK-EMPTY: 351; CHECK-NEXT: if.then.0: 352; CHECK-NEXT: Successor(s): if.end 353; CHECK-EMPTY: 354; CHECK-NEXT: if.end: 355; CHECK-NEXT: EMIT vp<[[NOT2:%.+]]> = not ir<%cmp2> 356; CHECK-NEXT: EMIT vp<[[SEL2:%.+]]> = select vp<[[NOT1]]> vp<[[NOT2]]> ir<false> 357; CHECK-NEXT: BLEND %ysd.0 = vp<[[PHI]]>/vp<[[OR1]]> ir<%psd>/vp<[[SEL2]]> 358; CHECK-NEXT: WIDEN store ir<%isd>, ir<%ysd.0> 359; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]> 360; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]> 361; CHECK-NEXT: No successors 362; CHECK-NEXT:} 363; CHECK-NEXT:No successors 364; CHECK-NEXT:} 365; 366entry: 367 br label %loop 368 369loop: 370 %iv = phi i64 [ 0, %entry ], [ %iv.next, %if.end ] 371 %isd = getelementptr inbounds i32, i32* %asd, i64 %iv 372 %lsd = load i32, i32* %isd, align 4 373 %psd = add nsw i32 %lsd, 23 374 %cmp1 = icmp slt i32 %lsd, 100 375 br i1 %cmp1, label %if.then, label %check, !dbg !7 376 377check: 378 %cmp2 = icmp sge i32 %lsd, 200 379 br i1 %cmp2, label %if.then, label %if.end, !dbg !8 380 381if.then: 382 %sd1 = sdiv i32 %psd, %lsd 383 br label %if.end 384 385if.end: 386 %ysd.0 = phi i32 [ %sd1, %if.then ], [ %psd, %check ] 387 store i32 %ysd.0, i32* %isd, align 4 388 %iv.next = add nuw nsw i64 %iv, 1 389 %exitcond = icmp eq i64 %iv.next, 128 390 br i1 %exitcond, label %exit, label %loop 391 392exit: 393 ret void 394} 395 396declare float @llvm.sqrt.f32(float) nounwind readnone 397declare float @llvm.fmuladd.f32(float, float, float) 398 399!llvm.dbg.cu = !{!0} 400!llvm.module.flags = !{!3, !4} 401 402!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2) 403!1 = !DIFile(filename: "/tmp/s.c", directory: "/tmp") 404!2 = !{} 405!3 = !{i32 2, !"Debug Info Version", i32 3} 406!4 = !{i32 7, !"PIC Level", i32 2} 407!5 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 4, type: !6, scopeLine: 4, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2) 408!6 = !DISubroutineType(types: !2) 409!7 = !DILocation(line: 5, column: 3, scope: !5) 410!8 = !DILocation(line: 5, column: 21, scope: !5) 411