1; RUN: opt < %s -force-vector-width=4 -force-vector-interleave=1 -loop-vectorize -S | FileCheck %s
2
3target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
4
5; CHECK-LABEL: @PR34687(
6; CHECK:       vector.body:
7; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %[[LATCH:.*]] ]
8; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ [[TMP17:%.*]], %[[LATCH]] ]
9; CHECK:       [[LATCH]]:
10; CHECK:         [[TMP13:%.*]] = and <4 x i32> [[VEC_PHI]], <i32 255, i32 255, i32 255, i32 255>
11; CHECK-NEXT:    [[TMP14:%.*]] = add <4 x i32> [[TMP13]], {{.*}}
12; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
13; CHECK:         [[TMP16:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i8>
14; CHECK-NEXT:    [[TMP17]] = zext <4 x i8> [[TMP16]] to <4 x i32>
15; CHECK-NEXT:    br i1 {{.*}}, label %middle.block, label %vector.body
16;
17define i8 @PR34687(i1 %c, i32 %x, i32 %n) {
18entry:
19  br label %for.body
20
21for.body:
22  %i = phi i32 [ 0, %entry ], [ %i.next, %if.end ]
23  %r = phi i32 [ 0, %entry ], [ %r.next, %if.end ]
24  br i1 %c, label %if.then, label %if.end
25
26if.then:
27  %tmp0 = sdiv i32 undef, undef
28  br label %if.end
29
30if.end:
31  %tmp1 = and i32 %r, 255
32  %i.next = add nsw i32 %i, 1
33  %r.next = add nuw nsw i32 %tmp1, %x
34  %cond = icmp eq i32 %i.next, %n
35  br i1 %cond, label %for.end, label %for.body
36
37for.end:
38  %tmp2 = phi i32 [ %r.next, %if.end ]
39  %tmp3 = trunc i32 %tmp2 to i8
40  ret i8 %tmp3
41}
42
43; CHECK-LABEL: @PR35734(
44; CHECK:       vector.ph:
45; CHECK:         [[TMP3:%.*]] = insertelement <4 x i32> zeroinitializer, i32 %y, i32 0
46; CHECK-NEXT:    br label %vector.body
47; CHECK:       vector.body:
48; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ]
49; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ [[TMP3]], %vector.ph ], [ [[TMP9:%.*]], %vector.body ]
50; CHECK:         [[TMP5:%.*]] = and <4 x i32> [[VEC_PHI]], <i32 1, i32 1, i32 1, i32 1>
51; CHECK-NEXT:    [[TMP6:%.*]] = add <4 x i32> [[TMP5]], <i32 -1, i32 -1, i32 -1, i32 -1>
52; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
53; CHECK:         [[TMP8:%.*]] = trunc <4 x i32> [[TMP6]] to <4 x i1>
54; CHECK-NEXT:    [[TMP9]] = sext <4 x i1> [[TMP8]] to <4 x i32>
55; CHECK-NEXT:    br i1 {{.*}}, label %middle.block, label %vector.body
56;
57define i32 @PR35734(i32 %x, i32 %y) {
58entry:
59  br label %for.body
60
61for.body:
62  %i = phi i32 [ %x, %entry ], [ %i.next, %for.body ]
63  %r = phi i32 [ %y, %entry ], [ %r.next, %for.body ]
64  %tmp0 = and i32 %r, 1
65  %r.next = add i32 %tmp0, -1
66  %i.next = add nsw i32 %i, 1
67  %cond = icmp sgt i32 %i, 77
68  br i1 %cond, label %for.end, label %for.body
69
70for.end:
71  %tmp1 = phi i32 [ %r.next, %for.body ]
72  ret i32 %tmp1
73}
74
75define i32 @pr51794_signed_negative(i16 %iv.start, i32 %xor.start) {
76; CHECK-LABEL: define {{.*}} @pr51794_signed_negative(
77; CHECK:   [[XOR_START:%.+]] = insertelement <4 x i32> zeroinitializer, i32 %xor.start, i32 0
78; CHECK-LABEL: vector.body:
79; CHECK:         [[XOR_RED:%.+]] = phi <4 x i32> [ [[XOR_START]], %vector.ph ], [ [[XOR_SEXT:%.+]], %vector.body ]
80; CHECK:         [[AND:%.+]] = and <4 x i32> [[XOR_RED]], <i32 1, i32 1, i32 1, i32 1>
81; CHECK-NEXT:    [[XOR:%.+]] = xor <4 x i32> [[AND]], <i32 -1, i32 -1, i32 -1, i32 -1>
82; CHECK:         [[XOR_TRUNC:%.+]] = trunc <4 x i32> [[XOR]] to <4 x i1>
83; CHECK-NEXT:    [[XOR_SEXT]] = sext <4 x i1> [[XOR_TRUNC]] to <4 x i32>
84;
85; CHECK-LABEL: middle.block:
86; CHECK-NEXT:   [[RES_TRUNC:%.+]] = trunc <4 x i32> [[XOR_SEXT]] to <4 x i1>
87; CHECK-NEXT:   [[RES_RED:%.+]]  = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> [[RES_TRUNC]])
88; CHECK-NEXT:   sext i1 [[RES_RED]] to i32
89;
90entry:
91  br label %loop
92
93loop:
94  %xor.red = phi i32 [ %xor.start, %entry ], [ %xor, %loop ]
95  %iv = phi i16 [ %iv.start, %entry ], [ %iv.next, %loop ]
96  %iv.next = add i16 %iv, -1
97  %and = and i32 %xor.red, 1
98  %xor = xor i32 %and, -1
99  %tobool.not = icmp eq i16 %iv.next, 0
100  br i1 %tobool.not, label %exit, label %loop
101
102exit:
103  %xor.lcssa = phi i32 [ %xor, %loop ]
104  ret i32 %xor.lcssa
105}
106
107define i32 @pr52485_signed_negative(i32 %xor.start) {
108; CHECK-LABEL: define {{.*}} @pr52485_signed_negative(
109; CHECK:   [[XOR_START:%.+]] = insertelement <4 x i32> zeroinitializer, i32 %xor.start, i32 0
110; CHECK-LABEL: vector.body:
111; CHECK:         [[XOR_RED:%.+]] = phi <4 x i32> [ [[XOR_START]], %vector.ph ], [ [[XOR_SEXT:%.+]], %vector.body ]
112; CHECK:         [[AND:%.+]] = and <4 x i32> [[XOR_RED]], <i32 255, i32 255, i32 255, i32 255>
113; CHECK-NEXT:    [[XOR:%.+]] = xor <4 x i32> [[AND]], <i32 -9, i32 -9, i32 -9, i32 -9>
114; CHECK:         [[XOR_TRUNC:%.+]] = trunc <4 x i32> [[XOR]] to <4 x i8>
115; CHECK-NEXT:    [[XOR_SEXT]] = sext <4 x i8> [[XOR_TRUNC]] to <4 x i32>
116;
117; CHECK-LABEL: middle.block:
118; CHECK-NEXT:   [[RES_TRUNC:%.+]] = trunc <4 x i32> [[XOR_SEXT]] to <4 x i8>
119; CHECK-NEXT:   [[RES_RED:%.+]]  = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> [[RES_TRUNC]])
120; CHECK-NEXT:   sext i8 [[RES_RED]] to i32
121;
122entry:
123  br label %loop
124
125loop:
126  %iv = phi i32 [ -23, %entry ], [ %iv.next, %loop ]
127  %xor.red = phi i32 [ %xor.start, %entry ], [ %xor, %loop ]
128  %and = and i32 %xor.red, 255
129  %xor = xor i32 %and, -9
130  %iv.next = add nuw nsw i32 %iv, 2
131  %cmp.not = icmp eq i32 %iv.next, -15
132  br i1 %cmp.not, label %exit, label %loop
133
134exit:
135  %xor.lcssa = phi i32 [ %xor, %loop ]
136  ret i32 %xor.lcssa
137}
138