1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -S | FileCheck %s 3 4; Test case for PR44488. Checks that the correct predicates are created for 5; branches where true and false successors are equal. See the checks involving 6; CMP1 and CMP2. 7 8@v_38 = global i16 12061, align 1 9@v_39 = global i16 11333, align 1 10 11define i16 @test_true_and_false_branch_equal() { 12; CHECK-LABEL: @test_true_and_false_branch_equal( 13; CHECK-NEXT: entry: 14; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 15; CHECK: vector.ph: 16; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 17; CHECK: vector.body: 18; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE2:%.*]] ] 19; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[INDEX]] to i16 20; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 99, [[TMP0]] 21; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[OFFSET_IDX]], i32 0 22; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> undef, <2 x i32> zeroinitializer 23; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i16> [[BROADCAST_SPLAT]], <i16 0, i16 1> 24; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[OFFSET_IDX]], 0 25; CHECK-NEXT: [[TMP2:%.*]] = load i16, i16* @v_38, align 1 26; CHECK-NEXT: [[TMP3:%.*]] = load i16, i16* @v_38, align 1 27; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i16> undef, i16 [[TMP2]], i32 0 28; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> [[TMP4]], i16 [[TMP3]], i32 1 29; CHECK-NEXT: [[TMP6:%.*]] = icmp eq <2 x i16> [[TMP5]], <i16 32767, i16 32767> 30; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <2 x i16> [[TMP5]], zeroinitializer 31; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i1> [[TMP7]], <i1 true, i1 true> 32; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0 33; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]] 34; CHECK: pred.srem.if: 35; CHECK-NEXT: [[TMP10:%.*]] = srem i16 5786, [[TMP2]] 36; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i16> undef, i16 [[TMP10]], i32 0 37; CHECK-NEXT: br label [[PRED_SREM_CONTINUE]] 38; CHECK: pred.srem.continue: 39; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i16> [ undef, [[VECTOR_BODY]] ], [ [[TMP11]], [[PRED_SREM_IF]] ] 40; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1 41; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_SREM_IF1:%.*]], label [[PRED_SREM_CONTINUE2]] 42; CHECK: pred.srem.if1: 43; CHECK-NEXT: [[TMP14:%.*]] = srem i16 5786, [[TMP3]] 44; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i16> [[TMP12]], i16 [[TMP14]], i32 1 45; CHECK-NEXT: br label [[PRED_SREM_CONTINUE2]] 46; CHECK: pred.srem.continue2: 47; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i16> [ [[TMP12]], [[PRED_SREM_CONTINUE]] ], [ [[TMP15]], [[PRED_SREM_IF1]] ] 48; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP7]], <2 x i16> <i16 5786, i16 5786>, <2 x i16> [[TMP16]] 49; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 0 50; CHECK-NEXT: store i16 [[TMP17]], i16* @v_39, align 1 51; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 1 52; CHECK-NEXT: store i16 [[TMP18]], i16* @v_39, align 1 53; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 2 54; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12 55; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0 56; CHECK: middle.block: 57; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 12, 12 58; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 59; CHECK: scalar.ph: 60; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 111, [[MIDDLE_BLOCK]] ], [ 99, [[ENTRY:%.*]] ] 61; CHECK-NEXT: br label [[FOR_BODY:%.*]] 62; CHECK: for.body: 63; CHECK-NEXT: [[I_07:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC7:%.*]], [[FOR_LATCH:%.*]] ] 64; CHECK-NEXT: [[LV:%.*]] = load i16, i16* @v_38, align 1 65; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i16 [[LV]], 32767 66; CHECK-NEXT: br i1 [[CMP1]], label [[COND_END:%.*]], label [[COND_END]] 67; CHECK: cond.end: 68; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i16 [[LV]], 0 69; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_LATCH]], label [[COND_FALSE4:%.*]] 70; CHECK: cond.false4: 71; CHECK-NEXT: [[REM:%.*]] = srem i16 5786, [[LV]] 72; CHECK-NEXT: br label [[FOR_LATCH]] 73; CHECK: for.latch: 74; CHECK-NEXT: [[COND6:%.*]] = phi i16 [ [[REM]], [[COND_FALSE4]] ], [ 5786, [[COND_END]] ] 75; CHECK-NEXT: store i16 [[COND6]], i16* @v_39, align 1 76; CHECK-NEXT: [[INC7]] = add nsw i16 [[I_07]], 1 77; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC7]], 111 78; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop !2 79; CHECK: exit: 80; CHECK-NEXT: [[RV:%.*]] = load i16, i16* @v_39, align 1 81; CHECK-NEXT: ret i16 [[RV]] 82; 83entry: 84 br label %for.body 85 86for.body: ; preds = %entry, %for.latch 87 %i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ] 88 %lv = load i16, i16* @v_38, align 1 89 %cmp1 = icmp eq i16 %lv, 32767 90 br i1 %cmp1, label %cond.end, label %cond.end 91 92cond.end: ; preds = %for.body, %for.body 93 %cmp2 = icmp eq i16 %lv, 0 94 br i1 %cmp2, label %for.latch, label %cond.false4 95 96cond.false4: ; preds = %cond.end 97 %rem = srem i16 5786, %lv 98 br label %for.latch 99 100for.latch: ; preds = %cond.end, %cond.false4 101 %cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ] 102 store i16 %cond6, i16* @v_39, align 1 103 %inc7 = add nsw i16 %i.07, 1 104 %cmp = icmp slt i16 %inc7, 111 105 br i1 %cmp, label %for.body, label %exit 106 107exit: ; preds = %for.latch 108 %rv = load i16, i16* @v_39, align 1 109 ret i16 %rv 110} 111