1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -passes=loop-vectorize -S | FileCheck %s
3
4; Test case for PR44488. Checks that the correct predicates are created for
5; branches where true and false successors are equal. See the checks involving
6; CMP1 and CMP2.
7
8@v_38 = global i16 12061, align 1
9@v_39 = global i16 11333, align 1
10
11define i16 @test_true_and_false_branch_equal() {
12; CHECK-LABEL: @test_true_and_false_branch_equal(
13; CHECK-NEXT:  entry:
14; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
15; CHECK:       vector.ph:
16; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
17; CHECK:       vector.body:
18; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE2:%.*]] ]
19; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* @v_38, align 1
20; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[TMP0]], i32 0
21; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
22; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i16> [[BROADCAST_SPLAT]], zeroinitializer
23; CHECK-NEXT:    [[TMP2:%.*]] = xor <2 x i1> [[TMP1]], <i1 true, i1 true>
24; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
25; CHECK-NEXT:    br i1 [[TMP3]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]]
26; CHECK:       pred.srem.if:
27; CHECK-NEXT:    [[TMP4:%.*]] = srem i16 5786, [[TMP0]]
28; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[TMP4]], i32 0
29; CHECK-NEXT:    br label [[PRED_SREM_CONTINUE]]
30; CHECK:       pred.srem.continue:
31; CHECK-NEXT:    [[TMP6:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP5]], [[PRED_SREM_IF]] ]
32; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
33; CHECK-NEXT:    br i1 [[TMP7]], label [[PRED_SREM_IF1:%.*]], label [[PRED_SREM_CONTINUE2]]
34; CHECK:       pred.srem.if1:
35; CHECK-NEXT:    [[TMP8:%.*]] = srem i16 5786, [[TMP0]]
36; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <2 x i16> [[TMP6]], i16 [[TMP8]], i32 1
37; CHECK-NEXT:    br label [[PRED_SREM_CONTINUE2]]
38; CHECK:       pred.srem.continue2:
39; CHECK-NEXT:    [[TMP10:%.*]] = phi <2 x i16> [ [[TMP6]], [[PRED_SREM_CONTINUE]] ], [ [[TMP9]], [[PRED_SREM_IF1]] ]
40; CHECK-NEXT:    [[PREDPHI:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> <i16 5786, i16 5786>, <2 x i16> [[TMP10]]
41; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 0
42; CHECK-NEXT:    store i16 [[TMP11]], i16* @v_39, align 1
43; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 1
44; CHECK-NEXT:    store i16 [[TMP12]], i16* @v_39, align 1
45; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
46; CHECK-NEXT:    [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12
47; CHECK-NEXT:    br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
48; CHECK:       middle.block:
49; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 12, 12
50; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
51; CHECK:       scalar.ph:
52; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i16 [ 111, [[MIDDLE_BLOCK]] ], [ 99, [[ENTRY:%.*]] ]
53; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
54; CHECK:       for.body:
55; CHECK-NEXT:    [[I_07:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC7:%.*]], [[FOR_LATCH:%.*]] ]
56; CHECK-NEXT:    [[LV:%.*]] = load i16, i16* @v_38, align 1
57; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i16 [[LV]], 32767
58; CHECK-NEXT:    br i1 [[CMP1]], label [[COND_END:%.*]], label [[COND_END]]
59; CHECK:       cond.end:
60; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i16 [[LV]], 0
61; CHECK-NEXT:    br i1 [[CMP2]], label [[FOR_LATCH]], label [[COND_FALSE4:%.*]]
62; CHECK:       cond.false4:
63; CHECK-NEXT:    [[REM:%.*]] = srem i16 5786, [[LV]]
64; CHECK-NEXT:    br label [[FOR_LATCH]]
65; CHECK:       for.latch:
66; CHECK-NEXT:    [[COND6:%.*]] = phi i16 [ [[REM]], [[COND_FALSE4]] ], [ 5786, [[COND_END]] ]
67; CHECK-NEXT:    store i16 [[COND6]], i16* @v_39, align 1
68; CHECK-NEXT:    [[INC7]] = add nsw i16 [[I_07]], 1
69; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i16 [[INC7]], 111
70; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop [[LOOP2:![0-9]+]]
71; CHECK:       exit:
72; CHECK-NEXT:    [[RV:%.*]] = load i16, i16* @v_39, align 1
73; CHECK-NEXT:    ret i16 [[RV]]
74;
75entry:
76  br label %for.body
77
78for.body:                                         ; preds = %entry, %for.latch
79  %i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ]
80  %lv = load i16, i16* @v_38, align 1
81  %cmp1 = icmp eq i16 %lv, 32767
82  br i1 %cmp1, label %cond.end, label %cond.end
83
84cond.end:                                         ; preds = %for.body, %for.body
85  %cmp2 = icmp eq i16 %lv, 0
86  br i1 %cmp2, label %for.latch, label %cond.false4
87
88cond.false4:                                      ; preds = %cond.end
89  %rem = srem i16 5786, %lv
90  br label %for.latch
91
92for.latch:                                        ; preds = %cond.end, %cond.false4
93  %cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ]
94  store i16 %cond6, i16* @v_39, align 1
95  %inc7 = add nsw i16 %i.07, 1
96  %cmp = icmp slt i16 %inc7, 111
97  br i1 %cmp, label %for.body, label %exit
98
99exit:                                 ; preds = %for.latch
100  %rv = load i16, i16* @v_39, align 1
101  ret i16 %rv
102}
103