1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine < %s | FileCheck %s --check-prefix=SSE 3; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=sandybridge < %s | FileCheck %s --check-prefix=AVX1 4; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=haswell < %s | FileCheck %s --check-prefix=AVX2 5; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=slm < %s | FileCheck %s --check-prefix=SSE 6; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=atom < %s | FileCheck %s --check-prefix=SSE 7 8define void @foo(i32* noalias nocapture %a, i32* noalias nocapture readonly %b) { 9; SSE-LABEL: @foo( 10; SSE-NEXT: entry: 11; SSE-NEXT: br label [[FOR_BODY:%.*]] 12; SSE: for.cond.cleanup: 13; SSE-NEXT: ret void 14; SSE: for.body: 15; SSE-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] 16; SSE-NEXT: [[TMP0:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 1 17; SSE-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] 18; SSE-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 19; SSE-NEXT: [[TMP2:%.*]] = or i64 [[TMP0]], 1 20; SSE-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP2]] 21; SSE-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4 22; SSE-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], [[TMP1]] 23; SSE-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]] 24; SSE-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX6]], align 4 25; SSE-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 26; SSE-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 1024 27; SSE-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]] 28; 29; AVX1-LABEL: @foo( 30; AVX1-NEXT: entry: 31; AVX1-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 32; AVX1: vector.ph: 33; AVX1-NEXT: br label [[VECTOR_BODY:%.*]] 34; AVX1: vector.body: 35; AVX1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 36; AVX1-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 37; AVX1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] 38; AVX1-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <8 x i32>* 39; AVX1-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, <8 x i32>* [[TMP2]], align 4 40; AVX1-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 41; AVX1-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7> 42; AVX1-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[STRIDED_VEC1]], [[STRIDED_VEC]] 43; AVX1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDEX]] 44; AVX1-NEXT: [[TMP5:%.*]] = bitcast i32* [[TMP4]] to <4 x i32>* 45; AVX1-NEXT: store <4 x i32> [[TMP3]], <4 x i32>* [[TMP5]], align 4 46; AVX1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 47; AVX1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 48; AVX1-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 49; AVX1: middle.block: 50; AVX1-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]] 51; AVX1: scalar.ph: 52; AVX1-NEXT: br label [[FOR_BODY:%.*]] 53; AVX1: for.cond.cleanup: 54; AVX1-NEXT: ret void 55; AVX1: for.body: 56; AVX1-NEXT: br i1 undef, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] 57; 58; AVX2-LABEL: @foo( 59; AVX2-NEXT: entry: 60; AVX2-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 61; AVX2: vector.ph: 62; AVX2-NEXT: br label [[VECTOR_BODY:%.*]] 63; AVX2: vector.body: 64; AVX2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 65; AVX2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1 66; AVX2-NEXT: [[TMP1:%.*]] = shl i64 [[INDEX]], 1 67; AVX2-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 16 68; AVX2-NEXT: [[TMP3:%.*]] = shl i64 [[INDEX]], 1 69; AVX2-NEXT: [[TMP4:%.*]] = or i64 [[TMP3]], 32 70; AVX2-NEXT: [[TMP5:%.*]] = shl i64 [[INDEX]], 1 71; AVX2-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 48 72; AVX2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]] 73; AVX2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP2]] 74; AVX2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP4]] 75; AVX2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP6]] 76; AVX2-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP7]] to <16 x i32>* 77; AVX2-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP8]] to <16 x i32>* 78; AVX2-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP9]] to <16 x i32>* 79; AVX2-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP10]] to <16 x i32>* 80; AVX2-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, <16 x i32>* [[TMP11]], align 4 81; AVX2-NEXT: [[WIDE_VEC1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP12]], align 4 82; AVX2-NEXT: [[WIDE_VEC2:%.*]] = load <16 x i32>, <16 x i32>* [[TMP13]], align 4 83; AVX2-NEXT: [[WIDE_VEC3:%.*]] = load <16 x i32>, <16 x i32>* [[TMP14]], align 4 84; AVX2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 85; AVX2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <16 x i32> [[WIDE_VEC1]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 86; AVX2-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <16 x i32> [[WIDE_VEC2]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 87; AVX2-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <16 x i32> [[WIDE_VEC3]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 88; AVX2-NEXT: [[STRIDED_VEC7:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 89; AVX2-NEXT: [[STRIDED_VEC8:%.*]] = shufflevector <16 x i32> [[WIDE_VEC1]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 90; AVX2-NEXT: [[STRIDED_VEC9:%.*]] = shufflevector <16 x i32> [[WIDE_VEC2]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 91; AVX2-NEXT: [[STRIDED_VEC10:%.*]] = shufflevector <16 x i32> [[WIDE_VEC3]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 92; AVX2-NEXT: [[TMP15:%.*]] = add nsw <8 x i32> [[STRIDED_VEC7]], [[STRIDED_VEC]] 93; AVX2-NEXT: [[TMP16:%.*]] = add nsw <8 x i32> [[STRIDED_VEC8]], [[STRIDED_VEC4]] 94; AVX2-NEXT: [[TMP17:%.*]] = add nsw <8 x i32> [[STRIDED_VEC9]], [[STRIDED_VEC5]] 95; AVX2-NEXT: [[TMP18:%.*]] = add nsw <8 x i32> [[STRIDED_VEC10]], [[STRIDED_VEC6]] 96; AVX2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDEX]] 97; AVX2-NEXT: [[TMP20:%.*]] = bitcast i32* [[TMP19]] to <8 x i32>* 98; AVX2-NEXT: store <8 x i32> [[TMP15]], <8 x i32>* [[TMP20]], align 4 99; AVX2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 8 100; AVX2-NEXT: [[TMP22:%.*]] = bitcast i32* [[TMP21]] to <8 x i32>* 101; AVX2-NEXT: store <8 x i32> [[TMP16]], <8 x i32>* [[TMP22]], align 4 102; AVX2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 16 103; AVX2-NEXT: [[TMP24:%.*]] = bitcast i32* [[TMP23]] to <8 x i32>* 104; AVX2-NEXT: store <8 x i32> [[TMP17]], <8 x i32>* [[TMP24]], align 4 105; AVX2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 24 106; AVX2-NEXT: [[TMP26:%.*]] = bitcast i32* [[TMP25]] to <8 x i32>* 107; AVX2-NEXT: store <8 x i32> [[TMP18]], <8 x i32>* [[TMP26]], align 4 108; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 109; AVX2-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 110; AVX2-NEXT: br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 111; AVX2: middle.block: 112; AVX2-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]] 113; AVX2: scalar.ph: 114; AVX2-NEXT: br label [[FOR_BODY:%.*]] 115; AVX2: for.cond.cleanup: 116; AVX2-NEXT: ret void 117; AVX2: for.body: 118; AVX2-NEXT: br i1 undef, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] 119; 120entry: 121 br label %for.body 122 123for.cond.cleanup: ; preds = %for.body 124 ret void 125 126for.body: ; preds = %for.body, %entry 127 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 128 %0 = shl nsw i64 %indvars.iv, 1 129 %arrayidx = getelementptr inbounds i32, i32* %b, i64 %0 130 %1 = load i32, i32* %arrayidx, align 4 131 %2 = or i64 %0, 1 132 %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %2 133 %3 = load i32, i32* %arrayidx3, align 4 134 %add4 = add nsw i32 %3, %1 135 %arrayidx6 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv 136 store i32 %add4, i32* %arrayidx6, align 4 137 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 138 %exitcond = icmp eq i64 %indvars.iv.next, 1024 139 br i1 %exitcond, label %for.cond.cleanup, label %for.body 140} 141