1; RUN: opt -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=CHECK-VF4UF1
2; RUN: opt -loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -mtriple aarch64-unknown-linux-gnu -mattr=+sve -S < %s | FileCheck %s --check-prefix=CHECK-VF4UF2
3
4; We vectorize this first order recurrence, with a set of insertelements for
5; each unrolled part. Make sure these insertelements are generated in-order,
6; because the shuffle of the first order recurrence will be added after the
7; insertelement of the last part UF - 1, assuming the latter appears after the
8; insertelements of all other parts.
9;
10; int PR33613(double *b, double j, int d) {
11;   int a = 0;
12;   for(int i = 0; i < 10240; i++, b+=25) {
13;     double f = b[d]; // Scalarize to form insertelements
14;     if (j * f)
15;       a++;
16;     j = f;
17;   }
18;   return a;
19; }
20;
21define i32 @PR33613(double* %b, double %j, i32 %d) #0 {
22; CHECK-VF4UF2-LABEL: @PR33613
23; CHECK-VF4UF2: vector.body
24; CHECK-VF4UF2: %[[VEC_RECUR:.*]] = phi <vscale x 4 x double> [ {{.*}}, %vector.ph ], [ {{.*}}, %vector.body ]
25; CHECK-VF4UF2: %[[SPLICE1:.*]] = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %[[VEC_RECUR]], <vscale x 4 x double> {{.*}}, i32 -1)
26; CHECK-VF4UF2-NEXT: %[[SPLICE2:.*]] = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %{{.*}}, <vscale x 4 x double> %{{.*}}, i32 -1)
27; CHECK-VF4UF2-NOT: insertelement <vscale x 4 x double>
28; CHECK-VF4UF2: middle.block
29entry:
30  %idxprom = sext i32 %d to i64
31  br label %for.body
32
33for.cond.cleanup:
34  %a.1.lcssa = phi i32 [ %a.1, %for.body ]
35  ret i32 %a.1.lcssa
36
37for.body:
38  %b.addr.012 = phi double* [ %b, %entry ], [ %add.ptr, %for.body ]
39  %i.011 = phi i32 [ 0, %entry ], [ %inc1, %for.body ]
40  %a.010 = phi i32 [ 0, %entry ], [ %a.1, %for.body ]
41  %j.addr.09 = phi double [ %j, %entry ], [ %0, %for.body ]
42  %arrayidx = getelementptr inbounds double, double* %b.addr.012, i64 %idxprom
43  %0 = load double, double* %arrayidx, align 8
44  %mul = fmul double %j.addr.09, %0
45  %tobool = fcmp une double %mul, 0.000000e+00
46  %inc = zext i1 %tobool to i32
47  %a.1 = add nsw i32 %a.010, %inc
48  %inc1 = add nuw nsw i32 %i.011, 1
49  %add.ptr = getelementptr inbounds double, double* %b.addr.012, i64 25
50  %exitcond = icmp eq i32 %inc1, 10240
51  br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !0
52}
53
54; PR34711: given three consecutive instructions such that the first will be
55; widened, the second is a cast that will be widened and needs to sink after the
56; third, and the third is a first-order-recurring load that will be replicated
57; instead of widened. Although the cast and the first instruction will both be
58; widened, and are originally adjacent to each other, make sure the replicated
59; load ends up appearing between them.
60;
61; void PR34711(short[2] *a, int *b, int *c, int n) {
62;   for(int i = 0; i < n; i++) {
63;     c[i] = 7;
64;     b[i] = (a[i][0] * a[i][1]);
65;   }
66; }
67;
68; Check that the sext sank after the load in the vector loop.
69define void @PR34711([2 x i16]* %a, i32* %b, i32* %c, i64 %n) #0 {
70; CHECK-VF4UF1-LABEL: @PR34711
71; CHECK-VF4UF1: vector.body
72; CHECK-VF4UF1: %[[VEC_RECUR:.*]] = phi <vscale x 4 x i16> [ %vector.recur.init, %vector.ph ], [ %[[MGATHER:.*]], %vector.body ]
73; CHECK-VF4UF1: %[[MGATHER]] = call <vscale x 4 x i16> @llvm.masked.gather.nxv4i16.nxv4p0i16(<vscale x 4 x i16*> {{.*}}, i32 2, <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i32 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i16> undef)
74; CHECK-VF4UF1-NEXT: %[[SPLICE:.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %[[VEC_RECUR]], <vscale x 4 x i16> %[[MGATHER]], i32 -1)
75; CHECK-VF4UF1-NEXT: %[[SXT1:.*]] = sext <vscale x 4 x i16> %[[SPLICE]] to <vscale x 4 x i32>
76; CHECK-VF4UF1-NEXT: %[[SXT2:.*]] = sext <vscale x 4 x i16> %[[MGATHER]] to <vscale x 4 x i32>
77; CHECK-VF4UF1-NEXT: mul nsw <vscale x 4 x i32> %[[SXT2]], %[[SXT1]]
78entry:
79  %pre.index = getelementptr inbounds [2 x i16], [2 x i16]* %a, i64 0, i64 0
80  %.pre = load i16, i16* %pre.index
81  br label %for.body
82
83for.body:
84  %0 = phi i16 [ %.pre, %entry ], [ %1, %for.body ]
85  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
86  %arraycidx = getelementptr inbounds i32, i32* %c, i64 %indvars.iv
87  %cur.index = getelementptr inbounds [2 x i16], [2 x i16]* %a, i64 %indvars.iv, i64 1
88  store i32 7, i32* %arraycidx   ; 1st instruction, to be widened.
89  %conv = sext i16 %0 to i32     ; 2nd, cast to sink after third.
90  %1 = load i16, i16* %cur.index ; 3rd, first-order-recurring load not widened.
91  %conv3 = sext i16 %1 to i32
92  %mul = mul nsw i32 %conv3, %conv
93  %arrayidx5 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
94  store i32 %mul, i32* %arrayidx5
95  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
96  %exitcond = icmp eq i64 %indvars.iv.next, %n
97  br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !0
98
99for.end:
100  ret void
101}
102
103attributes #0 = { vscale_range(1, 16) }
104!0 = distinct !{!0, !1}
105!1 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
106