1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes='loop-unroll<runtime>' -S %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-ni:1-p2:32:8:8:32-ni:2" 5 6; Make sure SCEVs for phis are properly invalidated after phis are modified. 7 8declare void @llvm.experimental.deoptimize.isVoid(...) 9 10declare i32 @get() 11 12define void @pr56282() { 13; CHECK-LABEL: @pr56282( 14; CHECK-NEXT: entry: 15; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 16; CHECK: outer.header: 17; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[INNER_2:%.*]] ] 18; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OUTER_IV]], 1 19; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]] 20; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], -1 21; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP1]], 7 22; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 7 23; CHECK-NEXT: br i1 [[TMP3]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[OUTER_HEADER_NEW:%.*]] 24; CHECK: outer.header.new: 25; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP1]], [[XTRAITER]] 26; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] 27; CHECK: inner.1.header: 28; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] 29; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[INNER_1_LATCH_7]] ] 30; CHECK-NEXT: [[INNER_1_IV_NEXT:%.*]] = add nuw nsw i64 [[INNER_1_IV]], 1 31; CHECK-NEXT: [[V:%.*]] = call i32 @get() 32; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i32 [[V]], 0 33; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[EXIT_DEOPT_LOOPEXIT:%.*]] 34; CHECK: inner.1.latch: 35; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 36; CHECK-NEXT: [[INNER_1_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT]], 1 37; CHECK-NEXT: [[V_1:%.*]] = call i32 @get() 38; CHECK-NEXT: [[C_1_1:%.*]] = icmp ugt i32 [[V_1]], 0 39; CHECK-NEXT: br i1 [[C_1_1]], label [[INNER_1_LATCH_1:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 40; CHECK: inner.1.latch.1: 41; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1 42; CHECK-NEXT: [[INNER_1_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_1]], 1 43; CHECK-NEXT: [[V_2:%.*]] = call i32 @get() 44; CHECK-NEXT: [[C_1_2:%.*]] = icmp ugt i32 [[V_2]], 0 45; CHECK-NEXT: br i1 [[C_1_2]], label [[INNER_1_LATCH_2:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 46; CHECK: inner.1.latch.2: 47; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1 48; CHECK-NEXT: [[INNER_1_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_2]], 1 49; CHECK-NEXT: [[V_3:%.*]] = call i32 @get() 50; CHECK-NEXT: [[C_1_3:%.*]] = icmp ugt i32 [[V_3]], 0 51; CHECK-NEXT: br i1 [[C_1_3]], label [[INNER_1_LATCH_3:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 52; CHECK: inner.1.latch.3: 53; CHECK-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1 54; CHECK-NEXT: [[INNER_1_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_3]], 1 55; CHECK-NEXT: [[V_4:%.*]] = call i32 @get() 56; CHECK-NEXT: [[C_1_4:%.*]] = icmp ugt i32 [[V_4]], 0 57; CHECK-NEXT: br i1 [[C_1_4]], label [[INNER_1_LATCH_4:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 58; CHECK: inner.1.latch.4: 59; CHECK-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1 60; CHECK-NEXT: [[INNER_1_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_4]], 1 61; CHECK-NEXT: [[V_5:%.*]] = call i32 @get() 62; CHECK-NEXT: [[C_1_5:%.*]] = icmp ugt i32 [[V_5]], 0 63; CHECK-NEXT: br i1 [[C_1_5]], label [[INNER_1_LATCH_5:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 64; CHECK: inner.1.latch.5: 65; CHECK-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1 66; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_5]], 1 67; CHECK-NEXT: [[V_6:%.*]] = call i32 @get() 68; CHECK-NEXT: [[C_1_6:%.*]] = icmp ugt i32 [[V_6]], 0 69; CHECK-NEXT: br i1 [[C_1_6]], label [[INNER_1_LATCH_6:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 70; CHECK: inner.1.latch.6: 71; CHECK-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1 72; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add nuw nsw i64 [[INNER_1_IV_NEXT_6]], 1 73; CHECK-NEXT: [[V_7:%.*]] = call i32 @get() 74; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0 75; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]] 76; CHECK: inner.1.latch.7: 77; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 78; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] 79; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT:%.*]] 80; CHECK: outer.middle.unr-lcssa.loopexit: 81; CHECK-NEXT: [[V_LCSSA1_PH_PH:%.*]] = phi i32 [ [[V_7]], [[INNER_1_LATCH_7]] ] 82; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_7]], [[INNER_1_LATCH_7]] ] 83; CHECK-NEXT: br label [[OUTER_MIDDLE_UNR_LCSSA]] 84; CHECK: outer.middle.unr-lcssa: 85; CHECK-NEXT: [[V_LCSSA1_PH:%.*]] = phi i32 [ undef, [[OUTER_HEADER]] ], [ [[V_LCSSA1_PH_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] 86; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] 87; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 88; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_EPIL_PREHEADER:%.*]], label [[OUTER_MIDDLE:%.*]] 89; CHECK: inner.1.header.epil.preheader: 90; CHECK-NEXT: br label [[INNER_1_HEADER_EPIL:%.*]] 91; CHECK: inner.1.header.epil: 92; CHECK-NEXT: [[INNER_1_IV_EPIL:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_EPIL:%.*]], [[INNER_1_LATCH_EPIL:%.*]] ] 93; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[INNER_1_LATCH_EPIL]] ] 94; CHECK-NEXT: [[INNER_1_IV_NEXT_EPIL]] = add nuw nsw i64 [[INNER_1_IV_EPIL]], 1 95; CHECK-NEXT: [[V_EPIL:%.*]] = call i32 @get() 96; CHECK-NEXT: [[C_1_EPIL:%.*]] = icmp ugt i32 [[V_EPIL]], 0 97; CHECK-NEXT: br i1 [[C_1_EPIL]], label [[INNER_1_LATCH_EPIL]], label [[EXIT_DEOPT_LOOPEXIT3:%.*]] 98; CHECK: inner.1.latch.epil: 99; CHECK-NEXT: [[C_2_EPIL:%.*]] = icmp ult i64 [[INNER_1_IV_EPIL]], [[OUTER_IV]] 100; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1 101; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]] 102; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[INNER_1_HEADER_EPIL]], label [[OUTER_MIDDLE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP0:![0-9]+]] 103; CHECK: outer.middle.epilog-lcssa: 104; CHECK-NEXT: [[V_LCSSA1_PH2:%.*]] = phi i32 [ [[V_EPIL]], [[INNER_1_LATCH_EPIL]] ] 105; CHECK-NEXT: br label [[OUTER_MIDDLE]] 106; CHECK: outer.middle: 107; CHECK-NEXT: [[V_LCSSA1:%.*]] = phi i32 [ [[V_LCSSA1_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ], [ [[V_LCSSA1_PH2]], [[OUTER_MIDDLE_EPILOG_LCSSA]] ] 108; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i32 [[V_LCSSA1]], 0 109; CHECK-NEXT: br i1 [[C_3]], label [[INNER_2_PREHEADER:%.*]], label [[EXIT:%.*]] 110; CHECK: inner.2.preheader: 111; CHECK-NEXT: br label [[INNER_2]] 112; CHECK: inner.2: 113; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw nsw i64 [[OUTER_IV]], 1 114; CHECK-NEXT: br label [[OUTER_HEADER]] 115; CHECK: exit: 116; CHECK-NEXT: ret void 117; CHECK: exit.deopt.loopexit: 118; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]] 119; CHECK: exit.deopt.loopexit3: 120; CHECK-NEXT: br label [[EXIT_DEOPT]] 121; CHECK: exit.deopt: 122; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 123; CHECK-NEXT: ret void 124; 125entry: 126 br label %outer.header 127 128outer.header: 129 %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ] 130 br label %inner.1.header 131 132inner.1.header: 133 %inner.1.iv = phi i64 [ 0, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ] 134 %inner.1.iv.next = add nuw nsw i64 %inner.1.iv, 1 135 %v = call i32 @get() 136 %c.1 = icmp ugt i32 %v, 0 137 br i1 %c.1, label %inner.1.latch, label %exit.deopt 138 139inner.1.latch: ; preds = %inner.1.header 140 %c.2 = icmp ult i64 %inner.1.iv, %outer.iv 141 br i1 %c.2, label %inner.1.header, label %outer.middle 142 143outer.middle: 144 %c.3 = icmp ugt i32 %v, 0 145 br i1 %c.3, label %inner.2, label %exit 146 147inner.2: 148 %inner.2.iv = phi i64 [ 0, %outer.middle ], [ %inner.2.iv.next, %inner.2 ] 149 %inner.2.iv.next = add nsw i64 %inner.2.iv, -1 150 %iv.trunc = trunc i64 %inner.2.iv to i32 151 %c.4 = icmp ult i32 %v, %iv.trunc 152 br i1 %c.4, label %inner.2, label %outer.latch 153 154outer.latch: 155 %outer.iv.next = add nuw nsw i64 %outer.iv, 1 156 br label %outer.header 157 158exit: 159 ret void 160 161exit.deopt: 162 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 163 ret void 164} 165