1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes='loop-unroll<runtime;partial>' -S %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-ni:1-p2:32:8:8:32-ni:2" 5 6; Make sure SCEVs for phis are properly invalidated after phis are modified. 7 8declare void @llvm.experimental.deoptimize.isVoid(...) 9 10declare i32 @get() 11 12define void @pr56282() { 13; CHECK-LABEL: @pr56282( 14; CHECK-NEXT: entry: 15; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 16; CHECK: outer.header: 17; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[INNER_2:%.*]] ] 18; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OUTER_IV]], 1 19; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]] 20; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], -1 21; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP1]], 7 22; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 7 23; CHECK-NEXT: br i1 [[TMP3]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[OUTER_HEADER_NEW:%.*]] 24; CHECK: outer.header.new: 25; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[TMP1]], [[XTRAITER]] 26; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] 27; CHECK: inner.1.header: 28; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] 29; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[OUTER_HEADER_NEW]] ], [ [[NITER_NEXT_7:%.*]], [[INNER_1_LATCH_7]] ] 30; CHECK-NEXT: [[INNER_1_IV_NEXT:%.*]] = add nuw nsw i64 [[INNER_1_IV]], 1 31; CHECK-NEXT: [[V:%.*]] = call i32 @get() 32; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i32 [[V]], 0 33; CHECK-NEXT: br i1 [[C_1]], label [[INNER_1_LATCH:%.*]], label [[EXIT_DEOPT_LOOPEXIT:%.*]] 34; CHECK: inner.1.latch: 35; CHECK-NEXT: [[NITER_NEXT:%.*]] = add nuw nsw i64 [[NITER]], 1 36; CHECK-NEXT: [[INNER_1_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT]], 1 37; CHECK-NEXT: [[V_1:%.*]] = call i32 @get() 38; CHECK-NEXT: [[C_1_1:%.*]] = icmp ugt i32 [[V_1]], 0 39; CHECK-NEXT: br i1 [[C_1_1]], label [[INNER_1_LATCH_1:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 40; CHECK: inner.1.latch.1: 41; CHECK-NEXT: [[NITER_NEXT_1:%.*]] = add nuw nsw i64 [[NITER_NEXT]], 1 42; CHECK-NEXT: [[INNER_1_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_1]], 1 43; CHECK-NEXT: [[V_2:%.*]] = call i32 @get() 44; CHECK-NEXT: [[C_1_2:%.*]] = icmp ugt i32 [[V_2]], 0 45; CHECK-NEXT: br i1 [[C_1_2]], label [[INNER_1_LATCH_2:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 46; CHECK: inner.1.latch.2: 47; CHECK-NEXT: [[NITER_NEXT_2:%.*]] = add nuw nsw i64 [[NITER_NEXT_1]], 1 48; CHECK-NEXT: [[INNER_1_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_2]], 1 49; CHECK-NEXT: [[V_3:%.*]] = call i32 @get() 50; CHECK-NEXT: [[C_1_3:%.*]] = icmp ugt i32 [[V_3]], 0 51; CHECK-NEXT: br i1 [[C_1_3]], label [[INNER_1_LATCH_3:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 52; CHECK: inner.1.latch.3: 53; CHECK-NEXT: [[NITER_NEXT_3:%.*]] = add nuw nsw i64 [[NITER_NEXT_2]], 1 54; CHECK-NEXT: [[INNER_1_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_3]], 1 55; CHECK-NEXT: [[V_4:%.*]] = call i32 @get() 56; CHECK-NEXT: [[C_1_4:%.*]] = icmp ugt i32 [[V_4]], 0 57; CHECK-NEXT: br i1 [[C_1_4]], label [[INNER_1_LATCH_4:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 58; CHECK: inner.1.latch.4: 59; CHECK-NEXT: [[NITER_NEXT_4:%.*]] = add nuw nsw i64 [[NITER_NEXT_3]], 1 60; CHECK-NEXT: [[INNER_1_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_4]], 1 61; CHECK-NEXT: [[V_5:%.*]] = call i32 @get() 62; CHECK-NEXT: [[C_1_5:%.*]] = icmp ugt i32 [[V_5]], 0 63; CHECK-NEXT: br i1 [[C_1_5]], label [[INNER_1_LATCH_5:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 64; CHECK: inner.1.latch.5: 65; CHECK-NEXT: [[NITER_NEXT_5:%.*]] = add nuw nsw i64 [[NITER_NEXT_4]], 1 66; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INNER_1_IV_NEXT_5]], 1 67; CHECK-NEXT: [[V_6:%.*]] = call i32 @get() 68; CHECK-NEXT: [[C_1_6:%.*]] = icmp ugt i32 [[V_6]], 0 69; CHECK-NEXT: br i1 [[C_1_6]], label [[INNER_1_LATCH_6:%.*]], label [[EXIT_DEOPT_LOOPEXIT]] 70; CHECK: inner.1.latch.6: 71; CHECK-NEXT: [[NITER_NEXT_6:%.*]] = add nuw nsw i64 [[NITER_NEXT_5]], 1 72; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add nuw nsw i64 [[INNER_1_IV_NEXT_6]], 1 73; CHECK-NEXT: [[V_7:%.*]] = call i32 @get() 74; CHECK-NEXT: [[C_1_7:%.*]] = icmp ugt i32 [[V_7]], 0 75; CHECK-NEXT: br i1 [[C_1_7]], label [[INNER_1_LATCH_7]], label [[EXIT_DEOPT_LOOPEXIT]] 76; CHECK: inner.1.latch.7: 77; CHECK-NEXT: [[NITER_NEXT_7]] = add i64 [[NITER_NEXT_6]], 1 78; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp ne i64 [[NITER_NEXT_7]], [[UNROLL_ITER]] 79; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[INNER_1_HEADER]], label [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT:%.*]] 80; CHECK: outer.middle.unr-lcssa.loopexit: 81; CHECK-NEXT: [[V_LCSSA1_PH_PH:%.*]] = phi i32 [ [[V_7]], [[INNER_1_LATCH_7]] ] 82; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_7]], [[INNER_1_LATCH_7]] ] 83; CHECK-NEXT: br label [[OUTER_MIDDLE_UNR_LCSSA]] 84; CHECK: outer.middle.unr-lcssa: 85; CHECK-NEXT: [[V_LCSSA1_PH:%.*]] = phi i32 [ undef, [[OUTER_HEADER]] ], [ [[V_LCSSA1_PH_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] 86; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[OUTER_MIDDLE_UNR_LCSSA_LOOPEXIT]] ] 87; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 88; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_EPIL_PREHEADER:%.*]], label [[OUTER_MIDDLE:%.*]] 89; CHECK: inner.1.header.epil.preheader: 90; CHECK-NEXT: br label [[INNER_1_HEADER_EPIL:%.*]] 91; CHECK: inner.1.header.epil: 92; CHECK-NEXT: [[INNER_1_IV_EPIL:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_EPIL:%.*]], [[INNER_1_LATCH_EPIL:%.*]] ] 93; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_EPIL_PREHEADER]] ], [ [[EPIL_ITER_NEXT:%.*]], [[INNER_1_LATCH_EPIL]] ] 94; CHECK-NEXT: [[INNER_1_IV_NEXT_EPIL]] = add nuw nsw i64 [[INNER_1_IV_EPIL]], 1 95; CHECK-NEXT: [[V_EPIL:%.*]] = call i32 @get() 96; CHECK-NEXT: [[C_1_EPIL:%.*]] = icmp ugt i32 [[V_EPIL]], 0 97; CHECK-NEXT: br i1 [[C_1_EPIL]], label [[INNER_1_LATCH_EPIL]], label [[EXIT_DEOPT_LOOPEXIT3:%.*]] 98; CHECK: inner.1.latch.epil: 99; CHECK-NEXT: [[C_2_EPIL:%.*]] = icmp ult i64 [[INNER_1_IV_EPIL]], [[OUTER_IV]] 100; CHECK-NEXT: [[EPIL_ITER_NEXT]] = add i64 [[EPIL_ITER]], 1 101; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp ne i64 [[EPIL_ITER_NEXT]], [[XTRAITER]] 102; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[INNER_1_HEADER_EPIL]], label [[OUTER_MIDDLE_EPILOG_LCSSA:%.*]], !llvm.loop [[LOOP0:![0-9]+]] 103; CHECK: outer.middle.epilog-lcssa: 104; CHECK-NEXT: [[V_LCSSA1_PH2:%.*]] = phi i32 [ [[V_EPIL]], [[INNER_1_LATCH_EPIL]] ] 105; CHECK-NEXT: br label [[OUTER_MIDDLE]] 106; CHECK: outer.middle: 107; CHECK-NEXT: [[V_LCSSA1:%.*]] = phi i32 [ [[V_LCSSA1_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ], [ [[V_LCSSA1_PH2]], [[OUTER_MIDDLE_EPILOG_LCSSA]] ] 108; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i32 [[V_LCSSA1]], 0 109; CHECK-NEXT: br i1 [[C_3]], label [[INNER_2_PREHEADER:%.*]], label [[EXIT:%.*]] 110; CHECK: inner.2.preheader: 111; CHECK-NEXT: br label [[INNER_2]] 112; CHECK: inner.2: 113; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw nsw i64 [[OUTER_IV]], 1 114; CHECK-NEXT: br label [[OUTER_HEADER]] 115; CHECK: exit: 116; CHECK-NEXT: ret void 117; CHECK: exit.deopt.loopexit: 118; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]] 119; CHECK: exit.deopt.loopexit3: 120; CHECK-NEXT: br label [[EXIT_DEOPT]] 121; CHECK: exit.deopt: 122; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 123; CHECK-NEXT: ret void 124; 125entry: 126 br label %outer.header 127 128outer.header: 129 %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ] 130 br label %inner.1.header 131 132inner.1.header: 133 %inner.1.iv = phi i64 [ 0, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ] 134 %inner.1.iv.next = add nuw nsw i64 %inner.1.iv, 1 135 %v = call i32 @get() 136 %c.1 = icmp ugt i32 %v, 0 137 br i1 %c.1, label %inner.1.latch, label %exit.deopt 138 139inner.1.latch: ; preds = %inner.1.header 140 %c.2 = icmp ult i64 %inner.1.iv, %outer.iv 141 br i1 %c.2, label %inner.1.header, label %outer.middle 142 143outer.middle: 144 %c.3 = icmp ugt i32 %v, 0 145 br i1 %c.3, label %inner.2, label %exit 146 147inner.2: 148 %inner.2.iv = phi i64 [ 0, %outer.middle ], [ %inner.2.iv.next, %inner.2 ] 149 %inner.2.iv.next = add nsw i64 %inner.2.iv, -1 150 %iv.trunc = trunc i64 %inner.2.iv to i32 151 %c.4 = icmp ult i32 %v, %iv.trunc 152 br i1 %c.4, label %inner.2, label %outer.latch 153 154outer.latch: 155 %outer.iv.next = add nuw nsw i64 %outer.iv, 1 156 br label %outer.header 157 158exit: 159 ret void 160 161exit.deopt: 162 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 163 ret void 164} 165 166declare void @bar() 167declare void @use.2(ptr, i32) 168 169define void @pr56286(i64 %x, ptr %src, ptr %dst, ptr %ptr.src) !prof !0 { 170; CHECK-LABEL: @pr56286( 171; CHECK-NEXT: bb: 172; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[X:%.*]], i64 1) 173; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[SMAX]], 1 174; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[X]] 175; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 176; CHECK: outer.header: 177; CHECK-NEXT: [[OUTER_P:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ [[L_1_LCSSA:%.*]], [[OUTER_LATCH:%.*]] ] 178; CHECK-NEXT: [[TMP2:%.*]] = freeze i64 [[TMP1]] 179; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP2]], -1 180; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP2]], 7 181; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0 182; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[INNER_1_HEADER_PROL_PREHEADER:%.*]], label [[INNER_1_HEADER_PROL_LOOPEXIT:%.*]] 183; CHECK: inner.1.header.prol.preheader: 184; CHECK-NEXT: br label [[INNER_1_HEADER_PROL:%.*]] 185; CHECK: inner.1.header.prol: 186; CHECK-NEXT: [[INNER_1_IV_PROL:%.*]] = phi i64 [ [[X]], [[INNER_1_HEADER_PROL_PREHEADER]] ], [ [[INNER_1_IV_NEXT_PROL:%.*]], [[INNER_1_LATCH_PROL:%.*]] ] 187; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ 0, [[INNER_1_HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_NEXT:%.*]], [[INNER_1_LATCH_PROL]] ] 188; CHECK-NEXT: [[CMP_1_PROL:%.*]] = icmp sgt i32 [[OUTER_P]], 0 189; CHECK-NEXT: br i1 [[CMP_1_PROL]], label [[EXIT_DEOPT_LOOPEXIT1:%.*]], label [[INNER_1_LATCH_PROL]] 190; CHECK: inner.1.latch.prol: 191; CHECK-NEXT: [[L_1_PROL:%.*]] = load i32, ptr [[SRC:%.*]], align 4 192; CHECK-NEXT: store i32 [[L_1_PROL]], ptr [[DST:%.*]], align 8 193; CHECK-NEXT: [[INNER_1_IV_NEXT_PROL]] = add i64 [[INNER_1_IV_PROL]], 1 194; CHECK-NEXT: [[CMP_2_PROL:%.*]] = icmp sgt i64 [[INNER_1_IV_PROL]], 0 195; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1 196; CHECK-NEXT: [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_NEXT]], [[XTRAITER]] 197; CHECK-NEXT: br i1 [[PROL_ITER_CMP]], label [[INNER_1_HEADER_PROL]], label [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !prof [[PROF3:![0-9]+]], !llvm.loop [[LOOP4:![0-9]+]] 198; CHECK: inner.1.header.prol.loopexit.unr-lcssa: 199; CHECK-NEXT: [[L_1_LCSSA_UNR_PH:%.*]] = phi i32 [ [[L_1_PROL]], [[INNER_1_LATCH_PROL]] ] 200; CHECK-NEXT: [[INNER_1_IV_UNR_PH:%.*]] = phi i64 [ [[INNER_1_IV_NEXT_PROL]], [[INNER_1_LATCH_PROL]] ] 201; CHECK-NEXT: br label [[INNER_1_HEADER_PROL_LOOPEXIT]] 202; CHECK: inner.1.header.prol.loopexit: 203; CHECK-NEXT: [[L_1_LCSSA_UNR:%.*]] = phi i32 [ undef, [[OUTER_HEADER]] ], [ [[L_1_LCSSA_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ] 204; CHECK-NEXT: [[INNER_1_IV_UNR:%.*]] = phi i64 [ [[X]], [[OUTER_HEADER]] ], [ [[INNER_1_IV_UNR_PH]], [[INNER_1_HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ] 205; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 7 206; CHECK-NEXT: br i1 [[TMP4]], label [[OUTER_MIDDLE:%.*]], label [[OUTER_HEADER_NEW:%.*]] 207; CHECK: outer.header.new: 208; CHECK-NEXT: br label [[INNER_1_HEADER:%.*]] 209; CHECK: inner.1.header: 210; CHECK-NEXT: [[INNER_1_IV:%.*]] = phi i64 [ [[INNER_1_IV_UNR]], [[OUTER_HEADER_NEW]] ], [ [[INNER_1_IV_NEXT_7:%.*]], [[INNER_1_LATCH_7:%.*]] ] 211; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0 212; CHECK-NEXT: br i1 [[CMP_1]], label [[EXIT_DEOPT_LOOPEXIT:%.*]], label [[INNER_1_LATCH:%.*]] 213; CHECK: inner.1.latch: 214; CHECK-NEXT: [[L_1:%.*]] = load i32, ptr [[SRC]], align 4 215; CHECK-NEXT: store i32 [[L_1]], ptr [[DST]], align 8 216; CHECK-NEXT: [[INNER_1_IV_NEXT:%.*]] = add i64 [[INNER_1_IV]], 1 217; CHECK-NEXT: [[CMP_1_1:%.*]] = icmp sgt i32 [[OUTER_P]], 0 218; CHECK-NEXT: br i1 [[CMP_1_1]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_1:%.*]] 219; CHECK: inner.1.latch.1: 220; CHECK-NEXT: [[L_1_1:%.*]] = load i32, ptr [[SRC]], align 4 221; CHECK-NEXT: store i32 [[L_1_1]], ptr [[DST]], align 8 222; CHECK-NEXT: [[INNER_1_IV_NEXT_1:%.*]] = add i64 [[INNER_1_IV_NEXT]], 1 223; CHECK-NEXT: [[CMP_1_2:%.*]] = icmp sgt i32 [[OUTER_P]], 0 224; CHECK-NEXT: br i1 [[CMP_1_2]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_2:%.*]] 225; CHECK: inner.1.latch.2: 226; CHECK-NEXT: [[L_1_2:%.*]] = load i32, ptr [[SRC]], align 4 227; CHECK-NEXT: store i32 [[L_1_2]], ptr [[DST]], align 8 228; CHECK-NEXT: [[INNER_1_IV_NEXT_2:%.*]] = add i64 [[INNER_1_IV_NEXT_1]], 1 229; CHECK-NEXT: [[CMP_1_3:%.*]] = icmp sgt i32 [[OUTER_P]], 0 230; CHECK-NEXT: br i1 [[CMP_1_3]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_3:%.*]] 231; CHECK: inner.1.latch.3: 232; CHECK-NEXT: [[L_1_3:%.*]] = load i32, ptr [[SRC]], align 4 233; CHECK-NEXT: store i32 [[L_1_3]], ptr [[DST]], align 8 234; CHECK-NEXT: [[INNER_1_IV_NEXT_3:%.*]] = add i64 [[INNER_1_IV_NEXT_2]], 1 235; CHECK-NEXT: [[CMP_1_4:%.*]] = icmp sgt i32 [[OUTER_P]], 0 236; CHECK-NEXT: br i1 [[CMP_1_4]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_4:%.*]] 237; CHECK: inner.1.latch.4: 238; CHECK-NEXT: [[L_1_4:%.*]] = load i32, ptr [[SRC]], align 4 239; CHECK-NEXT: store i32 [[L_1_4]], ptr [[DST]], align 8 240; CHECK-NEXT: [[INNER_1_IV_NEXT_4:%.*]] = add i64 [[INNER_1_IV_NEXT_3]], 1 241; CHECK-NEXT: [[CMP_1_5:%.*]] = icmp sgt i32 [[OUTER_P]], 0 242; CHECK-NEXT: br i1 [[CMP_1_5]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_5:%.*]] 243; CHECK: inner.1.latch.5: 244; CHECK-NEXT: [[L_1_5:%.*]] = load i32, ptr [[SRC]], align 4 245; CHECK-NEXT: store i32 [[L_1_5]], ptr [[DST]], align 8 246; CHECK-NEXT: [[INNER_1_IV_NEXT_5:%.*]] = add i64 [[INNER_1_IV_NEXT_4]], 1 247; CHECK-NEXT: [[CMP_1_6:%.*]] = icmp sgt i32 [[OUTER_P]], 0 248; CHECK-NEXT: br i1 [[CMP_1_6]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_6:%.*]] 249; CHECK: inner.1.latch.6: 250; CHECK-NEXT: [[L_1_6:%.*]] = load i32, ptr [[SRC]], align 4 251; CHECK-NEXT: store i32 [[L_1_6]], ptr [[DST]], align 8 252; CHECK-NEXT: [[INNER_1_IV_NEXT_6:%.*]] = add i64 [[INNER_1_IV_NEXT_5]], 1 253; CHECK-NEXT: [[CMP_1_7:%.*]] = icmp sgt i32 [[OUTER_P]], 0 254; CHECK-NEXT: br i1 [[CMP_1_7]], label [[EXIT_DEOPT_LOOPEXIT]], label [[INNER_1_LATCH_7]] 255; CHECK: inner.1.latch.7: 256; CHECK-NEXT: [[L_1_7:%.*]] = load i32, ptr [[SRC]], align 4 257; CHECK-NEXT: store i32 [[L_1_7]], ptr [[DST]], align 8 258; CHECK-NEXT: [[INNER_1_IV_NEXT_7]] = add i64 [[INNER_1_IV_NEXT_6]], 1 259; CHECK-NEXT: [[CMP_2_7:%.*]] = icmp sgt i64 [[INNER_1_IV_NEXT_6]], 0 260; CHECK-NEXT: br i1 [[CMP_2_7]], label [[OUTER_MIDDLE_UNR_LCSSA:%.*]], label [[INNER_1_HEADER]], !prof [[PROF5:![0-9]+]] 261; CHECK: outer.middle.unr-lcssa: 262; CHECK-NEXT: [[L_1_LCSSA_PH:%.*]] = phi i32 [ [[L_1_7]], [[INNER_1_LATCH_7]] ] 263; CHECK-NEXT: br label [[OUTER_MIDDLE]] 264; CHECK: outer.middle: 265; CHECK-NEXT: [[L_1_LCSSA]] = phi i32 [ [[L_1_LCSSA_UNR]], [[INNER_1_HEADER_PROL_LOOPEXIT]] ], [ [[L_1_LCSSA_PH]], [[OUTER_MIDDLE_UNR_LCSSA]] ] 266; CHECK-NEXT: br label [[INNER_2:%.*]] 267; CHECK: inner.2: 268; CHECK-NEXT: [[INNER_2_IV:%.*]] = phi i32 [ [[L_1_LCSSA]], [[OUTER_MIDDLE]] ], [ [[INNER_2_IV_NEXT_2:%.*]], [[INNER_2]] ] 269; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ 0, [[OUTER_MIDDLE]] ], [ [[TMP33_2:%.*]], [[INNER_2]] ] 270; CHECK-NEXT: [[L_2:%.*]] = load i32, ptr [[SRC]], align 8 271; CHECK-NEXT: [[INNER_2_IV_NEXT:%.*]] = add i32 [[INNER_2_IV]], 1 272; CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[PTR_SRC:%.*]], align 8 273; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[INNER_2_IV]], [[L_2]] 274; CHECK-NEXT: [[TMP281:%.*]] = call i32 @use.2(ptr [[TMP27]], i32 [[ADD_1]]) 275; CHECK-NEXT: [[TMP31:%.*]] = shl nuw nsw i32 [[TMP15]], 16 276; CHECK-NEXT: [[TMP32:%.*]] = add nuw i32 [[TMP31]], 262144 277; CHECK-NEXT: call void @bar() 278; CHECK-NEXT: call void @bar() 279; CHECK-NEXT: call void @bar() 280; CHECK-NEXT: call void @bar() 281; CHECK-NEXT: call void @bar() 282; CHECK-NEXT: call void @bar() 283; CHECK-NEXT: call void @bar() 284; CHECK-NEXT: call void @bar() 285; CHECK-NEXT: [[L_2_1:%.*]] = load i32, ptr [[SRC]], align 8 286; CHECK-NEXT: [[INNER_2_IV_NEXT_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], 1 287; CHECK-NEXT: [[TMP27_1:%.*]] = load ptr, ptr [[PTR_SRC]], align 8 288; CHECK-NEXT: [[ADD_1_1:%.*]] = add i32 [[INNER_2_IV_NEXT]], [[L_2_1]] 289; CHECK-NEXT: [[TMP281_1:%.*]] = call i32 @use.2(ptr [[TMP27_1]], i32 [[ADD_1_1]]) 290; CHECK-NEXT: [[TMP32_1:%.*]] = add nuw i32 [[TMP32]], 262144 291; CHECK-NEXT: call void @bar() 292; CHECK-NEXT: call void @bar() 293; CHECK-NEXT: call void @bar() 294; CHECK-NEXT: call void @bar() 295; CHECK-NEXT: call void @bar() 296; CHECK-NEXT: call void @bar() 297; CHECK-NEXT: call void @bar() 298; CHECK-NEXT: call void @bar() 299; CHECK-NEXT: [[L_2_2:%.*]] = load i32, ptr [[SRC]], align 8 300; CHECK-NEXT: [[INNER_2_IV_NEXT_2]] = add i32 [[INNER_2_IV_NEXT_1]], 1 301; CHECK-NEXT: [[TMP27_2:%.*]] = load ptr, ptr [[PTR_SRC]], align 8 302; CHECK-NEXT: [[ADD_1_2:%.*]] = add i32 [[INNER_2_IV_NEXT_1]], [[L_2_2]] 303; CHECK-NEXT: [[TMP281_2:%.*]] = call i32 @use.2(ptr [[TMP27_2]], i32 [[ADD_1_2]]) 304; CHECK-NEXT: [[TMP32_2:%.*]] = add nuw i32 [[TMP32_1]], 262144 305; CHECK-NEXT: [[TMP33_2]] = ashr exact i32 [[TMP32_2]], 16 306; CHECK-NEXT: call void @bar() 307; CHECK-NEXT: call void @bar() 308; CHECK-NEXT: call void @bar() 309; CHECK-NEXT: call void @bar() 310; CHECK-NEXT: call void @bar() 311; CHECK-NEXT: call void @bar() 312; CHECK-NEXT: call void @bar() 313; CHECK-NEXT: call void @bar() 314; CHECK-NEXT: [[CMP_3_2:%.*]] = icmp sgt i32 [[TMP32_1]], 2031616 315; CHECK-NEXT: br i1 [[CMP_3_2]], label [[OUTER_LATCH]], label [[INNER_2]] 316; CHECK: outer.latch: 317; CHECK-NEXT: br label [[OUTER_HEADER]] 318; CHECK: exit.deopt.loopexit: 319; CHECK-NEXT: br label [[EXIT_DEOPT:%.*]] 320; CHECK: exit.deopt.loopexit1: 321; CHECK-NEXT: br label [[EXIT_DEOPT]] 322; CHECK: exit.deopt: 323; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 324; CHECK-NEXT: ret void 325; 326bb: 327 br label %outer.header 328 329outer.header: 330 %outer.p = phi i32 [ 0, %bb ], [ %l.1, %outer.latch ] 331 br label %inner.1.header 332 333inner.1.header: 334 %inner.1.iv = phi i64 [ %x, %outer.header ], [ %inner.1.iv.next, %inner.1.latch ] 335 %cmp.1 = icmp sgt i32 %outer.p, 0 336 br i1 %cmp.1, label %exit.deopt, label %inner.1.latch 337 338inner.1.latch: 339 %l.1 = load i32, ptr %src, align 4 340 store i32 %l.1, ptr %dst, align 8 341 %inner.1.iv.next = add i64 %inner.1.iv, 1 342 %cmp.2 = icmp sgt i64 %inner.1.iv, 0 343 br i1 %cmp.2, label %outer.middle, label %inner.1.header, !prof !1 344 345outer.middle: 346 br label %inner.2 347 348inner.2: 349 %inner.2.iv = phi i32 [ %l.1, %outer.middle ], [ %inner.2.iv.next, %inner.2 ] 350 %tmp15 = phi i32 [ 0, %outer.middle ], [ %tmp33, %inner.2 ] 351 %l.2 = load i32, ptr %src , align 8 352 %l.3 = load i32, ptr %dst, align 4 353 %inner.2.iv.next = add i32 %inner.2.iv, 1 354 %tmp27 = load ptr, ptr %ptr.src 355 %add.1 = add i32 %inner.2.iv, %l.2 356 %add.2 = add i32 %add.1, %l.3 357 %tmp281 = call i32 @use.2(ptr %tmp27, i32 %add.1) 358 %tmp31 = shl nuw nsw i32 %tmp15, 16 359 %tmp32 = add nuw i32 %tmp31, 262144 360 %tmp33 = ashr exact i32 %tmp32, 16 361 call void @bar() 362 call void @bar() 363 call void @bar() 364 call void @bar() 365 call void @bar() 366 call void @bar() 367 call void @bar() 368 call void @bar() 369 %cmp.3 = icmp sgt i32 %tmp31, 2031616 370 br i1 %cmp.3, label %outer.latch, label %inner.2 371 372outer.latch: 373 br label %outer.header 374 375exit.deopt: 376 call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ] 377 ret void 378} 379 380!0 = !{!"function_entry_count", i64 32768} 381!1 = !{!"branch_weights", i32 1, i32 32} 382